drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dmub_psr.h"
  27 #include "dc.h"
  28 #include "dc_dmub_srv.h"
  29 #include "dmub/dmub_srv.h"
  30 #include "core_types.h"
  31
  32 #define MAX_PIPES 6
  33
  34 /*
  35  * Convert dmcub psr state to dmcu psr state.
  36  */
  37 static enum dc_psr_state convert_psr_state(uint32_t raw_state)
  38 {
  39         enum dc_psr_state state = PSR_STATE0;
  40
  41         if (raw_state == 0)
  42                 state = PSR_STATE0;
  43         else if (raw_state == 0x10)
  44                 state = PSR_STATE1;
  45         else if (raw_state == 0x11)
  46                 state = PSR_STATE1a;
  47         else if (raw_state == 0x20)
  48                 state = PSR_STATE2;
  49         else if (raw_state == 0x21)
  50                 state = PSR_STATE2a;
  51         else if (raw_state == 0x30)
  52                 state = PSR_STATE3;
  53         else if (raw_state == 0x31)
  54                 state = PSR_STATE3Init;
  55         else if (raw_state == 0x40)
  56                 state = PSR_STATE4;
  57         else if (raw_state == 0x41)
  58                 state = PSR_STATE4a;
  59         else if (raw_state == 0x42)
  60                 state = PSR_STATE4b;
  61         else if (raw_state == 0x43)
  62                 state = PSR_STATE4c;
  63         else if (raw_state == 0x44)
  64                 state = PSR_STATE4d;
  65         else if (raw_state == 0x50)
  66                 state = PSR_STATE5;
  67         else if (raw_state == 0x51)
  68                 state = PSR_STATE5a;
  69         else if (raw_state == 0x52)
  70                 state = PSR_STATE5b;
  71         else if (raw_state == 0x53)
  72                 state = PSR_STATE5c;
  73
  74         return state;
  75 }
  76
  77 /*
  78  * Get PSR state from firmware.
  79  */
  80 static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
  81 {
  82         struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
  83         uint32_t raw_state = 0;
  84         uint32_t retry_count = 0;
  85         enum dmub_status status;
  86
  87         do {
  88                 // Send gpint command and wait for ack
  89                 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
  90
  91                 if (status == DMUB_STATUS_OK) {
  92                         // GPINT was executed, get response
  93                         dmub_srv_get_gpint_response(srv, &raw_state);
  94                         *state = convert_psr_state(raw_state);
  95                 } else
  96                         // Return invalid state when GPINT times out
  97                         *state = PSR_STATE_INVALID;
  98
  99                 // Assert if max retry hit
 100                 if (retry_count >= 1000)
 101                         ASSERT(0);
 102         } while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
 103 }
 104
 105 /*
 106  * Set PSR version.
 107  */
 108 static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
 109 {
 110         union dmub_rb_cmd cmd;
 111         struct dc_context *dc = dmub->ctx;
 112
 113         if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)
 114                 return false;
 115
 116         memset(&cmd, 0, sizeof(cmd));
 117         cmd.psr_set_version.header.type = DMUB_CMD__PSR;
 118         cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;
 119         switch (stream->link->psr_settings.psr_version) {
 120         case DC_PSR_VERSION_1:
 121                 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
 122                 break;
 123         case DC_PSR_VERSION_UNSUPPORTED:
 124         default:
 125                 cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
 126                 break;
 127         }
 128         cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
 129         cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
 130         cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
 131
 132         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 133         dc_dmub_srv_cmd_execute(dc->dmub_srv);
 134         dc_dmub_srv_wait_idle(dc->dmub_srv);
 135
 136         return true;
 137 }
 138
 139 /*
 140  * Enable/Disable PSR.
 141  */
 142 static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
 143 {
 144         union dmub_rb_cmd cmd;
 145         struct dc_context *dc = dmub->ctx;
 146         uint32_t retry_count;
 147         enum dc_psr_state state = PSR_STATE0;
 148
 149         memset(&cmd, 0, sizeof(cmd));
 150         cmd.psr_enable.header.type = DMUB_CMD__PSR;
 151
 152         cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
 153         cmd.psr_enable.data.panel_inst = panel_inst;
 154
 155         if (enable)
 156                 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
 157         else
 158                 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE;
 159
 160         cmd.psr_enable.header.payload_bytes = 0; // Send header only
 161
 162         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 163         dc_dmub_srv_cmd_execute(dc->dmub_srv);
 164         dc_dmub_srv_wait_idle(dc->dmub_srv);
 165
 166         /* Below loops 1000 x 500us = 500 ms.
 167          *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
 168          *  least a few frames. Should never hit the max retry assert below.
 169          */
 170         if (wait) {
 171                 for (retry_count = 0; retry_count <= 1000; retry_count++) {
 172                         dmub_psr_get_state(dmub, &state, panel_inst);
 173
 174                         if (enable) {
 175                                 if (state != PSR_STATE0)
 176                                         break;
 177                         } else {
 178                                 if (state == PSR_STATE0)
 179                                         break;
 180                         }
 181
 182                         udelay(500);
 183                 }
 184
 185                 /* assert if max retry hit */
 186                 if (retry_count >= 1000)
 187                         ASSERT(0);
 188         }
 189 }
 190
 191 /*
 192  * Set PSR level.
 193  */
 194 static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
 195 {
 196         union dmub_rb_cmd cmd;
 197         enum dc_psr_state state = PSR_STATE0;
 198         struct dc_context *dc = dmub->ctx;
 199
 200         dmub_psr_get_state(dmub, &state, panel_inst);
 201
 202         if (state == PSR_STATE0)
 203                 return;
 204
 205         memset(&cmd, 0, sizeof(cmd));
 206         cmd.psr_set_level.header.type = DMUB_CMD__PSR;
 207         cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
 208         cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
 209         cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
 210         cmd.psr_set_level.psr_set_level_data.cmd_version = PSR_VERSION_1;
 211         cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
 212         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 213         dc_dmub_srv_cmd_execute(dc->dmub_srv);
 214         dc_dmub_srv_wait_idle(dc->dmub_srv);
 215 }
 216
 217 /*
 218  * Setup PSR by programming phy registers and sending psr hw context values to firmware.
 219  */
 220 static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 221                 struct dc_link *link,
 222                 struct psr_context *psr_context,
 223                 uint8_t panel_inst)
 224 {
 225         union dmub_rb_cmd cmd;
 226         struct dc_context *dc = dmub->ctx;
 227         struct dmub_cmd_psr_copy_settings_data *copy_settings_data
 228                 = &cmd.psr_copy_settings.psr_copy_settings_data;
 229         struct pipe_ctx *pipe_ctx = NULL;
 230         struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
 231         int i = 0;
 232
 233         for (i = 0; i < MAX_PIPES; i++) {
 234                 if (res_ctx->pipe_ctx[i].stream &&
 235                     res_ctx->pipe_ctx[i].stream->link == link &&
 236                     res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
 237                         pipe_ctx = &res_ctx->pipe_ctx[i];
 238                         //TODO: refactor for multi edp support
 239                         break;
 240                 }
 241         }
 242
 243         if (!pipe_ctx)
 244                 return false;
 245
 246         // First, set the psr version
 247         if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
 248                 return false;
 249
 250         // Program DP DPHY fast training registers
 251         link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
 252                         psr_context->psrExitLinkTrainingRequired);
 253
 254         // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
 255         link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
 256                         psr_context->sdpTransmitLineNumDeadline);
 257
 258         memset(&cmd, 0, sizeof(cmd));
 259         cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
 260         cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
 261         cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
 262
 263         // Hw insts
 264         copy_settings_data->dpphy_inst                          = psr_context->transmitterId;
 265         copy_settings_data->aux_inst                            = psr_context->channel;
 266         copy_settings_data->digfe_inst                          = psr_context->engineId;
 267         copy_settings_data->digbe_inst                          = psr_context->transmitterId;
 268
 269         copy_settings_data->mpcc_inst                           = pipe_ctx->plane_res.mpcc_inst;
 270
 271         if (pipe_ctx->plane_res.dpp)
 272                 copy_settings_data->dpp_inst                    = pipe_ctx->plane_res.dpp->inst;
 273         else
 274                 copy_settings_data->dpp_inst                    = 0;
 275         if (pipe_ctx->stream_res.opp)
 276                 copy_settings_data->opp_inst                    = pipe_ctx->stream_res.opp->inst;
 277         else
 278                 copy_settings_data->opp_inst                    = 0;
 279         if (pipe_ctx->stream_res.tg)
 280                 copy_settings_data->otg_inst                    = pipe_ctx->stream_res.tg->inst;
 281         else
 282                 copy_settings_data->otg_inst                    = 0;
 283
 284         // Misc
 285         copy_settings_data->psr_level                           = psr_context->psr_level.u32all;
 286         copy_settings_data->smu_optimizations_en                = psr_context->allow_smu_optimizations;
 287         copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
 288         copy_settings_data->frame_delay                         = psr_context->frame_delay;
 289         copy_settings_data->frame_cap_ind                       = psr_context->psrFrameCaptureIndicationReq;
 290         copy_settings_data->init_sdp_deadline                   = psr_context->sdpTransmitLineNumDeadline;
 291         copy_settings_data->debug.u32All = 0;
 292         copy_settings_data->debug.bitfields.visual_confirm      = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 293         copy_settings_data->debug.bitfields.use_hw_lock_mgr             = 1;
 294         copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 295         copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 296         copy_settings_data->cmd_version =  PSR_VERSION_1;
 297         copy_settings_data->panel_inst = panel_inst;
 298
 299         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 300         dc_dmub_srv_cmd_execute(dc->dmub_srv);
 301         dc_dmub_srv_wait_idle(dc->dmub_srv);
 302
 303         return true;
 304 }
 305
 306 /*
 307  * Send command to PSR to force static ENTER and ignore all state changes until exit
 308  */
 309 static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
 310 {
 311         union dmub_rb_cmd cmd;
 312         struct dc_context *dc = dmub->ctx;
 313
 314         memset(&cmd, 0, sizeof(cmd));
 315
 316         cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
 317         cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
 318         cmd.psr_force_static.header.type = DMUB_CMD__PSR;
 319         cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
 320         cmd.psr_enable.header.payload_bytes = 0;
 321
 322         dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 323         dc_dmub_srv_cmd_execute(dc->dmub_srv);
 324         dc_dmub_srv_wait_idle(dc->dmub_srv);
 325 }
 326
 327 /*
 328  * Get PSR residency from firmware.
 329  */
 330 static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
 331 {
 332         struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
 333         uint16_t param = (uint16_t)(panel_inst << 8);
 334
 335         /* Send gpint command and wait for ack */
 336         dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
 337
 338         dmub_srv_get_gpint_response(srv, residency);
 339 }
 340
 341 static const struct dmub_psr_funcs psr_funcs = {
 342         .psr_copy_settings              = dmub_psr_copy_settings,
 343         .psr_enable                     = dmub_psr_enable,
 344         .psr_get_state                  = dmub_psr_get_state,
 345         .psr_set_level                  = dmub_psr_set_level,
 346         .psr_force_static               = dmub_psr_force_static,
 347         .psr_get_residency              = dmub_psr_get_residency,
 348 };
 349
 350 /*
 351  * Construct PSR object.
 352  */
 353 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
 354 {
 355         psr->ctx = ctx;
 356         psr->funcs = &psr_funcs;
 357 }
 358
 359 /*
 360  * Allocate and initialize PSR object.
 361  */
 362 struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
 363 {
 364         struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
 365
 366         if (psr == NULL) {
 367                 BREAK_TO_DEBUGGER();
 368                 return NULL;
 369         }
 370
 371         dmub_psr_construct(psr, ctx);
 372
 373         return psr;
 374 }
 375
 376 /*
 377  * Deallocate PSR object.
 378  */
 379 void dmub_psr_destroy(struct dmub_psr **dmub)
 380 {
 381         kfree(*dmub);
 382         *dmub = NULL;
 383 }