2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 /* AND EdidUtility only needs a portion
29 * of this file, including the rest only
30 * causes additional issues.
33 #include "fixed31_32.h"
34 #include "irq_types.h"
35 #include "dc_dp_types.h"
36 #include "dc_hw_types.h"
37 #include "dal_types.h"
38 #include "grph_object_defs.h"
40 #ifdef CONFIG_DRM_AMD_DC_HDCP
41 #include "dm_cp_psp.h"
44 /* forward declarations */
45 struct dc_plane_state;
46 struct dc_stream_state;
52 /********************************
53 * Environment definitions
54 ********************************/
55 enum dce_environment {
56 DCE_ENV_PRODUCTION_DRV = 0,
57 /* Emulation on FPGA, in "Maximus" System.
58 * This environment enforces that *only* DC registers accessed.
59 * (access to non-DC registers will hang FPGA) */
61 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
62 * requirements of Diagnostics team. */
65 * Guest VM system, DC HW may exist but is not virtualized and
66 * should not be used. SW support for VDI only.
71 /* Note: use these macro definitions instead of direct comparison! */
72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \
73 (dce_environment == DCE_ENV_FPGA_MAXIMUS)
75 #define IS_DIAG_DC(dce_environment) \
76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
81 uint32_t pci_revision_id;
82 uint32_t hw_internal_rev;
85 uint32_t feature_flags;
86 uint32_t fake_paths_num;
87 void *atombios_base_address;
90 struct dc_perf_trace {
91 unsigned long read_count;
92 unsigned long write_count;
93 unsigned long last_entry_read;
94 unsigned long last_entry_write;
100 void *driver_context; /* e.g. amdgpu_device */
101 struct dc_perf_trace *perf_trace;
104 enum dce_environment dce_environment;
105 struct hw_asic_id asic_id;
107 /* todo: below should probably move to dc. to facilitate removal
108 * of AS we will store these here
110 enum dce_version dce_version;
111 struct dc_bios *dc_bios;
113 struct gpio_service *gpio_service;
114 uint32_t dc_sink_id_count;
115 uint32_t dc_stream_id_count;
116 uint32_t dc_edp_id_count;
117 uint64_t fbc_gpu_addr;
118 struct dc_dmub_srv *dmub_srv;
120 #ifdef CONFIG_DRM_AMD_DC_HDCP
121 struct cp_psp cp_psp;
126 #define DC_MAX_EDID_BUFFER_SIZE 1280
127 #define DC_EDID_BLOCK_SIZE 128
128 #define MAX_SURFACE_NUM 4
129 #define NUM_PIXEL_FORMATS 10
130 #define MAX_REPEATER_CNT 8
132 #include "dc_ddc_types.h"
141 enum view_3d_format {
142 VIEW_3D_FORMAT_NONE = 0,
143 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
144 VIEW_3D_FORMAT_SIDE_BY_SIDE,
145 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
146 VIEW_3D_FORMAT_COUNT,
147 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
150 enum plane_stereo_format {
151 PLANE_STEREO_FORMAT_NONE = 0,
152 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
153 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
154 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
155 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
156 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
157 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
160 /* TODO: Find way to calculate number of bits
161 * Please increase if pixel_format enum increases
162 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
165 enum dc_edid_connector_type {
166 DC_EDID_CONNECTOR_UNKNOWN = 0,
167 DC_EDID_CONNECTOR_ANALOG = 1,
168 DC_EDID_CONNECTOR_DIGITAL = 10,
169 DC_EDID_CONNECTOR_DVI = 11,
170 DC_EDID_CONNECTOR_HDMIA = 12,
171 DC_EDID_CONNECTOR_MDDI = 14,
172 DC_EDID_CONNECTOR_DISPLAYPORT = 15
175 enum dc_edid_status {
184 enum act_return_status {
190 /* audio capability from EDID*/
191 struct dc_cea_audio_mode {
192 uint8_t format_code; /* ucData[0] [6:3]*/
193 uint8_t channel_count; /* ucData[0] [2:0]*/
194 uint8_t sample_rate; /* ucData[1]*/
196 uint8_t sample_size; /* for LPCM*/
197 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
198 uint8_t max_bit_rate;
199 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
205 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
208 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
209 * is used. In this case we assume speaker location are: front left, front
210 * right and front center. */
211 #define DEFAULT_SPEAKER_LOCATION 5
213 #define DC_MAX_AUDIO_DESC_COUNT 16
215 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
217 union display_content_support {
220 unsigned int valid_content_type :1;
221 unsigned int game_content :1;
222 unsigned int cinema_content :1;
223 unsigned int photo_content :1;
224 unsigned int graphics_content :1;
225 unsigned int reserved :27;
229 struct dc_panel_patch {
230 unsigned int dppowerup_delay;
231 unsigned int extra_t12_ms;
232 unsigned int extra_delay_backlight_off;
233 unsigned int extra_t7_ms;
234 unsigned int skip_scdc_overwrite;
235 unsigned int delay_ignore_msa;
236 unsigned int disable_fec;
237 unsigned int extra_t3_ms;
238 unsigned int max_dsc_target_bpp_limit;
239 unsigned int skip_avmute;
242 struct dc_edid_caps {
243 /* sink identification */
244 uint16_t manufacturer_id;
246 uint32_t serial_number;
247 uint8_t manufacture_week;
248 uint8_t manufacture_year;
249 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
252 uint8_t speaker_flags;
253 uint32_t audio_mode_count;
254 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
255 uint32_t audio_latency;
256 uint32_t video_latency;
258 union display_content_support content_support;
263 uint32_t max_tmds_clk_mhz;
266 bool lte_340mcsc_scramble;
271 struct dc_panel_patch panel_patch;
279 struct dc_mode_flags {
280 /* note: part of refresh rate flag*/
281 uint32_t INTERLACE :1;
282 /* native display timing*/
284 /* preferred is the recommended mode, one per display */
285 uint32_t PREFERRED :1;
286 /* true if this mode should use reduced blanking timings
287 *_not_ related to the Reduced Blanking adjustment*/
288 uint32_t REDUCED_BLANKING :1;
289 /* note: part of refreshrate flag*/
290 uint32_t VIDEO_OPTIMIZED_RATE :1;
291 /* should be reported to upper layers as mode_flags*/
292 uint32_t PACKED_PIXEL_FORMAT :1;
294 uint32_t PREFERRED_VIEW :1;
295 /* this timing should be used only in tiled mode*/
296 uint32_t TILED_MODE :1;
297 uint32_t DSE_MODE :1;
298 /* Refresh rate divider when Miracast sink is using a
299 different rate than the output display device
300 Must be zero for wired displays and non-zero for
302 uint32_t MIRACAST_REFRESH_DIVIDER;
306 enum dc_timing_source {
307 TIMING_SOURCE_UNDEFINED,
309 /* explicitly specifed by user, most important*/
310 TIMING_SOURCE_USER_FORCED,
311 TIMING_SOURCE_USER_OVERRIDE,
312 TIMING_SOURCE_CUSTOM,
313 TIMING_SOURCE_EXPLICIT,
315 /* explicitly specified by the display device, more important*/
316 TIMING_SOURCE_EDID_CEA_SVD_3D,
317 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
318 TIMING_SOURCE_EDID_CEA_SVD_420,
319 TIMING_SOURCE_EDID_DETAILED,
320 TIMING_SOURCE_EDID_ESTABLISHED,
321 TIMING_SOURCE_EDID_STANDARD,
322 TIMING_SOURCE_EDID_CEA_SVD,
323 TIMING_SOURCE_EDID_CVT_3BYTE,
324 TIMING_SOURCE_EDID_4BYTE,
328 TIMING_SOURCE_HDMI_VIC,
330 /* implicitly specified by display device, still safe but less important*/
331 TIMING_SOURCE_DEFAULT,
333 /* only used for custom base modes */
334 TIMING_SOURCE_CUSTOM_BASE,
336 /* these timing might not work, least important*/
337 TIMING_SOURCE_RANGELIMIT,
338 TIMING_SOURCE_OS_FORCED,
339 TIMING_SOURCE_IMPLICIT,
341 /* only used by default mode list*/
342 TIMING_SOURCE_BASICMODE,
348 struct stereo_3d_features {
353 bool singleFrameSWPacked;
356 enum dc_timing_support_method {
357 TIMING_SUPPORT_METHOD_UNDEFINED,
358 TIMING_SUPPORT_METHOD_EXPLICIT,
359 TIMING_SUPPORT_METHOD_IMPLICIT,
360 TIMING_SUPPORT_METHOD_NATIVE
363 struct dc_mode_info {
364 uint32_t pixel_width;
365 uint32_t pixel_height;
367 /* Vertical refresh rate for progressive modes.
368 * Field rate for interlaced modes.*/
370 enum dc_timing_standard timing_standard;
371 enum dc_timing_source timing_source;
372 struct dc_mode_flags flags;
375 enum dc_power_state {
376 DC_POWER_STATE_ON = 1,
377 DC_POWER_STATE_STANDBY,
378 DC_POWER_STATE_SUSPEND,
383 enum dc_video_power_state {
384 DC_VIDEO_POWER_UNSPECIFIED = 0,
385 DC_VIDEO_POWER_ON = 1,
386 DC_VIDEO_POWER_STANDBY,
387 DC_VIDEO_POWER_SUSPEND,
389 DC_VIDEO_POWER_HIBERNATE,
390 DC_VIDEO_POWER_SHUTDOWN,
391 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
392 DC_VIDEO_POWER_AFTER_RESET,
393 DC_VIDEO_POWER_MAXIMUM
396 enum dc_acpi_cm_power_state {
397 DC_ACPI_CM_POWER_STATE_D0 = 1,
398 DC_ACPI_CM_POWER_STATE_D1 = 2,
399 DC_ACPI_CM_POWER_STATE_D2 = 4,
400 DC_ACPI_CM_POWER_STATE_D3 = 8
403 enum dc_connection_type {
405 dc_connection_single,
406 dc_connection_mst_branch,
407 dc_connection_sst_branch
410 struct dc_csc_adjustments {
411 struct fixed31_32 contrast;
412 struct fixed31_32 saturation;
413 struct fixed31_32 brightness;
414 struct fixed31_32 hue;
417 enum dpcd_downstream_port_max_bpc {
418 DOWN_STREAM_MAX_8BPC = 0,
419 DOWN_STREAM_MAX_10BPC,
420 DOWN_STREAM_MAX_12BPC,
421 DOWN_STREAM_MAX_16BPC
425 enum link_training_offset {
427 LTTPR_PHY_REPEATER1 = 1,
428 LTTPR_PHY_REPEATER2 = 2,
429 LTTPR_PHY_REPEATER3 = 3,
430 LTTPR_PHY_REPEATER4 = 4,
431 LTTPR_PHY_REPEATER5 = 5,
432 LTTPR_PHY_REPEATER6 = 6,
433 LTTPR_PHY_REPEATER7 = 7,
434 LTTPR_PHY_REPEATER8 = 8
437 struct dc_lttpr_caps {
438 union dpcd_rev revision;
440 uint8_t max_lane_count;
441 uint8_t max_link_rate;
442 uint8_t phy_repeater_cnt;
443 uint8_t max_ext_timeout;
444 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
447 struct dc_dongle_caps {
448 /* dongle type (DP converter, CV smart dongle) */
449 enum display_dongle_type dongle_type;
450 bool extendedCapValid;
451 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
452 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
453 bool is_dp_hdmi_s3d_converter;
454 bool is_dp_hdmi_ycbcr422_pass_through;
455 bool is_dp_hdmi_ycbcr420_pass_through;
456 bool is_dp_hdmi_ycbcr422_converter;
457 bool is_dp_hdmi_ycbcr420_converter;
458 uint32_t dp_hdmi_max_bpc;
459 uint32_t dp_hdmi_max_pixel_clk_in_khz;
462 enum scaling_transformation {
463 SCALING_TRANSFORMATION_UNINITIALIZED,
464 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
465 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
466 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
467 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
468 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
469 SCALING_TRANSFORMATION_INVALID = 0x80000000,
471 /* Flag the first and last */
472 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
473 SCALING_TRANSFORMATION_END =
474 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
477 enum display_content_type {
478 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
479 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
480 DISPLAY_CONTENT_TYPE_PHOTO = 2,
481 DISPLAY_CONTENT_TYPE_CINEMA = 4,
482 DISPLAY_CONTENT_TYPE_GAME = 8
485 enum cm_gamut_adjust_type {
486 CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
487 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
488 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
491 struct cm_grph_csc_adjustment {
492 struct fixed31_32 temperature_matrix[12];
493 enum cm_gamut_adjust_type gamut_adjust_type;
494 enum cm_gamut_coef_format gamut_coef_format;
498 struct dwb_stereo_params {
499 bool stereo_enabled; /* false: normal mode, true: 3D stereo */
500 enum dwb_stereo_type stereo_type; /* indicates stereo format */
501 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */
502 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */
505 struct dc_dwb_cnv_params {
506 unsigned int src_width; /* input active width */
507 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
508 unsigned int crop_width; /* cropped window width at cnv output */
509 bool crop_en; /* window cropping enable in cnv */
510 unsigned int crop_height; /* cropped window height at cnv output */
511 unsigned int crop_x; /* cropped window start x value at cnv output */
512 unsigned int crop_y; /* cropped window start y value at cnv output */
513 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
514 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
515 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */
516 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
517 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
520 struct dc_dwb_params {
521 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */
522 unsigned int hdr_mult; /* must be in FP1.6.12 */
523 struct cm_grph_csc_adjustment csc_params;
524 struct dwb_stereo_params stereo_params;
525 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
526 unsigned int dest_width; /* Destination width */
527 unsigned int dest_height; /* Destination height */
528 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
529 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */
530 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */
531 struct scaling_taps scaler_taps; /* Scaling taps */
532 enum dwb_subsample_position subsample_position;
533 struct dc_transfer_func *out_transfer_func;
538 union audio_sample_rates {
539 struct sample_rates {
545 uint8_t RATE_176_4:1;
552 struct audio_speaker_flags {
560 uint32_t SUPPORT_AI:1;
563 struct audio_speaker_info {
564 uint32_t ALLSPEAKERS:7;
565 uint32_t SUPPORT_AI:1;
569 struct audio_info_flags {
573 struct audio_speaker_flags speaker_flags;
574 struct audio_speaker_info info;
580 enum audio_format_code {
581 AUDIO_FORMAT_CODE_FIRST = 1,
582 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
584 AUDIO_FORMAT_CODE_AC3,
586 AUDIO_FORMAT_CODE_MPEG1,
588 AUDIO_FORMAT_CODE_MP3,
590 AUDIO_FORMAT_CODE_MPEG2,
591 AUDIO_FORMAT_CODE_AAC,
592 AUDIO_FORMAT_CODE_DTS,
593 AUDIO_FORMAT_CODE_ATRAC,
594 AUDIO_FORMAT_CODE_1BITAUDIO,
595 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
596 AUDIO_FORMAT_CODE_DTS_HD,
597 AUDIO_FORMAT_CODE_MAT_MLP,
598 AUDIO_FORMAT_CODE_DST,
599 AUDIO_FORMAT_CODE_WMAPRO,
600 AUDIO_FORMAT_CODE_LAST,
601 AUDIO_FORMAT_CODE_COUNT =
602 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
606 /* ucData[0] [6:3] */
607 enum audio_format_code format_code;
608 /* ucData[0] [2:0] */
609 uint8_t channel_count;
611 union audio_sample_rates sample_rates;
615 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
616 uint8_t max_bit_rate;
617 /* for Audio Formats 9-15 */
618 uint8_t vendor_specific;
623 struct audio_info_flags flags;
624 uint32_t video_latency;
625 uint32_t audio_latency;
626 uint32_t display_index;
627 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
628 uint32_t manufacture_id;
630 /* PortID used for ContainerID when defined */
633 /* this field must be last in this struct */
634 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
637 unsigned int audio_packet_type;
638 unsigned int max_audiosample_rate;
641 enum dc_infoframe_type {
642 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
643 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
644 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
645 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
646 DC_DP_INFOFRAME_TYPE_PPS = 0x10,
649 struct dc_info_packet {
658 struct dc_info_packet_128 {
667 #define DC_PLANE_UPDATE_TIMES_MAX 10
669 struct dc_plane_flip_time {
670 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
672 unsigned int prev_update_time_in_us;
692 PSR_STATE_INVALID = 0xFF
696 unsigned char psr_version;
697 unsigned int psr_rfb_setup_time;
698 bool psr_exit_link_training_required;
699 bool psr_frame_capture_indication_req;
700 unsigned int psr_sdp_transmit_line_num_deadline;
701 bool allow_smu_optimizations;
702 bool allow_multi_disp_optimizations;
705 union dmcu_psr_level {
707 unsigned int SKIP_CRC:1;
708 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
709 unsigned int SKIP_PHY_POWER_DOWN:1;
710 unsigned int SKIP_AUX_ACK_CHECK:1;
711 unsigned int SKIP_CRTC_DISABLE:1;
712 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
713 unsigned int SKIP_SMU_NOTIFICATION:1;
714 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
715 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
716 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
717 unsigned int RESERVED:22;
722 enum physical_phy_id {
734 PHYLD_UNKNOWN = (-1L)
738 PHY_TYPE_UNKNOWN = 1,
739 PHY_TYPE_PCIE_PHY = 2,
745 enum channel_id channel;
747 enum transmitter transmitterId;
748 /* Engine Id is used for Dig Be source select */
749 enum engine_id engineId;
750 /* Controller Id used for Dig Fe source select */
751 enum controller_id controllerId;
753 enum phy_type phyType;
754 /* Physical PHY Id used by SMU interpretation */
755 enum physical_phy_id smuPhyId;
756 /* Vertical total pixels from crtc timing.
757 * This is used for static screen detection.
758 * ie. If we want to detect half a frame,
759 * we use this to determine the hyst lines.
761 unsigned int crtcTimingVerticalTotal;
762 /* PSR supported from panel capabilities and
763 * current display configuration
765 bool psrSupportedDisplayConfig;
766 /* Whether fast link training is supported by the panel */
767 bool psrExitLinkTrainingRequired;
768 /* If RFB setup time is greater than the total VBLANK time,
769 * it is not possible for the sink to capture the video frame
770 * in the same frame the SDP is sent. In this case,
771 * the frame capture indication bit should be set and an extra
772 * static frame should be transmitted to the sink.
774 bool psrFrameCaptureIndicationReq;
775 /* Set the last possible line SDP may be transmitted without violating
776 * the RFB setup time or entering the active video frame.
778 unsigned int sdpTransmitLineNumDeadline;
779 /* The VSync rate in Hz used to calculate the
780 * step size for smooth brightness feature
782 unsigned int vsync_rate_hz;
783 unsigned int skipPsrWaitForPllLock;
784 unsigned int numberOfControllers;
785 /* Unused, for future use. To indicate that first changed frame from
786 * state3 shouldn't result in psr_inactive, but rather to perform
787 * an automatic single frame rfb_update.
789 bool rfb_update_auto_en;
790 /* Number of frame before entering static screen */
791 unsigned int timehyst_frames;
792 /* Partial frames before entering static screen */
793 unsigned int hyst_lines;
794 /* # of repeated AUX transaction attempts to make before
795 * indicating failure to the driver
797 unsigned int aux_repeats;
798 /* Controls hw blocks to power down during PSR active state */
799 union dmcu_psr_level psr_level;
800 /* Controls additional delay after remote frame capture before
801 * continuing powerd own
803 unsigned int frame_delay;
804 bool allow_smu_optimizations;
805 bool allow_multi_disp_optimizations;
808 struct colorspace_transform {
809 struct fixed31_32 matrix[12];
820 unsigned int memoryClock;
821 unsigned int displayClock;
822 unsigned int engineClock;
823 unsigned int maxSupportedDppClock;
824 unsigned int dppClock;
825 unsigned int socClock;
826 unsigned int dcfClockDeepSleep;
828 unsigned int phyClock;
833 DC_CLOCK_TYPE_DISPCLK = 0,
834 DC_CLOCK_TYPE_DPPCLK = 1,
837 struct dc_clock_config {
838 uint32_t max_clock_khz;
839 uint32_t min_clock_khz;
840 uint32_t bw_requirequired_clock_khz;
841 uint32_t current_clock_khz;/*current clock in use*/
844 /* DSC DPCD capabilities */
845 union dsc_slice_caps1 {
847 uint8_t NUM_SLICES_1 : 1;
848 uint8_t NUM_SLICES_2 : 1;
849 uint8_t RESERVED : 1;
850 uint8_t NUM_SLICES_4 : 1;
851 uint8_t NUM_SLICES_6 : 1;
852 uint8_t NUM_SLICES_8 : 1;
853 uint8_t NUM_SLICES_10 : 1;
854 uint8_t NUM_SLICES_12 : 1;
859 union dsc_slice_caps2 {
861 uint8_t NUM_SLICES_16 : 1;
862 uint8_t NUM_SLICES_20 : 1;
863 uint8_t NUM_SLICES_24 : 1;
864 uint8_t RESERVED : 5;
869 union dsc_color_formats {
872 uint8_t YCBCR_444 : 1;
873 uint8_t YCBCR_SIMPLE_422 : 1;
874 uint8_t YCBCR_NATIVE_422 : 1;
875 uint8_t YCBCR_NATIVE_420 : 1;
876 uint8_t RESERVED : 3;
881 union dsc_color_depth {
883 uint8_t RESERVED1 : 1;
884 uint8_t COLOR_DEPTH_8_BPC : 1;
885 uint8_t COLOR_DEPTH_10_BPC : 1;
886 uint8_t COLOR_DEPTH_12_BPC : 1;
887 uint8_t RESERVED2 : 3;
892 struct dsc_dec_dpcd_caps {
893 bool is_dsc_supported;
895 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
896 union dsc_slice_caps1 slice_caps1;
897 union dsc_slice_caps2 slice_caps2;
898 int32_t lb_bit_depth;
899 bool is_block_pred_supported;
900 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
901 union dsc_color_formats color_formats;
902 union dsc_color_depth color_depth;
903 int32_t throughput_mode_0_mps; /* In MPs */
904 int32_t throughput_mode_1_mps; /* In MPs */
905 int32_t max_slice_width;
906 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
908 /* Extended DSC caps */
909 uint32_t branch_overall_throughput_0_mps; /* In MPs */
910 uint32_t branch_overall_throughput_1_mps; /* In MPs */
911 uint32_t branch_max_line_width;
915 struct dc_golden_table {
916 uint16_t dc_golden_table_ver;
917 uint32_t aux_dphy_rx_control0_val;
918 uint32_t aux_dphy_tx_control_val;
919 uint32_t aux_dphy_rx_control1_val;
920 uint32_t dc_gpio_aux_ctrl_0_val;
921 uint32_t dc_gpio_aux_ctrl_1_val;
922 uint32_t dc_gpio_aux_ctrl_2_val;
923 uint32_t dc_gpio_aux_ctrl_3_val;
924 uint32_t dc_gpio_aux_ctrl_4_val;
925 uint32_t dc_gpio_aux_ctrl_5_val;
928 enum dc_gpu_mem_alloc_type {
929 DC_MEM_ALLOC_TYPE_GART,
930 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
931 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
932 DC_MEM_ALLOC_TYPE_AGP
935 enum dc_psr_version {
936 DC_PSR_VERSION_1 = 0,
937 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
940 /* Possible values of display_endpoint_id.endpoint */
941 enum display_endpoint_type {
942 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
943 DISPLAY_ENDPOINT_UNKNOWN = -1
946 /* Extends graphics_object_id with an additional member 'ep_type' for
947 * distinguishing between physical endpoints (with entries in BIOS connector table) and
950 struct display_endpoint_id {
951 struct graphics_object_id link_id;
952 enum display_endpoint_type ep_type;
955 #endif /* DC_TYPES_H_ */