2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #if defined(CONFIG_DRM_AMD_DC_HDCP)
33 #include "hdcp_types.h"
35 #include "gpio_types.h"
36 #include "link_service_types.h"
37 #include "grph_object_ctrl_defs.h"
38 #include <inc/hw/opp.h>
40 #include "inc/hw_sequencer.h"
41 #include "inc/compressor.h"
42 #include "inc/hw/dmcu.h"
43 #include "dml/display_mode_lib.h"
45 /* forward declaration */
48 #define DC_VER "3.2.137"
50 #define MAX_SURFACES 3
53 #define MAX_SINKS_PER_LINK 4
54 #define MIN_VIEWPORT_SIZE 12
57 /*******************************************************************************
58 * Display Core Interfaces
59 ******************************************************************************/
62 struct dmcu_version dmcu_version;
65 enum dp_protocol_version {
70 DC_PLANE_TYPE_INVALID,
71 DC_PLANE_TYPE_DCE_RGB,
72 DC_PLANE_TYPE_DCE_UNDERLAY,
73 DC_PLANE_TYPE_DCN_UNIVERSAL,
77 enum dc_plane_type type;
78 uint32_t blends_with_above : 1;
79 uint32_t blends_with_below : 1;
80 uint32_t per_pixel_alpha : 1;
82 uint32_t argb8888 : 1;
87 } pixel_format_support;
88 // max upscaling factor x1000
89 // upscaling factors are always >= 1
90 // for example, 1080p -> 8K is 4.0, or 4000 raw value
96 // max downscale factor x1000
97 // downscale factors are always <= 1
98 // for example, 8K -> 1080p is 0.25, or 250 raw value
103 } max_downscale_factor;
104 // minimal width/height
109 // Color management caps (DPP and MPC)
110 struct rom_curve_caps {
113 uint16_t gamma2_2 : 1;
118 struct dpp_color_caps {
119 uint16_t dcn_arch : 1; // all DCE generations treated the same
120 // input lut is different than most LUTs, just plain 256-entry lookup
121 uint16_t input_lut_shared : 1; // shared with DGAM
123 uint16_t dgam_ram : 1;
124 uint16_t post_csc : 1; // before gamut remap
125 uint16_t gamma_corr : 1;
127 // hdr_mult and gamut remap always available in DPP (in that order)
128 // 3d lut implies shaper LUT,
129 // it may be shared with MPC - check MPC:shared_3d_lut flag
130 uint16_t hw_3d_lut : 1;
131 uint16_t ogam_ram : 1; // blnd gam
133 uint16_t dgam_rom_for_yuv : 1;
134 struct rom_curve_caps dgam_rom_caps;
135 struct rom_curve_caps ogam_rom_caps;
138 struct mpc_color_caps {
139 uint16_t gamut_remap : 1;
140 uint16_t ogam_ram : 1;
142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
145 struct rom_curve_caps ogam_rom_caps;
148 struct dc_color_caps {
149 struct dpp_color_caps dpp;
150 struct mpc_color_caps mpc;
154 uint32_t max_streams;
157 uint32_t max_slave_planes;
158 uint32_t max_slave_yuv_planes;
159 uint32_t max_slave_rgb_planes;
161 uint32_t max_downscale_ratio;
162 uint32_t i2c_speed_in_khz;
163 uint32_t i2c_speed_in_khz_hdcp;
164 uint32_t dmdata_alloc_size;
165 unsigned int max_cursor_size;
166 unsigned int max_video_width;
167 unsigned int min_horizontal_blanking_period;
168 int linear_pitch_alignment;
169 bool dcc_const_color;
173 bool post_blend_color_processing;
174 bool force_dp_tps4_for_cp2520;
175 bool disable_dp_clk_share;
176 bool psp_setup_panel_mode;
177 bool extended_aux_timeout_support;
179 uint32_t num_of_internal_disp;
180 enum dp_protocol_version max_dp_protocol_version;
181 unsigned int mall_size_per_mem_channel;
182 unsigned int mall_size_total;
183 unsigned int cursor_cache_size;
184 struct dc_plane_cap planes[MAX_PLANES];
185 struct dc_color_caps color;
189 bool no_connect_phy_config;
191 bool skip_clock_update;
192 bool lt_early_cr_pattern;
195 struct dc_dcc_surface_param {
196 struct dc_size surface_size;
197 enum surface_pixel_format format;
198 enum swizzle_mode_values swizzle_mode;
199 enum dc_scan_direction scan;
202 struct dc_dcc_setting {
203 unsigned int max_compressed_blk_size;
204 unsigned int max_uncompressed_blk_size;
205 bool independent_64b_blks;
206 #if defined(CONFIG_DRM_AMD_DC_DCN)
207 //These bitfields to be used starting with DCN 3.0
209 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
210 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
211 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
212 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
217 struct dc_surface_dcc_cap {
220 struct dc_dcc_setting rgb;
224 struct dc_dcc_setting luma;
225 struct dc_dcc_setting chroma;
230 bool const_color_support;
233 struct dc_static_screen_params {
240 unsigned int num_frames;
244 /* Surface update type is used by dc_update_surfaces_and_stream
245 * The update type is determined at the very beginning of the function based
246 * on parameters passed in and decides how much programming (or updating) is
247 * going to be done during the call.
249 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
250 * logical calculations or hardware register programming. This update MUST be
251 * ISR safe on windows. Currently fast update will only be used to flip surface
254 * UPDATE_TYPE_MED is used for slower updates which require significant hw
255 * re-programming however do not affect bandwidth consumption or clock
256 * requirements. At present, this is the level at which front end updates
257 * that do not require us to run bw_calcs happen. These are in/out transfer func
258 * updates, viewport offset changes, recout size changes and pixel depth changes.
259 * This update can be done at ISR, but we want to minimize how often this happens.
261 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
262 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
263 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
264 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
265 * a full update. This cannot be done at ISR level and should be a rare event.
266 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
267 * underscan we don't expect to see this call at all.
270 enum surface_update_type {
271 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
272 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
273 UPDATE_TYPE_FULL, /* may need to shuffle resources */
276 /* Forward declaration*/
278 struct dc_plane_state;
282 struct dc_cap_funcs {
283 bool (*get_dcc_compression_cap)(const struct dc *dc,
284 const struct dc_dcc_surface_param *input,
285 struct dc_surface_dcc_cap *output);
288 struct link_training_settings;
291 /* Structure to hold configuration flags set by dm at dc creation. */
294 bool disable_disp_pll_sharing;
296 bool disable_fractional_pwm;
297 bool allow_seamless_boot_optimization;
298 bool power_down_display_on_boot;
299 bool edp_not_connected;
302 bool allow_lttpr_non_transparent_mode;
303 bool multi_mon_pp_mclk_switch;
306 #if defined(CONFIG_DRM_AMD_DC_DCN)
307 bool clamp_min_dcfclk;
309 uint64_t vblank_alignment_dto_params;
310 uint8_t vblank_alignment_max_frame_time_diff;
311 bool is_asymmetric_memory;
312 bool is_single_rank_dimm;
315 enum visual_confirm {
316 VISUAL_CONFIRM_DISABLE = 0,
317 VISUAL_CONFIRM_SURFACE = 1,
318 VISUAL_CONFIRM_HDR = 2,
319 VISUAL_CONFIRM_MPCTREE = 4,
320 VISUAL_CONFIRM_PSR = 5,
326 DCC_HALF_REQ_DISALBE = 2,
329 enum pipe_split_policy {
330 MPC_SPLIT_DYNAMIC = 0,
332 MPC_SPLIT_AVOID_MULT_DISP = 2,
335 enum wm_report_mode {
336 WM_REPORT_DEFAULT = 0,
337 WM_REPORT_OVERRIDE = 1,
340 dtm_level_p0 = 0,/*highest voltage*/
344 dtm_level_p4,/*when active_display_count = 0*/
348 DCN_PWR_STATE_UNKNOWN = -1,
349 DCN_PWR_STATE_MISSION_MODE = 0,
350 DCN_PWR_STATE_LOW_POWER = 3,
354 * For any clocks that may differ per pipe
355 * only the max is stored in this structure
359 int actual_dispclk_khz;
361 int actual_dppclk_khz;
362 int disp_dpp_voltage_level_khz;
365 int dcfclk_deep_sleep_khz;
369 bool p_state_change_support;
370 enum dcn_pwr_state pwr_state;
372 * Elements below are not compared for the purposes of
373 * optimization required
375 bool prev_p_state_change_support;
376 enum dtm_pstate dtm_level;
377 int max_supported_dppclk_khz;
378 int max_supported_dispclk_khz;
379 int bw_dppclk_khz; /*a copy of dppclk_khz*/
383 struct dc_bw_validation_profile {
386 unsigned long long total_ticks;
387 unsigned long long voltage_level_ticks;
388 unsigned long long watermark_ticks;
389 unsigned long long rq_dlg_ticks;
391 unsigned long long total_count;
392 unsigned long long skip_fast_count;
393 unsigned long long skip_pass_count;
394 unsigned long long skip_fail_count;
397 #define BW_VAL_TRACE_SETUP() \
398 unsigned long long end_tick = 0; \
399 unsigned long long voltage_level_tick = 0; \
400 unsigned long long watermark_tick = 0; \
401 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
402 dm_get_timestamp(dc->ctx) : 0
404 #define BW_VAL_TRACE_COUNT() \
405 if (dc->debug.bw_val_profile.enable) \
406 dc->debug.bw_val_profile.total_count++
408 #define BW_VAL_TRACE_SKIP(status) \
409 if (dc->debug.bw_val_profile.enable) { \
410 if (!voltage_level_tick) \
411 voltage_level_tick = dm_get_timestamp(dc->ctx); \
412 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
415 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
416 if (dc->debug.bw_val_profile.enable) \
417 voltage_level_tick = dm_get_timestamp(dc->ctx)
419 #define BW_VAL_TRACE_END_WATERMARKS() \
420 if (dc->debug.bw_val_profile.enable) \
421 watermark_tick = dm_get_timestamp(dc->ctx)
423 #define BW_VAL_TRACE_FINISH() \
424 if (dc->debug.bw_val_profile.enable) { \
425 end_tick = dm_get_timestamp(dc->ctx); \
426 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
427 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
428 if (watermark_tick) { \
429 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
430 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
434 union mem_low_power_enable_options {
446 struct dc_debug_options {
447 enum visual_confirm visual_confirm;
453 bool validation_trace;
454 bool bandwidth_calcs_trace;
455 int max_downscale_src_width;
457 /* stutter efficiency related */
458 bool disable_stutter;
460 enum dcc_option disable_dcc;
461 enum pipe_split_policy pipe_split_policy;
462 bool force_single_disp_pipe_split;
463 bool voltage_align_fclk;
464 bool disable_min_fclk;
466 bool disable_dfs_bypass;
467 bool disable_dpp_power_gate;
468 bool disable_hubp_power_gate;
469 bool disable_dsc_power_gate;
470 int dsc_min_slice_height_override;
471 int dsc_bpp_increment_div;
472 bool native422_support;
473 bool disable_pplib_wm_range;
474 enum wm_report_mode pplib_wm_report_mode;
475 unsigned int min_disp_clk_khz;
476 unsigned int min_dpp_clk_khz;
477 int sr_exit_time_dpm0_ns;
478 int sr_enter_plus_exit_time_dpm0_ns;
480 int sr_enter_plus_exit_time_ns;
481 int urgent_latency_ns;
482 uint32_t underflow_assert_delay_us;
483 int percent_of_ideal_drambw;
484 int dram_clock_change_latency_ns;
485 bool optimized_watermark;
487 bool disable_pplib_clock_request;
488 bool disable_clock_gate;
489 bool disable_mem_low_power;
492 bool force_abm_enable;
493 bool disable_stereo_support;
495 bool performance_trace;
496 bool az_endpoint_mute_only;
497 bool always_use_regamma;
498 bool recovery_enabled;
499 bool avoid_vbios_exec_table;
500 bool scl_reset_length10;
502 bool skip_detection_link_training;
503 uint32_t edid_read_retry_times;
504 bool remove_disconnect_edp;
505 unsigned int force_odm_combine; //bit vector based on otg inst
506 #if defined(CONFIG_DRM_AMD_DC_DCN)
507 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
509 unsigned int force_fclk_khz;
511 bool dmub_offload_enabled;
512 bool dmcub_emulation;
513 #if defined(CONFIG_DRM_AMD_DC_DCN)
514 bool disable_idle_power_optimizations;
515 unsigned int mall_size_override;
516 unsigned int mall_additional_timer_percent;
517 bool mall_error_as_fatal;
519 bool dmub_command_table; /* for testing only */
520 struct dc_bw_validation_profile bw_val_profile;
522 bool disable_48mhz_pwrdwn;
523 /* This forces a hard min on the DCFCLK requested to SMU/PP
524 * watermarks are not affected.
526 unsigned int force_min_dcfclk_mhz;
527 #if defined(CONFIG_DRM_AMD_DC_DCN)
530 bool disable_timing_sync;
532 int force_clock_mode;/*every mode change.*/
534 bool disable_dram_clock_change_vactive_support;
535 bool validate_dml_output;
536 bool enable_dmcub_surface_flip;
537 bool usbc_combo_phy_reset_wa;
539 bool enable_dram_clock_change_one_display_vactive;
540 union mem_low_power_enable_options enable_mem_low_power;
541 bool force_vblank_alignment;
543 /* Enable dmub aux for legacy ddc */
544 bool enable_dmub_aux_for_legacy_ddc;
545 bool optimize_edp_link_rate; /* eDP ILR */
546 /* force enable edp FEC */
547 bool force_enable_edp_fec;
548 /* FEC/PSR1 sequence enable delay in 100us */
549 uint8_t fec_enable_delay_in100us;
552 struct dc_debug_data {
553 uint32_t ltFailCount;
554 uint32_t i2cErrorCount;
555 uint32_t auxErrorCount;
558 struct dc_phy_addr_space_config {
571 uint64_t page_table_start_addr;
572 uint64_t page_table_end_addr;
573 uint64_t page_table_base_addr;
578 uint64_t page_table_default_page_addr;
581 struct dc_virtual_addr_space_config {
582 uint64_t page_table_base_addr;
583 uint64_t page_table_start_addr;
584 uint64_t page_table_end_addr;
585 uint32_t page_table_block_size_in_bytes;
586 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
589 struct dc_bounding_box_overrides {
591 int sr_enter_plus_exit_time_ns;
592 int urgent_latency_ns;
593 int percent_of_ideal_drambw;
594 int dram_clock_change_latency_ns;
595 int dummy_clock_change_latency_ns;
596 /* This forces a hard min on the DCFCLK we use
597 * for DML. Unlike the debug option for forcing
598 * DCFCLK, this override affects watermark calculations
603 struct resource_pool;
605 struct gpu_info_soc_bounding_box_v1_0;
607 struct dc_versions versions;
609 struct dc_cap_funcs cap_funcs;
610 struct dc_config config;
611 struct dc_debug_options debug;
612 struct dc_bounding_box_overrides bb_overrides;
613 struct dc_bug_wa work_arounds;
614 struct dc_context *ctx;
615 struct dc_phy_addr_space_config vm_pa_config;
618 struct dc_link *links[MAX_PIPES * 2];
620 struct dc_state *current_state;
621 struct resource_pool *res_pool;
623 struct clk_mgr *clk_mgr;
625 /* Display Engine Clock levels */
626 struct dm_pp_clock_levels sclk_lvls;
628 /* Inputs into BW and WM calculations. */
629 struct bw_calcs_dceip *bw_dceip;
630 struct bw_calcs_vbios *bw_vbios;
631 #ifdef CONFIG_DRM_AMD_DC_DCN
632 struct dcn_soc_bounding_box *dcn_soc;
633 struct dcn_ip_params *dcn_ip;
634 struct display_mode_lib dml;
638 struct hw_sequencer_funcs hwss;
639 struct dce_hwseq *hwseq;
641 /* Require to optimize clocks and bandwidth for added/removed planes */
642 bool optimized_required;
643 bool wm_optimized_required;
644 #if defined(CONFIG_DRM_AMD_DC_DCN)
645 bool idle_optimizations_allowed;
648 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
651 struct compressor *fbc_compressor;
653 struct dc_debug_data debug_data;
654 struct dpcd_vendor_signature vendor_signature;
656 const char *build_id;
657 struct vm_helper *vm_helper;
660 enum frame_buffer_mode {
661 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
662 FRAME_BUFFER_MODE_ZFB_ONLY,
663 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
666 struct dchub_init_data {
667 int64_t zfb_phys_addr_base;
668 int64_t zfb_mc_base_addr;
669 uint64_t zfb_size_in_byte;
670 enum frame_buffer_mode fb_mode;
671 bool dchub_initialzied;
672 bool dchub_info_valid;
675 struct dc_init_data {
676 struct hw_asic_id asic_id;
677 void *driver; /* ctx */
678 struct cgs_device *cgs_device;
679 struct dc_bounding_box_overrides bb_overrides;
681 int num_virtual_links;
683 * If 'vbios_override' not NULL, it will be called instead
684 * of the real VBIOS. Intended use is Diagnostics on FPGA.
686 struct dc_bios *vbios_override;
687 enum dce_environment dce_environment;
689 struct dmub_offload_funcs *dmub_if;
690 struct dc_reg_helper_state *dmub_offload;
692 struct dc_config flags;
695 struct dpcd_vendor_signature vendor_signature;
696 #if defined(CONFIG_DRM_AMD_DC_DCN)
697 bool force_smu_not_present;
701 struct dc_callback_init {
702 #ifdef CONFIG_DRM_AMD_DC_HDCP
703 struct cp_psp cp_psp;
709 struct dc *dc_create(const struct dc_init_data *init_params);
710 void dc_hardware_init(struct dc *dc);
712 int dc_get_vmid_use_vector(struct dc *dc);
713 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
714 /* Returns the number of vmids supported */
715 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
716 void dc_init_callbacks(struct dc *dc,
717 const struct dc_callback_init *init_params);
718 void dc_deinit_callbacks(struct dc *dc);
719 void dc_destroy(struct dc **dc);
721 /*******************************************************************************
723 ******************************************************************************/
726 TRANSFER_FUNC_POINTS = 1025
729 struct dc_hdr_static_metadata {
730 /* display chromaticities and white point in units of 0.00001 */
731 unsigned int chromaticity_green_x;
732 unsigned int chromaticity_green_y;
733 unsigned int chromaticity_blue_x;
734 unsigned int chromaticity_blue_y;
735 unsigned int chromaticity_red_x;
736 unsigned int chromaticity_red_y;
737 unsigned int chromaticity_white_point_x;
738 unsigned int chromaticity_white_point_y;
740 uint32_t min_luminance;
741 uint32_t max_luminance;
742 uint32_t maximum_content_light_level;
743 uint32_t maximum_frame_average_light_level;
746 enum dc_transfer_func_type {
748 TF_TYPE_DISTRIBUTED_POINTS,
753 struct dc_transfer_func_distributed_points {
754 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
755 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
756 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
758 uint16_t end_exponent;
759 uint16_t x_point_at_y1_red;
760 uint16_t x_point_at_y1_green;
761 uint16_t x_point_at_y1_blue;
764 enum dc_transfer_func_predefined {
765 TRANSFER_FUNCTION_SRGB,
766 TRANSFER_FUNCTION_BT709,
767 TRANSFER_FUNCTION_PQ,
768 TRANSFER_FUNCTION_LINEAR,
769 TRANSFER_FUNCTION_UNITY,
770 TRANSFER_FUNCTION_HLG,
771 TRANSFER_FUNCTION_HLG12,
772 TRANSFER_FUNCTION_GAMMA22,
773 TRANSFER_FUNCTION_GAMMA24,
774 TRANSFER_FUNCTION_GAMMA26
778 struct dc_transfer_func {
779 struct kref refcount;
780 enum dc_transfer_func_type type;
781 enum dc_transfer_func_predefined tf;
782 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
783 uint32_t sdr_ref_white_level;
785 struct pwl_params pwl;
786 struct dc_transfer_func_distributed_points tf_pts;
791 union dc_3dlut_state {
793 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
794 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
795 uint32_t rmu_mux_num:3; /*index of mux to use*/
796 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
797 uint32_t mpc_rmu1_mux:4;
798 uint32_t mpc_rmu2_mux:4;
799 uint32_t reserved:15;
806 struct kref refcount;
807 struct tetrahedral_params lut_3d;
808 struct fixed31_32 hdr_multiplier;
809 union dc_3dlut_state state;
812 * This structure is filled in by dc_surface_get_status and contains
813 * the last requested address and the currently active address so the called
814 * can determine if there are any outstanding flips
816 struct dc_plane_status {
817 struct dc_plane_address requested_address;
818 struct dc_plane_address current_address;
819 bool is_flip_pending;
823 union surface_update_flags {
826 uint32_t addr_update:1;
828 uint32_t dcc_change:1;
829 uint32_t color_space_change:1;
830 uint32_t horizontal_mirror_change:1;
831 uint32_t per_pixel_alpha_change:1;
832 uint32_t global_alpha_change:1;
834 uint32_t rotation_change:1;
835 uint32_t swizzle_change:1;
836 uint32_t scaling_change:1;
837 uint32_t position_change:1;
838 uint32_t in_transfer_func_change:1;
839 uint32_t input_csc_change:1;
840 uint32_t coeff_reduction_change:1;
841 uint32_t output_tf_change:1;
842 uint32_t pixel_format_change:1;
843 uint32_t plane_size_change:1;
844 uint32_t gamut_remap_change:1;
847 uint32_t new_plane:1;
848 uint32_t bpp_change:1;
849 uint32_t gamma_change:1;
850 uint32_t bandwidth_change:1;
851 uint32_t clock_change:1;
852 uint32_t stereo_format_change:1;
853 uint32_t full_update:1;
859 struct dc_plane_state {
860 struct dc_plane_address address;
861 struct dc_plane_flip_time time;
862 bool triplebuffer_flips;
863 struct scaling_taps scaling_quality;
864 struct rect src_rect;
865 struct rect dst_rect;
866 struct rect clip_rect;
868 struct plane_size plane_size;
869 union dc_tiling_info tiling_info;
871 struct dc_plane_dcc_param dcc;
873 struct dc_gamma *gamma_correction;
874 struct dc_transfer_func *in_transfer_func;
875 struct dc_bias_and_scale *bias_and_scale;
876 struct dc_csc_transform input_csc_color_matrix;
877 struct fixed31_32 coeff_reduction_factor;
878 struct fixed31_32 hdr_mult;
879 struct colorspace_transform gamut_remap_matrix;
881 // TODO: No longer used, remove
882 struct dc_hdr_static_metadata hdr_static_ctx;
884 enum dc_color_space color_space;
886 struct dc_3dlut *lut3d_func;
887 struct dc_transfer_func *in_shaper_func;
888 struct dc_transfer_func *blend_tf;
890 #if defined(CONFIG_DRM_AMD_DC_DCN)
891 struct dc_transfer_func *gamcor_tf;
893 enum surface_pixel_format format;
894 enum dc_rotation_angle rotation;
895 enum plane_stereo_format stereo_format;
897 bool is_tiling_rotated;
898 bool per_pixel_alpha;
900 int global_alpha_value;
903 bool horizontal_mirror;
906 union surface_update_flags update_flags;
907 bool flip_int_enabled;
908 bool skip_manual_trigger;
910 /* private to DC core */
911 struct dc_plane_status status;
912 struct dc_context *ctx;
914 /* HACK: Workaround for forcing full reprogramming under some conditions */
915 bool force_full_update;
917 /* private to dc_surface.c */
918 enum dc_irq_source irq_source;
919 struct kref refcount;
922 struct dc_plane_info {
923 struct plane_size plane_size;
924 union dc_tiling_info tiling_info;
925 struct dc_plane_dcc_param dcc;
926 enum surface_pixel_format format;
927 enum dc_rotation_angle rotation;
928 enum plane_stereo_format stereo_format;
929 enum dc_color_space color_space;
930 bool horizontal_mirror;
932 bool per_pixel_alpha;
934 int global_alpha_value;
935 bool input_csc_enabled;
939 struct dc_scaling_info {
940 struct rect src_rect;
941 struct rect dst_rect;
942 struct rect clip_rect;
943 struct scaling_taps scaling_quality;
946 struct dc_surface_update {
947 struct dc_plane_state *surface;
949 /* isr safe update parameters. null means no updates */
950 const struct dc_flip_addrs *flip_addr;
951 const struct dc_plane_info *plane_info;
952 const struct dc_scaling_info *scaling_info;
953 struct fixed31_32 hdr_mult;
954 /* following updates require alloc/sleep/spin that is not isr safe,
955 * null means no updates
957 const struct dc_gamma *gamma;
958 const struct dc_transfer_func *in_transfer_func;
960 const struct dc_csc_transform *input_csc_color_matrix;
961 const struct fixed31_32 *coeff_reduction_factor;
962 const struct dc_transfer_func *func_shaper;
963 const struct dc_3dlut *lut3d_func;
964 const struct dc_transfer_func *blend_tf;
965 const struct colorspace_transform *gamut_remap_matrix;
969 * Create a new surface with default parameters;
971 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
972 const struct dc_plane_status *dc_plane_get_status(
973 const struct dc_plane_state *plane_state);
975 void dc_plane_state_retain(struct dc_plane_state *plane_state);
976 void dc_plane_state_release(struct dc_plane_state *plane_state);
978 void dc_gamma_retain(struct dc_gamma *dc_gamma);
979 void dc_gamma_release(struct dc_gamma **dc_gamma);
980 struct dc_gamma *dc_create_gamma(void);
982 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
983 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
984 struct dc_transfer_func *dc_create_transfer_func(void);
986 struct dc_3dlut *dc_create_3dlut_func(void);
987 void dc_3dlut_func_release(struct dc_3dlut *lut);
988 void dc_3dlut_func_retain(struct dc_3dlut *lut);
990 * This structure holds a surface address. There could be multiple addresses
991 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
992 * as frame durations and DCC format can also be set.
994 struct dc_flip_addrs {
995 struct dc_plane_address address;
996 unsigned int flip_timestamp_in_us;
998 /* TODO: add flip duration for FreeSync */
999 bool triplebuffer_flips;
1002 void dc_post_update_surfaces_to_stream(
1005 #include "dc_stream.h"
1008 * Structure to store surface/stream associations for validation
1010 struct dc_validation_set {
1011 struct dc_stream_state *stream;
1012 struct dc_plane_state *plane_states[MAX_SURFACES];
1013 uint8_t plane_count;
1016 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1017 const struct dc_sink *sink,
1018 struct dc_crtc_timing *crtc_timing);
1020 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1022 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1024 bool dc_set_generic_gpio_for_stereo(bool enable,
1025 struct gpio_service *gpio_service);
1028 * fast_validate: we return after determining if we can support the new state,
1029 * but before we populate the programming info
1031 enum dc_status dc_validate_global_state(
1033 struct dc_state *new_ctx,
1034 bool fast_validate);
1037 void dc_resource_state_construct(
1038 const struct dc *dc,
1039 struct dc_state *dst_ctx);
1041 #if defined(CONFIG_DRM_AMD_DC_DCN)
1042 bool dc_acquire_release_mpc_3dlut(
1043 struct dc *dc, bool acquire,
1044 struct dc_stream_state *stream,
1045 struct dc_3dlut **lut,
1046 struct dc_transfer_func **shaper);
1049 void dc_resource_state_copy_construct(
1050 const struct dc_state *src_ctx,
1051 struct dc_state *dst_ctx);
1053 void dc_resource_state_copy_construct_current(
1054 const struct dc *dc,
1055 struct dc_state *dst_ctx);
1057 void dc_resource_state_destruct(struct dc_state *context);
1059 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1062 * TODO update to make it about validation sets
1063 * Set up streams and links associated to drive sinks
1064 * The streams parameter is an absolute set of all active streams.
1067 * Phy, Encoder, Timing Generator are programmed and enabled.
1068 * New streams are enabled with blank stream; no memory read.
1070 bool dc_commit_state(struct dc *dc, struct dc_state *context);
1072 struct dc_state *dc_create_state(struct dc *dc);
1073 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1074 void dc_retain_state(struct dc_state *context);
1075 void dc_release_state(struct dc_state *context);
1077 /*******************************************************************************
1079 ******************************************************************************/
1082 union dpcd_rev dpcd_rev;
1083 union max_lane_count max_ln_count;
1084 union max_down_spread max_down_spread;
1085 union dprx_feature dprx_feature;
1087 /* valid only for eDP v1.4 or higher*/
1088 uint8_t edp_supported_link_rates_count;
1089 enum dc_link_rate edp_supported_link_rates[8];
1091 /* dongle type (DP converter, CV smart dongle) */
1092 enum display_dongle_type dongle_type;
1093 /* branch device or sink device */
1095 /* Dongle's downstream count. */
1096 union sink_count sink_count;
1097 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1098 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1099 struct dc_dongle_caps dongle_caps;
1101 uint32_t sink_dev_id;
1102 int8_t sink_dev_id_str[6];
1103 int8_t sink_hw_revision;
1104 int8_t sink_fw_revision[2];
1106 uint32_t branch_dev_id;
1107 int8_t branch_dev_name[6];
1108 int8_t branch_hw_revision;
1109 int8_t branch_fw_revision[2];
1111 bool allow_invalid_MSA_timing_param;
1112 bool panel_mode_edp;
1113 bool dpcd_display_control_capable;
1114 bool ext_receiver_cap_field_present;
1115 bool dynamic_backlight_capable_edp;
1116 union dpcd_fec_capability fec_cap;
1117 struct dpcd_dsc_capabilities dsc_caps;
1118 struct dc_lttpr_caps lttpr_caps;
1119 struct psr_caps psr_caps;
1123 union dpcd_sink_ext_caps {
1125 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1126 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1128 uint8_t sdr_aux_backlight_control : 1;
1129 uint8_t hdr_aux_backlight_control : 1;
1130 uint8_t reserved_1 : 2;
1132 uint8_t reserved : 3;
1137 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1138 union hdcp_rx_caps {
1143 uint8_t repeater : 1;
1144 uint8_t hdcp_capable : 1;
1145 uint8_t reserved : 6;
1153 uint8_t HDCP_CAPABLE:1;
1161 union hdcp_rx_caps rx_caps;
1162 union hdcp_bcaps bcaps;
1166 #include "dc_link.h"
1168 #if defined(CONFIG_DRM_AMD_DC_DCN)
1169 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1172 /*******************************************************************************
1173 * Sink Interfaces - A sink corresponds to a display output device
1174 ******************************************************************************/
1176 struct dc_container_id {
1177 // 128bit GUID in binary form
1178 unsigned char guid[16];
1179 // 8 byte port ID -> ELD.PortID
1180 unsigned int portId[2];
1181 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1182 unsigned short manufacturerName;
1183 // 2 byte product code -> ELD.ProductCode
1184 unsigned short productCode;
1188 struct dc_sink_dsc_caps {
1189 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1190 // 'false' if they are sink's DSC caps
1191 bool is_virtual_dpcd_dsc;
1192 struct dsc_dec_dpcd_caps dsc_dec_caps;
1195 struct dc_sink_fec_caps {
1196 bool is_rx_fec_supported;
1197 bool is_topology_fec_supported;
1201 * The sink structure contains EDID and other display device properties
1204 enum signal_type sink_signal;
1205 struct dc_edid dc_edid; /* raw edid */
1206 struct dc_edid_caps edid_caps; /* parse display caps */
1207 struct dc_container_id *dc_container_id;
1208 uint32_t dongle_max_pix_clk;
1210 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1211 bool converter_disable_audio;
1213 struct dc_sink_dsc_caps dsc_caps;
1214 struct dc_sink_fec_caps fec_caps;
1216 bool is_vsc_sdp_colorimetry_supported;
1218 /* private to DC core */
1219 struct dc_link *link;
1220 struct dc_context *ctx;
1224 /* private to dc_sink.c */
1225 // refcount must be the last member in dc_sink, since we want the
1226 // sink structure to be logically cloneable up to (but not including)
1228 struct kref refcount;
1231 void dc_sink_retain(struct dc_sink *sink);
1232 void dc_sink_release(struct dc_sink *sink);
1234 struct dc_sink_init_data {
1235 enum signal_type sink_signal;
1236 struct dc_link *link;
1237 uint32_t dongle_max_pix_clk;
1238 bool converter_disable_audio;
1241 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1243 /* Newer interfaces */
1245 struct dc_plane_address address;
1246 struct dc_cursor_attributes attributes;
1250 /*******************************************************************************
1251 * Interrupt interfaces
1252 ******************************************************************************/
1253 enum dc_irq_source dc_interrupt_to_irq_source(
1257 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1258 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1259 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1260 struct dc *dc, uint32_t link_index);
1262 /*******************************************************************************
1264 ******************************************************************************/
1266 void dc_set_power_state(
1268 enum dc_acpi_cm_power_state power_state);
1269 void dc_resume(struct dc *dc);
1271 void dc_power_down_on_boot(struct dc *dc);
1273 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1277 enum hdcp_message_status dc_process_hdcp_msg(
1278 enum signal_type signal,
1279 struct dc_link *link,
1280 struct hdcp_protection_message *message_info);
1282 bool dc_is_dmcu_initialized(struct dc *dc);
1284 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1285 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1286 #if defined(CONFIG_DRM_AMD_DC_DCN)
1288 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1289 struct dc_cursor_attributes *cursor_attr);
1291 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1294 * blank all streams, and set min and max memory clock to
1295 * lowest and highest DPM level, respectively
1297 void dc_unlock_memory_clock_frequency(struct dc *dc);
1300 * set min memory clock to the min required for current mode,
1301 * max to maxDPM, and unblank streams
1303 void dc_lock_memory_clock_frequency(struct dc *dc);
1305 /* cleanup on driver unload */
1306 void dc_hardware_release(struct dc *dc);
1310 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1312 bool dc_enable_dmub_notifications(struct dc *dc);
1314 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1315 uint32_t link_index,
1316 struct aux_payload *payload);
1318 /*******************************************************************************
1320 ******************************************************************************/
1323 /*******************************************************************************
1324 * Disable acc mode Interfaces
1325 ******************************************************************************/
1326 void dc_disable_accelerated_mode(struct dc *dc);
1328 #endif /* DC_INTERFACE_H_ */