2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #if defined(CONFIG_DRM_AMD_DC_HDCP)
33 #include "hdcp_types.h"
35 #include "gpio_types.h"
36 #include "link_service_types.h"
37 #include "grph_object_ctrl_defs.h"
38 #include <inc/hw/opp.h>
40 #include "inc/hw_sequencer.h"
41 #include "inc/compressor.h"
42 #include "inc/hw/dmcu.h"
43 #include "dml/display_mode_lib.h"
45 /* forward declaration */
47 struct set_config_cmd_payload;
48 struct dmub_notification;
50 #define DC_VER "3.2.167"
52 #define MAX_SURFACES 3
55 #define MAX_SINKS_PER_LINK 4
56 #define MIN_VIEWPORT_SIZE 12
59 /*******************************************************************************
60 * Display Core Interfaces
61 ******************************************************************************/
64 struct dmcu_version dmcu_version;
67 enum dp_protocol_version {
72 DC_PLANE_TYPE_INVALID,
73 DC_PLANE_TYPE_DCE_RGB,
74 DC_PLANE_TYPE_DCE_UNDERLAY,
75 DC_PLANE_TYPE_DCN_UNIVERSAL,
78 // Sizes defined as multiples of 64KB
89 enum dc_plane_type type;
90 uint32_t blends_with_above : 1;
91 uint32_t blends_with_below : 1;
92 uint32_t per_pixel_alpha : 1;
94 uint32_t argb8888 : 1;
99 } pixel_format_support;
100 // max upscaling factor x1000
101 // upscaling factors are always >= 1
102 // for example, 1080p -> 8K is 4.0, or 4000 raw value
107 } max_upscale_factor;
108 // max downscale factor x1000
109 // downscale factors are always <= 1
110 // for example, 8K -> 1080p is 0.25, or 250 raw value
115 } max_downscale_factor;
116 // minimal width/height
121 // Color management caps (DPP and MPC)
122 struct rom_curve_caps {
125 uint16_t gamma2_2 : 1;
130 struct dpp_color_caps {
131 uint16_t dcn_arch : 1; // all DCE generations treated the same
132 // input lut is different than most LUTs, just plain 256-entry lookup
133 uint16_t input_lut_shared : 1; // shared with DGAM
135 uint16_t dgam_ram : 1;
136 uint16_t post_csc : 1; // before gamut remap
137 uint16_t gamma_corr : 1;
139 // hdr_mult and gamut remap always available in DPP (in that order)
140 // 3d lut implies shaper LUT,
141 // it may be shared with MPC - check MPC:shared_3d_lut flag
142 uint16_t hw_3d_lut : 1;
143 uint16_t ogam_ram : 1; // blnd gam
145 uint16_t dgam_rom_for_yuv : 1;
146 struct rom_curve_caps dgam_rom_caps;
147 struct rom_curve_caps ogam_rom_caps;
150 struct mpc_color_caps {
151 uint16_t gamut_remap : 1;
152 uint16_t ogam_ram : 1;
154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
157 struct rom_curve_caps ogam_rom_caps;
160 struct dc_color_caps {
161 struct dpp_color_caps dpp;
162 struct mpc_color_caps mpc;
166 uint32_t max_streams;
169 uint32_t max_slave_planes;
170 uint32_t max_slave_yuv_planes;
171 uint32_t max_slave_rgb_planes;
173 uint32_t max_downscale_ratio;
174 uint32_t i2c_speed_in_khz;
175 uint32_t i2c_speed_in_khz_hdcp;
176 uint32_t dmdata_alloc_size;
177 unsigned int max_cursor_size;
178 unsigned int max_video_width;
179 unsigned int min_horizontal_blanking_period;
180 int linear_pitch_alignment;
181 bool dcc_const_color;
185 bool post_blend_color_processing;
186 bool force_dp_tps4_for_cp2520;
187 bool disable_dp_clk_share;
188 bool psp_setup_panel_mode;
189 bool extended_aux_timeout_support;
191 uint32_t num_of_internal_disp;
192 enum dp_protocol_version max_dp_protocol_version;
193 unsigned int mall_size_per_mem_channel;
194 unsigned int mall_size_total;
195 unsigned int cursor_cache_size;
196 struct dc_plane_cap planes[MAX_PLANES];
197 struct dc_color_caps color;
198 #if defined(CONFIG_DRM_AMD_DC_DCN)
200 bool hdmi_frl_pcon_support;
202 bool edp_dsc_support;
203 bool vbios_lttpr_aware;
204 bool vbios_lttpr_enable;
208 bool no_connect_phy_config;
210 bool skip_clock_update;
211 bool lt_early_cr_pattern;
214 struct dc_dcc_surface_param {
215 struct dc_size surface_size;
216 enum surface_pixel_format format;
217 enum swizzle_mode_values swizzle_mode;
218 enum dc_scan_direction scan;
221 struct dc_dcc_setting {
222 unsigned int max_compressed_blk_size;
223 unsigned int max_uncompressed_blk_size;
224 bool independent_64b_blks;
225 #if defined(CONFIG_DRM_AMD_DC_DCN)
226 //These bitfields to be used starting with DCN
228 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
229 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN
230 uint32_t dcc_256_128_128 : 1; //available starting with DCN
231 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
236 struct dc_surface_dcc_cap {
239 struct dc_dcc_setting rgb;
243 struct dc_dcc_setting luma;
244 struct dc_dcc_setting chroma;
249 bool const_color_support;
252 struct dc_static_screen_params {
259 unsigned int num_frames;
263 /* Surface update type is used by dc_update_surfaces_and_stream
264 * The update type is determined at the very beginning of the function based
265 * on parameters passed in and decides how much programming (or updating) is
266 * going to be done during the call.
268 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
269 * logical calculations or hardware register programming. This update MUST be
270 * ISR safe on windows. Currently fast update will only be used to flip surface
273 * UPDATE_TYPE_MED is used for slower updates which require significant hw
274 * re-programming however do not affect bandwidth consumption or clock
275 * requirements. At present, this is the level at which front end updates
276 * that do not require us to run bw_calcs happen. These are in/out transfer func
277 * updates, viewport offset changes, recout size changes and pixel depth changes.
278 * This update can be done at ISR, but we want to minimize how often this happens.
280 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
281 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
282 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
283 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
284 * a full update. This cannot be done at ISR level and should be a rare event.
285 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
286 * underscan we don't expect to see this call at all.
289 enum surface_update_type {
290 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
291 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
292 UPDATE_TYPE_FULL, /* may need to shuffle resources */
295 /* Forward declaration*/
297 struct dc_plane_state;
301 struct dc_cap_funcs {
302 bool (*get_dcc_compression_cap)(const struct dc *dc,
303 const struct dc_dcc_surface_param *input,
304 struct dc_surface_dcc_cap *output);
307 struct link_training_settings;
309 #if defined(CONFIG_DRM_AMD_DC_DCN)
310 union allow_lttpr_non_transparent_mode {
318 /* Structure to hold configuration flags set by dm at dc creation. */
321 bool disable_disp_pll_sharing;
323 bool disable_fractional_pwm;
324 bool allow_seamless_boot_optimization;
325 bool power_down_display_on_boot;
326 bool edp_not_connected;
327 bool edp_no_power_sequencing;
330 #if defined(CONFIG_DRM_AMD_DC_DCN)
331 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
333 bool allow_lttpr_non_transparent_mode;
335 bool multi_mon_pp_mclk_switch;
338 bool enable_windowed_mpo_odm;
339 bool allow_edp_hotplug_detection;
340 #if defined(CONFIG_DRM_AMD_DC_DCN)
341 bool clamp_min_dcfclk;
343 uint64_t vblank_alignment_dto_params;
344 uint8_t vblank_alignment_max_frame_time_diff;
345 bool is_asymmetric_memory;
346 bool is_single_rank_dimm;
349 enum visual_confirm {
350 VISUAL_CONFIRM_DISABLE = 0,
351 VISUAL_CONFIRM_SURFACE = 1,
352 VISUAL_CONFIRM_HDR = 2,
353 VISUAL_CONFIRM_MPCTREE = 4,
354 VISUAL_CONFIRM_PSR = 5,
355 VISUAL_CONFIRM_SWIZZLE = 9,
358 enum dc_psr_power_opts {
359 psr_power_opt_invalid = 0x0,
360 psr_power_opt_smu_opt_static_screen = 0x1,
361 psr_power_opt_z10_static_screen = 0x10,
367 DCC_HALF_REQ_DISALBE = 2,
370 enum pipe_split_policy {
371 MPC_SPLIT_DYNAMIC = 0,
373 MPC_SPLIT_AVOID_MULT_DISP = 2,
376 enum wm_report_mode {
377 WM_REPORT_DEFAULT = 0,
378 WM_REPORT_OVERRIDE = 1,
381 dtm_level_p0 = 0,/*highest voltage*/
385 dtm_level_p4,/*when active_display_count = 0*/
389 DCN_PWR_STATE_UNKNOWN = -1,
390 DCN_PWR_STATE_MISSION_MODE = 0,
391 DCN_PWR_STATE_LOW_POWER = 3,
394 #if defined(CONFIG_DRM_AMD_DC_DCN)
395 enum dcn_zstate_support_state {
396 DCN_ZSTATE_SUPPORT_UNKNOWN,
397 DCN_ZSTATE_SUPPORT_ALLOW,
398 DCN_ZSTATE_SUPPORT_DISALLOW,
402 * For any clocks that may differ per pipe
403 * only the max is stored in this structure
407 int actual_dispclk_khz;
409 int actual_dppclk_khz;
410 int disp_dpp_voltage_level_khz;
413 int dcfclk_deep_sleep_khz;
417 bool p_state_change_support;
418 #if defined(CONFIG_DRM_AMD_DC_DCN)
419 enum dcn_zstate_support_state zstate_support;
422 enum dcn_pwr_state pwr_state;
424 * Elements below are not compared for the purposes of
425 * optimization required
427 bool prev_p_state_change_support;
428 enum dtm_pstate dtm_level;
429 int max_supported_dppclk_khz;
430 int max_supported_dispclk_khz;
431 int bw_dppclk_khz; /*a copy of dppclk_khz*/
435 struct dc_bw_validation_profile {
438 unsigned long long total_ticks;
439 unsigned long long voltage_level_ticks;
440 unsigned long long watermark_ticks;
441 unsigned long long rq_dlg_ticks;
443 unsigned long long total_count;
444 unsigned long long skip_fast_count;
445 unsigned long long skip_pass_count;
446 unsigned long long skip_fail_count;
449 #define BW_VAL_TRACE_SETUP() \
450 unsigned long long end_tick = 0; \
451 unsigned long long voltage_level_tick = 0; \
452 unsigned long long watermark_tick = 0; \
453 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
454 dm_get_timestamp(dc->ctx) : 0
456 #define BW_VAL_TRACE_COUNT() \
457 if (dc->debug.bw_val_profile.enable) \
458 dc->debug.bw_val_profile.total_count++
460 #define BW_VAL_TRACE_SKIP(status) \
461 if (dc->debug.bw_val_profile.enable) { \
462 if (!voltage_level_tick) \
463 voltage_level_tick = dm_get_timestamp(dc->ctx); \
464 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
467 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
468 if (dc->debug.bw_val_profile.enable) \
469 voltage_level_tick = dm_get_timestamp(dc->ctx)
471 #define BW_VAL_TRACE_END_WATERMARKS() \
472 if (dc->debug.bw_val_profile.enable) \
473 watermark_tick = dm_get_timestamp(dc->ctx)
475 #define BW_VAL_TRACE_FINISH() \
476 if (dc->debug.bw_val_profile.enable) { \
477 end_tick = dm_get_timestamp(dc->ctx); \
478 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
479 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
480 if (watermark_tick) { \
481 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
482 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
486 union mem_low_power_enable_options {
501 union root_clock_optimization_options {
513 uint32_t reserved: 22;
518 union dpia_debug_options {
520 uint32_t disable_dpia:1;
521 uint32_t force_non_lttpr:1;
522 uint32_t extend_aux_rd_interval:1;
523 uint32_t disable_mst_dsc_work_around:1;
524 uint32_t hpd_delay_in_ms:12;
525 uint32_t reserved:16;
530 struct dc_debug_data {
531 uint32_t ltFailCount;
532 uint32_t i2cErrorCount;
533 uint32_t auxErrorCount;
536 struct dc_phy_addr_space_config {
549 uint64_t page_table_start_addr;
550 uint64_t page_table_end_addr;
551 uint64_t page_table_base_addr;
552 bool base_addr_is_mc_addr;
557 uint64_t page_table_default_page_addr;
560 struct dc_virtual_addr_space_config {
561 uint64_t page_table_base_addr;
562 uint64_t page_table_start_addr;
563 uint64_t page_table_end_addr;
564 uint32_t page_table_block_size_in_bytes;
565 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
568 struct dc_bounding_box_overrides {
570 int sr_enter_plus_exit_time_ns;
571 int urgent_latency_ns;
572 int percent_of_ideal_drambw;
573 int dram_clock_change_latency_ns;
574 int dummy_clock_change_latency_ns;
575 /* This forces a hard min on the DCFCLK we use
576 * for DML. Unlike the debug option for forcing
577 * DCFCLK, this override affects watermark calculations
583 struct resource_pool;
586 struct dc_debug_options {
587 bool native422_support;
589 enum visual_confirm visual_confirm;
590 int visual_confirm_rect_height;
597 bool validation_trace;
598 bool bandwidth_calcs_trace;
599 int max_downscale_src_width;
601 /* stutter efficiency related */
602 bool disable_stutter;
604 enum dcc_option disable_dcc;
605 enum pipe_split_policy pipe_split_policy;
606 bool force_single_disp_pipe_split;
607 bool voltage_align_fclk;
608 bool disable_min_fclk;
610 bool disable_dfs_bypass;
611 bool disable_dpp_power_gate;
612 bool disable_hubp_power_gate;
613 bool disable_dsc_power_gate;
614 int dsc_min_slice_height_override;
615 int dsc_bpp_increment_div;
616 bool disable_pplib_wm_range;
617 enum wm_report_mode pplib_wm_report_mode;
618 unsigned int min_disp_clk_khz;
619 unsigned int min_dpp_clk_khz;
620 unsigned int min_dram_clk_khz;
621 int sr_exit_time_dpm0_ns;
622 int sr_enter_plus_exit_time_dpm0_ns;
624 int sr_enter_plus_exit_time_ns;
625 int urgent_latency_ns;
626 uint32_t underflow_assert_delay_us;
627 int percent_of_ideal_drambw;
628 int dram_clock_change_latency_ns;
629 bool optimized_watermark;
631 bool disable_pplib_clock_request;
632 bool disable_clock_gate;
633 bool disable_mem_low_power;
634 #if defined(CONFIG_DRM_AMD_DC_DCN)
639 bool force_abm_enable;
640 bool disable_stereo_support;
642 bool performance_trace;
643 bool az_endpoint_mute_only;
644 bool always_use_regamma;
645 bool recovery_enabled;
646 bool avoid_vbios_exec_table;
647 bool scl_reset_length10;
649 bool skip_detection_link_training;
650 uint32_t edid_read_retry_times;
651 bool remove_disconnect_edp;
652 unsigned int force_odm_combine; //bit vector based on otg inst
653 #if defined(CONFIG_DRM_AMD_DC_DCN)
654 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
657 unsigned int force_fclk_khz;
659 bool dmub_offload_enabled;
660 bool dmcub_emulation;
661 #if defined(CONFIG_DRM_AMD_DC_DCN)
662 bool disable_idle_power_optimizations;
663 unsigned int mall_size_override;
664 unsigned int mall_additional_timer_percent;
665 bool mall_error_as_fatal;
667 bool dmub_command_table; /* for testing only */
668 struct dc_bw_validation_profile bw_val_profile;
670 bool disable_48mhz_pwrdwn;
671 /* This forces a hard min on the DCFCLK requested to SMU/PP
672 * watermarks are not affected.
674 unsigned int force_min_dcfclk_mhz;
675 #if defined(CONFIG_DRM_AMD_DC_DCN)
678 bool disable_timing_sync;
680 int force_clock_mode;/*every mode change.*/
682 bool disable_dram_clock_change_vactive_support;
683 bool validate_dml_output;
684 bool enable_dmcub_surface_flip;
685 bool usbc_combo_phy_reset_wa;
686 bool disable_dsc_edp;
687 unsigned int force_dsc_edp_policy;
688 bool enable_dram_clock_change_one_display_vactive;
689 #if defined(CONFIG_DRM_AMD_DC_DCN)
690 /* TODO - remove once tested */
692 bool set_mst_en_for_sst;
694 bool force_dp2_lt_fallback_method;
696 union mem_low_power_enable_options enable_mem_low_power;
697 union root_clock_optimization_options root_clock_optimization;
698 bool hpo_optimization;
699 bool force_vblank_alignment;
701 /* Enable dmub aux for legacy ddc */
702 bool enable_dmub_aux_for_legacy_ddc;
703 bool optimize_edp_link_rate; /* eDP ILR */
704 /* FEC/PSR1 sequence enable delay in 100us */
705 uint8_t fec_enable_delay_in100us;
706 bool enable_driver_sequence_debug;
707 enum det_size crb_alloc_policy;
708 int crb_alloc_policy_min_disp_count;
709 #if defined(CONFIG_DRM_AMD_DC_DCN)
711 bool enable_sw_cntl_psr;
712 union dpia_debug_options dpia_debug;
714 bool apply_vendor_specific_lttpr_wa;
717 struct gpu_info_soc_bounding_box_v1_0;
719 struct dc_debug_options debug;
720 struct dc_versions versions;
722 struct dc_cap_funcs cap_funcs;
723 struct dc_config config;
724 struct dc_bounding_box_overrides bb_overrides;
725 struct dc_bug_wa work_arounds;
726 struct dc_context *ctx;
727 struct dc_phy_addr_space_config vm_pa_config;
730 struct dc_link *links[MAX_PIPES * 2];
732 struct dc_state *current_state;
733 struct resource_pool *res_pool;
735 struct clk_mgr *clk_mgr;
737 /* Display Engine Clock levels */
738 struct dm_pp_clock_levels sclk_lvls;
740 /* Inputs into BW and WM calculations. */
741 struct bw_calcs_dceip *bw_dceip;
742 struct bw_calcs_vbios *bw_vbios;
743 #ifdef CONFIG_DRM_AMD_DC_DCN
744 struct dcn_soc_bounding_box *dcn_soc;
745 struct dcn_ip_params *dcn_ip;
746 struct display_mode_lib dml;
750 struct hw_sequencer_funcs hwss;
751 struct dce_hwseq *hwseq;
753 /* Require to optimize clocks and bandwidth for added/removed planes */
754 bool optimized_required;
755 bool wm_optimized_required;
756 #if defined(CONFIG_DRM_AMD_DC_DCN)
757 bool idle_optimizations_allowed;
759 #if defined(CONFIG_DRM_AMD_DC_DCN)
760 bool enable_c20_dtm_b0;
763 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
766 struct compressor *fbc_compressor;
768 struct dc_debug_data debug_data;
769 struct dpcd_vendor_signature vendor_signature;
771 const char *build_id;
772 struct vm_helper *vm_helper;
775 enum frame_buffer_mode {
776 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
777 FRAME_BUFFER_MODE_ZFB_ONLY,
778 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
781 struct dchub_init_data {
782 int64_t zfb_phys_addr_base;
783 int64_t zfb_mc_base_addr;
784 uint64_t zfb_size_in_byte;
785 enum frame_buffer_mode fb_mode;
786 bool dchub_initialzied;
787 bool dchub_info_valid;
790 struct dc_init_data {
791 struct hw_asic_id asic_id;
792 void *driver; /* ctx */
793 struct cgs_device *cgs_device;
794 struct dc_bounding_box_overrides bb_overrides;
796 int num_virtual_links;
798 * If 'vbios_override' not NULL, it will be called instead
799 * of the real VBIOS. Intended use is Diagnostics on FPGA.
801 struct dc_bios *vbios_override;
802 enum dce_environment dce_environment;
804 struct dmub_offload_funcs *dmub_if;
805 struct dc_reg_helper_state *dmub_offload;
807 struct dc_config flags;
810 struct dpcd_vendor_signature vendor_signature;
811 #if defined(CONFIG_DRM_AMD_DC_DCN)
812 bool force_smu_not_present;
816 struct dc_callback_init {
817 #ifdef CONFIG_DRM_AMD_DC_HDCP
818 struct cp_psp cp_psp;
824 struct dc *dc_create(const struct dc_init_data *init_params);
825 void dc_hardware_init(struct dc *dc);
827 int dc_get_vmid_use_vector(struct dc *dc);
828 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
829 /* Returns the number of vmids supported */
830 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
831 void dc_init_callbacks(struct dc *dc,
832 const struct dc_callback_init *init_params);
833 void dc_deinit_callbacks(struct dc *dc);
834 void dc_destroy(struct dc **dc);
836 /*******************************************************************************
838 ******************************************************************************/
841 TRANSFER_FUNC_POINTS = 1025
844 struct dc_hdr_static_metadata {
845 /* display chromaticities and white point in units of 0.00001 */
846 unsigned int chromaticity_green_x;
847 unsigned int chromaticity_green_y;
848 unsigned int chromaticity_blue_x;
849 unsigned int chromaticity_blue_y;
850 unsigned int chromaticity_red_x;
851 unsigned int chromaticity_red_y;
852 unsigned int chromaticity_white_point_x;
853 unsigned int chromaticity_white_point_y;
855 uint32_t min_luminance;
856 uint32_t max_luminance;
857 uint32_t maximum_content_light_level;
858 uint32_t maximum_frame_average_light_level;
861 enum dc_transfer_func_type {
863 TF_TYPE_DISTRIBUTED_POINTS,
868 struct dc_transfer_func_distributed_points {
869 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
870 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
871 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
873 uint16_t end_exponent;
874 uint16_t x_point_at_y1_red;
875 uint16_t x_point_at_y1_green;
876 uint16_t x_point_at_y1_blue;
879 enum dc_transfer_func_predefined {
880 TRANSFER_FUNCTION_SRGB,
881 TRANSFER_FUNCTION_BT709,
882 TRANSFER_FUNCTION_PQ,
883 TRANSFER_FUNCTION_LINEAR,
884 TRANSFER_FUNCTION_UNITY,
885 TRANSFER_FUNCTION_HLG,
886 TRANSFER_FUNCTION_HLG12,
887 TRANSFER_FUNCTION_GAMMA22,
888 TRANSFER_FUNCTION_GAMMA24,
889 TRANSFER_FUNCTION_GAMMA26
893 struct dc_transfer_func {
894 struct kref refcount;
895 enum dc_transfer_func_type type;
896 enum dc_transfer_func_predefined tf;
897 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
898 uint32_t sdr_ref_white_level;
900 struct pwl_params pwl;
901 struct dc_transfer_func_distributed_points tf_pts;
906 union dc_3dlut_state {
908 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
909 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
910 uint32_t rmu_mux_num:3; /*index of mux to use*/
911 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
912 uint32_t mpc_rmu1_mux:4;
913 uint32_t mpc_rmu2_mux:4;
914 uint32_t reserved:15;
921 struct kref refcount;
922 struct tetrahedral_params lut_3d;
923 struct fixed31_32 hdr_multiplier;
924 union dc_3dlut_state state;
927 * This structure is filled in by dc_surface_get_status and contains
928 * the last requested address and the currently active address so the called
929 * can determine if there are any outstanding flips
931 struct dc_plane_status {
932 struct dc_plane_address requested_address;
933 struct dc_plane_address current_address;
934 bool is_flip_pending;
938 union surface_update_flags {
941 uint32_t addr_update:1;
943 uint32_t dcc_change:1;
944 uint32_t color_space_change:1;
945 uint32_t horizontal_mirror_change:1;
946 uint32_t per_pixel_alpha_change:1;
947 uint32_t global_alpha_change:1;
949 uint32_t rotation_change:1;
950 uint32_t swizzle_change:1;
951 uint32_t scaling_change:1;
952 uint32_t position_change:1;
953 uint32_t in_transfer_func_change:1;
954 uint32_t input_csc_change:1;
955 uint32_t coeff_reduction_change:1;
956 uint32_t output_tf_change:1;
957 uint32_t pixel_format_change:1;
958 uint32_t plane_size_change:1;
959 uint32_t gamut_remap_change:1;
962 uint32_t new_plane:1;
963 uint32_t bpp_change:1;
964 uint32_t gamma_change:1;
965 uint32_t bandwidth_change:1;
966 uint32_t clock_change:1;
967 uint32_t stereo_format_change:1;
969 uint32_t full_update:1;
975 struct dc_plane_state {
976 struct dc_plane_address address;
977 struct dc_plane_flip_time time;
978 bool triplebuffer_flips;
979 struct scaling_taps scaling_quality;
980 struct rect src_rect;
981 struct rect dst_rect;
982 struct rect clip_rect;
984 struct plane_size plane_size;
985 union dc_tiling_info tiling_info;
987 struct dc_plane_dcc_param dcc;
989 struct dc_gamma *gamma_correction;
990 struct dc_transfer_func *in_transfer_func;
991 struct dc_bias_and_scale *bias_and_scale;
992 struct dc_csc_transform input_csc_color_matrix;
993 struct fixed31_32 coeff_reduction_factor;
994 struct fixed31_32 hdr_mult;
995 struct colorspace_transform gamut_remap_matrix;
997 // TODO: No longer used, remove
998 struct dc_hdr_static_metadata hdr_static_ctx;
1000 enum dc_color_space color_space;
1002 struct dc_3dlut *lut3d_func;
1003 struct dc_transfer_func *in_shaper_func;
1004 struct dc_transfer_func *blend_tf;
1006 #if defined(CONFIG_DRM_AMD_DC_DCN)
1007 struct dc_transfer_func *gamcor_tf;
1009 enum surface_pixel_format format;
1010 enum dc_rotation_angle rotation;
1011 enum plane_stereo_format stereo_format;
1013 bool is_tiling_rotated;
1014 bool per_pixel_alpha;
1016 int global_alpha_value;
1018 bool flip_immediate;
1019 bool horizontal_mirror;
1022 union surface_update_flags update_flags;
1023 bool flip_int_enabled;
1024 bool skip_manual_trigger;
1026 /* private to DC core */
1027 struct dc_plane_status status;
1028 struct dc_context *ctx;
1030 /* HACK: Workaround for forcing full reprogramming under some conditions */
1031 bool force_full_update;
1033 /* private to dc_surface.c */
1034 enum dc_irq_source irq_source;
1035 struct kref refcount;
1038 struct dc_plane_info {
1039 struct plane_size plane_size;
1040 union dc_tiling_info tiling_info;
1041 struct dc_plane_dcc_param dcc;
1042 enum surface_pixel_format format;
1043 enum dc_rotation_angle rotation;
1044 enum plane_stereo_format stereo_format;
1045 enum dc_color_space color_space;
1046 bool horizontal_mirror;
1048 bool per_pixel_alpha;
1050 int global_alpha_value;
1051 bool input_csc_enabled;
1055 struct dc_scaling_info {
1056 struct rect src_rect;
1057 struct rect dst_rect;
1058 struct rect clip_rect;
1059 struct scaling_taps scaling_quality;
1062 struct dc_surface_update {
1063 struct dc_plane_state *surface;
1065 /* isr safe update parameters. null means no updates */
1066 const struct dc_flip_addrs *flip_addr;
1067 const struct dc_plane_info *plane_info;
1068 const struct dc_scaling_info *scaling_info;
1069 struct fixed31_32 hdr_mult;
1070 /* following updates require alloc/sleep/spin that is not isr safe,
1071 * null means no updates
1073 const struct dc_gamma *gamma;
1074 const struct dc_transfer_func *in_transfer_func;
1076 const struct dc_csc_transform *input_csc_color_matrix;
1077 const struct fixed31_32 *coeff_reduction_factor;
1078 const struct dc_transfer_func *func_shaper;
1079 const struct dc_3dlut *lut3d_func;
1080 const struct dc_transfer_func *blend_tf;
1081 const struct colorspace_transform *gamut_remap_matrix;
1085 * Create a new surface with default parameters;
1087 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1088 const struct dc_plane_status *dc_plane_get_status(
1089 const struct dc_plane_state *plane_state);
1091 void dc_plane_state_retain(struct dc_plane_state *plane_state);
1092 void dc_plane_state_release(struct dc_plane_state *plane_state);
1094 void dc_gamma_retain(struct dc_gamma *dc_gamma);
1095 void dc_gamma_release(struct dc_gamma **dc_gamma);
1096 struct dc_gamma *dc_create_gamma(void);
1098 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1099 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1100 struct dc_transfer_func *dc_create_transfer_func(void);
1102 struct dc_3dlut *dc_create_3dlut_func(void);
1103 void dc_3dlut_func_release(struct dc_3dlut *lut);
1104 void dc_3dlut_func_retain(struct dc_3dlut *lut);
1106 * This structure holds a surface address. There could be multiple addresses
1107 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
1108 * as frame durations and DCC format can also be set.
1110 struct dc_flip_addrs {
1111 struct dc_plane_address address;
1112 unsigned int flip_timestamp_in_us;
1113 bool flip_immediate;
1114 /* TODO: add flip duration for FreeSync */
1115 bool triplebuffer_flips;
1118 void dc_post_update_surfaces_to_stream(
1121 #include "dc_stream.h"
1124 * Structure to store surface/stream associations for validation
1126 struct dc_validation_set {
1127 struct dc_stream_state *stream;
1128 struct dc_plane_state *plane_states[MAX_SURFACES];
1129 uint8_t plane_count;
1132 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1133 const struct dc_sink *sink,
1134 struct dc_crtc_timing *crtc_timing);
1136 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1138 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1140 bool dc_set_generic_gpio_for_stereo(bool enable,
1141 struct gpio_service *gpio_service);
1144 * fast_validate: we return after determining if we can support the new state,
1145 * but before we populate the programming info
1147 enum dc_status dc_validate_global_state(
1149 struct dc_state *new_ctx,
1150 bool fast_validate);
1153 void dc_resource_state_construct(
1154 const struct dc *dc,
1155 struct dc_state *dst_ctx);
1157 #if defined(CONFIG_DRM_AMD_DC_DCN)
1158 bool dc_acquire_release_mpc_3dlut(
1159 struct dc *dc, bool acquire,
1160 struct dc_stream_state *stream,
1161 struct dc_3dlut **lut,
1162 struct dc_transfer_func **shaper);
1165 void dc_resource_state_copy_construct(
1166 const struct dc_state *src_ctx,
1167 struct dc_state *dst_ctx);
1169 void dc_resource_state_copy_construct_current(
1170 const struct dc *dc,
1171 struct dc_state *dst_ctx);
1173 void dc_resource_state_destruct(struct dc_state *context);
1175 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1178 * TODO update to make it about validation sets
1179 * Set up streams and links associated to drive sinks
1180 * The streams parameter is an absolute set of all active streams.
1183 * Phy, Encoder, Timing Generator are programmed and enabled.
1184 * New streams are enabled with blank stream; no memory read.
1186 bool dc_commit_state(struct dc *dc, struct dc_state *context);
1188 struct dc_state *dc_create_state(struct dc *dc);
1189 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1190 void dc_retain_state(struct dc_state *context);
1191 void dc_release_state(struct dc_state *context);
1193 /*******************************************************************************
1195 ******************************************************************************/
1198 union dpcd_rev dpcd_rev;
1199 union max_lane_count max_ln_count;
1200 union max_down_spread max_down_spread;
1201 union dprx_feature dprx_feature;
1203 /* valid only for eDP v1.4 or higher*/
1204 uint8_t edp_supported_link_rates_count;
1205 enum dc_link_rate edp_supported_link_rates[8];
1207 /* dongle type (DP converter, CV smart dongle) */
1208 enum display_dongle_type dongle_type;
1209 /* branch device or sink device */
1211 /* Dongle's downstream count. */
1212 union sink_count sink_count;
1213 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1214 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1215 struct dc_dongle_caps dongle_caps;
1217 uint32_t sink_dev_id;
1218 int8_t sink_dev_id_str[6];
1219 int8_t sink_hw_revision;
1220 int8_t sink_fw_revision[2];
1222 uint32_t branch_dev_id;
1223 int8_t branch_dev_name[6];
1224 int8_t branch_hw_revision;
1225 int8_t branch_fw_revision[2];
1227 bool allow_invalid_MSA_timing_param;
1228 bool panel_mode_edp;
1229 bool dpcd_display_control_capable;
1230 bool ext_receiver_cap_field_present;
1231 bool dynamic_backlight_capable_edp;
1232 union dpcd_fec_capability fec_cap;
1233 struct dpcd_dsc_capabilities dsc_caps;
1234 struct dc_lttpr_caps lttpr_caps;
1235 struct psr_caps psr_caps;
1236 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1238 #if defined(CONFIG_DRM_AMD_DC_DCN)
1239 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
1240 union dp_main_line_channel_coding_cap channel_coding_cap;
1241 union dp_sink_video_fallback_formats fallback_formats;
1242 union dp_fec_capability1 fec_cap1;
1246 union dpcd_sink_ext_caps {
1248 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1249 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1251 uint8_t sdr_aux_backlight_control : 1;
1252 uint8_t hdr_aux_backlight_control : 1;
1253 uint8_t reserved_1 : 2;
1255 uint8_t reserved : 3;
1260 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1261 union hdcp_rx_caps {
1266 uint8_t repeater : 1;
1267 uint8_t hdcp_capable : 1;
1268 uint8_t reserved : 6;
1276 uint8_t HDCP_CAPABLE:1;
1284 union hdcp_rx_caps rx_caps;
1285 union hdcp_bcaps bcaps;
1289 #include "dc_link.h"
1291 #if defined(CONFIG_DRM_AMD_DC_DCN)
1292 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1295 /*******************************************************************************
1296 * Sink Interfaces - A sink corresponds to a display output device
1297 ******************************************************************************/
1299 struct dc_container_id {
1300 // 128bit GUID in binary form
1301 unsigned char guid[16];
1302 // 8 byte port ID -> ELD.PortID
1303 unsigned int portId[2];
1304 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1305 unsigned short manufacturerName;
1306 // 2 byte product code -> ELD.ProductCode
1307 unsigned short productCode;
1311 struct dc_sink_dsc_caps {
1312 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1313 // 'false' if they are sink's DSC caps
1314 bool is_virtual_dpcd_dsc;
1315 #if defined(CONFIG_DRM_AMD_DC_DCN)
1316 // 'true' if MST topology supports DSC passthrough for sink
1317 // 'false' if MST topology does not support DSC passthrough
1318 bool is_dsc_passthrough_supported;
1320 struct dsc_dec_dpcd_caps dsc_dec_caps;
1323 struct dc_sink_fec_caps {
1324 bool is_rx_fec_supported;
1325 bool is_topology_fec_supported;
1329 * The sink structure contains EDID and other display device properties
1332 enum signal_type sink_signal;
1333 struct dc_edid dc_edid; /* raw edid */
1334 struct dc_edid_caps edid_caps; /* parse display caps */
1335 struct dc_container_id *dc_container_id;
1336 uint32_t dongle_max_pix_clk;
1338 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1339 bool converter_disable_audio;
1341 struct dc_sink_dsc_caps dsc_caps;
1342 struct dc_sink_fec_caps fec_caps;
1344 bool is_vsc_sdp_colorimetry_supported;
1346 /* private to DC core */
1347 struct dc_link *link;
1348 struct dc_context *ctx;
1352 /* private to dc_sink.c */
1353 // refcount must be the last member in dc_sink, since we want the
1354 // sink structure to be logically cloneable up to (but not including)
1356 struct kref refcount;
1359 void dc_sink_retain(struct dc_sink *sink);
1360 void dc_sink_release(struct dc_sink *sink);
1362 struct dc_sink_init_data {
1363 enum signal_type sink_signal;
1364 struct dc_link *link;
1365 uint32_t dongle_max_pix_clk;
1366 bool converter_disable_audio;
1369 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1371 /* Newer interfaces */
1373 struct dc_plane_address address;
1374 struct dc_cursor_attributes attributes;
1378 /*******************************************************************************
1379 * Interrupt interfaces
1380 ******************************************************************************/
1381 enum dc_irq_source dc_interrupt_to_irq_source(
1385 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1386 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1387 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1388 struct dc *dc, uint32_t link_index);
1390 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
1392 /*******************************************************************************
1394 ******************************************************************************/
1396 void dc_set_power_state(
1398 enum dc_acpi_cm_power_state power_state);
1399 void dc_resume(struct dc *dc);
1401 void dc_power_down_on_boot(struct dc *dc);
1403 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1407 enum hdcp_message_status dc_process_hdcp_msg(
1408 enum signal_type signal,
1409 struct dc_link *link,
1410 struct hdcp_protection_message *message_info);
1412 bool dc_is_dmcu_initialized(struct dc *dc);
1414 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1415 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1416 #if defined(CONFIG_DRM_AMD_DC_DCN)
1418 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1419 struct dc_cursor_attributes *cursor_attr);
1421 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1424 * blank all streams, and set min and max memory clock to
1425 * lowest and highest DPM level, respectively
1427 void dc_unlock_memory_clock_frequency(struct dc *dc);
1430 * set min memory clock to the min required for current mode,
1431 * max to maxDPM, and unblank streams
1433 void dc_lock_memory_clock_frequency(struct dc *dc);
1435 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
1436 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
1438 /* cleanup on driver unload */
1439 void dc_hardware_release(struct dc *dc);
1443 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1444 #if defined(CONFIG_DRM_AMD_DC_DCN)
1445 void dc_z10_restore(const struct dc *dc);
1446 void dc_z10_save_init(struct dc *dc);
1449 bool dc_enable_dmub_notifications(struct dc *dc);
1451 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1452 uint32_t link_index,
1453 struct aux_payload *payload);
1455 /* Get dc link index from dpia port index */
1456 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
1457 uint8_t dpia_port_index);
1459 bool dc_process_dmub_set_config_async(struct dc *dc,
1460 uint32_t link_index,
1461 struct set_config_cmd_payload *payload,
1462 struct dmub_notification *notify);
1464 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
1465 uint32_t link_index,
1466 uint8_t mst_alloc_slots,
1467 uint8_t *mst_slots_in_use);
1469 /*******************************************************************************
1471 ******************************************************************************/
1474 /*******************************************************************************
1475 * Disable acc mode Interfaces
1476 ******************************************************************************/
1477 void dc_disable_accelerated_mode(struct dc *dc);
1479 #endif /* DC_INTERFACE_H_ */