drivers/gpu/drm/amd/display/dc/core/dc_stream.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "basics/dc_common.h"
  31 #include "dc.h"
  32 #include "core_types.h"
  33 #include "resource.h"
  34 #include "ipp.h"
  35 #include "timing_generator.h"
  36
  37 #define DC_LOGGER dc->ctx->logger
  38
  39 /*******************************************************************************
  40  * Private functions
  41  ******************************************************************************/
  42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
  43 {
  44         if (sink->sink_signal == SIGNAL_TYPE_NONE)
  45                 stream->signal = stream->link->connector_signal;
  46         else
  47                 stream->signal = sink->sink_signal;
  48
  49         if (dc_is_dvi_signal(stream->signal)) {
  50                 if (stream->ctx->dc->caps.dual_link_dvi &&
  51                         (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
  52                         sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
  53                         stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
  54                 else
  55                         stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
  56         }
  57 }
  58
  59 static bool dc_stream_construct(struct dc_stream_state *stream,
  60         struct dc_sink *dc_sink_data)
  61 {
  62         uint32_t i = 0;
  63
  64         stream->sink = dc_sink_data;
  65         dc_sink_retain(dc_sink_data);
  66
  67         stream->ctx = dc_sink_data->ctx;
  68         stream->link = dc_sink_data->link;
  69         stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
  70         stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
  71         stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
  72         stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
  73
  74         /* Copy audio modes */
  75         /* TODO - Remove this translation */
  76         for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
  77         {
  78                 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
  79                 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
  80                 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
  81                 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
  82         }
  83         stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
  84         stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
  85         stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
  86         memmove(
  87                 stream->audio_info.display_name,
  88                 dc_sink_data->edid_caps.display_name,
  89                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
  90         stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
  91         stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
  92         stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
  93
  94         if (dc_sink_data->dc_container_id != NULL) {
  95                 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
  96
  97                 stream->audio_info.port_id[0] = dc_container_id->portId[0];
  98                 stream->audio_info.port_id[1] = dc_container_id->portId[1];
  99         } else {
 100                 /* TODO - WindowDM has implemented,
 101                 other DMs need Unhardcode port_id */
 102                 stream->audio_info.port_id[0] = 0x5558859e;
 103                 stream->audio_info.port_id[1] = 0xd989449;
 104         }
 105
 106         /* EDID CAP translation for HDMI 2.0 */
 107         stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
 108
 109         memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
 110         stream->timing.dsc_cfg.num_slices_h = 0;
 111         stream->timing.dsc_cfg.num_slices_v = 0;
 112         stream->timing.dsc_cfg.bits_per_pixel = 128;
 113         stream->timing.dsc_cfg.block_pred_enable = 1;
 114         stream->timing.dsc_cfg.linebuf_depth = 9;
 115         stream->timing.dsc_cfg.version_minor = 2;
 116         stream->timing.dsc_cfg.ycbcr422_simple = 0;
 117
 118         update_stream_signal(stream, dc_sink_data);
 119
 120         stream->out_transfer_func = dc_create_transfer_func();
 121         if (stream->out_transfer_func == NULL) {
 122                 dc_sink_release(dc_sink_data);
 123                 return false;
 124         }
 125         stream->out_transfer_func->type = TF_TYPE_BYPASS;
 126
 127         stream->stream_id = stream->ctx->dc_stream_id_count;
 128         stream->ctx->dc_stream_id_count++;
 129
 130         return true;
 131 }
 132
 133 static void dc_stream_destruct(struct dc_stream_state *stream)
 134 {
 135         dc_sink_release(stream->sink);
 136         if (stream->out_transfer_func != NULL) {
 137                 dc_transfer_func_release(stream->out_transfer_func);
 138                 stream->out_transfer_func = NULL;
 139         }
 140 }
 141
 142 void dc_stream_retain(struct dc_stream_state *stream)
 143 {
 144         kref_get(&stream->refcount);
 145 }
 146
 147 static void dc_stream_free(struct kref *kref)
 148 {
 149         struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
 150
 151         dc_stream_destruct(stream);
 152         kfree(stream);
 153 }
 154
 155 void dc_stream_release(struct dc_stream_state *stream)
 156 {
 157         if (stream != NULL) {
 158                 kref_put(&stream->refcount, dc_stream_free);
 159         }
 160 }
 161
 162 struct dc_stream_state *dc_create_stream_for_sink(
 163                 struct dc_sink *sink)
 164 {
 165         struct dc_stream_state *stream;
 166
 167         if (sink == NULL)
 168                 return NULL;
 169
 170         stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
 171         if (stream == NULL)
 172                 goto alloc_fail;
 173
 174         if (dc_stream_construct(stream, sink) == false)
 175                 goto construct_fail;
 176
 177         kref_init(&stream->refcount);
 178
 179         return stream;
 180
 181 construct_fail:
 182         kfree(stream);
 183
 184 alloc_fail:
 185         return NULL;
 186 }
 187
 188 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
 189 {
 190         struct dc_stream_state *new_stream;
 191
 192         new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
 193         if (!new_stream)
 194                 return NULL;
 195
 196         if (new_stream->sink)
 197                 dc_sink_retain(new_stream->sink);
 198
 199         if (new_stream->out_transfer_func)
 200                 dc_transfer_func_retain(new_stream->out_transfer_func);
 201
 202         new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
 203         new_stream->ctx->dc_stream_id_count++;
 204
 205         kref_init(&new_stream->refcount);
 206
 207         return new_stream;
 208 }
 209
 210 /**
 211  * dc_stream_get_status_from_state - Get stream status from given dc state
 212  * @state: DC state to find the stream status in
 213  * @stream: The stream to get the stream status for
 214  *
 215  * The given stream is expected to exist in the given dc state. Otherwise, NULL
 216  * will be returned.
 217  */
 218 struct dc_stream_status *dc_stream_get_status_from_state(
 219         struct dc_state *state,
 220         struct dc_stream_state *stream)
 221 {
 222         uint8_t i;
 223
 224         for (i = 0; i < state->stream_count; i++) {
 225                 if (stream == state->streams[i])
 226                         return &state->stream_status[i];
 227         }
 228
 229         return NULL;
 230 }
 231
 232 /**
 233  * dc_stream_get_status() - Get current stream status of the given stream state
 234  * @stream: The stream to get the stream status for.
 235  *
 236  * The given stream is expected to exist in dc->current_state. Otherwise, NULL
 237  * will be returned.
 238  */
 239 struct dc_stream_status *dc_stream_get_status(
 240         struct dc_stream_state *stream)
 241 {
 242         struct dc *dc = stream->ctx->dc;
 243         return dc_stream_get_status_from_state(dc->current_state, stream);
 244 }
 245
 246 #ifndef TRIM_FSFT
 247 /*
 248  * dc_optimize_timing_for_fsft() - dc to optimize timing
 249  */
 250 bool dc_optimize_timing_for_fsft(
 251         struct dc_stream_state *pStream,
 252         unsigned int max_input_rate_in_khz)
 253 {
 254         struct dc  *dc;
 255
 256         dc = pStream->ctx->dc;
 257
 258         return (dc->hwss.optimize_timing_for_fsft &&
 259                 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));
 260 }
 261 #endif
 262
 263 /*
 264  * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
 265  */
 266 bool dc_stream_set_cursor_attributes(
 267         struct dc_stream_state *stream,
 268         const struct dc_cursor_attributes *attributes)
 269 {
 270         int i;
 271         struct dc  *dc;
 272         struct resource_context *res_ctx;
 273         struct pipe_ctx *pipe_to_program = NULL;
 274 #if defined(CONFIG_DRM_AMD_DC_DCN)
 275         bool reset_idle_optimizations = false;
 276 #endif
 277
 278         if (NULL == stream) {
 279                 dm_error("DC: dc_stream is NULL!\n");
 280                 return false;
 281         }
 282         if (NULL == attributes) {
 283                 dm_error("DC: attributes is NULL!\n");
 284                 return false;
 285         }
 286
 287         if (attributes->address.quad_part == 0) {
 288                 dm_output_to_console("DC: Cursor address is 0!\n");
 289                 return false;
 290         }
 291
 292         dc = stream->ctx->dc;
 293         res_ctx = &dc->current_state->res_ctx;
 294         stream->cursor_attributes = *attributes;
 295
 296 #if defined(CONFIG_DRM_AMD_DC_DCN)
 297         dc_z10_restore(dc);
 298         /* disable idle optimizations while updating cursor */
 299         if (dc->idle_optimizations_allowed) {
 300                 dc_allow_idle_optimizations(dc, false);
 301                 reset_idle_optimizations = true;
 302         }
 303
 304 #endif
 305
 306         for (i = 0; i < MAX_PIPES; i++) {
 307                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 308
 309                 if (pipe_ctx->stream != stream)
 310                         continue;
 311
 312                 if (!pipe_to_program) {
 313                         pipe_to_program = pipe_ctx;
 314                         dc->hwss.cursor_lock(dc, pipe_to_program, true);
 315                 }
 316
 317                 dc->hwss.set_cursor_attribute(pipe_ctx);
 318                 if (dc->hwss.set_cursor_sdr_white_level)
 319                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
 320         }
 321
 322         if (pipe_to_program)
 323                 dc->hwss.cursor_lock(dc, pipe_to_program, false);
 324
 325 #if defined(CONFIG_DRM_AMD_DC_DCN)
 326         /* re-enable idle optimizations if necessary */
 327         if (reset_idle_optimizations)
 328                 dc_allow_idle_optimizations(dc, true);
 329
 330 #endif
 331         return true;
 332 }
 333
 334 bool dc_stream_set_cursor_position(
 335         struct dc_stream_state *stream,
 336         const struct dc_cursor_position *position)
 337 {
 338         int i;
 339         struct dc  *dc;
 340         struct resource_context *res_ctx;
 341         struct pipe_ctx *pipe_to_program = NULL;
 342 #if defined(CONFIG_DRM_AMD_DC_DCN)
 343         bool reset_idle_optimizations = false;
 344 #endif
 345
 346         if (NULL == stream) {
 347                 dm_error("DC: dc_stream is NULL!\n");
 348                 return false;
 349         }
 350
 351         if (NULL == position) {
 352                 dm_error("DC: cursor position is NULL!\n");
 353                 return false;
 354         }
 355
 356         dc = stream->ctx->dc;
 357         res_ctx = &dc->current_state->res_ctx;
 358 #if defined(CONFIG_DRM_AMD_DC_DCN)
 359         dc_z10_restore(dc);
 360
 361         /* disable idle optimizations if enabling cursor */
 362         if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
 363                 dc_allow_idle_optimizations(dc, false);
 364                 reset_idle_optimizations = true;
 365         }
 366
 367 #endif
 368         stream->cursor_position = *position;
 369
 370         for (i = 0; i < MAX_PIPES; i++) {
 371                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 372
 373                 if (pipe_ctx->stream != stream ||
 374                                 (!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||
 375                                 !pipe_ctx->plane_state ||
 376                                 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
 377                                 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
 378                         continue;
 379
 380                 if (!pipe_to_program) {
 381                         pipe_to_program = pipe_ctx;
 382                         dc->hwss.cursor_lock(dc, pipe_to_program, true);
 383                 }
 384
 385                 dc->hwss.set_cursor_position(pipe_ctx);
 386         }
 387
 388         if (pipe_to_program)
 389                 dc->hwss.cursor_lock(dc, pipe_to_program, false);
 390
 391 #if defined(CONFIG_DRM_AMD_DC_DCN)
 392         /* re-enable idle optimizations if necessary */
 393         if (reset_idle_optimizations)
 394                 dc_allow_idle_optimizations(dc, true);
 395
 396 #endif
 397         return true;
 398 }
 399
 400 bool dc_stream_add_writeback(struct dc *dc,
 401                 struct dc_stream_state *stream,
 402                 struct dc_writeback_info *wb_info)
 403 {
 404         bool isDrc = false;
 405         int i = 0;
 406         struct dwbc *dwb;
 407
 408         if (stream == NULL) {
 409                 dm_error("DC: dc_stream is NULL!\n");
 410                 return false;
 411         }
 412
 413         if (wb_info == NULL) {
 414                 dm_error("DC: dc_writeback_info is NULL!\n");
 415                 return false;
 416         }
 417
 418         if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
 419                 dm_error("DC: writeback pipe is invalid!\n");
 420                 return false;
 421         }
 422
 423         wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
 424
 425         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 426         dwb->dwb_is_drc = false;
 427
 428         /* recalculate and apply DML parameters */
 429
 430         for (i = 0; i < stream->num_wb_info; i++) {
 431                 /*dynamic update*/
 432                 if (stream->writeback_info[i].wb_enabled &&
 433                         stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
 434                         stream->writeback_info[i] = *wb_info;
 435                         isDrc = true;
 436                 }
 437         }
 438
 439         if (!isDrc) {
 440                 stream->writeback_info[stream->num_wb_info++] = *wb_info;
 441         }
 442
 443         if (dc->hwss.enable_writeback) {
 444                 struct dc_stream_status *stream_status = dc_stream_get_status(stream);
 445                 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 446                 dwb->otg_inst = stream_status->primary_otg_inst;
 447         }
 448         if (IS_DIAG_DC(dc->ctx->dce_environment)) {
 449                 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
 450                         dm_error("DC: update_bandwidth failed!\n");
 451                         return false;
 452                 }
 453
 454                 /* enable writeback */
 455                 if (dc->hwss.enable_writeback) {
 456                         struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 457
 458                         if (dwb->funcs->is_enabled(dwb)) {
 459                                 /* writeback pipe already enabled, only need to update */
 460                                 dc->hwss.update_writeback(dc, wb_info, dc->current_state);
 461                         } else {
 462                                 /* Enable writeback pipe from scratch*/
 463                                 dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
 464                         }
 465                 }
 466         }
 467         return true;
 468 }
 469
 470 bool dc_stream_remove_writeback(struct dc *dc,
 471                 struct dc_stream_state *stream,
 472                 uint32_t dwb_pipe_inst)
 473 {
 474         int i = 0, j = 0;
 475         if (stream == NULL) {
 476                 dm_error("DC: dc_stream is NULL!\n");
 477                 return false;
 478         }
 479
 480         if (dwb_pipe_inst >= MAX_DWB_PIPES) {
 481                 dm_error("DC: writeback pipe is invalid!\n");
 482                 return false;
 483         }
 484
 485 //      stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
 486         for (i = 0; i < stream->num_wb_info; i++) {
 487                 /*dynamic update*/
 488                 if (stream->writeback_info[i].wb_enabled &&
 489                         stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
 490                         stream->writeback_info[i].wb_enabled = false;
 491                 }
 492         }
 493
 494         /* remove writeback info for disabled writeback pipes from stream */
 495         for (i = 0, j = 0; i < stream->num_wb_info; i++) {
 496                 if (stream->writeback_info[i].wb_enabled) {
 497                         if (i != j)
 498                                 /* trim the array */
 499                                 stream->writeback_info[j] = stream->writeback_info[i];
 500                         j++;
 501                 }
 502         }
 503         stream->num_wb_info = j;
 504
 505         if (IS_DIAG_DC(dc->ctx->dce_environment)) {
 506                 /* recalculate and apply DML parameters */
 507                 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
 508                         dm_error("DC: update_bandwidth failed!\n");
 509                         return false;
 510                 }
 511
 512                 /* disable writeback */
 513                 if (dc->hwss.disable_writeback)
 514                         dc->hwss.disable_writeback(dc, dwb_pipe_inst);
 515         }
 516         return true;
 517 }
 518
 519 bool dc_stream_warmup_writeback(struct dc *dc,
 520                 int num_dwb,
 521                 struct dc_writeback_info *wb_info)
 522 {
 523         if (dc->hwss.mmhubbub_warmup)
 524                 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
 525         else
 526                 return false;
 527 }
 528 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
 529 {
 530         uint8_t i;
 531         struct dc  *dc = stream->ctx->dc;
 532         struct resource_context *res_ctx =
 533                 &dc->current_state->res_ctx;
 534
 535         for (i = 0; i < MAX_PIPES; i++) {
 536                 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
 537
 538                 if (res_ctx->pipe_ctx[i].stream != stream)
 539                         continue;
 540
 541                 return tg->funcs->get_frame_count(tg);
 542         }
 543
 544         return 0;
 545 }
 546
 547 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
 548                 const uint8_t *custom_sdp_message,
 549                 unsigned int sdp_message_size)
 550 {
 551         int i;
 552         struct dc  *dc;
 553         struct resource_context *res_ctx;
 554
 555         if (stream == NULL) {
 556                 dm_error("DC: dc_stream is NULL!\n");
 557                 return false;
 558         }
 559
 560         dc = stream->ctx->dc;
 561         res_ctx = &dc->current_state->res_ctx;
 562
 563         for (i = 0; i < MAX_PIPES; i++) {
 564                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 565
 566                 if (pipe_ctx->stream != stream)
 567                         continue;
 568
 569                 if (dc->hwss.send_immediate_sdp_message != NULL)
 570                         dc->hwss.send_immediate_sdp_message(pipe_ctx,
 571                                                                 custom_sdp_message,
 572                                                                 sdp_message_size);
 573                 else
 574                         DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
 575                         __func__);
 576
 577         }
 578
 579         return true;
 580 }
 581
 582 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
 583                                   uint32_t *v_blank_start,
 584                                   uint32_t *v_blank_end,
 585                                   uint32_t *h_position,
 586                                   uint32_t *v_position)
 587 {
 588         uint8_t i;
 589         bool ret = false;
 590         struct dc  *dc = stream->ctx->dc;
 591         struct resource_context *res_ctx =
 592                 &dc->current_state->res_ctx;
 593
 594         for (i = 0; i < MAX_PIPES; i++) {
 595                 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
 596
 597                 if (res_ctx->pipe_ctx[i].stream != stream)
 598                         continue;
 599
 600                 tg->funcs->get_scanoutpos(tg,
 601                                           v_blank_start,
 602                                           v_blank_end,
 603                                           h_position,
 604                                           v_position);
 605
 606                 ret = true;
 607                 break;
 608         }
 609
 610         return ret;
 611 }
 612
 613 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
 614 {
 615         struct pipe_ctx *pipe = NULL;
 616         int i;
 617
 618         if (!dc->hwss.dmdata_status_done)
 619                 return false;
 620
 621         for (i = 0; i < MAX_PIPES; i++) {
 622                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 623                 if (pipe->stream == stream)
 624                         break;
 625         }
 626         /* Stream not found, by default we'll assume HUBP fetched dm data */
 627         if (i == MAX_PIPES)
 628                 return true;
 629
 630         return dc->hwss.dmdata_status_done(pipe);
 631 }
 632
 633 bool dc_stream_set_dynamic_metadata(struct dc *dc,
 634                 struct dc_stream_state *stream,
 635                 struct dc_dmdata_attributes *attr)
 636 {
 637         struct pipe_ctx *pipe_ctx = NULL;
 638         struct hubp *hubp;
 639         int i;
 640
 641         /* Dynamic metadata is only supported on HDMI or DP */
 642         if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
 643                 return false;
 644
 645         /* Check hardware support */
 646         if (!dc->hwss.program_dmdata_engine)
 647                 return false;
 648
 649         for (i = 0; i < MAX_PIPES; i++) {
 650                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 651                 if (pipe_ctx->stream == stream)
 652                         break;
 653         }
 654
 655         if (i == MAX_PIPES)
 656                 return false;
 657
 658         hubp = pipe_ctx->plane_res.hubp;
 659         if (hubp == NULL)
 660                 return false;
 661
 662         pipe_ctx->stream->dmdata_address = attr->address;
 663
 664         dc->hwss.program_dmdata_engine(pipe_ctx);
 665
 666         if (hubp->funcs->dmdata_set_attributes != NULL &&
 667                         pipe_ctx->stream->dmdata_address.quad_part != 0) {
 668                 hubp->funcs->dmdata_set_attributes(hubp, attr);
 669         }
 670
 671         return true;
 672 }
 673
 674 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
 675                 struct dc_state *state,
 676                 struct dc_stream_state *stream)
 677 {
 678         if (dc->res_pool->funcs->add_dsc_to_stream_resource) {
 679                 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);
 680         } else {
 681                 return DC_NO_DSC_RESOURCE;
 682         }
 683 }
 684
 685 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
 686 {
 687         DC_LOG_DC(
 688                         "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
 689                         stream,
 690                         stream->src.x,
 691                         stream->src.y,
 692                         stream->src.width,
 693                         stream->src.height,
 694                         stream->dst.x,
 695                         stream->dst.y,
 696                         stream->dst.width,
 697                         stream->dst.height,
 698                         stream->output_color_space);
 699         DC_LOG_DC(
 700                         "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
 701                         stream->timing.pix_clk_100hz / 10,
 702                         stream->timing.h_total,
 703                         stream->timing.v_total,
 704                         stream->timing.pixel_encoding,
 705                         stream->timing.display_color_depth);
 706         DC_LOG_DC(
 707                         "\tlink: %d\n",
 708                         stream->link->link_index);
 709 }
 710