2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include "dm_services.h"
30 #include "basics/dc_common.h"
32 #include "core_types.h"
35 #include "timing_generator.h"
37 #define DC_LOGGER dc->ctx->logger
39 /*******************************************************************************
41 ******************************************************************************/
42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
44 if (sink->sink_signal == SIGNAL_TYPE_NONE)
45 stream->signal = stream->link->connector_signal;
47 stream->signal = sink->sink_signal;
49 if (dc_is_dvi_signal(stream->signal)) {
50 if (stream->ctx->dc->caps.dual_link_dvi &&
51 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
52 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
53 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
55 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
59 static bool dc_stream_construct(struct dc_stream_state *stream,
60 struct dc_sink *dc_sink_data)
64 stream->sink = dc_sink_data;
65 dc_sink_retain(dc_sink_data);
67 stream->ctx = dc_sink_data->ctx;
68 stream->link = dc_sink_data->link;
69 stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
70 stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
71 stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
72 stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
74 /* Copy audio modes */
75 /* TODO - Remove this translation */
76 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
78 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
79 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
80 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
81 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
83 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
84 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
85 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
87 stream->audio_info.display_name,
88 dc_sink_data->edid_caps.display_name,
89 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
90 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
91 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
92 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
94 if (dc_sink_data->dc_container_id != NULL) {
95 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
97 stream->audio_info.port_id[0] = dc_container_id->portId[0];
98 stream->audio_info.port_id[1] = dc_container_id->portId[1];
100 /* TODO - WindowDM has implemented,
101 other DMs need Unhardcode port_id */
102 stream->audio_info.port_id[0] = 0x5558859e;
103 stream->audio_info.port_id[1] = 0xd989449;
106 /* EDID CAP translation for HDMI 2.0 */
107 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
109 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
110 stream->timing.dsc_cfg.num_slices_h = 0;
111 stream->timing.dsc_cfg.num_slices_v = 0;
112 stream->timing.dsc_cfg.bits_per_pixel = 128;
113 stream->timing.dsc_cfg.block_pred_enable = 1;
114 stream->timing.dsc_cfg.linebuf_depth = 9;
115 stream->timing.dsc_cfg.version_minor = 2;
116 stream->timing.dsc_cfg.ycbcr422_simple = 0;
118 update_stream_signal(stream, dc_sink_data);
120 stream->out_transfer_func = dc_create_transfer_func();
121 if (stream->out_transfer_func == NULL) {
122 dc_sink_release(dc_sink_data);
125 stream->out_transfer_func->type = TF_TYPE_BYPASS;
127 stream->stream_id = stream->ctx->dc_stream_id_count;
128 stream->ctx->dc_stream_id_count++;
133 static void dc_stream_destruct(struct dc_stream_state *stream)
135 dc_sink_release(stream->sink);
136 if (stream->out_transfer_func != NULL) {
137 dc_transfer_func_release(stream->out_transfer_func);
138 stream->out_transfer_func = NULL;
142 void dc_stream_retain(struct dc_stream_state *stream)
144 kref_get(&stream->refcount);
147 static void dc_stream_free(struct kref *kref)
149 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
151 dc_stream_destruct(stream);
155 void dc_stream_release(struct dc_stream_state *stream)
157 if (stream != NULL) {
158 kref_put(&stream->refcount, dc_stream_free);
162 struct dc_stream_state *dc_create_stream_for_sink(
163 struct dc_sink *sink)
165 struct dc_stream_state *stream;
170 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
174 if (dc_stream_construct(stream, sink) == false)
177 kref_init(&stream->refcount);
188 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
190 struct dc_stream_state *new_stream;
192 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
196 if (new_stream->sink)
197 dc_sink_retain(new_stream->sink);
199 if (new_stream->out_transfer_func)
200 dc_transfer_func_retain(new_stream->out_transfer_func);
202 new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
203 new_stream->ctx->dc_stream_id_count++;
205 kref_init(&new_stream->refcount);
211 * dc_stream_get_status_from_state - Get stream status from given dc state
212 * @state: DC state to find the stream status in
213 * @stream: The stream to get the stream status for
215 * The given stream is expected to exist in the given dc state. Otherwise, NULL
218 struct dc_stream_status *dc_stream_get_status_from_state(
219 struct dc_state *state,
220 struct dc_stream_state *stream)
224 for (i = 0; i < state->stream_count; i++) {
225 if (stream == state->streams[i])
226 return &state->stream_status[i];
233 * dc_stream_get_status() - Get current stream status of the given stream state
234 * @stream: The stream to get the stream status for.
236 * The given stream is expected to exist in dc->current_state. Otherwise, NULL
239 struct dc_stream_status *dc_stream_get_status(
240 struct dc_stream_state *stream)
242 struct dc *dc = stream->ctx->dc;
243 return dc_stream_get_status_from_state(dc->current_state, stream);
248 * dc_optimize_timing_for_fsft() - dc to optimize timing
250 bool dc_optimize_timing_for_fsft(
251 struct dc_stream_state *pStream,
252 unsigned int max_input_rate_in_khz)
256 dc = pStream->ctx->dc;
258 return (dc->hwss.optimize_timing_for_fsft &&
259 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));
264 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
266 bool dc_stream_set_cursor_attributes(
267 struct dc_stream_state *stream,
268 const struct dc_cursor_attributes *attributes)
272 struct resource_context *res_ctx;
273 struct pipe_ctx *pipe_to_program = NULL;
274 #if defined(CONFIG_DRM_AMD_DC_DCN)
275 bool reset_idle_optimizations = false;
278 if (NULL == stream) {
279 dm_error("DC: dc_stream is NULL!\n");
282 if (NULL == attributes) {
283 dm_error("DC: attributes is NULL!\n");
287 if (attributes->address.quad_part == 0) {
288 dm_output_to_console("DC: Cursor address is 0!\n");
292 dc = stream->ctx->dc;
293 res_ctx = &dc->current_state->res_ctx;
294 stream->cursor_attributes = *attributes;
296 #if defined(CONFIG_DRM_AMD_DC_DCN)
298 /* disable idle optimizations while updating cursor */
299 if (dc->idle_optimizations_allowed) {
300 dc_allow_idle_optimizations(dc, false);
301 reset_idle_optimizations = true;
306 for (i = 0; i < MAX_PIPES; i++) {
307 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
309 if (pipe_ctx->stream != stream)
312 if (!pipe_to_program) {
313 pipe_to_program = pipe_ctx;
314 dc->hwss.cursor_lock(dc, pipe_to_program, true);
317 dc->hwss.set_cursor_attribute(pipe_ctx);
318 if (dc->hwss.set_cursor_sdr_white_level)
319 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
323 dc->hwss.cursor_lock(dc, pipe_to_program, false);
325 #if defined(CONFIG_DRM_AMD_DC_DCN)
326 /* re-enable idle optimizations if necessary */
327 if (reset_idle_optimizations)
328 dc_allow_idle_optimizations(dc, true);
334 bool dc_stream_set_cursor_position(
335 struct dc_stream_state *stream,
336 const struct dc_cursor_position *position)
340 struct resource_context *res_ctx;
341 struct pipe_ctx *pipe_to_program = NULL;
342 #if defined(CONFIG_DRM_AMD_DC_DCN)
343 bool reset_idle_optimizations = false;
346 if (NULL == stream) {
347 dm_error("DC: dc_stream is NULL!\n");
351 if (NULL == position) {
352 dm_error("DC: cursor position is NULL!\n");
356 dc = stream->ctx->dc;
357 res_ctx = &dc->current_state->res_ctx;
358 #if defined(CONFIG_DRM_AMD_DC_DCN)
361 /* disable idle optimizations if enabling cursor */
362 if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
363 dc_allow_idle_optimizations(dc, false);
364 reset_idle_optimizations = true;
368 stream->cursor_position = *position;
370 for (i = 0; i < MAX_PIPES; i++) {
371 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
373 if (pipe_ctx->stream != stream ||
374 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
375 !pipe_ctx->plane_state ||
376 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
377 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
380 if (!pipe_to_program) {
381 pipe_to_program = pipe_ctx;
382 dc->hwss.cursor_lock(dc, pipe_to_program, true);
385 dc->hwss.set_cursor_position(pipe_ctx);
389 dc->hwss.cursor_lock(dc, pipe_to_program, false);
391 #if defined(CONFIG_DRM_AMD_DC_DCN)
392 /* re-enable idle optimizations if necessary */
393 if (reset_idle_optimizations)
394 dc_allow_idle_optimizations(dc, true);
400 bool dc_stream_add_writeback(struct dc *dc,
401 struct dc_stream_state *stream,
402 struct dc_writeback_info *wb_info)
408 if (stream == NULL) {
409 dm_error("DC: dc_stream is NULL!\n");
413 if (wb_info == NULL) {
414 dm_error("DC: dc_writeback_info is NULL!\n");
418 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
419 dm_error("DC: writeback pipe is invalid!\n");
423 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
425 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
426 dwb->dwb_is_drc = false;
428 /* recalculate and apply DML parameters */
430 for (i = 0; i < stream->num_wb_info; i++) {
432 if (stream->writeback_info[i].wb_enabled &&
433 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
434 stream->writeback_info[i] = *wb_info;
440 stream->writeback_info[stream->num_wb_info++] = *wb_info;
443 if (dc->hwss.enable_writeback) {
444 struct dc_stream_status *stream_status = dc_stream_get_status(stream);
445 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
446 dwb->otg_inst = stream_status->primary_otg_inst;
448 if (IS_DIAG_DC(dc->ctx->dce_environment)) {
449 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
450 dm_error("DC: update_bandwidth failed!\n");
454 /* enable writeback */
455 if (dc->hwss.enable_writeback) {
456 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
458 if (dwb->funcs->is_enabled(dwb)) {
459 /* writeback pipe already enabled, only need to update */
460 dc->hwss.update_writeback(dc, wb_info, dc->current_state);
462 /* Enable writeback pipe from scratch*/
463 dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
470 bool dc_stream_remove_writeback(struct dc *dc,
471 struct dc_stream_state *stream,
472 uint32_t dwb_pipe_inst)
475 if (stream == NULL) {
476 dm_error("DC: dc_stream is NULL!\n");
480 if (dwb_pipe_inst >= MAX_DWB_PIPES) {
481 dm_error("DC: writeback pipe is invalid!\n");
485 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
486 for (i = 0; i < stream->num_wb_info; i++) {
488 if (stream->writeback_info[i].wb_enabled &&
489 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
490 stream->writeback_info[i].wb_enabled = false;
494 /* remove writeback info for disabled writeback pipes from stream */
495 for (i = 0, j = 0; i < stream->num_wb_info; i++) {
496 if (stream->writeback_info[i].wb_enabled) {
499 stream->writeback_info[j] = stream->writeback_info[i];
503 stream->num_wb_info = j;
505 if (IS_DIAG_DC(dc->ctx->dce_environment)) {
506 /* recalculate and apply DML parameters */
507 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
508 dm_error("DC: update_bandwidth failed!\n");
512 /* disable writeback */
513 if (dc->hwss.disable_writeback)
514 dc->hwss.disable_writeback(dc, dwb_pipe_inst);
519 bool dc_stream_warmup_writeback(struct dc *dc,
521 struct dc_writeback_info *wb_info)
523 if (dc->hwss.mmhubbub_warmup)
524 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
528 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
531 struct dc *dc = stream->ctx->dc;
532 struct resource_context *res_ctx =
533 &dc->current_state->res_ctx;
535 for (i = 0; i < MAX_PIPES; i++) {
536 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
538 if (res_ctx->pipe_ctx[i].stream != stream)
541 return tg->funcs->get_frame_count(tg);
547 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
548 const uint8_t *custom_sdp_message,
549 unsigned int sdp_message_size)
553 struct resource_context *res_ctx;
555 if (stream == NULL) {
556 dm_error("DC: dc_stream is NULL!\n");
560 dc = stream->ctx->dc;
561 res_ctx = &dc->current_state->res_ctx;
563 for (i = 0; i < MAX_PIPES; i++) {
564 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
566 if (pipe_ctx->stream != stream)
569 if (dc->hwss.send_immediate_sdp_message != NULL)
570 dc->hwss.send_immediate_sdp_message(pipe_ctx,
574 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
582 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
583 uint32_t *v_blank_start,
584 uint32_t *v_blank_end,
585 uint32_t *h_position,
586 uint32_t *v_position)
590 struct dc *dc = stream->ctx->dc;
591 struct resource_context *res_ctx =
592 &dc->current_state->res_ctx;
594 for (i = 0; i < MAX_PIPES; i++) {
595 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
597 if (res_ctx->pipe_ctx[i].stream != stream)
600 tg->funcs->get_scanoutpos(tg,
613 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
615 struct pipe_ctx *pipe = NULL;
618 if (!dc->hwss.dmdata_status_done)
621 for (i = 0; i < MAX_PIPES; i++) {
622 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
623 if (pipe->stream == stream)
626 /* Stream not found, by default we'll assume HUBP fetched dm data */
630 return dc->hwss.dmdata_status_done(pipe);
633 bool dc_stream_set_dynamic_metadata(struct dc *dc,
634 struct dc_stream_state *stream,
635 struct dc_dmdata_attributes *attr)
637 struct pipe_ctx *pipe_ctx = NULL;
641 /* Dynamic metadata is only supported on HDMI or DP */
642 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
645 /* Check hardware support */
646 if (!dc->hwss.program_dmdata_engine)
649 for (i = 0; i < MAX_PIPES; i++) {
650 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
651 if (pipe_ctx->stream == stream)
658 hubp = pipe_ctx->plane_res.hubp;
662 pipe_ctx->stream->dmdata_address = attr->address;
664 dc->hwss.program_dmdata_engine(pipe_ctx);
666 if (hubp->funcs->dmdata_set_attributes != NULL &&
667 pipe_ctx->stream->dmdata_address.quad_part != 0) {
668 hubp->funcs->dmdata_set_attributes(hubp, attr);
674 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
675 struct dc_state *state,
676 struct dc_stream_state *stream)
678 if (dc->res_pool->funcs->add_dsc_to_stream_resource) {
679 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);
681 return DC_NO_DSC_RESOURCE;
685 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
688 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
698 stream->output_color_space);
700 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
701 stream->timing.pix_clk_100hz / 10,
702 stream->timing.h_total,
703 stream->timing.v_total,
704 stream->timing.pixel_encoding,
705 stream->timing.display_color_depth);
708 stream->link->link_index);