drivers/gpu/drm/amd/display/dc/core/dc_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "resource.h"
  31 #include "include/irq_service_interface.h"
  32 #include "link_encoder.h"
  33 #include "stream_encoder.h"
  34 #include "opp.h"
  35 #include "timing_generator.h"
  36 #include "transform.h"
  37 #include "dccg.h"
  38 #include "dchubbub.h"
  39 #include "dpp.h"
  40 #include "core_types.h"
  41 #include "set_mode_types.h"
  42 #include "virtual/virtual_stream_encoder.h"
  43 #include "dpcd_defs.h"
  44
  45 #if defined(CONFIG_DRM_AMD_DC_SI)
  46 #include "dce60/dce60_resource.h"
  47 #endif
  48 #include "dce80/dce80_resource.h"
  49 #include "dce100/dce100_resource.h"
  50 #include "dce110/dce110_resource.h"
  51 #include "dce112/dce112_resource.h"
  52 #include "dce120/dce120_resource.h"
  53 #if defined(CONFIG_DRM_AMD_DC_DCN)
  54 #include "dcn10/dcn10_resource.h"
  55 #include "dcn20/dcn20_resource.h"
  56 #include "dcn21/dcn21_resource.h"
  57 #endif
  58 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
  59 #include "../dcn30/dcn30_resource.h"
  60 #endif
  61
  62 #define DC_LOGGER_INIT(logger)
  63
  64 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
  65 {
  66         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
  67         switch (asic_id.chip_family) {
  68
  69 #if defined(CONFIG_DRM_AMD_DC_SI)
  70         case FAMILY_SI:
  71                 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
  72                     ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
  73                     ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
  74                         dc_version = DCE_VERSION_6_0;
  75                 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
  76                         dc_version = DCE_VERSION_6_4;
  77                 else
  78                         dc_version = DCE_VERSION_6_1;
  79                 break;
  80 #endif
  81         case FAMILY_CI:
  82                 dc_version = DCE_VERSION_8_0;
  83                 break;
  84         case FAMILY_KV:
  85                 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
  86                     ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
  87                     ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
  88                         dc_version = DCE_VERSION_8_3;
  89                 else
  90                         dc_version = DCE_VERSION_8_1;
  91                 break;
  92         case FAMILY_CZ:
  93                 dc_version = DCE_VERSION_11_0;
  94                 break;
  95
  96         case FAMILY_VI:
  97                 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
  98                                 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
  99                         dc_version = DCE_VERSION_10_0;
 100                         break;
 101                 }
 102                 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
 103                                 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
 104                                 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
 105                         dc_version = DCE_VERSION_11_2;
 106                 }
 107                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
 108                         dc_version = DCE_VERSION_11_22;
 109                 break;
 110         case FAMILY_AI:
 111                 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
 112                         dc_version = DCE_VERSION_12_1;
 113                 else
 114                         dc_version = DCE_VERSION_12_0;
 115                 break;
 116 #if defined(CONFIG_DRM_AMD_DC_DCN)
 117         case FAMILY_RV:
 118                 dc_version = DCN_VERSION_1_0;
 119                 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
 120                         dc_version = DCN_VERSION_1_01;
 121                 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
 122                         dc_version = DCN_VERSION_2_1;
 123                 break;
 124 #endif
 125
 126         case FAMILY_NV:
 127                 dc_version = DCN_VERSION_2_0;
 128 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 129                 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
 130                         dc_version = DCN_VERSION_3_0;
 131 #endif
 132                 break;
 133         default:
 134                 dc_version = DCE_VERSION_UNKNOWN;
 135                 break;
 136         }
 137         return dc_version;
 138 }
 139
 140 struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 141                                               const struct dc_init_data *init_data,
 142                                               enum dce_version dc_version)
 143 {
 144         struct resource_pool *res_pool = NULL;
 145
 146         switch (dc_version) {
 147 #if defined(CONFIG_DRM_AMD_DC_SI)
 148         case DCE_VERSION_6_0:
 149                 res_pool = dce60_create_resource_pool(
 150                         init_data->num_virtual_links, dc);
 151                 break;
 152         case DCE_VERSION_6_1:
 153                 res_pool = dce61_create_resource_pool(
 154                         init_data->num_virtual_links, dc);
 155                 break;
 156         case DCE_VERSION_6_4:
 157                 res_pool = dce64_create_resource_pool(
 158                         init_data->num_virtual_links, dc);
 159                 break;
 160 #endif
 161         case DCE_VERSION_8_0:
 162                 res_pool = dce80_create_resource_pool(
 163                                 init_data->num_virtual_links, dc);
 164                 break;
 165         case DCE_VERSION_8_1:
 166                 res_pool = dce81_create_resource_pool(
 167                                 init_data->num_virtual_links, dc);
 168                 break;
 169         case DCE_VERSION_8_3:
 170                 res_pool = dce83_create_resource_pool(
 171                                 init_data->num_virtual_links, dc);
 172                 break;
 173         case DCE_VERSION_10_0:
 174                 res_pool = dce100_create_resource_pool(
 175                                 init_data->num_virtual_links, dc);
 176                 break;
 177         case DCE_VERSION_11_0:
 178                 res_pool = dce110_create_resource_pool(
 179                                 init_data->num_virtual_links, dc,
 180                                 init_data->asic_id);
 181                 break;
 182         case DCE_VERSION_11_2:
 183         case DCE_VERSION_11_22:
 184                 res_pool = dce112_create_resource_pool(
 185                                 init_data->num_virtual_links, dc);
 186                 break;
 187         case DCE_VERSION_12_0:
 188         case DCE_VERSION_12_1:
 189                 res_pool = dce120_create_resource_pool(
 190                                 init_data->num_virtual_links, dc);
 191                 break;
 192
 193 #if defined(CONFIG_DRM_AMD_DC_DCN)
 194         case DCN_VERSION_1_0:
 195         case DCN_VERSION_1_01:
 196                 res_pool = dcn10_create_resource_pool(init_data, dc);
 197                 break;
 198
 199
 200         case DCN_VERSION_2_0:
 201                 res_pool = dcn20_create_resource_pool(init_data, dc);
 202                 break;
 203         case DCN_VERSION_2_1:
 204                 res_pool = dcn21_create_resource_pool(init_data, dc);
 205                 break;
 206 #endif
 207 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 208         case DCN_VERSION_3_0:
 209                 res_pool = dcn30_create_resource_pool(init_data, dc);
 210                 break;
 211 #endif
 212
 213         default:
 214                 break;
 215         }
 216
 217         if (res_pool != NULL) {
 218                 if (dc->ctx->dc_bios->fw_info_valid) {
 219                         res_pool->ref_clocks.xtalin_clock_inKhz =
 220                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 221                         /* initialize with firmware data first, no all
 222                          * ASIC have DCCG SW component. FPGA or
 223                          * simulation need initialization of
 224                          * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
 225                          * with xtalin_clock_inKhz
 226                          */
 227                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 228                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 229                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 230                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 231                 } else
 232                         ASSERT_CRITICAL(false);
 233         }
 234
 235         return res_pool;
 236 }
 237
 238 void dc_destroy_resource_pool(struct dc  *dc)
 239 {
 240         if (dc) {
 241                 if (dc->res_pool)
 242                         dc->res_pool->funcs->destroy(&dc->res_pool);
 243
 244                 kfree(dc->hwseq);
 245         }
 246 }
 247
 248 static void update_num_audio(
 249         const struct resource_straps *straps,
 250         unsigned int *num_audio,
 251         struct audio_support *aud_support)
 252 {
 253         aud_support->dp_audio = true;
 254         aud_support->hdmi_audio_native = false;
 255         aud_support->hdmi_audio_on_dongle = false;
 256
 257         if (straps->hdmi_disable == 0) {
 258                 if (straps->dc_pinstraps_audio & 0x2) {
 259                         aud_support->hdmi_audio_on_dongle = true;
 260                         aud_support->hdmi_audio_native = true;
 261                 }
 262         }
 263
 264         switch (straps->audio_stream_number) {
 265         case 0: /* multi streams supported */
 266                 break;
 267         case 1: /* multi streams not supported */
 268                 *num_audio = 1;
 269                 break;
 270         default:
 271                 DC_ERR("DC: unexpected audio fuse!\n");
 272         }
 273 }
 274
 275 bool resource_construct(
 276         unsigned int num_virtual_links,
 277         struct dc  *dc,
 278         struct resource_pool *pool,
 279         const struct resource_create_funcs *create_funcs)
 280 {
 281         struct dc_context *ctx = dc->ctx;
 282         const struct resource_caps *caps = pool->res_cap;
 283         int i;
 284         unsigned int num_audio = caps->num_audio;
 285         struct resource_straps straps = {0};
 286
 287         if (create_funcs->read_dce_straps)
 288                 create_funcs->read_dce_straps(dc->ctx, &straps);
 289
 290         pool->audio_count = 0;
 291         if (create_funcs->create_audio) {
 292                 /* find the total number of streams available via the
 293                  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
 294                  * registers (one for each pin) starting from pin 1
 295                  * up to the max number of audio pins.
 296                  * We stop on the first pin where
 297                  * PORT_CONNECTIVITY == 1 (as instructed by HW team).
 298                  */
 299                 update_num_audio(&straps, &num_audio, &pool->audio_support);
 300                 for (i = 0; i < caps->num_audio; i++) {
 301                         struct audio *aud = create_funcs->create_audio(ctx, i);
 302
 303                         if (aud == NULL) {
 304                                 DC_ERR("DC: failed to create audio!\n");
 305                                 return false;
 306                         }
 307                         if (!aud->funcs->endpoint_valid(aud)) {
 308                                 aud->funcs->destroy(&aud);
 309                                 break;
 310                         }
 311                         pool->audios[i] = aud;
 312                         pool->audio_count++;
 313                 }
 314         }
 315
 316         pool->stream_enc_count = 0;
 317         if (create_funcs->create_stream_encoder) {
 318                 for (i = 0; i < caps->num_stream_encoder; i++) {
 319                         pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
 320                         if (pool->stream_enc[i] == NULL)
 321                                 DC_ERR("DC: failed to create stream_encoder!\n");
 322                         pool->stream_enc_count++;
 323                 }
 324         }
 325
 326 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 327         for (i = 0; i < caps->num_mpc_3dlut; i++) {
 328                 pool->mpc_lut[i] = dc_create_3dlut_func();
 329                 if (pool->mpc_lut[i] == NULL)
 330                         DC_ERR("DC: failed to create MPC 3dlut!\n");
 331                 pool->mpc_shaper[i] = dc_create_transfer_func();
 332                 if (pool->mpc_shaper[i] == NULL)
 333                         DC_ERR("DC: failed to create MPC shaper!\n");
 334         }
 335 #endif
 336         dc->caps.dynamic_audio = false;
 337         if (pool->audio_count < pool->stream_enc_count) {
 338                 dc->caps.dynamic_audio = true;
 339         }
 340         for (i = 0; i < num_virtual_links; i++) {
 341                 pool->stream_enc[pool->stream_enc_count] =
 342                         virtual_stream_encoder_create(
 343                                         ctx, ctx->dc_bios);
 344                 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
 345                         DC_ERR("DC: failed to create stream_encoder!\n");
 346                         return false;
 347                 }
 348                 pool->stream_enc_count++;
 349         }
 350
 351         dc->hwseq = create_funcs->create_hwseq(ctx);
 352
 353         return true;
 354 }
 355 static int find_matching_clock_source(
 356                 const struct resource_pool *pool,
 357                 struct clock_source *clock_source)
 358 {
 359
 360         int i;
 361
 362         for (i = 0; i < pool->clk_src_count; i++) {
 363                 if (pool->clock_sources[i] == clock_source)
 364                         return i;
 365         }
 366         return -1;
 367 }
 368
 369 void resource_unreference_clock_source(
 370                 struct resource_context *res_ctx,
 371                 const struct resource_pool *pool,
 372                 struct clock_source *clock_source)
 373 {
 374         int i = find_matching_clock_source(pool, clock_source);
 375
 376         if (i > -1)
 377                 res_ctx->clock_source_ref_count[i]--;
 378
 379         if (pool->dp_clock_source == clock_source)
 380                 res_ctx->dp_clock_source_ref_count--;
 381 }
 382
 383 void resource_reference_clock_source(
 384                 struct resource_context *res_ctx,
 385                 const struct resource_pool *pool,
 386                 struct clock_source *clock_source)
 387 {
 388         int i = find_matching_clock_source(pool, clock_source);
 389
 390         if (i > -1)
 391                 res_ctx->clock_source_ref_count[i]++;
 392
 393         if (pool->dp_clock_source == clock_source)
 394                 res_ctx->dp_clock_source_ref_count++;
 395 }
 396
 397 int resource_get_clock_source_reference(
 398                 struct resource_context *res_ctx,
 399                 const struct resource_pool *pool,
 400                 struct clock_source *clock_source)
 401 {
 402         int i = find_matching_clock_source(pool, clock_source);
 403
 404         if (i > -1)
 405                 return res_ctx->clock_source_ref_count[i];
 406
 407         if (pool->dp_clock_source == clock_source)
 408                 return res_ctx->dp_clock_source_ref_count;
 409
 410         return -1;
 411 }
 412
 413 bool resource_are_streams_timing_synchronizable(
 414         struct dc_stream_state *stream1,
 415         struct dc_stream_state *stream2)
 416 {
 417         if (stream1->timing.h_total != stream2->timing.h_total)
 418                 return false;
 419
 420         if (stream1->timing.v_total != stream2->timing.v_total)
 421                 return false;
 422
 423         if (stream1->timing.h_addressable
 424                                 != stream2->timing.h_addressable)
 425                 return false;
 426
 427         if (stream1->timing.v_addressable
 428                                 != stream2->timing.v_addressable)
 429                 return false;
 430
 431         if (stream1->timing.v_front_porch
 432                                 != stream2->timing.v_front_porch)
 433                 return false;
 434
 435         if (stream1->timing.pix_clk_100hz
 436                                 != stream2->timing.pix_clk_100hz)
 437                 return false;
 438
 439         if (stream1->clamping.c_depth != stream2->clamping.c_depth)
 440                 return false;
 441
 442         if (stream1->phy_pix_clk != stream2->phy_pix_clk
 443                         && (!dc_is_dp_signal(stream1->signal)
 444                         || !dc_is_dp_signal(stream2->signal)))
 445                 return false;
 446
 447         if (stream1->view_format != stream2->view_format)
 448                 return false;
 449
 450         if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
 451                 return false;
 452
 453         return true;
 454 }
 455 static bool is_dp_and_hdmi_sharable(
 456                 struct dc_stream_state *stream1,
 457                 struct dc_stream_state *stream2)
 458 {
 459         if (stream1->ctx->dc->caps.disable_dp_clk_share)
 460                 return false;
 461
 462         if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
 463                 stream2->clamping.c_depth != COLOR_DEPTH_888)
 464                 return false;
 465
 466         return true;
 467
 468 }
 469
 470 static bool is_sharable_clk_src(
 471         const struct pipe_ctx *pipe_with_clk_src,
 472         const struct pipe_ctx *pipe)
 473 {
 474         if (pipe_with_clk_src->clock_source == NULL)
 475                 return false;
 476
 477         if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
 478                 return false;
 479
 480         if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
 481                 (dc_is_dp_signal(pipe->stream->signal) &&
 482                 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
 483                                      pipe->stream)))
 484                 return false;
 485
 486         if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
 487                         && dc_is_dual_link_signal(pipe->stream->signal))
 488                 return false;
 489
 490         if (dc_is_hdmi_signal(pipe->stream->signal)
 491                         && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
 492                 return false;
 493
 494         if (!resource_are_streams_timing_synchronizable(
 495                         pipe_with_clk_src->stream, pipe->stream))
 496                 return false;
 497
 498         return true;
 499 }
 500
 501 struct clock_source *resource_find_used_clk_src_for_sharing(
 502                                         struct resource_context *res_ctx,
 503                                         struct pipe_ctx *pipe_ctx)
 504 {
 505         int i;
 506
 507         for (i = 0; i < MAX_PIPES; i++) {
 508                 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
 509                         return res_ctx->pipe_ctx[i].clock_source;
 510         }
 511
 512         return NULL;
 513 }
 514
 515 static enum pixel_format convert_pixel_format_to_dalsurface(
 516                 enum surface_pixel_format surface_pixel_format)
 517 {
 518         enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
 519
 520         switch (surface_pixel_format) {
 521         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
 522                 dal_pixel_format = PIXEL_FORMAT_INDEX8;
 523                 break;
 524         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 525                 dal_pixel_format = PIXEL_FORMAT_RGB565;
 526                 break;
 527         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 528                 dal_pixel_format = PIXEL_FORMAT_RGB565;
 529                 break;
 530         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 531                 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
 532                 break;
 533         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 534                 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
 535                 break;
 536         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 537                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
 538                 break;
 539         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 540                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
 541                 break;
 542         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 543                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
 544                 break;
 545         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 546         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 547                 dal_pixel_format = PIXEL_FORMAT_FP16;
 548                 break;
 549         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 550         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 551                 dal_pixel_format = PIXEL_FORMAT_420BPP8;
 552                 break;
 553         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 554         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 555                 dal_pixel_format = PIXEL_FORMAT_420BPP10;
 556                 break;
 557         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 558         default:
 559                 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
 560                 break;
 561         }
 562         return dal_pixel_format;
 563 }
 564
 565 static inline void get_vp_scan_direction(
 566         enum dc_rotation_angle rotation,
 567         bool horizontal_mirror,
 568         bool *orthogonal_rotation,
 569         bool *flip_vert_scan_dir,
 570         bool *flip_horz_scan_dir)
 571 {
 572         *orthogonal_rotation = false;
 573         *flip_vert_scan_dir = false;
 574         *flip_horz_scan_dir = false;
 575         if (rotation == ROTATION_ANGLE_180) {
 576                 *flip_vert_scan_dir = true;
 577                 *flip_horz_scan_dir = true;
 578         } else if (rotation == ROTATION_ANGLE_90) {
 579                 *orthogonal_rotation = true;
 580                 *flip_horz_scan_dir = true;
 581         } else if (rotation == ROTATION_ANGLE_270) {
 582                 *orthogonal_rotation = true;
 583                 *flip_vert_scan_dir = true;
 584         }
 585
 586         if (horizontal_mirror)
 587                 *flip_horz_scan_dir = !*flip_horz_scan_dir;
 588 }
 589
 590 int get_num_mpc_splits(struct pipe_ctx *pipe)
 591 {
 592         int mpc_split_count = 0;
 593         struct pipe_ctx *other_pipe = pipe->bottom_pipe;
 594
 595         while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
 596                 mpc_split_count++;
 597                 other_pipe = other_pipe->bottom_pipe;
 598         }
 599         other_pipe = pipe->top_pipe;
 600         while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
 601                 mpc_split_count++;
 602                 other_pipe = other_pipe->top_pipe;
 603         }
 604
 605         return mpc_split_count;
 606 }
 607
 608 int get_num_odm_splits(struct pipe_ctx *pipe)
 609 {
 610         int odm_split_count = 0;
 611         struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
 612         while (next_pipe) {
 613                 odm_split_count++;
 614                 next_pipe = next_pipe->next_odm_pipe;
 615         }
 616         pipe = pipe->prev_odm_pipe;
 617         while (pipe) {
 618                 odm_split_count++;
 619                 pipe = pipe->prev_odm_pipe;
 620         }
 621         return odm_split_count;
 622 }
 623
 624 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
 625 {
 626         *split_count = get_num_odm_splits(pipe_ctx);
 627         *split_idx = 0;
 628         if (*split_count == 0) {
 629                 /*Check for mpc split*/
 630                 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
 631
 632                 *split_count = get_num_mpc_splits(pipe_ctx);
 633                 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
 634                         (*split_idx)++;
 635                         split_pipe = split_pipe->top_pipe;
 636                 }
 637         } else {
 638                 /*Get odm split index*/
 639                 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
 640
 641                 while (split_pipe) {
 642                         (*split_idx)++;
 643                         split_pipe = split_pipe->prev_odm_pipe;
 644                 }
 645         }
 646 }
 647
 648 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 649 {
 650         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 651         const struct dc_stream_state *stream = pipe_ctx->stream;
 652         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 653         struct rect surf_src = plane_state->src_rect;
 654         struct rect clip, dest;
 655         int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
 656                         || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
 657         int split_count = 0;
 658         int split_idx = 0;
 659         bool orthogonal_rotation, flip_y_start, flip_x_start;
 660
 661         calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
 662
 663         if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
 664                 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
 665                 split_count = 0;
 666                 split_idx = 0;
 667         }
 668
 669         /* The actual clip is an intersection between stream
 670          * source and surface clip
 671          */
 672         dest = plane_state->dst_rect;
 673         clip.x = stream->src.x > plane_state->clip_rect.x ?
 674                         stream->src.x : plane_state->clip_rect.x;
 675
 676         clip.width = stream->src.x + stream->src.width <
 677                         plane_state->clip_rect.x + plane_state->clip_rect.width ?
 678                         stream->src.x + stream->src.width - clip.x :
 679                         plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
 680
 681         clip.y = stream->src.y > plane_state->clip_rect.y ?
 682                         stream->src.y : plane_state->clip_rect.y;
 683
 684         clip.height = stream->src.y + stream->src.height <
 685                         plane_state->clip_rect.y + plane_state->clip_rect.height ?
 686                         stream->src.y + stream->src.height - clip.y :
 687                         plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
 688
 689         /*
 690          * Need to calculate how scan origin is shifted in vp space
 691          * to correctly rotate clip and dst
 692          */
 693         get_vp_scan_direction(
 694                         plane_state->rotation,
 695                         plane_state->horizontal_mirror,
 696                         &orthogonal_rotation,
 697                         &flip_y_start,
 698                         &flip_x_start);
 699
 700         if (orthogonal_rotation) {
 701                 swap(clip.x, clip.y);
 702                 swap(clip.width, clip.height);
 703                 swap(dest.x, dest.y);
 704                 swap(dest.width, dest.height);
 705         }
 706         if (flip_x_start) {
 707                 clip.x = dest.x + dest.width - clip.x - clip.width;
 708                 dest.x = 0;
 709         }
 710         if (flip_y_start) {
 711                 clip.y = dest.y + dest.height - clip.y - clip.height;
 712                 dest.y = 0;
 713         }
 714
 715         /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
 716          * num_pixels = clip.num_pix * scl_ratio
 717          */
 718         data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
 719         data->viewport.width = clip.width * surf_src.width / dest.width;
 720
 721         data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
 722         data->viewport.height = clip.height * surf_src.height / dest.height;
 723
 724         /* Handle split */
 725         if (split_count) {
 726                 /* extra pixels in the division remainder need to go to pipes after
 727                  * the extra pixel index minus one(epimo) defined here as:
 728                  */
 729                 int epimo = 0;
 730
 731                 if (orthogonal_rotation) {
 732                         if (flip_y_start)
 733                                 split_idx = split_count - split_idx;
 734
 735                         epimo = split_count - data->viewport.height % (split_count + 1);
 736
 737                         data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
 738                         if (split_idx > epimo)
 739                                 data->viewport.y += split_idx - epimo - 1;
 740                         data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
 741                 } else {
 742                         if (flip_x_start)
 743                                 split_idx = split_count - split_idx;
 744
 745                         epimo = split_count - data->viewport.width % (split_count + 1);
 746
 747                         data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
 748                         if (split_idx > epimo)
 749                                 data->viewport.x += split_idx - epimo - 1;
 750                         data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
 751                 }
 752         }
 753
 754         /* Round down, compensate in init */
 755         data->viewport_c.x = data->viewport.x / vpc_div;
 756         data->viewport_c.y = data->viewport.y / vpc_div;
 757         data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
 758         data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
 759
 760         /* Round up, assume original video size always even dimensions */
 761         data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
 762         data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
 763
 764         data->viewport_unadjusted = data->viewport;
 765         data->viewport_c_unadjusted = data->viewport_c;
 766 }
 767
 768 static void calculate_recout(struct pipe_ctx *pipe_ctx)
 769 {
 770         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 771         const struct dc_stream_state *stream = pipe_ctx->stream;
 772         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 773         struct rect surf_clip = plane_state->clip_rect;
 774         bool pri_split_tb = pipe_ctx->bottom_pipe &&
 775                         pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
 776                         stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
 777         bool sec_split_tb = pipe_ctx->top_pipe &&
 778                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
 779                         stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
 780         int split_count = 0;
 781         int split_idx = 0;
 782
 783         calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
 784
 785         /*
 786          * Only the leftmost ODM pipe should be offset by a nonzero distance
 787          */
 788         if (!pipe_ctx->prev_odm_pipe) {
 789                 data->recout.x = stream->dst.x;
 790                 if (stream->src.x < surf_clip.x)
 791                         data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
 792                                                 / stream->src.width;
 793
 794         } else
 795                 data->recout.x = 0;
 796
 797         data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
 798         if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
 799                 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
 800
 801         data->recout.y = stream->dst.y;
 802         if (stream->src.y < surf_clip.y)
 803                 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
 804                                                 / stream->src.height;
 805
 806         data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
 807         if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
 808                 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
 809
 810         /* Handle h & v split, handle rotation using viewport */
 811         if (sec_split_tb) {
 812                 data->recout.y += data->recout.height / 2;
 813                 /* Floor primary pipe, ceil 2ndary pipe */
 814                 data->recout.height = (data->recout.height + 1) / 2;
 815         } else if (pri_split_tb)
 816                 data->recout.height /= 2;
 817         else if (split_count) {
 818                 /* extra pixels in the division remainder need to go to pipes after
 819                  * the extra pixel index minus one(epimo) defined here as:
 820                  */
 821                 int epimo = split_count - data->recout.width % (split_count + 1);
 822
 823                 /*no recout offset due to odm */
 824                 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
 825                         data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
 826                         if (split_idx > epimo)
 827                                 data->recout.x += split_idx - epimo - 1;
 828                 }
 829                 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
 830         }
 831 }
 832
 833 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
 834 {
 835         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 836         const struct dc_stream_state *stream = pipe_ctx->stream;
 837         struct rect surf_src = plane_state->src_rect;
 838         const int in_w = stream->src.width;
 839         const int in_h = stream->src.height;
 840         const int out_w = stream->dst.width;
 841         const int out_h = stream->dst.height;
 842
 843         /*Swap surf_src height and width since scaling ratios are in recout rotation*/
 844         if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
 845                         pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
 846                 swap(surf_src.height, surf_src.width);
 847
 848         pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
 849                                         surf_src.width,
 850                                         plane_state->dst_rect.width);
 851         pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
 852                                         surf_src.height,
 853                                         plane_state->dst_rect.height);
 854
 855         if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
 856                 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
 857         else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
 858                 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
 859
 860         pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
 861                 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
 862         pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
 863                 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
 864
 865         pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
 866         pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
 867
 868         if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
 869                         || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
 870                 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
 871                 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
 872         }
 873         pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
 874                         pipe_ctx->plane_res.scl_data.ratios.horz, 19);
 875         pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
 876                         pipe_ctx->plane_res.scl_data.ratios.vert, 19);
 877         pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
 878                         pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
 879         pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
 880                         pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 881 }
 882
 883 static inline void adjust_vp_and_init_for_seamless_clip(
 884                 bool flip_scan_dir,
 885                 int recout_skip,
 886                 int src_size,
 887                 int taps,
 888                 struct fixed31_32 ratio,
 889                 struct fixed31_32 *init,
 890                 int *vp_offset,
 891                 int *vp_size)
 892 {
 893         if (!flip_scan_dir) {
 894                 /* Adjust for viewport end clip-off */
 895                 if ((*vp_offset + *vp_size) < src_size) {
 896                         int vp_clip = src_size - *vp_size - *vp_offset;
 897                         int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
 898
 899                         int_part = int_part > 0 ? int_part : 0;
 900                         *vp_size += int_part < vp_clip ? int_part : vp_clip;
 901                 }
 902
 903                 /* Adjust for non-0 viewport offset */
 904                 if (*vp_offset) {
 905                         int int_part;
 906
 907                         *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
 908                         int_part = dc_fixpt_floor(*init) - *vp_offset;
 909                         if (int_part < taps) {
 910                                 int int_adj = *vp_offset >= (taps - int_part) ?
 911                                                         (taps - int_part) : *vp_offset;
 912                                 *vp_offset -= int_adj;
 913                                 *vp_size += int_adj;
 914                                 int_part += int_adj;
 915                         } else if (int_part > taps) {
 916                                 *vp_offset += int_part - taps;
 917                                 *vp_size -= int_part - taps;
 918                                 int_part = taps;
 919                         }
 920                         init->value &= 0xffffffff;
 921                         *init = dc_fixpt_add_int(*init, int_part);
 922                 }
 923         } else {
 924                 /* Adjust for non-0 viewport offset */
 925                 if (*vp_offset) {
 926                         int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
 927
 928                         int_part = int_part > 0 ? int_part : 0;
 929                         *vp_size += int_part < *vp_offset ? int_part : *vp_offset;
 930                         *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
 931                 }
 932
 933                 /* Adjust for viewport end clip-off */
 934                 if ((*vp_offset + *vp_size) < src_size) {
 935                         int int_part;
 936                         int end_offset = src_size - *vp_offset - *vp_size;
 937
 938                         /*
 939                          * this is init if vp had no offset, keep in mind this is from the
 940                          * right side of vp due to scan direction
 941                          */
 942                         *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
 943                         /*
 944                          * this is the difference between first pixel of viewport available to read
 945                          * and init position, takning into account scan direction
 946                          */
 947                         int_part = dc_fixpt_floor(*init) - end_offset;
 948                         if (int_part < taps) {
 949                                 int int_adj = end_offset >= (taps - int_part) ?
 950                                                         (taps - int_part) : end_offset;
 951                                 *vp_size += int_adj;
 952                                 int_part += int_adj;
 953                         } else if (int_part > taps) {
 954                                 *vp_size += int_part - taps;
 955                                 int_part = taps;
 956                         }
 957                         init->value &= 0xffffffff;
 958                         *init = dc_fixpt_add_int(*init, int_part);
 959                 }
 960         }
 961 }
 962
 963 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
 964 {
 965         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 966         const struct dc_stream_state *stream = pipe_ctx->stream;
 967         struct pipe_ctx *odm_pipe = pipe_ctx;
 968         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 969         struct rect src = pipe_ctx->plane_state->src_rect;
 970         int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
 971         int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
 972                         || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
 973         bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
 974         int odm_idx = 0;
 975
 976         /*
 977          * Need to calculate the scan direction for viewport to make adjustments
 978          */
 979         get_vp_scan_direction(
 980                         plane_state->rotation,
 981                         plane_state->horizontal_mirror,
 982                         &orthogonal_rotation,
 983                         &flip_vert_scan_dir,
 984                         &flip_horz_scan_dir);
 985
 986         /* Calculate src rect rotation adjusted to recout space */
 987         surf_size_h = src.x + src.width;
 988         surf_size_v = src.y + src.height;
 989         if (flip_horz_scan_dir)
 990                 src.x = 0;
 991         if (flip_vert_scan_dir)
 992                 src.y = 0;
 993         if (orthogonal_rotation) {
 994                 swap(src.x, src.y);
 995                 swap(src.width, src.height);
 996         }
 997
 998         /*modified recout_skip_h calculation due to odm having no recout offset*/
 999         while (odm_pipe->prev_odm_pipe) {
1000                 odm_idx++;
1001                 odm_pipe = odm_pipe->prev_odm_pipe;
1002         }
1003         /*odm_pipe is the leftmost pipe in the ODM group*/
1004         recout_skip_h = odm_idx * data->recout.width;
1005
1006         /* Recout matching initial vp offset = recout_offset - (stream dst offset +
1007          *                      ((surf dst offset - stream src offset) * 1/ stream scaling ratio)
1008          *                      - (surf surf_src offset * 1/ full scl ratio))
1009          */
1010         recout_skip_h += odm_pipe->plane_res.scl_data.recout.x
1011                                 - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
1012                                         * stream->dst.width / stream->src.width -
1013                                         src.x * plane_state->dst_rect.width / src.width
1014                                         * stream->dst.width / stream->src.width);
1015
1016
1017         recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
1018                                         * stream->dst.height / stream->src.height -
1019                                         src.y * plane_state->dst_rect.height / src.height
1020                                         * stream->dst.height / stream->src.height);
1021         if (orthogonal_rotation)
1022                 swap(recout_skip_h, recout_skip_v);
1023         /*
1024          * Init calculated according to formula:
1025          *      init = (scaling_ratio + number_of_taps + 1) / 2
1026          *      init_bot = init + scaling_ratio
1027          *      init_c = init + truncated_vp_c_offset(from calculate viewport)
1028          */
1029         data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
1030                         dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
1031
1032         data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
1033                         dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
1034
1035         data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
1036                         dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
1037
1038         data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
1039                         dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
1040
1041         /*
1042          * Taps, inits and scaling ratios are in recout space need to rotate
1043          * to viewport rotation before adjustment
1044          */
1045         adjust_vp_and_init_for_seamless_clip(
1046                         flip_horz_scan_dir,
1047                         recout_skip_h,
1048                         surf_size_h,
1049                         orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps,
1050                         orthogonal_rotation ? data->ratios.vert : data->ratios.horz,
1051                         orthogonal_rotation ? &data->inits.v : &data->inits.h,
1052                         &data->viewport.x,
1053                         &data->viewport.width);
1054         adjust_vp_and_init_for_seamless_clip(
1055                         flip_horz_scan_dir,
1056                         recout_skip_h,
1057                         surf_size_h / vpc_div,
1058                         orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c,
1059                         orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c,
1060                         orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c,
1061                         &data->viewport_c.x,
1062                         &data->viewport_c.width);
1063         adjust_vp_and_init_for_seamless_clip(
1064                         flip_vert_scan_dir,
1065                         recout_skip_v,
1066                         surf_size_v,
1067                         orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
1068                         orthogonal_rotation ? data->ratios.horz : data->ratios.vert,
1069                         orthogonal_rotation ? &data->inits.h : &data->inits.v,
1070                         &data->viewport.y,
1071                         &data->viewport.height);
1072         adjust_vp_and_init_for_seamless_clip(
1073                         flip_vert_scan_dir,
1074                         recout_skip_v,
1075                         surf_size_v / vpc_div,
1076                         orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c,
1077                         orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c,
1078                         orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c,
1079                         &data->viewport_c.y,
1080                         &data->viewport_c.height);
1081
1082         /* Interlaced inits based on final vert inits */
1083         data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
1084         data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
1085
1086 }
1087
1088 /*
1089  * When handling 270 rotation in mixed SLS mode, we have
1090  * stream->timing.h_border_left that is non zero.  If we are doing
1091  * pipe-splitting, this h_border_left value gets added to recout.x and when it
1092  * calls calculate_inits_and_adj_vp() and
1093  * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a
1094  * pipe to be incorrect.
1095  *
1096  * To fix this, instead of using stream->timing.h_border_left, we can use
1097  * stream->dst.x to represent the border instead.  So we will set h_border_left
1098  * to 0 and shift the appropriate amount in stream->dst.x.  We will then
1099  * perform all calculations in resource_build_scaling_params() based on this
1100  * and then restore the h_border_left and stream->dst.x to their original
1101  * values.
1102  *
1103  * shift_border_left_to_dst() will shift the amount of h_border_left to
1104  * stream->dst.x and set h_border_left to 0.  restore_border_left_from_dst()
1105  * will restore h_border_left and stream->dst.x back to their original values
1106  * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
1107  * original h_border_left value in its calculation.
1108  */
1109 int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
1110 {
1111         int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
1112
1113         if (store_h_border_left) {
1114                 pipe_ctx->stream->timing.h_border_left = 0;
1115                 pipe_ctx->stream->dst.x += store_h_border_left;
1116         }
1117         return store_h_border_left;
1118 }
1119
1120 void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
1121                                   int store_h_border_left)
1122 {
1123         pipe_ctx->stream->dst.x -= store_h_border_left;
1124         pipe_ctx->stream->timing.h_border_left = store_h_border_left;
1125 }
1126
1127 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1128 {
1129         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1130         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1131         bool res = false;
1132         int store_h_border_left = shift_border_left_to_dst(pipe_ctx);
1133         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1134         /* Important: scaling ratio calculation requires pixel format,
1135          * lb depth calculation requires recout and taps require scaling ratios.
1136          * Inits require viewport, taps, ratios and recout of split pipe
1137          */
1138         pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1139                         pipe_ctx->plane_state->format);
1140
1141         calculate_scaling_ratios(pipe_ctx);
1142
1143         calculate_viewport(pipe_ctx);
1144
1145         if (pipe_ctx->plane_res.scl_data.viewport.height < 12 ||
1146                 pipe_ctx->plane_res.scl_data.viewport.width < 12) {
1147                 if (store_h_border_left) {
1148                         restore_border_left_from_dst(pipe_ctx,
1149                                 store_h_border_left);
1150                 }
1151                 return false;
1152         }
1153
1154         calculate_recout(pipe_ctx);
1155
1156         /**
1157          * Setting line buffer pixel depth to 24bpp yields banding
1158          * on certain displays, such as the Sharp 4k
1159          */
1160         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1161         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1162
1163         pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
1164         pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
1165
1166         pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1167                 store_h_border_left + timing->h_border_right;
1168         pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1169                 timing->v_border_top + timing->v_border_bottom;
1170         if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1171                 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1172
1173         /* Taps calculations */
1174         if (pipe_ctx->plane_res.xfm != NULL)
1175                 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1176                                 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1177
1178         if (pipe_ctx->plane_res.dpp != NULL)
1179                 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1180                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1181
1182
1183         if (!res) {
1184                 /* Try 24 bpp linebuffer */
1185                 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1186
1187                 if (pipe_ctx->plane_res.xfm != NULL)
1188                         res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1189                                         pipe_ctx->plane_res.xfm,
1190                                         &pipe_ctx->plane_res.scl_data,
1191                                         &plane_state->scaling_quality);
1192
1193                 if (pipe_ctx->plane_res.dpp != NULL)
1194                         res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1195                                         pipe_ctx->plane_res.dpp,
1196                                         &pipe_ctx->plane_res.scl_data,
1197                                         &plane_state->scaling_quality);
1198         }
1199
1200         if (res)
1201                 /* May need to re-check lb size after this in some obscure scenario */
1202                 calculate_inits_and_adj_vp(pipe_ctx);
1203
1204         DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d  Recout: height:%d width:%d x:%d y:%d  HACTIVE:%d VACTIVE:%d\n"
1205                         "src_rect: height:%d width:%d x:%d y:%d  dst_rect: height:%d width:%d x:%d y:%d  clip_rect: height:%d width:%d x:%d y:%d\n",
1206                         __func__,
1207                         pipe_ctx->pipe_idx,
1208                         pipe_ctx->plane_res.scl_data.viewport.height,
1209                         pipe_ctx->plane_res.scl_data.viewport.width,
1210                         pipe_ctx->plane_res.scl_data.viewport.x,
1211                         pipe_ctx->plane_res.scl_data.viewport.y,
1212                         pipe_ctx->plane_res.scl_data.recout.height,
1213                         pipe_ctx->plane_res.scl_data.recout.width,
1214                         pipe_ctx->plane_res.scl_data.recout.x,
1215                         pipe_ctx->plane_res.scl_data.recout.y,
1216                         pipe_ctx->plane_res.scl_data.h_active,
1217                         pipe_ctx->plane_res.scl_data.v_active,
1218                         plane_state->src_rect.height,
1219                         plane_state->src_rect.width,
1220                         plane_state->src_rect.x,
1221                         plane_state->src_rect.y,
1222                         plane_state->dst_rect.height,
1223                         plane_state->dst_rect.width,
1224                         plane_state->dst_rect.x,
1225                         plane_state->dst_rect.y,
1226                         plane_state->clip_rect.height,
1227                         plane_state->clip_rect.width,
1228                         plane_state->clip_rect.x,
1229                         plane_state->clip_rect.y);
1230
1231         if (store_h_border_left)
1232                 restore_border_left_from_dst(pipe_ctx, store_h_border_left);
1233
1234         return res;
1235 }
1236
1237
1238 enum dc_status resource_build_scaling_params_for_context(
1239         const struct dc  *dc,
1240         struct dc_state *context)
1241 {
1242         int i;
1243
1244         for (i = 0; i < MAX_PIPES; i++) {
1245                 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1246                                 context->res_ctx.pipe_ctx[i].stream != NULL)
1247                         if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1248                                 return DC_FAIL_SCALING;
1249         }
1250
1251         return DC_OK;
1252 }
1253
1254 struct pipe_ctx *find_idle_secondary_pipe(
1255                 struct resource_context *res_ctx,
1256                 const struct resource_pool *pool,
1257                 const struct pipe_ctx *primary_pipe)
1258 {
1259         int i;
1260         struct pipe_ctx *secondary_pipe = NULL;
1261
1262         /*
1263          * We add a preferred pipe mapping to avoid the chance that
1264          * MPCCs already in use will need to be reassigned to other trees.
1265          * For example, if we went with the strict, assign backwards logic:
1266          *
1267          * (State 1)
1268          * Display A on, no surface, top pipe = 0
1269          * Display B on, no surface, top pipe = 1
1270          *
1271          * (State 2)
1272          * Display A on, no surface, top pipe = 0
1273          * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1274          *
1275          * (State 3)
1276          * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1277          * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1278          *
1279          * The state 2->3 transition requires remapping MPCC 5 from display B
1280          * to display A.
1281          *
1282          * However, with the preferred pipe logic, state 2 would look like:
1283          *
1284          * (State 2)
1285          * Display A on, no surface, top pipe = 0
1286          * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1287          *
1288          * This would then cause 2->3 to not require remapping any MPCCs.
1289          */
1290         if (primary_pipe) {
1291                 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1292                 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1293                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1294                         secondary_pipe->pipe_idx = preferred_pipe_idx;
1295                 }
1296         }
1297
1298         /*
1299          * search backwards for the second pipe to keep pipe
1300          * assignment more consistent
1301          */
1302         if (!secondary_pipe)
1303                 for (i = pool->pipe_count - 1; i >= 0; i--) {
1304                         if (res_ctx->pipe_ctx[i].stream == NULL) {
1305                                 secondary_pipe = &res_ctx->pipe_ctx[i];
1306                                 secondary_pipe->pipe_idx = i;
1307                                 break;
1308                         }
1309                 }
1310
1311         return secondary_pipe;
1312 }
1313
1314 struct pipe_ctx *resource_get_head_pipe_for_stream(
1315                 struct resource_context *res_ctx,
1316                 struct dc_stream_state *stream)
1317 {
1318         int i;
1319
1320         for (i = 0; i < MAX_PIPES; i++) {
1321                 if (res_ctx->pipe_ctx[i].stream == stream
1322                                 && !res_ctx->pipe_ctx[i].top_pipe
1323                                 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
1324                         return &res_ctx->pipe_ctx[i];
1325         }
1326         return NULL;
1327 }
1328
1329 static struct pipe_ctx *resource_get_tail_pipe(
1330                 struct resource_context *res_ctx,
1331                 struct pipe_ctx *head_pipe)
1332 {
1333         struct pipe_ctx *tail_pipe;
1334
1335         tail_pipe = head_pipe->bottom_pipe;
1336
1337         while (tail_pipe) {
1338                 head_pipe = tail_pipe;
1339                 tail_pipe = tail_pipe->bottom_pipe;
1340         }
1341
1342         return head_pipe;
1343 }
1344
1345 /*
1346  * A free_pipe for a stream is defined here as a pipe
1347  * that has no surface attached yet
1348  */
1349 static struct pipe_ctx *acquire_free_pipe_for_head(
1350                 struct dc_state *context,
1351                 const struct resource_pool *pool,
1352                 struct pipe_ctx *head_pipe)
1353 {
1354         int i;
1355         struct resource_context *res_ctx = &context->res_ctx;
1356
1357         if (!head_pipe->plane_state)
1358                 return head_pipe;
1359
1360         /* Re-use pipe already acquired for this stream if available*/
1361         for (i = pool->pipe_count - 1; i >= 0; i--) {
1362                 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
1363                                 !res_ctx->pipe_ctx[i].plane_state) {
1364                         return &res_ctx->pipe_ctx[i];
1365                 }
1366         }
1367
1368         /*
1369          * At this point we have no re-useable pipe for this stream and we need
1370          * to acquire an idle one to satisfy the request
1371          */
1372
1373         if (!pool->funcs->acquire_idle_pipe_for_layer)
1374                 return NULL;
1375
1376         return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
1377 }
1378
1379 #if defined(CONFIG_DRM_AMD_DC_DCN)
1380 static int acquire_first_split_pipe(
1381                 struct resource_context *res_ctx,
1382                 const struct resource_pool *pool,
1383                 struct dc_stream_state *stream)
1384 {
1385         int i;
1386
1387         for (i = 0; i < pool->pipe_count; i++) {
1388                 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1389
1390                 if (split_pipe->top_pipe &&
1391                                 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1392                         split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1393                         if (split_pipe->bottom_pipe)
1394                                 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1395
1396                         if (split_pipe->top_pipe->plane_state)
1397                                 resource_build_scaling_params(split_pipe->top_pipe);
1398
1399                         memset(split_pipe, 0, sizeof(*split_pipe));
1400                         split_pipe->stream_res.tg = pool->timing_generators[i];
1401                         split_pipe->plane_res.hubp = pool->hubps[i];
1402                         split_pipe->plane_res.ipp = pool->ipps[i];
1403                         split_pipe->plane_res.dpp = pool->dpps[i];
1404                         split_pipe->stream_res.opp = pool->opps[i];
1405                         split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1406                         split_pipe->pipe_idx = i;
1407
1408                         split_pipe->stream = stream;
1409                         return i;
1410                 }
1411         }
1412         return -1;
1413 }
1414 #endif
1415
1416 bool dc_add_plane_to_context(
1417                 const struct dc *dc,
1418                 struct dc_stream_state *stream,
1419                 struct dc_plane_state *plane_state,
1420                 struct dc_state *context)
1421 {
1422         int i;
1423         struct resource_pool *pool = dc->res_pool;
1424         struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
1425         struct dc_stream_status *stream_status = NULL;
1426
1427         for (i = 0; i < context->stream_count; i++)
1428                 if (context->streams[i] == stream) {
1429                         stream_status = &context->stream_status[i];
1430                         break;
1431                 }
1432         if (stream_status == NULL) {
1433                 dm_error("Existing stream not found; failed to attach surface!\n");
1434                 return false;
1435         }
1436
1437
1438         if (stream_status->plane_count == MAX_SURFACE_NUM) {
1439                 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1440                                 plane_state, MAX_SURFACE_NUM);
1441                 return false;
1442         }
1443
1444         head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1445
1446         if (!head_pipe) {
1447                 dm_error("Head pipe not found for stream_state %p !\n", stream);
1448                 return false;
1449         }
1450
1451         /* retain new surface, but only once per stream */
1452         dc_plane_state_retain(plane_state);
1453
1454         while (head_pipe) {
1455                 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
1456
1457         #if defined(CONFIG_DRM_AMD_DC_DCN)
1458                 if (!free_pipe) {
1459                         int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1460                         if (pipe_idx >= 0)
1461                                 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1462                 }
1463         #endif
1464                 if (!free_pipe) {
1465                         dc_plane_state_release(plane_state);
1466                         return false;
1467                 }
1468
1469                 free_pipe->plane_state = plane_state;
1470
1471                 if (head_pipe != free_pipe) {
1472                         tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1473                         ASSERT(tail_pipe);
1474                         free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1475                         free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1476                         free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1477                         free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1478                         free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1479                         free_pipe->clock_source = tail_pipe->clock_source;
1480                         free_pipe->top_pipe = tail_pipe;
1481                         tail_pipe->bottom_pipe = free_pipe;
1482                 }
1483                 head_pipe = head_pipe->next_odm_pipe;
1484         }
1485         /* assign new surfaces*/
1486         stream_status->plane_states[stream_status->plane_count] = plane_state;
1487
1488         stream_status->plane_count++;
1489
1490         return true;
1491 }
1492
1493 bool dc_remove_plane_from_context(
1494                 const struct dc *dc,
1495                 struct dc_stream_state *stream,
1496                 struct dc_plane_state *plane_state,
1497                 struct dc_state *context)
1498 {
1499         int i;
1500         struct dc_stream_status *stream_status = NULL;
1501         struct resource_pool *pool = dc->res_pool;
1502
1503         for (i = 0; i < context->stream_count; i++)
1504                 if (context->streams[i] == stream) {
1505                         stream_status = &context->stream_status[i];
1506                         break;
1507                 }
1508
1509         if (stream_status == NULL) {
1510                 dm_error("Existing stream not found; failed to remove plane.\n");
1511                 return false;
1512         }
1513
1514         /* release pipe for plane*/
1515         for (i = pool->pipe_count - 1; i >= 0; i--) {
1516                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1517
1518                 if (pipe_ctx->plane_state == plane_state) {
1519                         if (pipe_ctx->top_pipe)
1520                                 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1521
1522                         /* Second condition is to avoid setting NULL to top pipe
1523                          * of tail pipe making it look like head pipe in subsequent
1524                          * deletes
1525                          */
1526                         if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1527                                 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1528
1529                         /*
1530                          * For head pipe detach surfaces from pipe for tail
1531                          * pipe just zero it out
1532                          */
1533                         if (!pipe_ctx->top_pipe)
1534                                 pipe_ctx->plane_state = NULL;
1535                         else
1536                                 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1537                 }
1538         }
1539
1540
1541         for (i = 0; i < stream_status->plane_count; i++) {
1542                 if (stream_status->plane_states[i] == plane_state) {
1543
1544                         dc_plane_state_release(stream_status->plane_states[i]);
1545                         break;
1546                 }
1547         }
1548
1549         if (i == stream_status->plane_count) {
1550                 dm_error("Existing plane_state not found; failed to detach it!\n");
1551                 return false;
1552         }
1553
1554         stream_status->plane_count--;
1555
1556         /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1557         for (; i < stream_status->plane_count; i++)
1558                 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1559
1560         stream_status->plane_states[stream_status->plane_count] = NULL;
1561
1562         return true;
1563 }
1564
1565 bool dc_rem_all_planes_for_stream(
1566                 const struct dc *dc,
1567                 struct dc_stream_state *stream,
1568                 struct dc_state *context)
1569 {
1570         int i, old_plane_count;
1571         struct dc_stream_status *stream_status = NULL;
1572         struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1573
1574         for (i = 0; i < context->stream_count; i++)
1575                         if (context->streams[i] == stream) {
1576                                 stream_status = &context->stream_status[i];
1577                                 break;
1578                         }
1579
1580         if (stream_status == NULL) {
1581                 dm_error("Existing stream %p not found!\n", stream);
1582                 return false;
1583         }
1584
1585         old_plane_count = stream_status->plane_count;
1586
1587         for (i = 0; i < old_plane_count; i++)
1588                 del_planes[i] = stream_status->plane_states[i];
1589
1590         for (i = 0; i < old_plane_count; i++)
1591                 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1592                         return false;
1593
1594         return true;
1595 }
1596
1597 static bool add_all_planes_for_stream(
1598                 const struct dc *dc,
1599                 struct dc_stream_state *stream,
1600                 const struct dc_validation_set set[],
1601                 int set_count,
1602                 struct dc_state *context)
1603 {
1604         int i, j;
1605
1606         for (i = 0; i < set_count; i++)
1607                 if (set[i].stream == stream)
1608                         break;
1609
1610         if (i == set_count) {
1611                 dm_error("Stream %p not found in set!\n", stream);
1612                 return false;
1613         }
1614
1615         for (j = 0; j < set[i].plane_count; j++)
1616                 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1617                         return false;
1618
1619         return true;
1620 }
1621
1622 bool dc_add_all_planes_for_stream(
1623                 const struct dc *dc,
1624                 struct dc_stream_state *stream,
1625                 struct dc_plane_state * const *plane_states,
1626                 int plane_count,
1627                 struct dc_state *context)
1628 {
1629         struct dc_validation_set set;
1630         int i;
1631
1632         set.stream = stream;
1633         set.plane_count = plane_count;
1634
1635         for (i = 0; i < plane_count; i++)
1636                 set.plane_states[i] = plane_states[i];
1637
1638         return add_all_planes_for_stream(dc, stream, &set, 1, context);
1639 }
1640
1641 static bool is_timing_changed(struct dc_stream_state *cur_stream,
1642                 struct dc_stream_state *new_stream)
1643 {
1644         if (cur_stream == NULL)
1645                 return true;
1646
1647         /* If sink pointer changed, it means this is a hotplug, we should do
1648          * full hw setting.
1649          */
1650         if (cur_stream->sink != new_stream->sink)
1651                 return true;
1652
1653         /* If output color space is changed, need to reprogram info frames */
1654         if (cur_stream->output_color_space != new_stream->output_color_space)
1655                 return true;
1656
1657         return memcmp(
1658                 &cur_stream->timing,
1659                 &new_stream->timing,
1660                 sizeof(struct dc_crtc_timing)) != 0;
1661 }
1662
1663 static bool are_stream_backends_same(
1664         struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
1665 {
1666         if (stream_a == stream_b)
1667                 return true;
1668
1669         if (stream_a == NULL || stream_b == NULL)
1670                 return false;
1671
1672         if (is_timing_changed(stream_a, stream_b))
1673                 return false;
1674
1675         if (stream_a->dpms_off != stream_b->dpms_off)
1676                 return false;
1677
1678         return true;
1679 }
1680
1681 /**
1682  * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1683  *
1684  * Checks if there a difference between the two states
1685  * that would require a mode change.
1686  *
1687  * Does not compare cursor position or attributes.
1688  */
1689 bool dc_is_stream_unchanged(
1690         struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1691 {
1692
1693         if (!are_stream_backends_same(old_stream, stream))
1694                 return false;
1695
1696         if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1697                 return false;
1698
1699         return true;
1700 }
1701
1702 /**
1703  * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1704  */
1705 bool dc_is_stream_scaling_unchanged(
1706         struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1707 {
1708         if (old_stream == stream)
1709                 return true;
1710
1711         if (old_stream == NULL || stream == NULL)
1712                 return false;
1713
1714         if (memcmp(&old_stream->src,
1715                         &stream->src,
1716                         sizeof(struct rect)) != 0)
1717                 return false;
1718
1719         if (memcmp(&old_stream->dst,
1720                         &stream->dst,
1721                         sizeof(struct rect)) != 0)
1722                 return false;
1723
1724         return true;
1725 }
1726
1727 static void update_stream_engine_usage(
1728                 struct resource_context *res_ctx,
1729                 const struct resource_pool *pool,
1730                 struct stream_encoder *stream_enc,
1731                 bool acquired)
1732 {
1733         int i;
1734
1735         for (i = 0; i < pool->stream_enc_count; i++) {
1736                 if (pool->stream_enc[i] == stream_enc)
1737                         res_ctx->is_stream_enc_acquired[i] = acquired;
1738         }
1739 }
1740
1741 /* TODO: release audio object */
1742 void update_audio_usage(
1743                 struct resource_context *res_ctx,
1744                 const struct resource_pool *pool,
1745                 struct audio *audio,
1746                 bool acquired)
1747 {
1748         int i;
1749         for (i = 0; i < pool->audio_count; i++) {
1750                 if (pool->audios[i] == audio)
1751                         res_ctx->is_audio_acquired[i] = acquired;
1752         }
1753 }
1754
1755 static int acquire_first_free_pipe(
1756                 struct resource_context *res_ctx,
1757                 const struct resource_pool *pool,
1758                 struct dc_stream_state *stream)
1759 {
1760         int i;
1761
1762         for (i = 0; i < pool->pipe_count; i++) {
1763                 if (!res_ctx->pipe_ctx[i].stream) {
1764                         struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1765
1766                         pipe_ctx->stream_res.tg = pool->timing_generators[i];
1767                         pipe_ctx->plane_res.mi = pool->mis[i];
1768                         pipe_ctx->plane_res.hubp = pool->hubps[i];
1769                         pipe_ctx->plane_res.ipp = pool->ipps[i];
1770                         pipe_ctx->plane_res.xfm = pool->transforms[i];
1771                         pipe_ctx->plane_res.dpp = pool->dpps[i];
1772                         pipe_ctx->stream_res.opp = pool->opps[i];
1773                         if (pool->dpps[i])
1774                                 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
1775                         pipe_ctx->pipe_idx = i;
1776
1777
1778                         pipe_ctx->stream = stream;
1779                         return i;
1780                 }
1781         }
1782         return -1;
1783 }
1784
1785 static struct audio *find_first_free_audio(
1786                 struct resource_context *res_ctx,
1787                 const struct resource_pool *pool,
1788                 enum engine_id id,
1789                 enum dce_version dc_version)
1790 {
1791         int i, available_audio_count;
1792
1793         available_audio_count = pool->audio_count;
1794
1795         for (i = 0; i < available_audio_count; i++) {
1796                 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1797                         /*we have enough audio endpoint, find the matching inst*/
1798                         if (id != i)
1799                                 continue;
1800                         return pool->audios[i];
1801                 }
1802         }
1803
1804         /* use engine id to find free audio */
1805         if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1806                 return pool->audios[id];
1807         }
1808         /*not found the matching one, first come first serve*/
1809         for (i = 0; i < available_audio_count; i++) {
1810                 if (res_ctx->is_audio_acquired[i] == false) {
1811                         return pool->audios[i];
1812                 }
1813         }
1814         return 0;
1815 }
1816
1817 /**
1818  * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1819  */
1820 enum dc_status dc_add_stream_to_ctx(
1821                 struct dc *dc,
1822                 struct dc_state *new_ctx,
1823                 struct dc_stream_state *stream)
1824 {
1825         enum dc_status res;
1826         DC_LOGGER_INIT(dc->ctx->logger);
1827
1828         if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
1829                 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1830                 return DC_ERROR_UNEXPECTED;
1831         }
1832
1833         new_ctx->streams[new_ctx->stream_count] = stream;
1834         dc_stream_retain(stream);
1835         new_ctx->stream_count++;
1836
1837         res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1838         if (res != DC_OK)
1839                 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1840
1841         return res;
1842 }
1843
1844 /**
1845  * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1846  */
1847 enum dc_status dc_remove_stream_from_ctx(
1848                         struct dc *dc,
1849                         struct dc_state *new_ctx,
1850                         struct dc_stream_state *stream)
1851 {
1852         int i;
1853         struct dc_context *dc_ctx = dc->ctx;
1854         struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1855         struct pipe_ctx *odm_pipe;
1856
1857         if (!del_pipe) {
1858                 DC_ERROR("Pipe not found for stream %p !\n", stream);
1859                 return DC_ERROR_UNEXPECTED;
1860         }
1861
1862         odm_pipe = del_pipe->next_odm_pipe;
1863
1864         /* Release primary pipe */
1865         ASSERT(del_pipe->stream_res.stream_enc);
1866         update_stream_engine_usage(
1867                         &new_ctx->res_ctx,
1868                                 dc->res_pool,
1869                         del_pipe->stream_res.stream_enc,
1870                         false);
1871
1872         if (del_pipe->stream_res.audio)
1873                 update_audio_usage(
1874                         &new_ctx->res_ctx,
1875                         dc->res_pool,
1876                         del_pipe->stream_res.audio,
1877                         false);
1878
1879         resource_unreference_clock_source(&new_ctx->res_ctx,
1880                                           dc->res_pool,
1881                                           del_pipe->clock_source);
1882
1883         if (dc->res_pool->funcs->remove_stream_from_ctx)
1884                 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
1885
1886         while (odm_pipe) {
1887                 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1888
1889                 memset(odm_pipe, 0, sizeof(*odm_pipe));
1890                 odm_pipe = next_odm_pipe;
1891         }
1892         memset(del_pipe, 0, sizeof(*del_pipe));
1893
1894         for (i = 0; i < new_ctx->stream_count; i++)
1895                 if (new_ctx->streams[i] == stream)
1896                         break;
1897
1898         if (new_ctx->streams[i] != stream) {
1899                 DC_ERROR("Context doesn't have stream %p !\n", stream);
1900                 return DC_ERROR_UNEXPECTED;
1901         }
1902
1903         dc_stream_release(new_ctx->streams[i]);
1904         new_ctx->stream_count--;
1905
1906         /* Trim back arrays */
1907         for (; i < new_ctx->stream_count; i++) {
1908                 new_ctx->streams[i] = new_ctx->streams[i + 1];
1909                 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
1910         }
1911
1912         new_ctx->streams[new_ctx->stream_count] = NULL;
1913         memset(
1914                         &new_ctx->stream_status[new_ctx->stream_count],
1915                         0,
1916                         sizeof(new_ctx->stream_status[0]));
1917
1918         return DC_OK;
1919 }
1920
1921 static struct dc_stream_state *find_pll_sharable_stream(
1922                 struct dc_stream_state *stream_needs_pll,
1923                 struct dc_state *context)
1924 {
1925         int i;
1926
1927         for (i = 0; i < context->stream_count; i++) {
1928                 struct dc_stream_state *stream_has_pll = context->streams[i];
1929
1930                 /* We are looking for non dp, non virtual stream */
1931                 if (resource_are_streams_timing_synchronizable(
1932                         stream_needs_pll, stream_has_pll)
1933                         && !dc_is_dp_signal(stream_has_pll->signal)
1934                         && stream_has_pll->link->connector_signal
1935                         != SIGNAL_TYPE_VIRTUAL)
1936                         return stream_has_pll;
1937
1938         }
1939
1940         return NULL;
1941 }
1942
1943 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
1944 {
1945         uint32_t pix_clk = timing->pix_clk_100hz;
1946         uint32_t normalized_pix_clk = pix_clk;
1947
1948         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1949                 pix_clk /= 2;
1950         if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
1951                 switch (timing->display_color_depth) {
1952                 case COLOR_DEPTH_666:
1953                 case COLOR_DEPTH_888:
1954                         normalized_pix_clk = pix_clk;
1955                         break;
1956                 case COLOR_DEPTH_101010:
1957                         normalized_pix_clk = (pix_clk * 30) / 24;
1958                         break;
1959                 case COLOR_DEPTH_121212:
1960                         normalized_pix_clk = (pix_clk * 36) / 24;
1961                 break;
1962                 case COLOR_DEPTH_161616:
1963                         normalized_pix_clk = (pix_clk * 48) / 24;
1964                 break;
1965                 default:
1966                         ASSERT(0);
1967                 break;
1968                 }
1969         }
1970         return normalized_pix_clk;
1971 }
1972
1973 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
1974 {
1975         /* update actual pixel clock on all streams */
1976         if (dc_is_hdmi_signal(stream->signal))
1977                 stream->phy_pix_clk = get_norm_pix_clk(
1978                         &stream->timing) / 10;
1979         else
1980                 stream->phy_pix_clk =
1981                         stream->timing.pix_clk_100hz / 10;
1982
1983         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1984                 stream->phy_pix_clk *= 2;
1985 }
1986
1987 static int acquire_resource_from_hw_enabled_state(
1988                 struct resource_context *res_ctx,
1989                 const struct resource_pool *pool,
1990                 struct dc_stream_state *stream)
1991 {
1992         struct dc_link *link = stream->link;
1993         unsigned int i, inst, tg_inst = 0;
1994
1995         /* Check for enabled DIG to identify enabled display */
1996         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1997                 return -1;
1998
1999         inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2000
2001         if (inst == ENGINE_ID_UNKNOWN)
2002                 return -1;
2003
2004         for (i = 0; i < pool->stream_enc_count; i++) {
2005                 if (pool->stream_enc[i]->id == inst) {
2006                         tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2007                                 pool->stream_enc[i]);
2008                         break;
2009                 }
2010         }
2011
2012         // tg_inst not found
2013         if (i == pool->stream_enc_count)
2014                 return -1;
2015
2016         if (tg_inst >= pool->timing_generator_count)
2017                 return -1;
2018
2019         if (!res_ctx->pipe_ctx[tg_inst].stream) {
2020                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2021
2022                 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2023                 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
2024                 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
2025                 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
2026                 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
2027                 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
2028                 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
2029
2030                 if (pool->dpps[tg_inst]) {
2031                         pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
2032
2033                         // Read DPP->MPCC->OPP Pipe from HW State
2034                         if (pool->mpc->funcs->read_mpcc_state) {
2035                                 struct mpcc_state s = {0};
2036
2037                                 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2038
2039                                 if (s.dpp_id < MAX_MPCC)
2040                                         pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id;
2041
2042                                 if (s.bot_mpcc_id < MAX_MPCC)
2043                                         pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2044                                                         &pool->mpc->mpcc_array[s.bot_mpcc_id];
2045
2046                                 if (s.opp_id < MAX_OPP)
2047                                         pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2048                         }
2049                 }
2050                 pipe_ctx->pipe_idx = tg_inst;
2051
2052                 pipe_ctx->stream = stream;
2053                 return tg_inst;
2054         }
2055
2056         return -1;
2057 }
2058
2059 enum dc_status resource_map_pool_resources(
2060                 const struct dc  *dc,
2061                 struct dc_state *context,
2062                 struct dc_stream_state *stream)
2063 {
2064         const struct resource_pool *pool = dc->res_pool;
2065         int i;
2066         struct dc_context *dc_ctx = dc->ctx;
2067         struct pipe_ctx *pipe_ctx = NULL;
2068         int pipe_idx = -1;
2069         struct dc_bios *dcb = dc->ctx->dc_bios;
2070
2071         calculate_phy_pix_clks(stream);
2072
2073         /* TODO: Check Linux */
2074         if (dc->config.allow_seamless_boot_optimization &&
2075                         !dcb->funcs->is_accelerated_mode(dcb)) {
2076                 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
2077                         stream->apply_seamless_boot_optimization = true;
2078         }
2079
2080         if (stream->apply_seamless_boot_optimization)
2081                 pipe_idx = acquire_resource_from_hw_enabled_state(
2082                                 &context->res_ctx,
2083                                 pool,
2084                                 stream);
2085
2086         if (pipe_idx < 0)
2087                 /* acquire new resources */
2088                 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
2089
2090 #ifdef CONFIG_DRM_AMD_DC_DCN
2091         if (pipe_idx < 0)
2092                 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
2093 #endif
2094
2095         if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
2096                 return DC_NO_CONTROLLER_RESOURCE;
2097
2098         pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2099
2100         pipe_ctx->stream_res.stream_enc =
2101                 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
2102                         &context->res_ctx, pool, stream);
2103
2104         if (!pipe_ctx->stream_res.stream_enc)
2105                 return DC_NO_STREAM_ENC_RESOURCE;
2106
2107         update_stream_engine_usage(
2108                 &context->res_ctx, pool,
2109                 pipe_ctx->stream_res.stream_enc,
2110                 true);
2111
2112         /* TODO: Add check if ASIC support and EDID audio */
2113         if (!stream->converter_disable_audio &&
2114             dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
2115             stream->audio_info.mode_count && stream->audio_info.flags.all) {
2116                 pipe_ctx->stream_res.audio = find_first_free_audio(
2117                 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
2118
2119                 /*
2120                  * Audio assigned in order first come first get.
2121                  * There are asics which has number of audio
2122                  * resources less then number of pipes
2123                  */
2124                 if (pipe_ctx->stream_res.audio)
2125                         update_audio_usage(&context->res_ctx, pool,
2126                                            pipe_ctx->stream_res.audio, true);
2127         }
2128
2129         /* Add ABM to the resource if on EDP */
2130         if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
2131 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2132                 if (pool->abm)
2133                         pipe_ctx->stream_res.abm = pool->abm;
2134                 else
2135                         pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2136 #else
2137                 pipe_ctx->stream_res.abm = pool->abm;
2138 #endif
2139         }
2140
2141         for (i = 0; i < context->stream_count; i++)
2142                 if (context->streams[i] == stream) {
2143                         context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2144                         context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
2145                         context->stream_status[i].audio_inst =
2146                                 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2147
2148                         return DC_OK;
2149                 }
2150
2151         DC_ERROR("Stream %p not found in new ctx!\n", stream);
2152         return DC_ERROR_UNEXPECTED;
2153 }
2154
2155 /**
2156  * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2157  * Is a shallow copy.  Increments refcounts on existing streams and planes.
2158  * @dc: copy out of dc->current_state
2159  * @dst_ctx: copy into this
2160  */
2161 void dc_resource_state_copy_construct_current(
2162                 const struct dc *dc,
2163                 struct dc_state *dst_ctx)
2164 {
2165         dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2166 }
2167
2168
2169 void dc_resource_state_construct(
2170                 const struct dc *dc,
2171                 struct dc_state *dst_ctx)
2172 {
2173         dst_ctx->clk_mgr = dc->clk_mgr;
2174 }
2175
2176
2177 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2178 {
2179         return dc->res_pool->res_cap->num_dsc > 0;
2180 }
2181
2182
2183 /**
2184  * dc_validate_global_state() - Determine if HW can support a given state
2185  * Checks HW resource availability and bandwidth requirement.
2186  * @dc: dc struct for this driver
2187  * @new_ctx: state to be validated
2188  * @fast_validate: set to true if only yes/no to support matters
2189  *
2190  * Return: DC_OK if the result can be programmed.  Otherwise, an error code.
2191  */
2192 enum dc_status dc_validate_global_state(
2193                 struct dc *dc,
2194                 struct dc_state *new_ctx,
2195                 bool fast_validate)
2196 {
2197         enum dc_status result = DC_ERROR_UNEXPECTED;
2198         int i, j;
2199
2200         if (!new_ctx)
2201                 return DC_ERROR_UNEXPECTED;
2202
2203         if (dc->res_pool->funcs->validate_global) {
2204                 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2205                 if (result != DC_OK)
2206                         return result;
2207         }
2208
2209         for (i = 0; i < new_ctx->stream_count; i++) {
2210                 struct dc_stream_state *stream = new_ctx->streams[i];
2211
2212                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2213                         struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2214
2215                         if (pipe_ctx->stream != stream)
2216                                 continue;
2217
2218                         if (dc->res_pool->funcs->patch_unknown_plane_state &&
2219                                         pipe_ctx->plane_state &&
2220                                         pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2221                                 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
2222                                 if (result != DC_OK)
2223                                         return result;
2224                         }
2225
2226                         /* Switch to dp clock source only if there is
2227                          * no non dp stream that shares the same timing
2228                          * with the dp stream.
2229                          */
2230                         if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2231                                 !find_pll_sharable_stream(stream, new_ctx)) {
2232
2233                                 resource_unreference_clock_source(
2234                                                 &new_ctx->res_ctx,
2235                                                 dc->res_pool,
2236                                                 pipe_ctx->clock_source);
2237
2238                                 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2239                                 resource_reference_clock_source(
2240                                                 &new_ctx->res_ctx,
2241                                                 dc->res_pool,
2242                                                  pipe_ctx->clock_source);
2243                         }
2244                 }
2245         }
2246
2247         result = resource_build_scaling_params_for_context(dc, new_ctx);
2248
2249         if (result == DC_OK)
2250                 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
2251                         result = DC_FAIL_BANDWIDTH_VALIDATE;
2252
2253         return result;
2254 }
2255
2256 static void patch_gamut_packet_checksum(
2257                 struct dc_info_packet *gamut_packet)
2258 {
2259         /* For gamut we recalc checksum */
2260         if (gamut_packet->valid) {
2261                 uint8_t chk_sum = 0;
2262                 uint8_t *ptr;
2263                 uint8_t i;
2264
2265                 /*start of the Gamut data. */
2266                 ptr = &gamut_packet->sb[3];
2267
2268                 for (i = 0; i <= gamut_packet->sb[1]; i++)
2269                         chk_sum += ptr[i];
2270
2271                 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
2272         }
2273 }
2274
2275 static void set_avi_info_frame(
2276                 struct dc_info_packet *info_packet,
2277                 struct pipe_ctx *pipe_ctx)
2278 {
2279         struct dc_stream_state *stream = pipe_ctx->stream;
2280         enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
2281         uint32_t pixel_encoding = 0;
2282         enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2283         enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2284         bool itc = false;
2285         uint8_t itc_value = 0;
2286         uint8_t cn0_cn1 = 0;
2287         unsigned int cn0_cn1_value = 0;
2288         uint8_t *check_sum = NULL;
2289         uint8_t byte_index = 0;
2290         union hdmi_info_packet hdmi_info;
2291         union display_content_support support = {0};
2292         unsigned int vic = pipe_ctx->stream->timing.vic;
2293         enum dc_timing_3d_format format;
2294
2295         memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2296
2297         color_space = pipe_ctx->stream->output_color_space;
2298         if (color_space == COLOR_SPACE_UNKNOWN)
2299                 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
2300                         COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
2301
2302         /* Initialize header */
2303         hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
2304         /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2305         * not be used in HDMI 2.0 (Section 10.1) */
2306         hdmi_info.bits.header.version = 2;
2307         hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
2308
2309         /*
2310          * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2311          * according to HDMI 2.0 spec (Section 10.1)
2312          */
2313
2314         switch (stream->timing.pixel_encoding) {
2315         case PIXEL_ENCODING_YCBCR422:
2316                 pixel_encoding = 1;
2317                 break;
2318
2319         case PIXEL_ENCODING_YCBCR444:
2320                 pixel_encoding = 2;
2321                 break;
2322         case PIXEL_ENCODING_YCBCR420:
2323                 pixel_encoding = 3;
2324                 break;
2325
2326         case PIXEL_ENCODING_RGB:
2327         default:
2328                 pixel_encoding = 0;
2329         }
2330
2331         /* Y0_Y1_Y2 : The pixel encoding */
2332         /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
2333         hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
2334
2335         /* A0 = 1 Active Format Information valid */
2336         hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
2337
2338         /* B0, B1 = 3; Bar info data is valid */
2339         hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
2340
2341         hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
2342
2343         /* S0, S1 : Underscan / Overscan */
2344         /* TODO: un-hardcode scan type */
2345         scan_type = SCANNING_TYPE_UNDERSCAN;
2346         hdmi_info.bits.S0_S1 = scan_type;
2347
2348         /* C0, C1 : Colorimetry */
2349         if (color_space == COLOR_SPACE_YCBCR709 ||
2350                         color_space == COLOR_SPACE_YCBCR709_LIMITED)
2351                 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
2352         else if (color_space == COLOR_SPACE_YCBCR601 ||
2353                         color_space == COLOR_SPACE_YCBCR601_LIMITED)
2354                 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
2355         else {
2356                 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
2357         }
2358         if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
2359                         color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2360                         color_space == COLOR_SPACE_2020_YCBCR) {
2361                 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2362                 hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
2363         } else if (color_space == COLOR_SPACE_ADOBERGB) {
2364                 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2365                 hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
2366         }
2367
2368         /* TODO: un-hardcode aspect ratio */
2369         aspect = stream->timing.aspect_ratio;
2370
2371         switch (aspect) {
2372         case ASPECT_RATIO_4_3:
2373         case ASPECT_RATIO_16_9:
2374                 hdmi_info.bits.M0_M1 = aspect;
2375                 break;
2376
2377         case ASPECT_RATIO_NO_DATA:
2378         case ASPECT_RATIO_64_27:
2379         case ASPECT_RATIO_256_135:
2380         default:
2381                 hdmi_info.bits.M0_M1 = 0;
2382         }
2383
2384         /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
2385         hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
2386
2387         /* TODO: un-hardcode cn0_cn1 and itc */
2388
2389         cn0_cn1 = 0;
2390         cn0_cn1_value = 0;
2391
2392         itc = true;
2393         itc_value = 1;
2394
2395         support = stream->content_support;
2396
2397         if (itc) {
2398                 if (!support.bits.valid_content_type) {
2399                         cn0_cn1_value = 0;
2400                 } else {
2401                         if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2402                                 if (support.bits.graphics_content == 1) {
2403                                         cn0_cn1_value = 0;
2404                                 }
2405                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2406                                 if (support.bits.photo_content == 1) {
2407                                         cn0_cn1_value = 1;
2408                                 } else {
2409                                         cn0_cn1_value = 0;
2410                                         itc_value = 0;
2411                                 }
2412                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2413                                 if (support.bits.cinema_content == 1) {
2414                                         cn0_cn1_value = 2;
2415                                 } else {
2416                                         cn0_cn1_value = 0;
2417                                         itc_value = 0;
2418                                 }
2419                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2420                                 if (support.bits.game_content == 1) {
2421                                         cn0_cn1_value = 3;
2422                                 } else {
2423                                         cn0_cn1_value = 0;
2424                                         itc_value = 0;
2425                                 }
2426                         }
2427                 }
2428                 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2429                 hdmi_info.bits.ITC = itc_value;
2430         }
2431
2432         /* TODO : We should handle YCC quantization */
2433         /* but we do not have matrix calculation */
2434         if (stream->qs_bit == 1 &&
2435                         stream->qy_bit == 1) {
2436                 if (color_space == COLOR_SPACE_SRGB ||
2437                         color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
2438                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
2439                         hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2440                 } else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2441                                         color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
2442                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_LIMITED_RANGE;
2443                         hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2444                 } else {
2445                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
2446                         hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2447                 }
2448         } else {
2449                 hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
2450                 hdmi_info.bits.YQ0_YQ1   = YYC_QUANTIZATION_LIMITED_RANGE;
2451         }
2452
2453         ///VIC
2454         format = stream->timing.timing_3d_format;
2455         /*todo, add 3DStereo support*/
2456         if (format != TIMING_3D_FORMAT_NONE) {
2457                 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
2458                 switch (pipe_ctx->stream->timing.hdmi_vic) {
2459                 case 1:
2460                         vic = 95;
2461                         break;
2462                 case 2:
2463                         vic = 94;
2464                         break;
2465                 case 3:
2466                         vic = 93;
2467                         break;
2468                 case 4:
2469                         vic = 98;
2470                         break;
2471                 default:
2472                         break;
2473                 }
2474         }
2475         /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
2476         hdmi_info.bits.VIC0_VIC7 = vic;
2477         if (vic >= 128)
2478                 hdmi_info.bits.header.version = 3;
2479         /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2480          * the Source shall use 20 AVI InfoFrame Version 4
2481          */
2482         if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2483                         hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2484                 hdmi_info.bits.header.version = 4;
2485                 hdmi_info.bits.header.length = 14;
2486         }
2487
2488         /* pixel repetition
2489          * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2490          * repetition start from 1 */
2491         hdmi_info.bits.PR0_PR3 = 0;
2492
2493         /* Bar Info
2494          * barTop:    Line Number of End of Top Bar.
2495          * barBottom: Line Number of Start of Bottom Bar.
2496          * barLeft:   Pixel Number of End of Left Bar.
2497          * barRight:  Pixel Number of Start of Right Bar. */
2498         hdmi_info.bits.bar_top = stream->timing.v_border_top;
2499         hdmi_info.bits.bar_bottom = (stream->timing.v_total
2500                         - stream->timing.v_border_bottom + 1);
2501         hdmi_info.bits.bar_left  = stream->timing.h_border_left;
2502         hdmi_info.bits.bar_right = (stream->timing.h_total
2503                         - stream->timing.h_border_right + 1);
2504
2505     /* Additional Colorimetry Extension
2506      * Used in conduction with C0-C1 and EC0-EC2
2507      * 0 = DCI-P3 RGB (D65)
2508      * 1 = DCI-P3 RGB (theater)
2509      */
2510         hdmi_info.bits.ACE0_ACE3 = 0;
2511
2512         /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2513         check_sum = &hdmi_info.packet_raw_data.sb[0];
2514
2515         *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
2516
2517         for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
2518                 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2519
2520         /* one byte complement */
2521         *check_sum = (uint8_t) (0x100 - *check_sum);
2522
2523         /* Store in hw_path_mode */
2524         info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2525         info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2526         info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2527
2528         for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2529                 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2530
2531         info_packet->valid = true;
2532 }
2533
2534 static void set_vendor_info_packet(
2535                 struct dc_info_packet *info_packet,
2536                 struct dc_stream_state *stream)
2537 {
2538         /* SPD info packet for FreeSync */
2539
2540         /* Check if Freesync is supported. Return if false. If true,
2541          * set the corresponding bit in the info packet
2542          */
2543         if (!stream->vsp_infopacket.valid)
2544                 return;
2545
2546         *info_packet = stream->vsp_infopacket;
2547 }
2548
2549 static void set_spd_info_packet(
2550                 struct dc_info_packet *info_packet,
2551                 struct dc_stream_state *stream)
2552 {
2553         /* SPD info packet for FreeSync */
2554
2555         /* Check if Freesync is supported. Return if false. If true,
2556          * set the corresponding bit in the info packet
2557          */
2558         if (!stream->vrr_infopacket.valid)
2559                 return;
2560
2561         *info_packet = stream->vrr_infopacket;
2562 }
2563
2564 static void set_hdr_static_info_packet(
2565                 struct dc_info_packet *info_packet,
2566                 struct dc_stream_state *stream)
2567 {
2568         /* HDR Static Metadata info packet for HDR10 */
2569
2570         if (!stream->hdr_static_metadata.valid ||
2571                         stream->use_dynamic_meta)
2572                 return;
2573
2574         *info_packet = stream->hdr_static_metadata;
2575 }
2576
2577 static void set_vsc_info_packet(
2578                 struct dc_info_packet *info_packet,
2579                 struct dc_stream_state *stream)
2580 {
2581         if (!stream->vsc_infopacket.valid)
2582                 return;
2583
2584         *info_packet = stream->vsc_infopacket;
2585 }
2586
2587 void dc_resource_state_destruct(struct dc_state *context)
2588 {
2589         int i, j;
2590
2591         for (i = 0; i < context->stream_count; i++) {
2592                 for (j = 0; j < context->stream_status[i].plane_count; j++)
2593                         dc_plane_state_release(
2594                                 context->stream_status[i].plane_states[j]);
2595
2596                 context->stream_status[i].plane_count = 0;
2597                 dc_stream_release(context->streams[i]);
2598                 context->streams[i] = NULL;
2599         }
2600 }
2601
2602 void dc_resource_state_copy_construct(
2603                 const struct dc_state *src_ctx,
2604                 struct dc_state *dst_ctx)
2605 {
2606         int i, j;
2607         struct kref refcount = dst_ctx->refcount;
2608
2609         *dst_ctx = *src_ctx;
2610
2611         for (i = 0; i < MAX_PIPES; i++) {
2612                 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2613
2614                 if (cur_pipe->top_pipe)
2615                         cur_pipe->top_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2616
2617                 if (cur_pipe->bottom_pipe)
2618                         cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2619
2620                 if (cur_pipe->next_odm_pipe)
2621                         cur_pipe->next_odm_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2622
2623                 if (cur_pipe->prev_odm_pipe)
2624                         cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2625         }
2626
2627         for (i = 0; i < dst_ctx->stream_count; i++) {
2628                 dc_stream_retain(dst_ctx->streams[i]);
2629                 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2630                         dc_plane_state_retain(
2631                                 dst_ctx->stream_status[i].plane_states[j]);
2632         }
2633
2634         /* context refcount should not be overridden */
2635         dst_ctx->refcount = refcount;
2636
2637 }
2638
2639 struct clock_source *dc_resource_find_first_free_pll(
2640                 struct resource_context *res_ctx,
2641                 const struct resource_pool *pool)
2642 {
2643         int i;
2644
2645         for (i = 0; i < pool->clk_src_count; ++i) {
2646                 if (res_ctx->clock_source_ref_count[i] == 0)
2647                         return pool->clock_sources[i];
2648         }
2649
2650         return NULL;
2651 }
2652
2653 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2654 {
2655         enum signal_type signal = SIGNAL_TYPE_NONE;
2656         struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
2657
2658         /* default all packets to invalid */
2659         info->avi.valid = false;
2660         info->gamut.valid = false;
2661         info->vendor.valid = false;
2662         info->spd.valid = false;
2663         info->hdrsmd.valid = false;
2664         info->vsc.valid = false;
2665
2666         signal = pipe_ctx->stream->signal;
2667
2668         /* HDMi and DP have different info packets*/
2669         if (dc_is_hdmi_signal(signal)) {
2670                 set_avi_info_frame(&info->avi, pipe_ctx);
2671
2672                 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2673
2674                 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2675
2676                 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2677
2678         } else if (dc_is_dp_signal(signal)) {
2679                 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2680
2681                 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2682
2683                 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2684         }
2685
2686         patch_gamut_packet_checksum(&info->gamut);
2687 }
2688
2689 enum dc_status resource_map_clock_resources(
2690                 const struct dc  *dc,
2691                 struct dc_state *context,
2692                 struct dc_stream_state *stream)
2693 {
2694         /* acquire new resources */
2695         const struct resource_pool *pool = dc->res_pool;
2696         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2697                                 &context->res_ctx, stream);
2698
2699         if (!pipe_ctx)
2700                 return DC_ERROR_UNEXPECTED;
2701
2702         if (dc_is_dp_signal(pipe_ctx->stream->signal)
2703                 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2704                 pipe_ctx->clock_source = pool->dp_clock_source;
2705         else {
2706                 pipe_ctx->clock_source = NULL;
2707
2708                 if (!dc->config.disable_disp_pll_sharing)
2709                         pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
2710                                 &context->res_ctx,
2711                                 pipe_ctx);
2712
2713                 if (pipe_ctx->clock_source == NULL)
2714                         pipe_ctx->clock_source =
2715                                 dc_resource_find_first_free_pll(
2716                                         &context->res_ctx,
2717                                         pool);
2718         }
2719
2720         if (pipe_ctx->clock_source == NULL)
2721                 return DC_NO_CLOCK_SOURCE_RESOURCE;
2722
2723         resource_reference_clock_source(
2724                 &context->res_ctx, pool,
2725                 pipe_ctx->clock_source);
2726
2727         return DC_OK;
2728 }
2729
2730 /*
2731  * Note: We need to disable output if clock sources change,
2732  * since bios does optimization and doesn't apply if changing
2733  * PHY when not already disabled.
2734  */
2735 bool pipe_need_reprogram(
2736                 struct pipe_ctx *pipe_ctx_old,
2737                 struct pipe_ctx *pipe_ctx)
2738 {
2739         if (!pipe_ctx_old->stream)
2740                 return false;
2741
2742         if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2743                 return true;
2744
2745         if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2746                 return true;
2747
2748         if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
2749                 return true;
2750
2751         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2752                         && pipe_ctx_old->stream != pipe_ctx->stream)
2753                 return true;
2754
2755         if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
2756                 return true;
2757
2758         if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2759                 return true;
2760
2761         if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2762                 return true;
2763
2764         if (false == pipe_ctx_old->stream->link->link_state_valid &&
2765                 false == pipe_ctx_old->stream->dpms_off)
2766                 return true;
2767
2768         if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
2769                 return true;
2770
2771         return false;
2772 }
2773
2774 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
2775                 struct bit_depth_reduction_params *fmt_bit_depth)
2776 {
2777         enum dc_dither_option option = stream->dither_option;
2778         enum dc_pixel_encoding pixel_encoding =
2779                         stream->timing.pixel_encoding;
2780
2781         memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2782
2783         if (option == DITHER_OPTION_DEFAULT) {
2784                 switch (stream->timing.display_color_depth) {
2785                 case COLOR_DEPTH_666:
2786                         option = DITHER_OPTION_SPATIAL6;
2787                         break;
2788                 case COLOR_DEPTH_888:
2789                         option = DITHER_OPTION_SPATIAL8;
2790                         break;
2791                 case COLOR_DEPTH_101010:
2792                         option = DITHER_OPTION_SPATIAL10;
2793                         break;
2794                 default:
2795                         option = DITHER_OPTION_DISABLE;
2796                 }
2797         }
2798
2799         if (option == DITHER_OPTION_DISABLE)
2800                 return;
2801
2802         if (option == DITHER_OPTION_TRUN6) {
2803                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2804                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
2805         } else if (option == DITHER_OPTION_TRUN8 ||
2806                         option == DITHER_OPTION_TRUN8_SPATIAL6 ||
2807                         option == DITHER_OPTION_TRUN8_FM6) {
2808                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2809                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
2810         } else if (option == DITHER_OPTION_TRUN10        ||
2811                         option == DITHER_OPTION_TRUN10_SPATIAL6   ||
2812                         option == DITHER_OPTION_TRUN10_SPATIAL8   ||
2813                         option == DITHER_OPTION_TRUN10_FM8     ||
2814                         option == DITHER_OPTION_TRUN10_FM6     ||
2815                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2816                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2817                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2818         }
2819
2820         /* special case - Formatter can only reduce by 4 bits at most.
2821          * When reducing from 12 to 6 bits,
2822          * HW recommends we use trunc with round mode
2823          * (if we did nothing, trunc to 10 bits would be used)
2824          * note that any 12->10 bit reduction is ignored prior to DCE8,
2825          * as the input was 10 bits.
2826          */
2827         if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
2828                         option == DITHER_OPTION_SPATIAL6 ||
2829                         option == DITHER_OPTION_FM6) {
2830                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
2831                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
2832                 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
2833         }
2834
2835         /* spatial dither
2836          * note that spatial modes 1-3 are never used
2837          */
2838         if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM            ||
2839                         option == DITHER_OPTION_SPATIAL6 ||
2840                         option == DITHER_OPTION_TRUN10_SPATIAL6      ||
2841                         option == DITHER_OPTION_TRUN8_SPATIAL6) {
2842                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2843                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
2844                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2845                 fmt_bit_depth->flags.RGB_RANDOM =
2846                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2847         } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM            ||
2848                         option == DITHER_OPTION_SPATIAL8 ||
2849                         option == DITHER_OPTION_SPATIAL8_FM6        ||
2850                         option == DITHER_OPTION_TRUN10_SPATIAL8      ||
2851                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2852                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2853                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
2854                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2855                 fmt_bit_depth->flags.RGB_RANDOM =
2856                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2857         } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
2858                         option == DITHER_OPTION_SPATIAL10 ||
2859                         option == DITHER_OPTION_SPATIAL10_FM8 ||
2860                         option == DITHER_OPTION_SPATIAL10_FM6) {
2861                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
2862                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
2863                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
2864                 fmt_bit_depth->flags.RGB_RANDOM =
2865                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
2866         }
2867
2868         if (option == DITHER_OPTION_SPATIAL6 ||
2869                         option == DITHER_OPTION_SPATIAL8 ||
2870                         option == DITHER_OPTION_SPATIAL10) {
2871                 fmt_bit_depth->flags.FRAME_RANDOM = 0;
2872         } else {
2873                 fmt_bit_depth->flags.FRAME_RANDOM = 1;
2874         }
2875
2876         //////////////////////
2877         //// temporal dither
2878         //////////////////////
2879         if (option == DITHER_OPTION_FM6           ||
2880                         option == DITHER_OPTION_SPATIAL8_FM6     ||
2881                         option == DITHER_OPTION_SPATIAL10_FM6     ||
2882                         option == DITHER_OPTION_TRUN10_FM6     ||
2883                         option == DITHER_OPTION_TRUN8_FM6      ||
2884                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
2885                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2886                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
2887         } else if (option == DITHER_OPTION_FM8        ||
2888                         option == DITHER_OPTION_SPATIAL10_FM8  ||
2889                         option == DITHER_OPTION_TRUN10_FM8) {
2890                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2891                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
2892         } else if (option == DITHER_OPTION_FM10) {
2893                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
2894                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
2895         }
2896
2897         fmt_bit_depth->pixel_encoding = pixel_encoding;
2898 }
2899
2900 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
2901 {
2902         struct dc_link *link = stream->link;
2903         struct timing_generator *tg = dc->res_pool->timing_generators[0];
2904         enum dc_status res = DC_OK;
2905
2906         calculate_phy_pix_clks(stream);
2907
2908         if (!tg->funcs->validate_timing(tg, &stream->timing))
2909                 res = DC_FAIL_CONTROLLER_VALIDATE;
2910
2911         if (res == DC_OK) {
2912                 if (!link->link_enc->funcs->validate_output_with_stream(
2913                                                 link->link_enc, stream))
2914                         res = DC_FAIL_ENC_VALIDATE;
2915         }
2916
2917         /* TODO: validate audio ASIC caps, encoder */
2918
2919         if (res == DC_OK)
2920                 res = dc_link_validate_mode_timing(stream,
2921                       link,
2922                       &stream->timing);
2923
2924         return res;
2925 }
2926
2927 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
2928 {
2929         enum dc_status res = DC_OK;
2930
2931         /* TODO For now validates pixel format only */
2932         if (dc->res_pool->funcs->validate_plane)
2933                 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
2934
2935         return res;
2936 }
2937
2938 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
2939 {
2940         switch (format) {
2941         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2942                 return 8;
2943         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2944         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2945                 return 12;
2946         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2947         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2948         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2949         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2950                 return 16;
2951         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2952         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2953         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2954         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2955         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2956 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
2957         case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
2958         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2959 #endif
2960                 return 32;
2961         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2962         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2963         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2964                 return 64;
2965         default:
2966                 ASSERT_CRITICAL(false);
2967                 return -1;
2968         }
2969 }
2970 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
2971 {
2972         if (modes) {
2973                 if (modes->sample_rates.rate.RATE_192)
2974                         return 192000;
2975                 if (modes->sample_rates.rate.RATE_176_4)
2976                         return 176400;
2977                 if (modes->sample_rates.rate.RATE_96)
2978                         return 96000;
2979                 if (modes->sample_rates.rate.RATE_88_2)
2980                         return 88200;
2981                 if (modes->sample_rates.rate.RATE_48)
2982                         return 48000;
2983                 if (modes->sample_rates.rate.RATE_44_1)
2984                         return 44100;
2985                 if (modes->sample_rates.rate.RATE_32)
2986                         return 32000;
2987         }
2988         /*original logic when no audio info*/
2989         return 441000;
2990 }
2991
2992 void get_audio_check(struct audio_info *aud_modes,
2993         struct audio_check *audio_chk)
2994 {
2995         unsigned int i;
2996         unsigned int max_sample_rate = 0;
2997
2998         if (aud_modes) {
2999                 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
3000
3001                 audio_chk->max_audiosample_rate = 0;
3002                 for (i = 0; i < aud_modes->mode_count; i++) {
3003                         max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
3004                         if (audio_chk->max_audiosample_rate < max_sample_rate)
3005                                 audio_chk->max_audiosample_rate = max_sample_rate;
3006                         /*dts takes the same as type 2: AP = 0.25*/
3007                 }
3008                 /*check which one take more bandwidth*/
3009                 if (audio_chk->max_audiosample_rate > 192000)
3010                         audio_chk->audio_packet_type = 0x9;/*AP =1*/
3011                 audio_chk->acat = 0;/*not support*/
3012         }
3013 }
3014