drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17
  18 /*Travis*/
  19 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  20 /*Nutmeg*/
  21 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  22
  23 #define DC_LOGGER \
  24         link->ctx->logger
  25 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  26
  27 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
  28
  29         /* maximum pre emphasis level allowed for each voltage swing level*/
  30         static const enum dc_pre_emphasis
  31         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  32                                             PRE_EMPHASIS_LEVEL2,
  33                                             PRE_EMPHASIS_LEVEL1,
  34                                             PRE_EMPHASIS_DISABLED };
  35
  36 enum {
  37         POST_LT_ADJ_REQ_LIMIT = 6,
  38         POST_LT_ADJ_REQ_TIMEOUT = 200
  39 };
  40
  41 enum {
  42         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  43         /* to avoid infinite loop where-in the receiver
  44          * switches between different VS
  45          */
  46         LINK_TRAINING_MAX_CR_RETRY = 100
  47 };
  48
  49 static bool decide_fallback_link_setting(
  50                 struct dc_link_settings initial_link_settings,
  51                 struct dc_link_settings *current_link_setting,
  52                 enum link_training_result training_result);
  53 static struct dc_link_settings get_common_supported_link_settings(
  54                 struct dc_link_settings link_setting_a,
  55                 struct dc_link_settings link_setting_b);
  56
  57 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  58                 const struct dc_link_settings *link_settings)
  59 {
  60         union training_aux_rd_interval training_rd_interval;
  61         uint32_t wait_in_micro_secs = 100;
  62
  63         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  64         core_link_read_dpcd(
  65                         link,
  66                         DP_TRAINING_AUX_RD_INTERVAL,
  67                         (uint8_t *)&training_rd_interval,
  68                         sizeof(training_rd_interval));
  69         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  70                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  71         return wait_in_micro_secs;
  72 }
  73
  74 static uint32_t get_eq_training_aux_rd_interval(
  75         struct dc_link *link,
  76         const struct dc_link_settings *link_settings)
  77 {
  78         union training_aux_rd_interval training_rd_interval;
  79         uint32_t wait_in_micro_secs = 400;
  80
  81         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  82         /* overwrite the delay if rev > 1.1*/
  83         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  84                 /* DP 1.2 or later - retrieve delay through
  85                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  86                 core_link_read_dpcd(
  87                         link,
  88                         DP_TRAINING_AUX_RD_INTERVAL,
  89                         (uint8_t *)&training_rd_interval,
  90                         sizeof(training_rd_interval));
  91
  92                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  93                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  94         }
  95
  96         return wait_in_micro_secs;
  97 }
  98
  99 static void wait_for_training_aux_rd_interval(
 100         struct dc_link *link,
 101         uint32_t wait_in_micro_secs)
 102 {
 103         udelay(wait_in_micro_secs);
 104
 105         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 106                 __func__,
 107                 wait_in_micro_secs);
 108 }
 109
 110 static void dpcd_set_training_pattern(
 111         struct dc_link *link,
 112         union dpcd_training_pattern dpcd_pattern)
 113 {
 114         core_link_write_dpcd(
 115                 link,
 116                 DP_TRAINING_PATTERN_SET,
 117                 &dpcd_pattern.raw,
 118                 1);
 119
 120         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 121                 __func__,
 122                 DP_TRAINING_PATTERN_SET,
 123                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 124 }
 125
 126 static enum dc_dp_training_pattern decide_cr_training_pattern(
 127                 const struct dc_link_settings *link_settings)
 128 {
 129         return DP_TRAINING_PATTERN_SEQUENCE_1;
 130 }
 131
 132 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 133                 const struct dc_link_settings *link_settings)
 134 {
 135         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 136         struct encoder_feature_support *features = &link->link_enc->features;
 137         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 138
 139         if (features->flags.bits.IS_TPS3_CAPABLE)
 140                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 141
 142         if (features->flags.bits.IS_TPS4_CAPABLE)
 143                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 144
 145         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 146                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 147                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 148
 149         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 150                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 151                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 152
 153         return DP_TRAINING_PATTERN_SEQUENCE_2;
 154 }
 155
 156 static void dpcd_set_link_settings(
 157         struct dc_link *link,
 158         const struct link_training_settings *lt_settings)
 159 {
 160         uint8_t rate;
 161
 162         union down_spread_ctrl downspread = { {0} };
 163         union lane_count_set lane_count_set = { {0} };
 164
 165         downspread.raw = (uint8_t)
 166         (lt_settings->link_settings.link_spread);
 167
 168         lane_count_set.bits.LANE_COUNT_SET =
 169         lt_settings->link_settings.lane_count;
 170
 171         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 172         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 173
 174
 175         if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 176                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 177                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 178         }
 179
 180         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 181                 &downspread.raw, sizeof(downspread));
 182
 183         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 184                 &lane_count_set.raw, 1);
 185
 186         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 187                         lt_settings->link_settings.use_link_rate_set == true) {
 188                 rate = 0;
 189                 /* WA for some MUX chips that will power down with eDP and lose supported
 190                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 191                  * MUX chip gets link rate set back before link training.
 192                  */
 193                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 194                         uint8_t supported_link_rates[16];
 195
 196                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 197                                         supported_link_rates, sizeof(supported_link_rates));
 198                 }
 199                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 200                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 201                                 &lt_settings->link_settings.link_rate_set, 1);
 202         } else {
 203                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 204                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 205         }
 206
 207         if (rate) {
 208                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 209                         __func__,
 210                         DP_LINK_BW_SET,
 211                         lt_settings->link_settings.link_rate,
 212                         DP_LANE_COUNT_SET,
 213                         lt_settings->link_settings.lane_count,
 214                         lt_settings->enhanced_framing,
 215                         DP_DOWNSPREAD_CTRL,
 216                         lt_settings->link_settings.link_spread);
 217         } else {
 218                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 219                         __func__,
 220                         DP_LINK_RATE_SET,
 221                         lt_settings->link_settings.link_rate_set,
 222                         DP_LANE_COUNT_SET,
 223                         lt_settings->link_settings.lane_count,
 224                         lt_settings->enhanced_framing,
 225                         DP_DOWNSPREAD_CTRL,
 226                         lt_settings->link_settings.link_spread);
 227         }
 228 }
 229
 230 static enum dpcd_training_patterns
 231         dc_dp_training_pattern_to_dpcd_training_pattern(
 232         struct dc_link *link,
 233         enum dc_dp_training_pattern pattern)
 234 {
 235         enum dpcd_training_patterns dpcd_tr_pattern =
 236         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 237
 238         switch (pattern) {
 239         case DP_TRAINING_PATTERN_SEQUENCE_1:
 240                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 241                 break;
 242         case DP_TRAINING_PATTERN_SEQUENCE_2:
 243                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 244                 break;
 245         case DP_TRAINING_PATTERN_SEQUENCE_3:
 246                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 247                 break;
 248         case DP_TRAINING_PATTERN_SEQUENCE_4:
 249                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 250                 break;
 251         default:
 252                 ASSERT(0);
 253                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 254                         __func__, pattern);
 255                 break;
 256         }
 257
 258         return dpcd_tr_pattern;
 259 }
 260
 261 static uint8_t dc_dp_initialize_scrambling_data_symbols(
 262         struct dc_link *link,
 263         enum dc_dp_training_pattern pattern)
 264 {
 265         uint8_t disable_scrabled_data_symbols = 0;
 266
 267         switch (pattern) {
 268         case DP_TRAINING_PATTERN_SEQUENCE_1:
 269         case DP_TRAINING_PATTERN_SEQUENCE_2:
 270         case DP_TRAINING_PATTERN_SEQUENCE_3:
 271                 disable_scrabled_data_symbols = 1;
 272                 break;
 273         case DP_TRAINING_PATTERN_SEQUENCE_4:
 274                 disable_scrabled_data_symbols = 0;
 275                 break;
 276         default:
 277                 ASSERT(0);
 278                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 279                         __func__, pattern);
 280                 break;
 281         }
 282         return disable_scrabled_data_symbols;
 283 }
 284
 285 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 286 {
 287         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 288 }
 289
 290 static void dpcd_set_lt_pattern_and_lane_settings(
 291         struct dc_link *link,
 292         const struct link_training_settings *lt_settings,
 293         enum dc_dp_training_pattern pattern,
 294         uint32_t offset)
 295 {
 296         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 297
 298         uint32_t dpcd_base_lt_offset;
 299
 300         uint8_t dpcd_lt_buffer[5] = {0};
 301         union dpcd_training_pattern dpcd_pattern = { {0} };
 302         uint32_t lane;
 303         uint32_t size_in_bytes;
 304         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 305         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 306
 307         if (is_repeater(link, offset))
 308                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 309                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 310
 311         /*****************************************************************
 312         * DpcdAddress_TrainingPatternSet
 313         *****************************************************************/
 314         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 315                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 316
 317         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 318                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 319
 320         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 321                 = dpcd_pattern.raw;
 322
 323         if (is_repeater(link, offset)) {
 324                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 325                         __func__,
 326                         offset,
 327                         dpcd_base_lt_offset,
 328                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 329         } else {
 330                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 331                         __func__,
 332                         dpcd_base_lt_offset,
 333                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 334         }
 335         /*****************************************************************
 336         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 337         *****************************************************************/
 338         for (lane = 0; lane <
 339                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 340
 341                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 342                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 343                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 344                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 345
 346                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 347                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 348                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 349                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 350                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 351                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 352         }
 353
 354         /* concatenate everything into one buffer*/
 355
 356         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 357
 358          // 0x00103 - 0x00102
 359         memmove(
 360                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 361                 dpcd_lane,
 362                 size_in_bytes);
 363
 364         if (is_repeater(link, offset)) {
 365                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 366                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 367                         __func__,
 368                         offset,
 369                         dpcd_base_lt_offset,
 370                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 371                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 372                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 373                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 374         } else {
 375                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 376                         __func__,
 377                         dpcd_base_lt_offset,
 378                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 379                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 380                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 381                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 382         }
 383         if (edp_workaround) {
 384                 /* for eDP write in 2 parts because the 5-byte burst is
 385                 * causing issues on some eDP panels (EPR#366724)
 386                 */
 387                 core_link_write_dpcd(
 388                         link,
 389                         DP_TRAINING_PATTERN_SET,
 390                         &dpcd_pattern.raw,
 391                         sizeof(dpcd_pattern.raw));
 392
 393                 core_link_write_dpcd(
 394                         link,
 395                         DP_TRAINING_LANE0_SET,
 396                         (uint8_t *)(dpcd_lane),
 397                         size_in_bytes);
 398
 399                 } else
 400                 /* write it all in (1 + number-of-lanes)-byte burst*/
 401                         core_link_write_dpcd(
 402                                 link,
 403                                 dpcd_base_lt_offset,
 404                                 dpcd_lt_buffer,
 405                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 406
 407         link->cur_lane_setting = lt_settings->lane_settings[0];
 408 }
 409
 410 static bool is_cr_done(enum dc_lane_count ln_count,
 411         union lane_status *dpcd_lane_status)
 412 {
 413         uint32_t lane;
 414         /*LANEx_CR_DONE bits All 1's?*/
 415         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 416                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 417                         return false;
 418         }
 419         return true;
 420 }
 421
 422 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 423         union lane_status *dpcd_lane_status,
 424         union lane_align_status_updated *lane_status_updated)
 425 {
 426         uint32_t lane;
 427         if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
 428                 return false;
 429         else {
 430                 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 431                         if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
 432                                 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 433                                 return false;
 434                 }
 435         }
 436         return true;
 437 }
 438
 439 static void update_drive_settings(
 440                 struct link_training_settings *dest,
 441                 struct link_training_settings src)
 442 {
 443         uint32_t lane;
 444         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 445                 if (dest->voltage_swing == NULL)
 446                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 447                 else
 448                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 449
 450                 if (dest->pre_emphasis == NULL)
 451                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 452                 else
 453                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 454
 455                 if (dest->post_cursor2 == NULL)
 456                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 457                 else
 458                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 459         }
 460 }
 461
 462 static uint8_t get_nibble_at_index(const uint8_t *buf,
 463         uint32_t index)
 464 {
 465         uint8_t nibble;
 466         nibble = buf[index / 2];
 467
 468         if (index % 2)
 469                 nibble >>= 4;
 470         else
 471                 nibble &= 0x0F;
 472
 473         return nibble;
 474 }
 475
 476 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 477         enum dc_voltage_swing voltage)
 478 {
 479         enum dc_pre_emphasis pre_emphasis;
 480         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 481
 482         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 483                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 484
 485         return pre_emphasis;
 486
 487 }
 488
 489 static void find_max_drive_settings(
 490         const struct link_training_settings *link_training_setting,
 491         struct link_training_settings *max_lt_setting)
 492 {
 493         uint32_t lane;
 494         struct dc_lane_settings max_requested;
 495
 496         max_requested.VOLTAGE_SWING =
 497                 link_training_setting->
 498                 lane_settings[0].VOLTAGE_SWING;
 499         max_requested.PRE_EMPHASIS =
 500                 link_training_setting->
 501                 lane_settings[0].PRE_EMPHASIS;
 502         /*max_requested.postCursor2 =
 503          * link_training_setting->laneSettings[0].postCursor2;*/
 504
 505         /* Determine what the maximum of the requested settings are*/
 506         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 507                         lane++) {
 508                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 509                         max_requested.VOLTAGE_SWING)
 510
 511                         max_requested.VOLTAGE_SWING =
 512                         link_training_setting->
 513                         lane_settings[lane].VOLTAGE_SWING;
 514
 515                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 516                                 max_requested.PRE_EMPHASIS)
 517                         max_requested.PRE_EMPHASIS =
 518                         link_training_setting->
 519                         lane_settings[lane].PRE_EMPHASIS;
 520
 521                 /*
 522                 if (link_training_setting->laneSettings[lane].postCursor2 >
 523                  max_requested.postCursor2)
 524                 {
 525                 max_requested.postCursor2 =
 526                 link_training_setting->laneSettings[lane].postCursor2;
 527                 }
 528                 */
 529         }
 530
 531         /* make sure the requested settings are
 532          * not higher than maximum settings*/
 533         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 534                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 535
 536         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 537                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 538         /*
 539         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 540         max_requested.postCursor2 = PostCursor2_MaxLevel;
 541         */
 542
 543         /* make sure the pre-emphasis matches the voltage swing*/
 544         if (max_requested.PRE_EMPHASIS >
 545                 get_max_pre_emphasis_for_voltage_swing(
 546                         max_requested.VOLTAGE_SWING))
 547                 max_requested.PRE_EMPHASIS =
 548                 get_max_pre_emphasis_for_voltage_swing(
 549                         max_requested.VOLTAGE_SWING);
 550
 551         /*
 552          * Post Cursor2 levels are completely independent from
 553          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 554          * can only be applied to each allowable combination of voltage
 555          * swing and pre-emphasis levels */
 556          /* if ( max_requested.postCursor2 >
 557           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 558           *  max_requested.postCursor2 =
 559           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 560           */
 561
 562         max_lt_setting->link_settings.link_rate =
 563                 link_training_setting->link_settings.link_rate;
 564         max_lt_setting->link_settings.lane_count =
 565         link_training_setting->link_settings.lane_count;
 566         max_lt_setting->link_settings.link_spread =
 567                 link_training_setting->link_settings.link_spread;
 568
 569         for (lane = 0; lane <
 570                 link_training_setting->link_settings.lane_count;
 571                 lane++) {
 572                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 573                         max_requested.VOLTAGE_SWING;
 574                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 575                         max_requested.PRE_EMPHASIS;
 576                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 577                  * max_requested.postCursor2;
 578                  */
 579         }
 580
 581 }
 582
 583 static void get_lane_status_and_drive_settings(
 584         struct dc_link *link,
 585         const struct link_training_settings *link_training_setting,
 586         union lane_status *ln_status,
 587         union lane_align_status_updated *ln_status_updated,
 588         struct link_training_settings *req_settings,
 589         uint32_t offset)
 590 {
 591         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 592         uint8_t lane_adjust_offset = 4;
 593         unsigned int lane01_adjust_address;
 594         uint8_t dpcd_buf[6] = {0};
 595         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 596         struct link_training_settings request_settings = { {0} };
 597         uint32_t lane;
 598
 599         memset(req_settings, '\0', sizeof(struct link_training_settings));
 600
 601         if (is_repeater(link, offset)) {
 602                 lane01_status_address =
 603                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 604                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 605                 lane_adjust_offset = 3;
 606         }
 607
 608         core_link_read_dpcd(
 609                 link,
 610                 lane01_status_address,
 611                 (uint8_t *)(dpcd_buf),
 612                 sizeof(dpcd_buf));
 613
 614         for (lane = 0; lane <
 615                 (uint32_t)(link_training_setting->link_settings.lane_count);
 616                 lane++) {
 617
 618                 ln_status[lane].raw =
 619                         get_nibble_at_index(&dpcd_buf[0], lane);
 620                 dpcd_lane_adjust[lane].raw =
 621                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 622         }
 623
 624         ln_status_updated->raw = dpcd_buf[2];
 625
 626         if (is_repeater(link, offset)) {
 627                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 628                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 629                         __func__,
 630                         offset,
 631                         lane01_status_address, dpcd_buf[0],
 632                         lane01_status_address + 1, dpcd_buf[1]);
 633         } else {
 634                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 635                         __func__,
 636                         lane01_status_address, dpcd_buf[0],
 637                         lane01_status_address + 1, dpcd_buf[1]);
 638         }
 639         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 640
 641         if (is_repeater(link, offset))
 642                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 643                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 644
 645         if (is_repeater(link, offset)) {
 646                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 647                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 648                                         __func__,
 649                                         offset,
 650                                         lane01_adjust_address,
 651                                         dpcd_buf[lane_adjust_offset],
 652                                         lane01_adjust_address + 1,
 653                                         dpcd_buf[lane_adjust_offset + 1]);
 654         } else {
 655                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 656                         __func__,
 657                         lane01_adjust_address,
 658                         dpcd_buf[lane_adjust_offset],
 659                         lane01_adjust_address + 1,
 660                         dpcd_buf[lane_adjust_offset + 1]);
 661         }
 662
 663         /*copy to req_settings*/
 664         request_settings.link_settings.lane_count =
 665                 link_training_setting->link_settings.lane_count;
 666         request_settings.link_settings.link_rate =
 667                 link_training_setting->link_settings.link_rate;
 668         request_settings.link_settings.link_spread =
 669                 link_training_setting->link_settings.link_spread;
 670
 671         for (lane = 0; lane <
 672                 (uint32_t)(link_training_setting->link_settings.lane_count);
 673                 lane++) {
 674
 675                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 676                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 677                                 VOLTAGE_SWING_LANE);
 678                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 679                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 680                                 PRE_EMPHASIS_LANE);
 681         }
 682
 683         /*Note: for postcursor2, read adjusted
 684          * postcursor2 settings from*/
 685         /*DpcdAddress_AdjustRequestPostCursor2 =
 686          *0x020C (not implemented yet)*/
 687
 688         /* we find the maximum of the requested settings across all lanes*/
 689         /* and set this maximum for all lanes*/
 690         find_max_drive_settings(&request_settings, req_settings);
 691
 692         /* if post cursor 2 is needed in the future,
 693          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 694          */
 695
 696 }
 697
 698 static void dpcd_set_lane_settings(
 699         struct dc_link *link,
 700         const struct link_training_settings *link_training_setting,
 701         uint32_t offset)
 702 {
 703         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 704         uint32_t lane;
 705         unsigned int lane0_set_address;
 706
 707         lane0_set_address = DP_TRAINING_LANE0_SET;
 708
 709         if (is_repeater(link, offset))
 710                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 711                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 712
 713         for (lane = 0; lane <
 714                 (uint32_t)(link_training_setting->
 715                 link_settings.lane_count);
 716                 lane++) {
 717                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 718                         (uint8_t)(link_training_setting->
 719                         lane_settings[lane].VOLTAGE_SWING);
 720                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 721                         (uint8_t)(link_training_setting->
 722                         lane_settings[lane].PRE_EMPHASIS);
 723                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 724                         (link_training_setting->
 725                         lane_settings[lane].VOLTAGE_SWING ==
 726                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 727                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 728                         (link_training_setting->
 729                         lane_settings[lane].PRE_EMPHASIS ==
 730                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 731         }
 732
 733         core_link_write_dpcd(link,
 734                 lane0_set_address,
 735                 (uint8_t *)(dpcd_lane),
 736                 link_training_setting->link_settings.lane_count);
 737
 738         /*
 739         if (LTSettings.link.rate == LinkRate_High2)
 740         {
 741                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 742                 for ( uint32_t lane = 0;
 743                 lane < lane_count_DPMax; lane++)
 744                 {
 745                         dpcd_lane2[lane].bits.post_cursor2_set =
 746                         static_cast<unsigned char>(
 747                         LTSettings.laneSettings[lane].postCursor2);
 748                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 749                 }
 750                 m_pDpcdAccessSrv->WriteDpcdData(
 751                 DpcdAddress_Lane0Set2,
 752                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 753                 LTSettings.link.lanes);
 754         }
 755         */
 756
 757         if (is_repeater(link, offset)) {
 758                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 759                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 760                         __func__,
 761                         offset,
 762                         lane0_set_address,
 763                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 764                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 765                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 766                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 767
 768         } else {
 769                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 770                         __func__,
 771                         lane0_set_address,
 772                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 773                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 774                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 775                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 776         }
 777         link->cur_lane_setting = link_training_setting->lane_settings[0];
 778
 779 }
 780
 781 static bool is_max_vs_reached(
 782         const struct link_training_settings *lt_settings)
 783 {
 784         uint32_t lane;
 785         for (lane = 0; lane <
 786                 (uint32_t)(lt_settings->link_settings.lane_count);
 787                 lane++) {
 788                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 789                         == VOLTAGE_SWING_MAX_LEVEL)
 790                         return true;
 791         }
 792         return false;
 793
 794 }
 795
 796 static bool perform_post_lt_adj_req_sequence(
 797         struct dc_link *link,
 798         struct link_training_settings *lt_settings)
 799 {
 800         enum dc_lane_count lane_count =
 801         lt_settings->link_settings.lane_count;
 802
 803         uint32_t adj_req_count;
 804         uint32_t adj_req_timer;
 805         bool req_drv_setting_changed;
 806         uint32_t lane;
 807
 808         req_drv_setting_changed = false;
 809         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 810         adj_req_count++) {
 811
 812                 req_drv_setting_changed = false;
 813
 814                 for (adj_req_timer = 0;
 815                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 816                         adj_req_timer++) {
 817
 818                         struct link_training_settings req_settings;
 819                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 820                         union lane_align_status_updated
 821                                 dpcd_lane_status_updated;
 822
 823                         get_lane_status_and_drive_settings(
 824                         link,
 825                         lt_settings,
 826                         dpcd_lane_status,
 827                         &dpcd_lane_status_updated,
 828                         &req_settings,
 829                         DPRX);
 830
 831                         if (dpcd_lane_status_updated.bits.
 832                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 833                                 return true;
 834
 835                         if (!is_cr_done(lane_count, dpcd_lane_status))
 836                                 return false;
 837
 838                         if (!is_ch_eq_done(
 839                                 lane_count,
 840                                 dpcd_lane_status,
 841                                 &dpcd_lane_status_updated))
 842                                 return false;
 843
 844                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 845
 846                                 if (lt_settings->
 847                                 lane_settings[lane].VOLTAGE_SWING !=
 848                                 req_settings.lane_settings[lane].
 849                                 VOLTAGE_SWING ||
 850                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 851                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 852
 853                                         req_drv_setting_changed = true;
 854                                         break;
 855                                 }
 856                         }
 857
 858                         if (req_drv_setting_changed) {
 859                                 update_drive_settings(
 860                                         lt_settings, req_settings);
 861
 862                                 dc_link_dp_set_drive_settings(link,
 863                                                 lt_settings);
 864                                 break;
 865                         }
 866
 867                         msleep(1);
 868                 }
 869
 870                 if (!req_drv_setting_changed) {
 871                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 872                                 __func__);
 873
 874                         ASSERT(0);
 875                         return true;
 876                 }
 877         }
 878         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 879                 __func__);
 880
 881         ASSERT(0);
 882         return true;
 883
 884 }
 885
 886 /* Only used for channel equalization */
 887 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 888 {
 889         unsigned int aux_rd_interval_us = 400;
 890
 891         switch (dpcd_aux_read_interval) {
 892         case 0x01:
 893                 aux_rd_interval_us = 4000;
 894                 break;
 895         case 0x02:
 896                 aux_rd_interval_us = 8000;
 897                 break;
 898         case 0x03:
 899                 aux_rd_interval_us = 12000;
 900                 break;
 901         case 0x04:
 902                 aux_rd_interval_us = 16000;
 903                 break;
 904         default:
 905                 break;
 906         }
 907
 908         return aux_rd_interval_us;
 909 }
 910
 911 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 912                                         union lane_status *dpcd_lane_status)
 913 {
 914         enum link_training_result result = LINK_TRAINING_SUCCESS;
 915
 916         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 917                 result = LINK_TRAINING_CR_FAIL_LANE0;
 918         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 919                 result = LINK_TRAINING_CR_FAIL_LANE1;
 920         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 921                 result = LINK_TRAINING_CR_FAIL_LANE23;
 922         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 923                 result = LINK_TRAINING_CR_FAIL_LANE23;
 924         return result;
 925 }
 926
 927 static enum link_training_result perform_channel_equalization_sequence(
 928         struct dc_link *link,
 929         struct link_training_settings *lt_settings,
 930         uint32_t offset)
 931 {
 932         struct link_training_settings req_settings;
 933         enum dc_dp_training_pattern tr_pattern;
 934         uint32_t retries_ch_eq;
 935         uint32_t wait_time_microsec;
 936         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 937         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 938         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 939
 940         /* Note: also check that TPS4 is a supported feature*/
 941
 942         tr_pattern = lt_settings->pattern_for_eq;
 943
 944         if (is_repeater(link, offset))
 945                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 946
 947         dp_set_hw_training_pattern(link, tr_pattern, offset);
 948
 949         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 950                 retries_ch_eq++) {
 951
 952                 dp_set_hw_lane_settings(link, lt_settings, offset);
 953
 954                 /* 2. update DPCD*/
 955                 if (!retries_ch_eq)
 956                         /* EPR #361076 - write as a 5-byte burst,
 957                          * but only for the 1-st iteration
 958                          */
 959
 960                         dpcd_set_lt_pattern_and_lane_settings(
 961                                 link,
 962                                 lt_settings,
 963                                 tr_pattern, offset);
 964                 else
 965                         dpcd_set_lane_settings(link, lt_settings, offset);
 966
 967                 /* 3. wait for receiver to lock-on*/
 968                 wait_time_microsec = lt_settings->eq_pattern_time;
 969
 970                 if (is_repeater(link, offset))
 971                         wait_time_microsec =
 972                                         translate_training_aux_read_interval(
 973                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 974
 975                 wait_for_training_aux_rd_interval(
 976                                 link,
 977                                 wait_time_microsec);
 978
 979                 /* 4. Read lane status and requested
 980                  * drive settings as set by the sink*/
 981
 982                 get_lane_status_and_drive_settings(
 983                         link,
 984                         lt_settings,
 985                         dpcd_lane_status,
 986                         &dpcd_lane_status_updated,
 987                         &req_settings,
 988                         offset);
 989
 990                 /* 5. check CR done*/
 991                 if (!is_cr_done(lane_count, dpcd_lane_status))
 992                         return LINK_TRAINING_EQ_FAIL_CR;
 993
 994                 /* 6. check CHEQ done*/
 995                 if (is_ch_eq_done(lane_count,
 996                         dpcd_lane_status,
 997                         &dpcd_lane_status_updated))
 998                         return LINK_TRAINING_SUCCESS;
 999
1000                 /* 7. update VS/PE/PC2 in lt_settings*/
1001                 update_drive_settings(lt_settings, req_settings);
1002         }
1003
1004         return LINK_TRAINING_EQ_FAIL_EQ;
1005
1006 }
1007 #define TRAINING_AUX_RD_INTERVAL 100 //us
1008
1009 static void start_clock_recovery_pattern_early(struct dc_link *link,
1010                 struct link_training_settings *lt_settings,
1011                 uint32_t offset)
1012 {
1013         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1014                         __func__);
1015         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1016         dp_set_hw_lane_settings(link, lt_settings, offset);
1017         udelay(400);
1018 }
1019
1020 static enum link_training_result perform_clock_recovery_sequence(
1021         struct dc_link *link,
1022         struct link_training_settings *lt_settings,
1023         uint32_t offset)
1024 {
1025         uint32_t retries_cr;
1026         uint32_t retry_count;
1027         uint32_t wait_time_microsec;
1028         struct link_training_settings req_settings;
1029         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1030         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1031         union lane_align_status_updated dpcd_lane_status_updated;
1032
1033         retries_cr = 0;
1034         retry_count = 0;
1035
1036         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1037                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1038
1039         /* najeeb - The synaptics MST hub can put the LT in
1040         * infinite loop by switching the VS
1041         */
1042         /* between level 0 and level 1 continuously, here
1043         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1044         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1045                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1046
1047                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1048                 memset(&dpcd_lane_status_updated, '\0',
1049                 sizeof(dpcd_lane_status_updated));
1050
1051                 /* 1. call HWSS to set lane settings*/
1052                 dp_set_hw_lane_settings(
1053                                 link,
1054                                 lt_settings,
1055                                 offset);
1056
1057                 /* 2. update DPCD of the receiver*/
1058                 if (!retry_count)
1059                         /* EPR #361076 - write as a 5-byte burst,
1060                          * but only for the 1-st iteration.*/
1061                         dpcd_set_lt_pattern_and_lane_settings(
1062                                         link,
1063                                         lt_settings,
1064                                         lt_settings->pattern_for_cr,
1065                                         offset);
1066                 else
1067                         dpcd_set_lane_settings(
1068                                         link,
1069                                         lt_settings,
1070                                         offset);
1071
1072                 /* 3. wait receiver to lock-on*/
1073                 wait_time_microsec = lt_settings->cr_pattern_time;
1074
1075                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1076                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1077
1078                 wait_for_training_aux_rd_interval(
1079                                 link,
1080                                 wait_time_microsec);
1081
1082                 /* 4. Read lane status and requested drive
1083                 * settings as set by the sink
1084                 */
1085                 get_lane_status_and_drive_settings(
1086                                 link,
1087                                 lt_settings,
1088                                 dpcd_lane_status,
1089                                 &dpcd_lane_status_updated,
1090                                 &req_settings,
1091                                 offset);
1092
1093                 /* 5. check CR done*/
1094                 if (is_cr_done(lane_count, dpcd_lane_status))
1095                         return LINK_TRAINING_SUCCESS;
1096
1097                 /* 6. max VS reached*/
1098                 if (is_max_vs_reached(lt_settings))
1099                         break;
1100
1101                 /* 7. same lane settings*/
1102                 /* Note: settings are the same for all lanes,
1103                  * so comparing first lane is sufficient*/
1104                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1105                         req_settings.lane_settings[0].VOLTAGE_SWING)
1106                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1107                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1108                         retries_cr++;
1109                 else
1110                         retries_cr = 0;
1111
1112                 /* 8. update VS/PE/PC2 in lt_settings*/
1113                 update_drive_settings(lt_settings, req_settings);
1114
1115                 retry_count++;
1116         }
1117
1118         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1119                 ASSERT(0);
1120                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1121                         __func__,
1122                         LINK_TRAINING_MAX_CR_RETRY);
1123
1124         }
1125
1126         return get_cr_failure(lane_count, dpcd_lane_status);
1127 }
1128
1129 static inline enum link_training_result perform_link_training_int(
1130         struct dc_link *link,
1131         struct link_training_settings *lt_settings,
1132         enum link_training_result status)
1133 {
1134         union lane_count_set lane_count_set = { {0} };
1135
1136         /* 4. mainlink output idle pattern*/
1137         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1138
1139         /*
1140          * 5. post training adjust if required
1141          * If the upstream DPTX and downstream DPRX both support TPS4,
1142          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1143          */
1144         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1145                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
1146                 return status;
1147
1148         if (status == LINK_TRAINING_SUCCESS &&
1149                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1150                 status = LINK_TRAINING_LQA_FAIL;
1151
1152         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1153         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1154         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1155
1156         core_link_write_dpcd(
1157                 link,
1158                 DP_LANE_COUNT_SET,
1159                 &lane_count_set.raw,
1160                 sizeof(lane_count_set));
1161
1162         return status;
1163 }
1164
1165 static enum link_training_result check_link_loss_status(
1166         struct dc_link *link,
1167         const struct link_training_settings *link_training_setting)
1168 {
1169         enum link_training_result status = LINK_TRAINING_SUCCESS;
1170         union lane_status lane_status;
1171         uint8_t dpcd_buf[6] = {0};
1172         uint32_t lane;
1173
1174         core_link_read_dpcd(
1175                         link,
1176                         DP_SINK_COUNT,
1177                         (uint8_t *)(dpcd_buf),
1178                         sizeof(dpcd_buf));
1179
1180         /*parse lane status*/
1181         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1182                 /*
1183                  * check lanes status
1184                  */
1185                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1186
1187                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1188                         !lane_status.bits.CR_DONE_0 ||
1189                         !lane_status.bits.SYMBOL_LOCKED_0) {
1190                         /* if one of the channel equalization, clock
1191                          * recovery or symbol lock is dropped
1192                          * consider it as (link has been
1193                          * dropped) dp sink status has changed
1194                          */
1195                         status = LINK_TRAINING_LINK_LOSS;
1196                         break;
1197                 }
1198         }
1199
1200         return status;
1201 }
1202
1203 static void initialize_training_settings(
1204          struct dc_link *link,
1205         const struct dc_link_settings *link_setting,
1206         const struct dc_link_training_overrides *overrides,
1207         struct link_training_settings *lt_settings)
1208 {
1209         uint32_t lane;
1210
1211         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1212
1213         /* Initialize link settings */
1214         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1215         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1216
1217         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1218                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1219         else
1220                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1221
1222         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1223                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1224         else
1225                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1226
1227         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1228
1229         /* TODO hard coded to SS for now
1230          * lt_settings.link_settings.link_spread =
1231          * dal_display_path_is_ss_supported(
1232          * path_mode->display_path) ?
1233          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1234          * LINK_SPREAD_DISABLED;
1235          */
1236         /* Initialize link spread */
1237         if (link->dp_ss_off)
1238                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1239         else if (overrides->downspread != NULL)
1240                 lt_settings->link_settings.link_spread
1241                         = *overrides->downspread
1242                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1243                         : LINK_SPREAD_DISABLED;
1244         else
1245                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1246
1247         /* Initialize lane settings overrides */
1248         if (overrides->voltage_swing != NULL)
1249                 lt_settings->voltage_swing = overrides->voltage_swing;
1250
1251         if (overrides->pre_emphasis != NULL)
1252                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1253
1254         if (overrides->post_cursor2 != NULL)
1255                 lt_settings->post_cursor2 = overrides->post_cursor2;
1256
1257         /* Initialize lane settings (VS/PE/PC2) */
1258         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1259                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1260                         lt_settings->voltage_swing != NULL ?
1261                         *lt_settings->voltage_swing :
1262                         VOLTAGE_SWING_LEVEL0;
1263                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1264                         lt_settings->pre_emphasis != NULL ?
1265                         *lt_settings->pre_emphasis
1266                         : PRE_EMPHASIS_DISABLED;
1267                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1268                         lt_settings->post_cursor2 != NULL ?
1269                         *lt_settings->post_cursor2
1270                         : POST_CURSOR2_DISABLED;
1271         }
1272
1273         /* Initialize training timings */
1274         if (overrides->cr_pattern_time != NULL)
1275                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1276         else
1277                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1278
1279         if (overrides->eq_pattern_time != NULL)
1280                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1281         else
1282                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1283
1284         if (overrides->pattern_for_cr != NULL)
1285                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1286         else
1287                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1288         if (overrides->pattern_for_eq != NULL)
1289                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1290         else
1291                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1292
1293         if (overrides->enhanced_framing != NULL)
1294                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1295         else
1296                 lt_settings->enhanced_framing = 1;
1297 }
1298
1299 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1300 {
1301         switch (lttpr_repeater_count) {
1302         case 0x80: // 1 lttpr repeater
1303                 return 1;
1304         case 0x40: // 2 lttpr repeaters
1305                 return 2;
1306         case 0x20: // 3 lttpr repeaters
1307                 return 3;
1308         case 0x10: // 4 lttpr repeaters
1309                 return 4;
1310         case 0x08: // 5 lttpr repeaters
1311                 return 5;
1312         case 0x04: // 6 lttpr repeaters
1313                 return 6;
1314         case 0x02: // 7 lttpr repeaters
1315                 return 7;
1316         case 0x01: // 8 lttpr repeaters
1317                 return 8;
1318         default:
1319                 break;
1320         }
1321         return 0; // invalid value
1322 }
1323
1324 static void configure_lttpr_mode_transparent(struct dc_link *link)
1325 {
1326         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1327
1328         core_link_write_dpcd(link,
1329                         DP_PHY_REPEATER_MODE,
1330                         (uint8_t *)&repeater_mode,
1331                         sizeof(repeater_mode));
1332 }
1333
1334 static void configure_lttpr_mode_non_transparent(struct dc_link *link)
1335 {
1336         /* aux timeout is already set to extended */
1337         /* RESET/SET lttpr mode to enable non transparent mode */
1338         uint8_t repeater_cnt;
1339         uint32_t aux_interval_address;
1340         uint8_t repeater_id;
1341         enum dc_status result = DC_ERROR_UNEXPECTED;
1342         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1343
1344         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1345         result = core_link_write_dpcd(link,
1346                         DP_PHY_REPEATER_MODE,
1347                         (uint8_t *)&repeater_mode,
1348                         sizeof(repeater_mode));
1349
1350         if (result == DC_OK) {
1351                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1352         }
1353
1354         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1355
1356                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1357
1358                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1359                 result = core_link_write_dpcd(link,
1360                                 DP_PHY_REPEATER_MODE,
1361                                 (uint8_t *)&repeater_mode,
1362                                 sizeof(repeater_mode));
1363
1364                 if (result == DC_OK) {
1365                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1366                 }
1367
1368                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1369                 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1370                         aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1371                                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1372                         core_link_read_dpcd(
1373                                 link,
1374                                 aux_interval_address,
1375                                 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1376                                 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1377                         link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1378                 }
1379         }
1380 }
1381
1382 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1383 {
1384         union dpcd_training_pattern dpcd_pattern = { {0} };
1385
1386         const uint32_t dpcd_base_lt_offset =
1387                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1388                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1389         /* Set training not in progress*/
1390         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1391
1392         core_link_write_dpcd(
1393                 link,
1394                 dpcd_base_lt_offset,
1395                 &dpcd_pattern.raw,
1396                 1);
1397
1398         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1399                 __func__,
1400                 offset,
1401                 dpcd_base_lt_offset,
1402                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1403 }
1404
1405 static void print_status_message(
1406         struct dc_link *link,
1407         const struct link_training_settings *lt_settings,
1408         enum link_training_result status)
1409 {
1410         char *link_rate = "Unknown";
1411         char *lt_result = "Unknown";
1412         char *lt_spread = "Disabled";
1413
1414         switch (lt_settings->link_settings.link_rate) {
1415         case LINK_RATE_LOW:
1416                 link_rate = "RBR";
1417                 break;
1418         case LINK_RATE_RATE_2:
1419                 link_rate = "R2";
1420                 break;
1421         case LINK_RATE_RATE_3:
1422                 link_rate = "R3";
1423                 break;
1424         case LINK_RATE_HIGH:
1425                 link_rate = "HBR";
1426                 break;
1427         case LINK_RATE_RBR2:
1428                 link_rate = "RBR2";
1429                 break;
1430         case LINK_RATE_RATE_6:
1431                 link_rate = "R6";
1432                 break;
1433         case LINK_RATE_HIGH2:
1434                 link_rate = "HBR2";
1435                 break;
1436         case LINK_RATE_HIGH3:
1437                 link_rate = "HBR3";
1438                 break;
1439         default:
1440                 break;
1441         }
1442
1443         switch (status) {
1444         case LINK_TRAINING_SUCCESS:
1445                 lt_result = "pass";
1446                 break;
1447         case LINK_TRAINING_CR_FAIL_LANE0:
1448                 lt_result = "CR failed lane0";
1449                 break;
1450         case LINK_TRAINING_CR_FAIL_LANE1:
1451                 lt_result = "CR failed lane1";
1452                 break;
1453         case LINK_TRAINING_CR_FAIL_LANE23:
1454                 lt_result = "CR failed lane23";
1455                 break;
1456         case LINK_TRAINING_EQ_FAIL_CR:
1457                 lt_result = "CR failed in EQ";
1458                 break;
1459         case LINK_TRAINING_EQ_FAIL_EQ:
1460                 lt_result = "EQ failed";
1461                 break;
1462         case LINK_TRAINING_LQA_FAIL:
1463                 lt_result = "LQA failed";
1464                 break;
1465         case LINK_TRAINING_LINK_LOSS:
1466                 lt_result = "Link loss";
1467                 break;
1468         default:
1469                 break;
1470         }
1471
1472         switch (lt_settings->link_settings.link_spread) {
1473         case LINK_SPREAD_DISABLED:
1474                 lt_spread = "Disabled";
1475                 break;
1476         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1477                 lt_spread = "0.5% 30KHz";
1478                 break;
1479         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1480                 lt_spread = "0.5% 33KHz";
1481                 break;
1482         default:
1483                 break;
1484         }
1485
1486         /* Connectivity log: link training */
1487         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1488                                 link_rate,
1489                                 lt_settings->link_settings.lane_count,
1490                                 lt_result,
1491                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1492                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1493                                 lt_spread);
1494 }
1495
1496 void dc_link_dp_set_drive_settings(
1497         struct dc_link *link,
1498         struct link_training_settings *lt_settings)
1499 {
1500         /* program ASIC PHY settings*/
1501         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1502
1503         /* Notify DP sink the PHY settings from source */
1504         dpcd_set_lane_settings(link, lt_settings, DPRX);
1505 }
1506
1507 bool dc_link_dp_perform_link_training_skip_aux(
1508         struct dc_link *link,
1509         const struct dc_link_settings *link_setting)
1510 {
1511         struct link_training_settings lt_settings;
1512
1513         initialize_training_settings(
1514                         link,
1515                         link_setting,
1516                         &link->preferred_training_settings,
1517                         &lt_settings);
1518
1519         /* 1. Perform_clock_recovery_sequence. */
1520
1521         /* transmit training pattern for clock recovery */
1522         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1523
1524         /* call HWSS to set lane settings*/
1525         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1526
1527         /* wait receiver to lock-on*/
1528         wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1529
1530         /* 2. Perform_channel_equalization_sequence. */
1531
1532         /* transmit training pattern for channel equalization. */
1533         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1534
1535         /* call HWSS to set lane settings*/
1536         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1537
1538         /* wait receiver to lock-on. */
1539         wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1540
1541         /* 3. Perform_link_training_int. */
1542
1543         /* Mainlink output idle pattern. */
1544         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1545
1546         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1547
1548         return true;
1549 }
1550
1551 enum link_training_result dc_link_dp_perform_link_training(
1552         struct dc_link *link,
1553         const struct dc_link_settings *link_setting,
1554         bool skip_video_pattern)
1555 {
1556         enum link_training_result status = LINK_TRAINING_SUCCESS;
1557         struct link_training_settings lt_settings;
1558         union dpcd_training_pattern dpcd_pattern = { { 0 } };
1559
1560         bool fec_enable;
1561         uint8_t repeater_cnt;
1562         uint8_t repeater_id;
1563
1564         initialize_training_settings(
1565                         link,
1566                         link_setting,
1567                         &link->preferred_training_settings,
1568                         &lt_settings);
1569
1570         /* Configure lttpr mode */
1571         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1572                 configure_lttpr_mode_non_transparent(link);
1573         else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1574                 configure_lttpr_mode_transparent(link);
1575
1576         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1577                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1578
1579         /* 1. set link rate, lane count and spread. */
1580         dpcd_set_link_settings(link, &lt_settings);
1581
1582         if (link->preferred_training_settings.fec_enable != NULL)
1583                 fec_enable = *link->preferred_training_settings.fec_enable;
1584         else
1585                 fec_enable = true;
1586
1587         dp_set_fec_ready(link, fec_enable);
1588
1589         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1590
1591                 /* 2. perform link training (set link training done
1592                  *  to false is done as well)
1593                  */
1594                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1595
1596                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1597                                 repeater_id--) {
1598                         status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1599
1600                         if (status != LINK_TRAINING_SUCCESS)
1601                                 break;
1602
1603                         status = perform_channel_equalization_sequence(link,
1604                                         &lt_settings,
1605                                         repeater_id);
1606
1607                         if (status != LINK_TRAINING_SUCCESS)
1608                                 break;
1609
1610                         repeater_training_done(link, repeater_id);
1611                 }
1612         }
1613
1614         if (status == LINK_TRAINING_SUCCESS) {
1615                 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1616         if (status == LINK_TRAINING_SUCCESS) {
1617                 status = perform_channel_equalization_sequence(link,
1618                                         &lt_settings,
1619                                         DPRX);
1620                 }
1621         }
1622
1623         /* 3. set training not in progress*/
1624         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1625         dpcd_set_training_pattern(link, dpcd_pattern);
1626         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1627                 status = perform_link_training_int(link,
1628                                 &lt_settings,
1629                                 status);
1630         }
1631
1632         /* delay 5ms after Main Link output idle pattern and then check
1633          * DPCD 0202h.
1634          */
1635         if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1636                 msleep(5);
1637                 status = check_link_loss_status(link, &lt_settings);
1638         }
1639
1640         /* 6. print status message*/
1641         print_status_message(link, &lt_settings, status);
1642
1643         if (status != LINK_TRAINING_SUCCESS)
1644                 link->ctx->dc->debug_data.ltFailCount++;
1645
1646         return status;
1647 }
1648
1649 static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1650 {
1651         struct dc_link *link = stream->link;
1652         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1653 #ifdef CONFIG_DRM_AMD_DC_HDCP
1654         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1655 #endif
1656
1657         /* ASSR must be supported on the panel */
1658         if (panel_mode == DP_PANEL_MODE_DEFAULT)
1659                 return panel_mode;
1660
1661         /* eDP or internal DP only */
1662         if (link->connector_signal != SIGNAL_TYPE_EDP &&
1663                 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1664                  link->is_internal_display))
1665                 return DP_PANEL_MODE_DEFAULT;
1666
1667 #ifdef CONFIG_DRM_AMD_DC_HDCP
1668         if (cp_psp && cp_psp->funcs.enable_assr) {
1669                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1670                         /* since eDP implies ASSR on, change panel
1671                          * mode to disable ASSR
1672                          */
1673                         panel_mode = DP_PANEL_MODE_DEFAULT;
1674                 }
1675         } else
1676                 panel_mode = DP_PANEL_MODE_DEFAULT;
1677
1678 #else
1679         /* turn off ASSR if the implementation is not compiled in */
1680         panel_mode = DP_PANEL_MODE_DEFAULT;
1681 #endif
1682         return panel_mode;
1683 }
1684
1685 bool perform_link_training_with_retries(
1686         const struct dc_link_settings *link_setting,
1687         bool skip_video_pattern,
1688         int attempts,
1689         struct pipe_ctx *pipe_ctx,
1690         enum signal_type signal)
1691 {
1692         uint8_t j;
1693         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1694         struct dc_stream_state *stream = pipe_ctx->stream;
1695         struct dc_link *link = stream->link;
1696         enum dp_panel_mode panel_mode;
1697
1698         /* We need to do this before the link training to ensure the idle pattern in SST
1699          * mode will be sent right after the link training
1700          */
1701         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1702                                                         pipe_ctx->stream_res.stream_enc->id, true);
1703
1704         for (j = 0; j < attempts; ++j) {
1705
1706                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1707                         __func__, (unsigned int)j + 1, attempts);
1708
1709                 dp_enable_link_phy(
1710                         link,
1711                         signal,
1712                         pipe_ctx->clock_source->id,
1713                         link_setting);
1714
1715                 if (stream->sink_patches.dppowerup_delay > 0) {
1716                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1717
1718                         msleep(delay_dp_power_up_in_ms);
1719                 }
1720
1721                 panel_mode = try_enable_assr(stream);
1722                 dp_set_panel_mode(link, panel_mode);
1723                 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1724                          link->link_index,
1725                          panel_mode != DP_PANEL_MODE_DEFAULT);
1726
1727                 if (link->aux_access_disabled) {
1728                         dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1729                         return true;
1730                 } else {
1731                         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1732
1733                                 status = dc_link_dp_perform_link_training(
1734                                                                                 link,
1735                                                                                 link_setting,
1736                                                                                 skip_video_pattern);
1737                         if (status == LINK_TRAINING_SUCCESS)
1738                                 return true;
1739                 }
1740
1741                 /* latest link training still fail, skip delay and keep PHY on
1742                  */
1743                 if (j == (attempts - 1))
1744                         break;
1745
1746                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1747                         __func__, (unsigned int)j + 1, attempts);
1748
1749                 dp_disable_link_phy(link, signal);
1750
1751                 msleep(delay_between_attempts);
1752
1753                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1754         }
1755
1756         return false;
1757 }
1758
1759 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1760 {
1761         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1762         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1763
1764         if (dp_cs != NULL) {
1765                 dp_cs_id = dp_cs->id;
1766         } else {
1767                 /*
1768                  * dp clock source is not initialized for some reason.
1769                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1770                  */
1771                 ASSERT(dp_cs);
1772         }
1773
1774         return dp_cs_id;
1775 }
1776
1777 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1778 {
1779         if (mst_enable == false &&
1780                 link->type == dc_connection_mst_branch) {
1781                 /* Disable MST on link. Use only local sink. */
1782                 dp_disable_link_phy_mst(link, link->connector_signal);
1783
1784                 link->type = dc_connection_single;
1785                 link->local_sink = link->remote_sinks[0];
1786                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1787         } else if (mst_enable == true &&
1788                         link->type == dc_connection_single &&
1789                         link->remote_sinks[0] != NULL) {
1790                 /* Re-enable MST on link. */
1791                 dp_disable_link_phy(link, link->connector_signal);
1792                 dp_enable_mst_on_sink(link, true);
1793
1794                 link->type = dc_connection_mst_branch;
1795                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1796         }
1797 }
1798
1799 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1800 {
1801         /* Begin Sync LT. During this time,
1802          * DPCD:600h must not be powered down.
1803          */
1804         link->sync_lt_in_progress = true;
1805
1806         /*Clear any existing preferred settings.*/
1807         memset(&link->preferred_training_settings, 0,
1808                 sizeof(struct dc_link_training_overrides));
1809         memset(&link->preferred_link_setting, 0,
1810                 sizeof(struct dc_link_settings));
1811
1812         return true;
1813 }
1814
1815 enum link_training_result dc_link_dp_sync_lt_attempt(
1816     struct dc_link *link,
1817     struct dc_link_settings *link_settings,
1818     struct dc_link_training_overrides *lt_overrides)
1819 {
1820         struct link_training_settings lt_settings;
1821         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1822         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1823         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1824         bool fec_enable = false;
1825
1826         initialize_training_settings(
1827                 link,
1828                 link_settings,
1829                 lt_overrides,
1830                 &lt_settings);
1831
1832         /* Setup MST Mode */
1833         if (lt_overrides->mst_enable)
1834                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1835
1836         /* Disable link */
1837         dp_disable_link_phy(link, link->connector_signal);
1838
1839         /* Enable link */
1840         dp_cs_id = get_clock_source_id(link);
1841         dp_enable_link_phy(link, link->connector_signal,
1842                 dp_cs_id, link_settings);
1843
1844         /* Set FEC enable */
1845         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1846         dp_set_fec_ready(link, fec_enable);
1847
1848         if (lt_overrides->alternate_scrambler_reset) {
1849                 if (*lt_overrides->alternate_scrambler_reset)
1850                         panel_mode = DP_PANEL_MODE_EDP;
1851                 else
1852                         panel_mode = DP_PANEL_MODE_DEFAULT;
1853         } else
1854                 panel_mode = dp_get_panel_mode(link);
1855
1856         dp_set_panel_mode(link, panel_mode);
1857
1858         /* Attempt to train with given link training settings */
1859         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1860                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1861
1862         /* Set link rate, lane count and spread. */
1863         dpcd_set_link_settings(link, &lt_settings);
1864
1865         /* 2. perform link training (set link training done
1866          *  to false is done as well)
1867          */
1868         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1869         if (lt_status == LINK_TRAINING_SUCCESS) {
1870                 lt_status = perform_channel_equalization_sequence(link,
1871                                                 &lt_settings,
1872                                                 DPRX);
1873         }
1874
1875         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1876         /* 4. print status message*/
1877         print_status_message(link, &lt_settings, lt_status);
1878
1879         return lt_status;
1880 }
1881
1882 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1883 {
1884         /* If input parameter is set, shut down phy.
1885          * Still shouldn't turn off dp_receiver (DPCD:600h)
1886          */
1887         if (link_down == true) {
1888                 dp_disable_link_phy(link, link->connector_signal);
1889                 dp_set_fec_ready(link, false);
1890         }
1891
1892         link->sync_lt_in_progress = false;
1893         return true;
1894 }
1895
1896 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1897 {
1898         struct dc_link_settings max_link_cap = {0};
1899
1900         /* get max link encoder capability */
1901         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1902
1903         /* Lower link settings based on sink's link cap */
1904         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1905                 max_link_cap.lane_count =
1906                                 link->reported_link_cap.lane_count;
1907         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1908                 max_link_cap.link_rate =
1909                                 link->reported_link_cap.link_rate;
1910         if (link->reported_link_cap.link_spread <
1911                         max_link_cap.link_spread)
1912                 max_link_cap.link_spread =
1913                                 link->reported_link_cap.link_spread;
1914         /*
1915          * account for lttpr repeaters cap
1916          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1917          */
1918         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1919                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1920                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1921
1922                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1923                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1924
1925                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
1926                                                 __func__,
1927                                                 max_link_cap.lane_count,
1928                                                 max_link_cap.link_rate);
1929         }
1930         return max_link_cap;
1931 }
1932
1933 enum dc_status read_hpd_rx_irq_data(
1934         struct dc_link *link,
1935         union hpd_irq_data *irq_data)
1936 {
1937         static enum dc_status retval;
1938
1939         /* The HW reads 16 bytes from 200h on HPD,
1940          * but if we get an AUX_DEFER, the HW cannot retry
1941          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1942          * fail, so we now explicitly read 6 bytes which is
1943          * the req from the above mentioned test cases.
1944          *
1945          * For DP 1.4 we need to read those from 2002h range.
1946          */
1947         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1948                 retval = core_link_read_dpcd(
1949                         link,
1950                         DP_SINK_COUNT,
1951                         irq_data->raw,
1952                         sizeof(union hpd_irq_data));
1953         else {
1954                 /* Read 14 bytes in a single read and then copy only the required fields.
1955                  * This is more efficient than doing it in two separate AUX reads. */
1956
1957                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1958
1959                 retval = core_link_read_dpcd(
1960                         link,
1961                         DP_SINK_COUNT_ESI,
1962                         tmp,
1963                         sizeof(tmp));
1964
1965                 if (retval != DC_OK)
1966                         return retval;
1967
1968                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1969                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1970                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1971                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1972                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1973                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1974         }
1975
1976         return retval;
1977 }
1978
1979 static bool hpd_rx_irq_check_link_loss_status(
1980         struct dc_link *link,
1981         union hpd_irq_data *hpd_irq_dpcd_data)
1982 {
1983         uint8_t irq_reg_rx_power_state = 0;
1984         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1985         union lane_status lane_status;
1986         uint32_t lane;
1987         bool sink_status_changed;
1988         bool return_code;
1989
1990         sink_status_changed = false;
1991         return_code = false;
1992
1993         if (link->cur_link_settings.lane_count == 0)
1994                 return return_code;
1995
1996         /*1. Check that Link Status changed, before re-training.*/
1997
1998         /*parse lane status*/
1999         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2000                 /* check status of lanes 0,1
2001                  * changed DpcdAddress_Lane01Status (0x202)
2002                  */
2003                 lane_status.raw = get_nibble_at_index(
2004                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2005                         lane);
2006
2007                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2008                         !lane_status.bits.CR_DONE_0 ||
2009                         !lane_status.bits.SYMBOL_LOCKED_0) {
2010                         /* if one of the channel equalization, clock
2011                          * recovery or symbol lock is dropped
2012                          * consider it as (link has been
2013                          * dropped) dp sink status has changed
2014                          */
2015                         sink_status_changed = true;
2016                         break;
2017                 }
2018         }
2019
2020         /* Check interlane align.*/
2021         if (sink_status_changed ||
2022                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2023
2024                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2025
2026                 return_code = true;
2027
2028                 /*2. Check that we can handle interrupt: Not in FS DOS,
2029                  *  Not in "Display Timeout" state, Link is trained.
2030                  */
2031                 dpcd_result = core_link_read_dpcd(link,
2032                         DP_SET_POWER,
2033                         &irq_reg_rx_power_state,
2034                         sizeof(irq_reg_rx_power_state));
2035
2036                 if (dpcd_result != DC_OK) {
2037                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2038                                 __func__);
2039                 } else {
2040                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2041                                 return_code = false;
2042                 }
2043         }
2044
2045         return return_code;
2046 }
2047
2048 bool dp_verify_link_cap(
2049         struct dc_link *link,
2050         struct dc_link_settings *known_limit_link_setting,
2051         int *fail_count)
2052 {
2053         struct dc_link_settings max_link_cap = {0};
2054         struct dc_link_settings cur_link_setting = {0};
2055         struct dc_link_settings *cur = &cur_link_setting;
2056         struct dc_link_settings initial_link_settings = {0};
2057         bool success;
2058         bool skip_link_training;
2059         bool skip_video_pattern;
2060         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2061         enum link_training_result status;
2062         union hpd_irq_data irq_data;
2063
2064         if (link->dc->debug.skip_detection_link_training) {
2065                 link->verified_link_cap = *known_limit_link_setting;
2066                 return true;
2067         }
2068
2069         memset(&irq_data, 0, sizeof(irq_data));
2070         success = false;
2071         skip_link_training = false;
2072
2073         max_link_cap = get_max_link_cap(link);
2074
2075         /* Grant extended timeout request */
2076         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2077                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2078
2079                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2080         }
2081
2082         /* TODO implement override and monitor patch later */
2083
2084         /* try to train the link from high to low to
2085          * find the physical link capability
2086          */
2087         /* disable PHY done possible by BIOS, will be done by driver itself */
2088         dp_disable_link_phy(link, link->connector_signal);
2089
2090         dp_cs_id = get_clock_source_id(link);
2091
2092         /* link training starts with the maximum common settings
2093          * supported by both sink and ASIC.
2094          */
2095         initial_link_settings = get_common_supported_link_settings(
2096                         *known_limit_link_setting,
2097                         max_link_cap);
2098         cur_link_setting = initial_link_settings;
2099
2100         /* Temporary Renoir-specific workaround for SWDEV-215184;
2101          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2102          * so add extra cycle of enabling and disabling the PHY before first link training.
2103          */
2104         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2105                         link->dc->debug.usbc_combo_phy_reset_wa) {
2106                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2107                 dp_disable_link_phy(link, link->connector_signal);
2108         }
2109
2110         do {
2111                 skip_video_pattern = true;
2112
2113                 if (cur->link_rate == LINK_RATE_LOW)
2114                         skip_video_pattern = false;
2115
2116                 dp_enable_link_phy(
2117                                 link,
2118                                 link->connector_signal,
2119                                 dp_cs_id,
2120                                 cur);
2121
2122
2123                 if (skip_link_training)
2124                         success = true;
2125                 else {
2126                         status = dc_link_dp_perform_link_training(
2127                                                         link,
2128                                                         cur,
2129                                                         skip_video_pattern);
2130                         if (status == LINK_TRAINING_SUCCESS)
2131                                 success = true;
2132                         else
2133                                 (*fail_count)++;
2134                 }
2135
2136                 if (success) {
2137                         link->verified_link_cap = *cur;
2138                         udelay(1000);
2139                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2140                                 if (hpd_rx_irq_check_link_loss_status(
2141                                                 link,
2142                                                 &irq_data))
2143                                         (*fail_count)++;
2144                 }
2145                 /* always disable the link before trying another
2146                  * setting or before returning we'll enable it later
2147                  * based on the actual mode we're driving
2148                  */
2149                 dp_disable_link_phy(link, link->connector_signal);
2150         } while (!success && decide_fallback_link_setting(
2151                         initial_link_settings, cur, status));
2152
2153         /* Link Training failed for all Link Settings
2154          *  (Lane Count is still unknown)
2155          */
2156         if (!success) {
2157                 /* If all LT fails for all settings,
2158                  * set verified = failed safe (1 lane low)
2159                  */
2160                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2161                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2162
2163                 link->verified_link_cap.link_spread =
2164                 LINK_SPREAD_DISABLED;
2165         }
2166
2167
2168         return success;
2169 }
2170
2171 bool dp_verify_link_cap_with_retries(
2172         struct dc_link *link,
2173         struct dc_link_settings *known_limit_link_setting,
2174         int attempts)
2175 {
2176         uint8_t i = 0;
2177         bool success = false;
2178
2179         for (i = 0; i < attempts; i++) {
2180                 int fail_count = 0;
2181                 enum dc_connection_type type = dc_connection_none;
2182
2183                 memset(&link->verified_link_cap, 0,
2184                                 sizeof(struct dc_link_settings));
2185                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2186                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2187                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2188                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2189                         break;
2190                 } else if (dp_verify_link_cap(link,
2191                                 &link->reported_link_cap,
2192                                 &fail_count) && fail_count == 0) {
2193                         success = true;
2194                         break;
2195                 }
2196                 msleep(10);
2197         }
2198         return success;
2199 }
2200
2201 bool dp_verify_mst_link_cap(
2202         struct dc_link *link)
2203 {
2204         struct dc_link_settings max_link_cap = {0};
2205
2206         max_link_cap = get_max_link_cap(link);
2207         link->verified_link_cap = get_common_supported_link_settings(
2208                 link->reported_link_cap,
2209                 max_link_cap);
2210
2211         return true;
2212 }
2213
2214 static struct dc_link_settings get_common_supported_link_settings(
2215                 struct dc_link_settings link_setting_a,
2216                 struct dc_link_settings link_setting_b)
2217 {
2218         struct dc_link_settings link_settings = {0};
2219
2220         link_settings.lane_count =
2221                 (link_setting_a.lane_count <=
2222                         link_setting_b.lane_count) ?
2223                         link_setting_a.lane_count :
2224                         link_setting_b.lane_count;
2225         link_settings.link_rate =
2226                 (link_setting_a.link_rate <=
2227                         link_setting_b.link_rate) ?
2228                         link_setting_a.link_rate :
2229                         link_setting_b.link_rate;
2230         link_settings.link_spread = LINK_SPREAD_DISABLED;
2231
2232         /* in DP compliance test, DPR-120 may have
2233          * a random value in its MAX_LINK_BW dpcd field.
2234          * We map it to the maximum supported link rate that
2235          * is smaller than MAX_LINK_BW in this case.
2236          */
2237         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2238                 link_settings.link_rate = LINK_RATE_HIGH3;
2239         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2240                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2241                 link_settings.link_rate = LINK_RATE_HIGH2;
2242         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2243                         && link_settings.link_rate > LINK_RATE_HIGH) {
2244                 link_settings.link_rate = LINK_RATE_HIGH;
2245         } else if (link_settings.link_rate < LINK_RATE_HIGH
2246                         && link_settings.link_rate > LINK_RATE_LOW) {
2247                 link_settings.link_rate = LINK_RATE_LOW;
2248         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2249                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2250         }
2251
2252         return link_settings;
2253 }
2254
2255 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2256 {
2257         return lane_count <= LANE_COUNT_ONE;
2258 }
2259
2260 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2261 {
2262         return link_rate <= LINK_RATE_LOW;
2263 }
2264
2265 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2266 {
2267         switch (lane_count) {
2268         case LANE_COUNT_FOUR:
2269                 return LANE_COUNT_TWO;
2270         case LANE_COUNT_TWO:
2271                 return LANE_COUNT_ONE;
2272         case LANE_COUNT_ONE:
2273                 return LANE_COUNT_UNKNOWN;
2274         default:
2275                 return LANE_COUNT_UNKNOWN;
2276         }
2277 }
2278
2279 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2280 {
2281         switch (link_rate) {
2282         case LINK_RATE_HIGH3:
2283                 return LINK_RATE_HIGH2;
2284         case LINK_RATE_HIGH2:
2285                 return LINK_RATE_HIGH;
2286         case LINK_RATE_HIGH:
2287                 return LINK_RATE_LOW;
2288         case LINK_RATE_LOW:
2289                 return LINK_RATE_UNKNOWN;
2290         default:
2291                 return LINK_RATE_UNKNOWN;
2292         }
2293 }
2294
2295 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2296 {
2297         switch (lane_count) {
2298         case LANE_COUNT_ONE:
2299                 return LANE_COUNT_TWO;
2300         case LANE_COUNT_TWO:
2301                 return LANE_COUNT_FOUR;
2302         default:
2303                 return LANE_COUNT_UNKNOWN;
2304         }
2305 }
2306
2307 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2308 {
2309         switch (link_rate) {
2310         case LINK_RATE_LOW:
2311                 return LINK_RATE_HIGH;
2312         case LINK_RATE_HIGH:
2313                 return LINK_RATE_HIGH2;
2314         case LINK_RATE_HIGH2:
2315                 return LINK_RATE_HIGH3;
2316         default:
2317                 return LINK_RATE_UNKNOWN;
2318         }
2319 }
2320
2321 /*
2322  * function: set link rate and lane count fallback based
2323  * on current link setting and last link training result
2324  * return value:
2325  *                      true - link setting could be set
2326  *                      false - has reached minimum setting
2327  *                                      and no further fallback could be done
2328  */
2329 static bool decide_fallback_link_setting(
2330                 struct dc_link_settings initial_link_settings,
2331                 struct dc_link_settings *current_link_setting,
2332                 enum link_training_result training_result)
2333 {
2334         if (!current_link_setting)
2335                 return false;
2336
2337         switch (training_result) {
2338         case LINK_TRAINING_CR_FAIL_LANE0:
2339         case LINK_TRAINING_CR_FAIL_LANE1:
2340         case LINK_TRAINING_CR_FAIL_LANE23:
2341         case LINK_TRAINING_LQA_FAIL:
2342         {
2343                 if (!reached_minimum_link_rate
2344                                 (current_link_setting->link_rate)) {
2345                         current_link_setting->link_rate =
2346                                 reduce_link_rate(
2347                                         current_link_setting->link_rate);
2348                 } else if (!reached_minimum_lane_count
2349                                 (current_link_setting->lane_count)) {
2350                         current_link_setting->link_rate =
2351                                 initial_link_settings.link_rate;
2352                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2353                                 return false;
2354                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2355                                 current_link_setting->lane_count =
2356                                                 LANE_COUNT_ONE;
2357                         else if (training_result ==
2358                                         LINK_TRAINING_CR_FAIL_LANE23)
2359                                 current_link_setting->lane_count =
2360                                                 LANE_COUNT_TWO;
2361                         else
2362                                 current_link_setting->lane_count =
2363                                         reduce_lane_count(
2364                                         current_link_setting->lane_count);
2365                 } else {
2366                         return false;
2367                 }
2368                 break;
2369         }
2370         case LINK_TRAINING_EQ_FAIL_EQ:
2371         {
2372                 if (!reached_minimum_lane_count
2373                                 (current_link_setting->lane_count)) {
2374                         current_link_setting->lane_count =
2375                                 reduce_lane_count(
2376                                         current_link_setting->lane_count);
2377                 } else if (!reached_minimum_link_rate
2378                                 (current_link_setting->link_rate)) {
2379                         current_link_setting->link_rate =
2380                                 reduce_link_rate(
2381                                         current_link_setting->link_rate);
2382                 } else {
2383                         return false;
2384                 }
2385                 break;
2386         }
2387         case LINK_TRAINING_EQ_FAIL_CR:
2388         {
2389                 if (!reached_minimum_link_rate
2390                                 (current_link_setting->link_rate)) {
2391                         current_link_setting->link_rate =
2392                                 reduce_link_rate(
2393                                         current_link_setting->link_rate);
2394                 } else {
2395                         return false;
2396                 }
2397                 break;
2398         }
2399         default:
2400                 return false;
2401         }
2402         return true;
2403 }
2404
2405 bool dp_validate_mode_timing(
2406         struct dc_link *link,
2407         const struct dc_crtc_timing *timing)
2408 {
2409         uint32_t req_bw;
2410         uint32_t max_bw;
2411
2412         const struct dc_link_settings *link_setting;
2413
2414         /*always DP fail safe mode*/
2415         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2416                 timing->h_addressable == (uint32_t) 640 &&
2417                 timing->v_addressable == (uint32_t) 480)
2418                 return true;
2419
2420         link_setting = dc_link_get_link_cap(link);
2421
2422         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2423         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2424                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2425                 link_setting = &link->verified_link_cap;
2426         */
2427
2428         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2429         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2430
2431         if (req_bw <= max_bw) {
2432                 /* remember the biggest mode here, during
2433                  * initial link training (to get
2434                  * verified_link_cap), LS sends event about
2435                  * cannot train at reported cap to upper
2436                  * layer and upper layer will re-enumerate modes.
2437                  * this is not necessary if the lower
2438                  * verified_link_cap is enough to drive
2439                  * all the modes */
2440
2441                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2442                 /* if (flags.DYNAMIC_VALIDATION == 1)
2443                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2444                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2445                 return true;
2446         } else
2447                 return false;
2448 }
2449
2450 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2451 {
2452         struct dc_link_settings initial_link_setting = {
2453                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2454         struct dc_link_settings current_link_setting =
2455                         initial_link_setting;
2456         uint32_t link_bw;
2457
2458         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2459                 return false;
2460
2461         /* search for the minimum link setting that:
2462          * 1. is supported according to the link training result
2463          * 2. could support the b/w requested by the timing
2464          */
2465         while (current_link_setting.link_rate <=
2466                         link->verified_link_cap.link_rate) {
2467                 link_bw = dc_link_bandwidth_kbps(
2468                                 link,
2469                                 &current_link_setting);
2470                 if (req_bw <= link_bw) {
2471                         *link_setting = current_link_setting;
2472                         return true;
2473                 }
2474
2475                 if (current_link_setting.lane_count <
2476                                 link->verified_link_cap.lane_count) {
2477                         current_link_setting.lane_count =
2478                                         increase_lane_count(
2479                                                         current_link_setting.lane_count);
2480                 } else {
2481                         current_link_setting.link_rate =
2482                                         increase_link_rate(
2483                                                         current_link_setting.link_rate);
2484                         current_link_setting.lane_count =
2485                                         initial_link_setting.lane_count;
2486                 }
2487         }
2488
2489         return false;
2490 }
2491
2492 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2493 {
2494         struct dc_link_settings initial_link_setting;
2495         struct dc_link_settings current_link_setting;
2496         uint32_t link_bw;
2497
2498         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2499                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2500                 *link_setting = link->verified_link_cap;
2501                 return true;
2502         }
2503
2504         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2505         initial_link_setting.lane_count = LANE_COUNT_ONE;
2506         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2507         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2508         initial_link_setting.use_link_rate_set = true;
2509         initial_link_setting.link_rate_set = 0;
2510         current_link_setting = initial_link_setting;
2511
2512         /* search for the minimum link setting that:
2513          * 1. is supported according to the link training result
2514          * 2. could support the b/w requested by the timing
2515          */
2516         while (current_link_setting.link_rate <=
2517                         link->verified_link_cap.link_rate) {
2518                 link_bw = dc_link_bandwidth_kbps(
2519                                 link,
2520                                 &current_link_setting);
2521                 if (req_bw <= link_bw) {
2522                         *link_setting = current_link_setting;
2523                         return true;
2524                 }
2525
2526                 if (current_link_setting.lane_count <
2527                                 link->verified_link_cap.lane_count) {
2528                         current_link_setting.lane_count =
2529                                         increase_lane_count(
2530                                                         current_link_setting.lane_count);
2531                 } else {
2532                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2533                                 current_link_setting.link_rate_set++;
2534                                 current_link_setting.link_rate =
2535                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2536                                 current_link_setting.lane_count =
2537                                                                         initial_link_setting.lane_count;
2538                         } else
2539                                 break;
2540                 }
2541         }
2542         return false;
2543 }
2544
2545 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2546 {
2547         *link_setting = link->verified_link_cap;
2548         return true;
2549 }
2550
2551 void decide_link_settings(struct dc_stream_state *stream,
2552         struct dc_link_settings *link_setting)
2553 {
2554         struct dc_link *link;
2555         uint32_t req_bw;
2556
2557         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2558
2559         link = stream->link;
2560
2561         /* if preferred is specified through AMDDP, use it, if it's enough
2562          * to drive the mode
2563          */
2564         if (link->preferred_link_setting.lane_count !=
2565                         LANE_COUNT_UNKNOWN &&
2566                         link->preferred_link_setting.link_rate !=
2567                                         LINK_RATE_UNKNOWN) {
2568                 *link_setting =  link->preferred_link_setting;
2569                 return;
2570         }
2571
2572         /* MST doesn't perform link training for now
2573          * TODO: add MST specific link training routine
2574          */
2575         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2576                 if (decide_mst_link_settings(link, link_setting))
2577                         return;
2578         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2579                 if (decide_edp_link_settings(link, link_setting, req_bw))
2580                         return;
2581         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2582                 return;
2583
2584         BREAK_TO_DEBUGGER();
2585         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2586
2587         *link_setting = link->verified_link_cap;
2588 }
2589
2590 /*************************Short Pulse IRQ***************************/
2591 static bool allow_hpd_rx_irq(const struct dc_link *link)
2592 {
2593         /*
2594          * Don't handle RX IRQ unless one of following is met:
2595          * 1) The link is established (cur_link_settings != unknown)
2596          * 2) We kicked off MST detection
2597          * 3) We know we're dealing with an active dongle
2598          */
2599
2600         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2601                 (link->type == dc_connection_mst_branch) ||
2602                 is_dp_active_dongle(link))
2603                 return true;
2604
2605         return false;
2606 }
2607
2608 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2609 {
2610         union dpcd_psr_configuration psr_configuration;
2611
2612         if (!link->psr_settings.psr_feature_enabled)
2613                 return false;
2614
2615         dm_helpers_dp_read_dpcd(
2616                 link->ctx,
2617                 link,
2618                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2619                 &psr_configuration.raw,
2620                 sizeof(psr_configuration.raw));
2621
2622
2623         if (psr_configuration.bits.ENABLE) {
2624                 unsigned char dpcdbuf[3] = {0};
2625                 union psr_error_status psr_error_status;
2626                 union psr_sink_psr_status psr_sink_psr_status;
2627
2628                 dm_helpers_dp_read_dpcd(
2629                         link->ctx,
2630                         link,
2631                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2632                         (unsigned char *) dpcdbuf,
2633                         sizeof(dpcdbuf));
2634
2635                 /*DPCD 2006h   ERROR STATUS*/
2636                 psr_error_status.raw = dpcdbuf[0];
2637                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2638                 psr_sink_psr_status.raw = dpcdbuf[2];
2639
2640                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2641                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2642                                 psr_error_status.bits.VSC_SDP_ERROR) {
2643                         /* Acknowledge and clear error bits */
2644                         dm_helpers_dp_write_dpcd(
2645                                 link->ctx,
2646                                 link,
2647                                 8198,/*DpcdAddress_PSR_Error_Status*/
2648                                 &psr_error_status.raw,
2649                                 sizeof(psr_error_status.raw));
2650
2651                         /* PSR error, disable and re-enable PSR */
2652                         dc_link_set_psr_allow_active(link, false, true, false);
2653                         dc_link_set_psr_allow_active(link, true, true, false);
2654
2655                         return true;
2656                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2657                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2658                         /* No error is detect, PSR is active.
2659                          * We should return with IRQ_HPD handled without
2660                          * checking for loss of sync since PSR would have
2661                          * powered down main link.
2662                          */
2663                         return true;
2664                 }
2665         }
2666         return false;
2667 }
2668
2669 static void dp_test_send_link_training(struct dc_link *link)
2670 {
2671         struct dc_link_settings link_settings = {0};
2672
2673         core_link_read_dpcd(
2674                         link,
2675                         DP_TEST_LANE_COUNT,
2676                         (unsigned char *)(&link_settings.lane_count),
2677                         1);
2678         core_link_read_dpcd(
2679                         link,
2680                         DP_TEST_LINK_RATE,
2681                         (unsigned char *)(&link_settings.link_rate),
2682                         1);
2683
2684         /* Set preferred link settings */
2685         link->verified_link_cap.lane_count = link_settings.lane_count;
2686         link->verified_link_cap.link_rate = link_settings.link_rate;
2687
2688         dp_retrain_link_dp_test(link, &link_settings, false);
2689 }
2690
2691 /* TODO Raven hbr2 compliance eye output is unstable
2692  * (toggling on and off) with debugger break
2693  * This caueses intermittent PHY automation failure
2694  * Need to look into the root cause */
2695 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2696 {
2697         union phy_test_pattern dpcd_test_pattern;
2698         union lane_adjust dpcd_lane_adjustment[2];
2699         unsigned char dpcd_post_cursor_2_adjustment = 0;
2700         unsigned char test_80_bit_pattern[
2701                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2702                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2703         enum dp_test_pattern test_pattern;
2704         struct dc_link_training_settings link_settings;
2705         union lane_adjust dpcd_lane_adjust;
2706         unsigned int lane;
2707         struct link_training_settings link_training_settings;
2708         int i = 0;
2709
2710         dpcd_test_pattern.raw = 0;
2711         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2712         memset(&link_settings, 0, sizeof(link_settings));
2713
2714         /* get phy test pattern and pattern parameters from DP receiver */
2715         core_link_read_dpcd(
2716                         link,
2717                         DP_PHY_TEST_PATTERN,
2718                         &dpcd_test_pattern.raw,
2719                         sizeof(dpcd_test_pattern));
2720         core_link_read_dpcd(
2721                         link,
2722                         DP_ADJUST_REQUEST_LANE0_1,
2723                         &dpcd_lane_adjustment[0].raw,
2724                         sizeof(dpcd_lane_adjustment));
2725
2726         /*get post cursor 2 parameters
2727          * For DP 1.1a or eariler, this DPCD register's value is 0
2728          * For DP 1.2 or later:
2729          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2730          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2731          */
2732         core_link_read_dpcd(
2733                         link,
2734                         DP_ADJUST_REQUEST_POST_CURSOR2,
2735                         &dpcd_post_cursor_2_adjustment,
2736                         sizeof(dpcd_post_cursor_2_adjustment));
2737
2738         /* translate request */
2739         switch (dpcd_test_pattern.bits.PATTERN) {
2740         case PHY_TEST_PATTERN_D10_2:
2741                 test_pattern = DP_TEST_PATTERN_D102;
2742                 break;
2743         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2744                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2745                 break;
2746         case PHY_TEST_PATTERN_PRBS7:
2747                 test_pattern = DP_TEST_PATTERN_PRBS7;
2748                 break;
2749         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2750                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2751                 break;
2752         case PHY_TEST_PATTERN_CP2520_1:
2753                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2754                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2755                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2756                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2757                 break;
2758         case PHY_TEST_PATTERN_CP2520_2:
2759                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2760                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2761                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2762                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2763                 break;
2764         case PHY_TEST_PATTERN_CP2520_3:
2765                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2766                 break;
2767         default:
2768                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2769         break;
2770         }
2771
2772         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2773                 core_link_read_dpcd(
2774                                 link,
2775                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2776                                 test_80_bit_pattern,
2777                                 sizeof(test_80_bit_pattern));
2778
2779         /* prepare link training settings */
2780         link_settings.link = link->cur_link_settings;
2781
2782         for (lane = 0; lane <
2783                 (unsigned int)(link->cur_link_settings.lane_count);
2784                 lane++) {
2785                 dpcd_lane_adjust.raw =
2786                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2787                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2788                         (enum dc_voltage_swing)
2789                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2790                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2791                         (enum dc_pre_emphasis)
2792                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2793                 link_settings.lane_settings[lane].POST_CURSOR2 =
2794                         (enum dc_post_cursor2)
2795                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2796         }
2797
2798         for (i = 0; i < 4; i++)
2799                 link_training_settings.lane_settings[i] =
2800                                 link_settings.lane_settings[i];
2801         link_training_settings.link_settings = link_settings.link;
2802         link_training_settings.allow_invalid_msa_timing_param = false;
2803         /*Usage: Measure DP physical lane signal
2804          * by DP SI test equipment automatically.
2805          * PHY test pattern request is generated by equipment via HPD interrupt.
2806          * HPD needs to be active all the time. HPD should be active
2807          * all the time. Do not touch it.
2808          * forward request to DS
2809          */
2810         dc_link_dp_set_test_pattern(
2811                 link,
2812                 test_pattern,
2813                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2814                 &link_training_settings,
2815                 test_80_bit_pattern,
2816                 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2817                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2818 }
2819
2820 static void dp_test_send_link_test_pattern(struct dc_link *link)
2821 {
2822         union link_test_pattern dpcd_test_pattern;
2823         union test_misc dpcd_test_params;
2824         enum dp_test_pattern test_pattern;
2825         enum dp_test_pattern_color_space test_pattern_color_space =
2826                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2827         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2828         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2829         struct pipe_ctx *pipe_ctx = NULL;
2830         int i;
2831
2832         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2833         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2834
2835         for (i = 0; i < MAX_PIPES; i++) {
2836                 if (pipes[i].stream == NULL)
2837                         continue;
2838
2839                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2840                         pipe_ctx = &pipes[i];
2841                         break;
2842                 }
2843         }
2844
2845         if (pipe_ctx == NULL)
2846                 return;
2847
2848         /* get link test pattern and pattern parameters */
2849         core_link_read_dpcd(
2850                         link,
2851                         DP_TEST_PATTERN,
2852                         &dpcd_test_pattern.raw,
2853                         sizeof(dpcd_test_pattern));
2854         core_link_read_dpcd(
2855                         link,
2856                         DP_TEST_MISC0,
2857                         &dpcd_test_params.raw,
2858                         sizeof(dpcd_test_params));
2859
2860         switch (dpcd_test_pattern.bits.PATTERN) {
2861         case LINK_TEST_PATTERN_COLOR_RAMP:
2862                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2863         break;
2864         case LINK_TEST_PATTERN_VERTICAL_BARS:
2865                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2866         break; /* black and white */
2867         case LINK_TEST_PATTERN_COLOR_SQUARES:
2868                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2869                                 TEST_DYN_RANGE_VESA ?
2870                                 DP_TEST_PATTERN_COLOR_SQUARES :
2871                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2872         break;
2873         default:
2874                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2875         break;
2876         }
2877
2878         if (dpcd_test_params.bits.CLR_FORMAT == 0)
2879                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2880         else
2881                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2882                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2883                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2884
2885         switch (dpcd_test_params.bits.BPC) {
2886         case 0: // 6 bits
2887                 requestColorDepth = COLOR_DEPTH_666;
2888                 break;
2889         case 1: // 8 bits
2890                 requestColorDepth = COLOR_DEPTH_888;
2891                 break;
2892         case 2: // 10 bits
2893                 requestColorDepth = COLOR_DEPTH_101010;
2894                 break;
2895         case 3: // 12 bits
2896                 requestColorDepth = COLOR_DEPTH_121212;
2897                 break;
2898         default:
2899                 break;
2900         }
2901
2902         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
2903                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
2904                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
2905                                 __func__,
2906                                 pipe_ctx->stream->timing.display_color_depth,
2907                                 requestColorDepth);
2908                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
2909                 dp_update_dsc_config(pipe_ctx);
2910         }
2911
2912         dc_link_dp_set_test_pattern(
2913                         link,
2914                         test_pattern,
2915                         test_pattern_color_space,
2916                         NULL,
2917                         NULL,
2918                         0);
2919 }
2920
2921 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2922 {
2923         union audio_test_mode            dpcd_test_mode = {0};
2924         struct audio_test_pattern_type   dpcd_pattern_type = {0};
2925         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2926         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2927
2928         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2929         struct pipe_ctx *pipe_ctx = &pipes[0];
2930         unsigned int channel_count;
2931         unsigned int channel = 0;
2932         unsigned int modes = 0;
2933         unsigned int sampling_rate_in_hz = 0;
2934
2935         // get audio test mode and test pattern parameters
2936         core_link_read_dpcd(
2937                 link,
2938                 DP_TEST_AUDIO_MODE,
2939                 &dpcd_test_mode.raw,
2940                 sizeof(dpcd_test_mode));
2941
2942         core_link_read_dpcd(
2943                 link,
2944                 DP_TEST_AUDIO_PATTERN_TYPE,
2945                 &dpcd_pattern_type.value,
2946                 sizeof(dpcd_pattern_type));
2947
2948         channel_count = dpcd_test_mode.bits.channel_count + 1;
2949
2950         // read pattern periods for requested channels when sawTooth pattern is requested
2951         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2952                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2953
2954                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2955                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2956                 // read period for each channel
2957                 for (channel = 0; channel < channel_count; channel++) {
2958                         core_link_read_dpcd(
2959                                                         link,
2960                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
2961                                                         &dpcd_pattern_period[channel].raw,
2962                                                         sizeof(dpcd_pattern_period[channel]));
2963                 }
2964         }
2965
2966         // translate sampling rate
2967         switch (dpcd_test_mode.bits.sampling_rate) {
2968         case AUDIO_SAMPLING_RATE_32KHZ:
2969                 sampling_rate_in_hz = 32000;
2970                 break;
2971         case AUDIO_SAMPLING_RATE_44_1KHZ:
2972                 sampling_rate_in_hz = 44100;
2973                 break;
2974         case AUDIO_SAMPLING_RATE_48KHZ:
2975                 sampling_rate_in_hz = 48000;
2976                 break;
2977         case AUDIO_SAMPLING_RATE_88_2KHZ:
2978                 sampling_rate_in_hz = 88200;
2979                 break;
2980         case AUDIO_SAMPLING_RATE_96KHZ:
2981                 sampling_rate_in_hz = 96000;
2982                 break;
2983         case AUDIO_SAMPLING_RATE_176_4KHZ:
2984                 sampling_rate_in_hz = 176400;
2985                 break;
2986         case AUDIO_SAMPLING_RATE_192KHZ:
2987                 sampling_rate_in_hz = 192000;
2988                 break;
2989         default:
2990                 sampling_rate_in_hz = 0;
2991                 break;
2992         }
2993
2994         link->audio_test_data.flags.test_requested = 1;
2995         link->audio_test_data.flags.disable_video = disable_video;
2996         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2997         link->audio_test_data.channel_count = channel_count;
2998         link->audio_test_data.pattern_type = test_pattern;
2999
3000         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3001                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3002                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3003                 }
3004         }
3005 }
3006
3007 static void handle_automated_test(struct dc_link *link)
3008 {
3009         union test_request test_request;
3010         union test_response test_response;
3011
3012         memset(&test_request, 0, sizeof(test_request));
3013         memset(&test_response, 0, sizeof(test_response));
3014
3015         core_link_read_dpcd(
3016                 link,
3017                 DP_TEST_REQUEST,
3018                 &test_request.raw,
3019                 sizeof(union test_request));
3020         if (test_request.bits.LINK_TRAINING) {
3021                 /* ACK first to let DP RX test box monitor LT sequence */
3022                 test_response.bits.ACK = 1;
3023                 core_link_write_dpcd(
3024                         link,
3025                         DP_TEST_RESPONSE,
3026                         &test_response.raw,
3027                         sizeof(test_response));
3028                 dp_test_send_link_training(link);
3029                 /* no acknowledge request is needed again */
3030                 test_response.bits.ACK = 0;
3031         }
3032         if (test_request.bits.LINK_TEST_PATTRN) {
3033                 dp_test_send_link_test_pattern(link);
3034                 test_response.bits.ACK = 1;
3035         }
3036
3037         if (test_request.bits.AUDIO_TEST_PATTERN) {
3038                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3039                 test_response.bits.ACK = 1;
3040         }
3041
3042         if (test_request.bits.PHY_TEST_PATTERN) {
3043                 dp_test_send_phy_test_pattern(link);
3044                 test_response.bits.ACK = 1;
3045         }
3046
3047         /* send request acknowledgment */
3048         if (test_response.bits.ACK)
3049                 core_link_write_dpcd(
3050                         link,
3051                         DP_TEST_RESPONSE,
3052                         &test_response.raw,
3053                         sizeof(test_response));
3054 }
3055
3056 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3057 {
3058         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3059         union device_service_irq device_service_clear = { { 0 } };
3060         enum dc_status result;
3061         bool status = false;
3062         struct pipe_ctx *pipe_ctx;
3063         int i;
3064
3065         if (out_link_loss)
3066                 *out_link_loss = false;
3067         /* For use cases related to down stream connection status change,
3068          * PSR and device auto test, refer to function handle_sst_hpd_irq
3069          * in DAL2.1*/
3070
3071         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3072                 __func__, link->link_index);
3073
3074
3075          /* All the "handle_hpd_irq_xxx()" methods
3076                  * should be called only after
3077                  * dal_dpsst_ls_read_hpd_irq_data
3078                  * Order of calls is important too
3079                  */
3080         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3081         if (out_hpd_irq_dpcd_data)
3082                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3083
3084         if (result != DC_OK) {
3085                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3086                         __func__);
3087                 return false;
3088         }
3089
3090         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3091                 device_service_clear.bits.AUTOMATED_TEST = 1;
3092                 core_link_write_dpcd(
3093                         link,
3094                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3095                         &device_service_clear.raw,
3096                         sizeof(device_service_clear.raw));
3097                 device_service_clear.raw = 0;
3098                 handle_automated_test(link);
3099                 return false;
3100         }
3101
3102         if (!allow_hpd_rx_irq(link)) {
3103                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3104                         __func__, link->link_index);
3105                 return false;
3106         }
3107
3108         if (handle_hpd_irq_psr_sink(link))
3109                 /* PSR-related error was detected and handled */
3110                 return true;
3111
3112         /* If PSR-related error handled, Main link may be off,
3113          * so do not handle as a normal sink status change interrupt.
3114          */
3115
3116         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3117                 return true;
3118
3119         /* check if we have MST msg and return since we poll for it */
3120         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3121                 return false;
3122
3123         /* For now we only handle 'Downstream port status' case.
3124          * If we got sink count changed it means
3125          * Downstream port status changed,
3126          * then DM should call DC to do the detection.
3127          * NOTE: Do not handle link loss on eDP since it is internal link*/
3128         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3129                 hpd_rx_irq_check_link_loss_status(
3130                         link,
3131                         &hpd_irq_dpcd_data)) {
3132                 /* Connectivity log: link loss */
3133                 CONN_DATA_LINK_LOSS(link,
3134                                         hpd_irq_dpcd_data.raw,
3135                                         sizeof(hpd_irq_dpcd_data),
3136                                         "Status: ");
3137
3138                 for (i = 0; i < MAX_PIPES; i++) {
3139                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3140                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3141                                 break;
3142                 }
3143
3144                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3145                         return false;
3146
3147
3148                 for (i = 0; i < MAX_PIPES; i++) {
3149                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3150                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3151                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3152                                 core_link_disable_stream(pipe_ctx);
3153                 }
3154
3155                 for (i = 0; i < MAX_PIPES; i++) {
3156                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3157                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3158                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3159                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3160                 }
3161
3162                 status = false;
3163                 if (out_link_loss)
3164                         *out_link_loss = true;
3165         }
3166
3167         if (link->type == dc_connection_active_dongle &&
3168                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3169                         != link->dpcd_sink_count)
3170                 status = true;
3171
3172         /* reasons for HPD RX:
3173          * 1. Link Loss - ie Re-train the Link
3174          * 2. MST sideband message
3175          * 3. Automated Test - ie. Internal Commit
3176          * 4. CP (copy protection) - (not interesting for DM???)
3177          * 5. DRR
3178          * 6. Downstream Port status changed
3179          * -ie. Detect - this the only one
3180          * which is interesting for DM because
3181          * it must call dc_link_detect.
3182          */
3183         return status;
3184 }
3185
3186 /*query dpcd for version and mst cap addresses*/
3187 bool is_mst_supported(struct dc_link *link)
3188 {
3189         bool mst          = false;
3190         enum dc_status st = DC_OK;
3191         union dpcd_rev rev;
3192         union mstm_cap cap;
3193
3194         if (link->preferred_training_settings.mst_enable &&
3195                 *link->preferred_training_settings.mst_enable == false) {
3196                 return false;
3197         }
3198
3199         rev.raw  = 0;
3200         cap.raw  = 0;
3201
3202         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3203                         sizeof(rev));
3204
3205         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3206
3207                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3208                                 &cap.raw, sizeof(cap));
3209                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3210                         mst = true;
3211         }
3212         return mst;
3213
3214 }
3215
3216 bool is_dp_active_dongle(const struct dc_link *link)
3217 {
3218         return link->dpcd_caps.is_branch_dev;
3219 }
3220
3221 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3222 {
3223         switch (bpc) {
3224         case DOWN_STREAM_MAX_8BPC:
3225                 return 8;
3226         case DOWN_STREAM_MAX_10BPC:
3227                 return 10;
3228         case DOWN_STREAM_MAX_12BPC:
3229                 return 12;
3230         case DOWN_STREAM_MAX_16BPC:
3231                 return 16;
3232         default:
3233                 break;
3234         }
3235
3236         return -1;
3237 }
3238
3239 static void read_dp_device_vendor_id(struct dc_link *link)
3240 {
3241         struct dp_device_vendor_id dp_id;
3242
3243         /* read IEEE branch device id */
3244         core_link_read_dpcd(
3245                 link,
3246                 DP_BRANCH_OUI,
3247                 (uint8_t *)&dp_id,
3248                 sizeof(dp_id));
3249
3250         link->dpcd_caps.branch_dev_id =
3251                 (dp_id.ieee_oui[0] << 16) +
3252                 (dp_id.ieee_oui[1] << 8) +
3253                 dp_id.ieee_oui[2];
3254
3255         memmove(
3256                 link->dpcd_caps.branch_dev_name,
3257                 dp_id.ieee_device_id,
3258                 sizeof(dp_id.ieee_device_id));
3259 }
3260
3261
3262
3263 static void get_active_converter_info(
3264         uint8_t data, struct dc_link *link)
3265 {
3266         union dp_downstream_port_present ds_port = { .byte = data };
3267         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3268
3269         /* decode converter info*/
3270         if (!ds_port.fields.PORT_PRESENT) {
3271                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3272                 ddc_service_set_dongle_type(link->ddc,
3273                                 link->dpcd_caps.dongle_type);
3274                 link->dpcd_caps.is_branch_dev = false;
3275                 return;
3276         }
3277
3278         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3279         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3280
3281         switch (ds_port.fields.PORT_TYPE) {
3282         case DOWNSTREAM_VGA:
3283                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3284                 break;
3285         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3286                 /* At this point we don't know is it DVI or HDMI or DP++,
3287                  * assume DVI.*/
3288                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3289                 break;
3290         default:
3291                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3292                 break;
3293         }
3294
3295         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3296                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3297                 union dwnstream_port_caps_byte0 *port_caps =
3298                         (union dwnstream_port_caps_byte0 *)det_caps;
3299                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3300                                 det_caps, sizeof(det_caps)) == DC_OK) {
3301
3302                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3303                         /*Handle DP case as DONGLE_NONE*/
3304                         case DOWN_STREAM_DETAILED_DP:
3305                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3306                                 break;
3307                         case DOWN_STREAM_DETAILED_VGA:
3308                                 link->dpcd_caps.dongle_type =
3309                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3310                                 break;
3311                         case DOWN_STREAM_DETAILED_DVI:
3312                                 link->dpcd_caps.dongle_type =
3313                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3314                                 break;
3315                         case DOWN_STREAM_DETAILED_HDMI:
3316                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3317                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3318                                 link->dpcd_caps.dongle_type =
3319                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3320
3321                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3322                                 if (ds_port.fields.DETAILED_CAPS) {
3323
3324                                         union dwnstream_port_caps_byte3_hdmi
3325                                                 hdmi_caps = {.raw = det_caps[3] };
3326                                         union dwnstream_port_caps_byte2
3327                                                 hdmi_color_caps = {.raw = det_caps[2] };
3328                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3329                                                 det_caps[1] * 2500;
3330
3331                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3332                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3333                                         /*YCBCR capability only for HDMI case*/
3334                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3335                                                         == DOWN_STREAM_DETAILED_HDMI) {
3336                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3337                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3338                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3339                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3340                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3341                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3342                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3343                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3344                                         }
3345
3346                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3347                                                 translate_dpcd_max_bpc(
3348                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3349
3350                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3351                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3352                                 }
3353
3354                                 break;
3355                         }
3356                 }
3357         }
3358
3359         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3360
3361         {
3362                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3363
3364                 core_link_read_dpcd(
3365                         link,
3366                         DP_BRANCH_REVISION_START,
3367                         (uint8_t *)&dp_hw_fw_revision,
3368                         sizeof(dp_hw_fw_revision));
3369
3370                 link->dpcd_caps.branch_hw_revision =
3371                         dp_hw_fw_revision.ieee_hw_rev;
3372
3373                 memmove(
3374                         link->dpcd_caps.branch_fw_revision,
3375                         dp_hw_fw_revision.ieee_fw_rev,
3376                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3377         }
3378 }
3379
3380 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3381                 int length)
3382 {
3383         int retry = 0;
3384
3385         if (!link->dpcd_caps.dpcd_rev.raw) {
3386                 do {
3387                         dp_receiver_power_ctrl(link, true);
3388                         core_link_read_dpcd(link, DP_DPCD_REV,
3389                                                         dpcd_data, length);
3390                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3391                                 DP_DPCD_REV -
3392                                 DP_DPCD_REV];
3393                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3394         }
3395
3396         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3397                 switch (link->dpcd_caps.branch_dev_id) {
3398                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3399                  * all internal circuits including AUX communication preventing
3400                  * reading DPCD table and EDID (spec violation).
3401                  * Encoder will skip DP RX power down on disable_output to
3402                  * keep receiver powered all the time.*/
3403                 case DP_BRANCH_DEVICE_ID_0010FA:
3404                 case DP_BRANCH_DEVICE_ID_0080E1:
3405                 case DP_BRANCH_DEVICE_ID_00E04C:
3406                         link->wa_flags.dp_keep_receiver_powered = true;
3407                         break;
3408
3409                 /* TODO: May need work around for other dongles. */
3410                 default:
3411                         link->wa_flags.dp_keep_receiver_powered = false;
3412                         break;
3413                 }
3414         } else
3415                 link->wa_flags.dp_keep_receiver_powered = false;
3416 }
3417
3418 /* Read additional sink caps defined in source specific DPCD area
3419  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3420  */
3421 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3422 {
3423         uint8_t dpcd_data;
3424
3425         if (!link)
3426                 return false;
3427
3428         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3429                 return false;
3430
3431         link->dpcd_sink_ext_caps.raw = dpcd_data;
3432         return true;
3433 }
3434
3435 static bool retrieve_link_cap(struct dc_link *link)
3436 {
3437         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3438          * which means size 16 will be good for both of those DPCD register block reads
3439          */
3440         uint8_t dpcd_data[16];
3441         uint8_t lttpr_dpcd_data[6];
3442
3443         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3444          */
3445         uint8_t dpcd_dprx_data = '\0';
3446         uint8_t dpcd_power_state = '\0';
3447
3448         struct dp_device_vendor_id sink_id;
3449         union down_stream_port_count down_strm_port_count;
3450         union edp_configuration_cap edp_config_cap;
3451         union dp_downstream_port_present ds_port = { 0 };
3452         enum dc_status status = DC_ERROR_UNEXPECTED;
3453         uint32_t read_dpcd_retry_cnt = 3;
3454         int i;
3455         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3456         bool is_lttpr_present = false;
3457         const uint32_t post_oui_delay = 30; // 30ms
3458         bool vbios_lttpr_enable = false;
3459         bool vbios_lttpr_interop = false;
3460         struct dc_bios *bios = link->dc->ctx->dc_bios;
3461
3462         memset(dpcd_data, '\0', sizeof(dpcd_data));
3463         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3464         memset(&down_strm_port_count,
3465                 '\0', sizeof(union down_stream_port_count));
3466         memset(&edp_config_cap, '\0',
3467                 sizeof(union edp_configuration_cap));
3468
3469         /* if extended timeout is supported in hardware,
3470          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3471          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3472          */
3473         dc_link_aux_try_to_configure_timeout(link->ddc,
3474                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3475
3476         status = core_link_read_dpcd(link, DP_SET_POWER,
3477                                 &dpcd_power_state, sizeof(dpcd_power_state));
3478
3479         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3480          * section 2.3.1.2, if AUX CH may be powered down due to
3481          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3482          * signal and may need up to 1 ms before being able to reply.
3483          */
3484         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3485                 udelay(1000);
3486
3487         dpcd_set_source_specific_data(link);
3488         /* Sink may need to configure internals based on vendor, so allow some
3489          * time before proceeding with possibly vendor specific transactions
3490          */
3491         msleep(post_oui_delay);
3492
3493         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3494                 status = core_link_read_dpcd(
3495                                 link,
3496                                 DP_DPCD_REV,
3497                                 dpcd_data,
3498                                 sizeof(dpcd_data));
3499                 if (status == DC_OK)
3500                         break;
3501         }
3502
3503         if (status != DC_OK) {
3504                 dm_error("%s: Read dpcd data failed.\n", __func__);
3505                 return false;
3506         }
3507
3508         /* Query BIOS to determine if LTTPR functionality is forced on by system */
3509         if (bios->funcs->get_lttpr_caps) {
3510                 enum bp_result bp_query_result;
3511                 uint8_t is_vbios_lttpr_enable = 0;
3512
3513                 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3514                 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3515         }
3516
3517         if (bios->funcs->get_lttpr_interop) {
3518                 enum bp_result bp_query_result;
3519                 uint8_t is_vbios_interop_enabled = 0;
3520
3521                 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3522                 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3523         }
3524
3525         /*
3526          * Logic to determine LTTPR mode
3527          */
3528         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3529         if (vbios_lttpr_enable && vbios_lttpr_interop)
3530                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3531         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3532                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3533                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3534                 else
3535                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3536         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3537                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3538                         || !link->dc->caps.extended_aux_timeout_support)
3539                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3540                 else
3541                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3542         }
3543
3544         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3545                 /* By reading LTTPR capability, RX assumes that we will enable
3546                  * LTTPR extended aux timeout if LTTPR is present.
3547                  */
3548                 status = core_link_read_dpcd(
3549                                 link,
3550                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3551                                 lttpr_dpcd_data,
3552                                 sizeof(lttpr_dpcd_data));
3553
3554                 link->dpcd_caps.lttpr_caps.revision.raw =
3555                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3556                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3557
3558                 link->dpcd_caps.lttpr_caps.max_link_rate =
3559                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3560                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3561
3562                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3563                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3564                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3565
3566                 link->dpcd_caps.lttpr_caps.max_lane_count =
3567                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3568                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3569
3570                 link->dpcd_caps.lttpr_caps.mode =
3571                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3572                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3573
3574                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3575                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3576                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3577
3578                 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3579                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3580                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3581                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3582                 if (is_lttpr_present)
3583                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3584                 else
3585                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3586         }
3587
3588         if (!is_lttpr_present)
3589                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3590
3591
3592         {
3593                 union training_aux_rd_interval aux_rd_interval;
3594
3595                 aux_rd_interval.raw =
3596                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3597
3598                 link->dpcd_caps.ext_receiver_cap_field_present =
3599                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3600
3601                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3602                         uint8_t ext_cap_data[16];
3603
3604                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3605                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3606                                 status = core_link_read_dpcd(
3607                                 link,
3608                                 DP_DP13_DPCD_REV,
3609                                 ext_cap_data,
3610                                 sizeof(ext_cap_data));
3611                                 if (status == DC_OK) {
3612                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3613                                         break;
3614                                 }
3615                         }
3616                         if (status != DC_OK)
3617                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3618                 }
3619         }
3620
3621         link->dpcd_caps.dpcd_rev.raw =
3622                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3623
3624         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3625                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3626                         status = core_link_read_dpcd(
3627                                         link,
3628                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3629                                         &dpcd_dprx_data,
3630                                         sizeof(dpcd_dprx_data));
3631                         if (status == DC_OK)
3632                                 break;
3633                 }
3634
3635                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3636
3637                 if (status != DC_OK)
3638                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3639         }
3640
3641         else {
3642                 link->dpcd_caps.dprx_feature.raw = 0;
3643         }
3644
3645
3646         /* Error condition checking...
3647          * It is impossible for Sink to report Max Lane Count = 0.
3648          * It is possible for Sink to report Max Link Rate = 0, if it is
3649          * an eDP device that is reporting specialized link rates in the
3650          * SUPPORTED_LINK_RATE table.
3651          */
3652         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3653                 return false;
3654
3655         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3656                                  DP_DPCD_REV];
3657
3658         read_dp_device_vendor_id(link);
3659
3660         get_active_converter_info(ds_port.byte, link);
3661
3662         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3663
3664         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3665                                  DP_DPCD_REV];
3666
3667         link->dpcd_caps.allow_invalid_MSA_timing_param =
3668                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3669
3670         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3671                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3672
3673         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3674                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3675
3676         link->reported_link_cap.lane_count =
3677                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3678         link->reported_link_cap.link_rate = dpcd_data[
3679                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3680         link->reported_link_cap.link_spread =
3681                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3682                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3683
3684         edp_config_cap.raw = dpcd_data[
3685                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3686         link->dpcd_caps.panel_mode_edp =
3687                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3688         link->dpcd_caps.dpcd_display_control_capable =
3689                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3690
3691         link->test_pattern_enabled = false;
3692         link->compliance_test_state.raw = 0;
3693
3694         /* read sink count */
3695         core_link_read_dpcd(link,
3696                         DP_SINK_COUNT,
3697                         &link->dpcd_caps.sink_count.raw,
3698                         sizeof(link->dpcd_caps.sink_count.raw));
3699
3700         /* read sink ieee oui */
3701         core_link_read_dpcd(link,
3702                         DP_SINK_OUI,
3703                         (uint8_t *)(&sink_id),
3704                         sizeof(sink_id));
3705
3706         link->dpcd_caps.sink_dev_id =
3707                         (sink_id.ieee_oui[0] << 16) +
3708                         (sink_id.ieee_oui[1] << 8) +
3709                         (sink_id.ieee_oui[2]);
3710
3711         memmove(
3712                 link->dpcd_caps.sink_dev_id_str,
3713                 sink_id.ieee_device_id,
3714                 sizeof(sink_id.ieee_device_id));
3715
3716         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3717         {
3718                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3719
3720                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3721                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3722                             sizeof(str_mbp_2017))) {
3723                         link->reported_link_cap.link_rate = 0x0c;
3724                 }
3725         }
3726
3727         core_link_read_dpcd(
3728                 link,
3729                 DP_SINK_HW_REVISION_START,
3730                 (uint8_t *)&dp_hw_fw_revision,
3731                 sizeof(dp_hw_fw_revision));
3732
3733         link->dpcd_caps.sink_hw_revision =
3734                 dp_hw_fw_revision.ieee_hw_rev;
3735
3736         memmove(
3737                 link->dpcd_caps.sink_fw_revision,
3738                 dp_hw_fw_revision.ieee_fw_rev,
3739                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3740
3741         memset(&link->dpcd_caps.dsc_caps, '\0',
3742                         sizeof(link->dpcd_caps.dsc_caps));
3743         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3744         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3745         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3746                 status = core_link_read_dpcd(
3747                                 link,
3748                                 DP_FEC_CAPABILITY,
3749                                 &link->dpcd_caps.fec_cap.raw,
3750                                 sizeof(link->dpcd_caps.fec_cap.raw));
3751                 status = core_link_read_dpcd(
3752                                 link,
3753                                 DP_DSC_SUPPORT,
3754                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3755                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3756                 status = core_link_read_dpcd(
3757                                 link,
3758                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3759                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3760                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3761         }
3762
3763         if (!dpcd_read_sink_ext_caps(link))
3764                 link->dpcd_sink_ext_caps.raw = 0;
3765
3766         /* Connectivity log: detection */
3767         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3768
3769         return true;
3770 }
3771
3772 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3773 {
3774         uint8_t dpcd_data[16];
3775         uint32_t read_dpcd_retry_cnt = 3;
3776         enum dc_status status = DC_ERROR_UNEXPECTED;
3777         union dp_downstream_port_present ds_port = { 0 };
3778         union down_stream_port_count down_strm_port_count;
3779         union edp_configuration_cap edp_config_cap;
3780
3781         int i;
3782
3783         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3784                 status = core_link_read_dpcd(
3785                                 link,
3786                                 DP_DPCD_REV,
3787                                 dpcd_data,
3788                                 sizeof(dpcd_data));
3789                 if (status == DC_OK)
3790                         break;
3791         }
3792
3793         link->dpcd_caps.dpcd_rev.raw =
3794                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3795
3796         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3797                 return false;
3798
3799         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3800                         DP_DPCD_REV];
3801
3802         get_active_converter_info(ds_port.byte, link);
3803
3804         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3805                         DP_DPCD_REV];
3806
3807         link->dpcd_caps.allow_invalid_MSA_timing_param =
3808                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3809
3810         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3811                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3812
3813         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3814                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3815
3816         link->reported_link_cap.lane_count =
3817                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3818         link->reported_link_cap.link_rate = dpcd_data[
3819                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3820         link->reported_link_cap.link_spread =
3821                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3822                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3823
3824         edp_config_cap.raw = dpcd_data[
3825                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3826         link->dpcd_caps.panel_mode_edp =
3827                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3828         link->dpcd_caps.dpcd_display_control_capable =
3829                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3830
3831         return true;
3832 }
3833
3834 bool detect_dp_sink_caps(struct dc_link *link)
3835 {
3836         return retrieve_link_cap(link);
3837
3838         /* dc init_hw has power encoder using default
3839          * signal for connector. For native DP, no
3840          * need to power up encoder again. If not native
3841          * DP, hw_init may need check signal or power up
3842          * encoder here.
3843          */
3844         /* TODO save sink caps in link->sink */
3845 }
3846
3847 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3848 {
3849         enum dc_link_rate link_rate;
3850         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3851         switch (link_rate_in_khz) {
3852         case 1620000:
3853                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
3854                 break;
3855         case 2160000:
3856                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
3857                 break;
3858         case 2430000:
3859                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
3860                 break;
3861         case 2700000:
3862                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
3863                 break;
3864         case 3240000:
3865                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
3866                 break;
3867         case 4320000:
3868                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
3869                 break;
3870         case 5400000:
3871                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
3872                 break;
3873         case 8100000:
3874                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
3875                 break;
3876         default:
3877                 link_rate = LINK_RATE_UNKNOWN;
3878                 break;
3879         }
3880         return link_rate;
3881 }
3882
3883 void detect_edp_sink_caps(struct dc_link *link)
3884 {
3885         uint8_t supported_link_rates[16];
3886         uint32_t entry;
3887         uint32_t link_rate_in_khz;
3888         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3889         uint8_t backlight_adj_cap;
3890
3891         retrieve_link_cap(link);
3892         link->dpcd_caps.edp_supported_link_rates_count = 0;
3893         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3894
3895         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3896                         (link->dc->debug.optimize_edp_link_rate ||
3897                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3898                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3899                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3900                                                         supported_link_rates, sizeof(supported_link_rates));
3901
3902                 for (entry = 0; entry < 16; entry += 2) {
3903                         // DPCD register reports per-lane link rate = 16-bit link rate capability
3904                         // value X 200 kHz. Need multiplier to find link rate in kHz.
3905                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3906                                                                                 supported_link_rates[entry]) * 200;
3907
3908                         if (link_rate_in_khz != 0) {
3909                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
3910                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3911                                 link->dpcd_caps.edp_supported_link_rates_count++;
3912
3913                                 if (link->reported_link_cap.link_rate < link_rate)
3914                                         link->reported_link_cap.link_rate = link_rate;
3915                         }
3916                 }
3917         }
3918         link->verified_link_cap = link->reported_link_cap;
3919
3920         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
3921                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
3922
3923         link->dpcd_caps.dynamic_backlight_capable_edp =
3924                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
3925
3926         dc_link_set_default_brightness_aux(link);
3927 }
3928
3929 void dc_link_dp_enable_hpd(const struct dc_link *link)
3930 {
3931         struct link_encoder *encoder = link->link_enc;
3932
3933         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3934                 encoder->funcs->enable_hpd(encoder);
3935 }
3936
3937 void dc_link_dp_disable_hpd(const struct dc_link *link)
3938 {
3939         struct link_encoder *encoder = link->link_enc;
3940
3941         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3942                 encoder->funcs->disable_hpd(encoder);
3943 }
3944
3945 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3946 {
3947         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3948                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3949                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
3950                 return true;
3951         else
3952                 return false;
3953 }
3954
3955 static void set_crtc_test_pattern(struct dc_link *link,
3956                                 struct pipe_ctx *pipe_ctx,
3957                                 enum dp_test_pattern test_pattern,
3958                                 enum dp_test_pattern_color_space test_pattern_color_space)
3959 {
3960         enum controller_dp_test_pattern controller_test_pattern;
3961         enum dc_color_depth color_depth = pipe_ctx->
3962                 stream->timing.display_color_depth;
3963         struct bit_depth_reduction_params params;
3964         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3965         int width = pipe_ctx->stream->timing.h_addressable +
3966                 pipe_ctx->stream->timing.h_border_left +
3967                 pipe_ctx->stream->timing.h_border_right;
3968         int height = pipe_ctx->stream->timing.v_addressable +
3969                 pipe_ctx->stream->timing.v_border_bottom +
3970                 pipe_ctx->stream->timing.v_border_top;
3971
3972         memset(&params, 0, sizeof(params));
3973
3974         switch (test_pattern) {
3975         case DP_TEST_PATTERN_COLOR_SQUARES:
3976                 controller_test_pattern =
3977                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3978         break;
3979         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3980                 controller_test_pattern =
3981                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3982         break;
3983         case DP_TEST_PATTERN_VERTICAL_BARS:
3984                 controller_test_pattern =
3985                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3986         break;
3987         case DP_TEST_PATTERN_HORIZONTAL_BARS:
3988                 controller_test_pattern =
3989                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3990         break;
3991         case DP_TEST_PATTERN_COLOR_RAMP:
3992                 controller_test_pattern =
3993                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3994         break;
3995         default:
3996                 controller_test_pattern =
3997                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3998         break;
3999         }
4000
4001         switch (test_pattern) {
4002         case DP_TEST_PATTERN_COLOR_SQUARES:
4003         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4004         case DP_TEST_PATTERN_VERTICAL_BARS:
4005         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4006         case DP_TEST_PATTERN_COLOR_RAMP:
4007         {
4008                 /* disable bit depth reduction */
4009                 pipe_ctx->stream->bit_depth_params = params;
4010                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4011                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4012                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4013                                 controller_test_pattern, color_depth);
4014                 else if (link->dc->hwss.set_disp_pattern_generator) {
4015                         struct pipe_ctx *odm_pipe;
4016                         enum controller_dp_color_space controller_color_space;
4017                         int opp_cnt = 1;
4018                         int offset = 0;
4019                         int dpg_width = width;
4020
4021                         switch (test_pattern_color_space) {
4022                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4023                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4024                                 break;
4025                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4026                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4027                                 break;
4028                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4029                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4030                                 break;
4031                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4032                         default:
4033                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4034                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4035                                 ASSERT(0);
4036                                 break;
4037                         }
4038
4039                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4040                                 opp_cnt++;
4041                         dpg_width = width / opp_cnt;
4042                         offset = dpg_width;
4043
4044                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4045                                         pipe_ctx,
4046                                         controller_test_pattern,
4047                                         controller_color_space,
4048                                         color_depth,
4049                                         NULL,
4050                                         dpg_width,
4051                                         height,
4052                                         0);
4053
4054                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4055                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4056
4057                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4058                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4059                                                 odm_pipe,
4060                                                 controller_test_pattern,
4061                                                 controller_color_space,
4062                                                 color_depth,
4063                                                 NULL,
4064                                                 dpg_width,
4065                                                 height,
4066                                                 offset);
4067                                 offset += offset;
4068                         }
4069                 }
4070         }
4071         break;
4072         case DP_TEST_PATTERN_VIDEO_MODE:
4073         {
4074                 /* restore bitdepth reduction */
4075                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4076                 pipe_ctx->stream->bit_depth_params = params;
4077                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4078                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4079                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4080                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4081                                 color_depth);
4082                 else if (link->dc->hwss.set_disp_pattern_generator) {
4083                         struct pipe_ctx *odm_pipe;
4084                         int opp_cnt = 1;
4085                         int dpg_width = width;
4086
4087                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4088                                 opp_cnt++;
4089
4090                         dpg_width = width / opp_cnt;
4091                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4092                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4093
4094                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4095                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4096                                                 odm_pipe,
4097                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4098                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4099                                                 color_depth,
4100                                                 NULL,
4101                                                 dpg_width,
4102                                                 height,
4103                                                 0);
4104                         }
4105                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4106                                         pipe_ctx,
4107                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4108                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4109                                         color_depth,
4110                                         NULL,
4111                                         dpg_width,
4112                                         height,
4113                                         0);
4114                 }
4115         }
4116         break;
4117
4118         default:
4119         break;
4120         }
4121 }
4122
4123 bool dc_link_dp_set_test_pattern(
4124         struct dc_link *link,
4125         enum dp_test_pattern test_pattern,
4126         enum dp_test_pattern_color_space test_pattern_color_space,
4127         const struct link_training_settings *p_link_settings,
4128         const unsigned char *p_custom_pattern,
4129         unsigned int cust_pattern_size)
4130 {
4131         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4132         struct pipe_ctx *pipe_ctx = NULL;
4133         unsigned int lane;
4134         unsigned int i;
4135         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4136         union dpcd_training_pattern training_pattern;
4137         enum dpcd_phy_test_patterns pattern;
4138
4139         memset(&training_pattern, 0, sizeof(training_pattern));
4140
4141         for (i = 0; i < MAX_PIPES; i++) {
4142                 if (pipes[i].stream == NULL)
4143                         continue;
4144
4145                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4146                         pipe_ctx = &pipes[i];
4147                         break;
4148                 }
4149         }
4150
4151         if (pipe_ctx == NULL)
4152                 return false;
4153
4154         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4155         if (link->test_pattern_enabled && test_pattern ==
4156                         DP_TEST_PATTERN_VIDEO_MODE) {
4157                 /* Set CRTC Test Pattern */
4158                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4159                 dp_set_hw_test_pattern(link, test_pattern,
4160                                 (uint8_t *)p_custom_pattern,
4161                                 (uint32_t)cust_pattern_size);
4162
4163                 /* Unblank Stream */
4164                 link->dc->hwss.unblank_stream(
4165                         pipe_ctx,
4166                         &link->verified_link_cap);
4167                 /* TODO:m_pHwss->MuteAudioEndpoint
4168                  * (pPathMode->pDisplayPath, false);
4169                  */
4170
4171                 /* Reset Test Pattern state */
4172                 link->test_pattern_enabled = false;
4173
4174                 return true;
4175         }
4176
4177         /* Check for PHY Test Patterns */
4178         if (is_dp_phy_pattern(test_pattern)) {
4179                 /* Set DPCD Lane Settings before running test pattern */
4180                 if (p_link_settings != NULL) {
4181                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4182                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4183                 }
4184
4185                 /* Blank stream if running test pattern */
4186                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4187                         /*TODO:
4188                          * m_pHwss->
4189                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4190                          */
4191                         /* Blank stream */
4192                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4193                 }
4194
4195                 dp_set_hw_test_pattern(link, test_pattern,
4196                                 (uint8_t *)p_custom_pattern,
4197                                 (uint32_t)cust_pattern_size);
4198
4199                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4200                         /* Set Test Pattern state */
4201                         link->test_pattern_enabled = true;
4202                         if (p_link_settings != NULL)
4203                                 dpcd_set_link_settings(link,
4204                                                 p_link_settings);
4205                 }
4206
4207                 switch (test_pattern) {
4208                 case DP_TEST_PATTERN_VIDEO_MODE:
4209                         pattern = PHY_TEST_PATTERN_NONE;
4210                         break;
4211                 case DP_TEST_PATTERN_D102:
4212                         pattern = PHY_TEST_PATTERN_D10_2;
4213                         break;
4214                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4215                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4216                         break;
4217                 case DP_TEST_PATTERN_PRBS7:
4218                         pattern = PHY_TEST_PATTERN_PRBS7;
4219                         break;
4220                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4221                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4222                         break;
4223                 case DP_TEST_PATTERN_CP2520_1:
4224                         pattern = PHY_TEST_PATTERN_CP2520_1;
4225                         break;
4226                 case DP_TEST_PATTERN_CP2520_2:
4227                         pattern = PHY_TEST_PATTERN_CP2520_2;
4228                         break;
4229                 case DP_TEST_PATTERN_CP2520_3:
4230                         pattern = PHY_TEST_PATTERN_CP2520_3;
4231                         break;
4232                 default:
4233                         return false;
4234                 }
4235
4236                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4237                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4238                         return false;
4239
4240                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4241                         /* tell receiver that we are sending qualification
4242                          * pattern DP 1.2 or later - DP receiver's link quality
4243                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4244                          * register (0x10B~0x10E)\
4245                          */
4246                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4247                                 link_qual_pattern[lane] =
4248                                                 (unsigned char)(pattern);
4249
4250                         core_link_write_dpcd(link,
4251                                         DP_LINK_QUAL_LANE0_SET,
4252                                         link_qual_pattern,
4253                                         sizeof(link_qual_pattern));
4254                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4255                            link->dpcd_caps.dpcd_rev.raw == 0) {
4256                         /* tell receiver that we are sending qualification
4257                          * pattern DP 1.1a or earlier - DP receiver's link
4258                          * quality pattern is set using
4259                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4260                          * register (0x102). We will use v_1.3 when we are
4261                          * setting test pattern for DP 1.1.
4262                          */
4263                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4264                                             &training_pattern.raw,
4265                                             sizeof(training_pattern));
4266                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4267                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4268                                              &training_pattern.raw,
4269                                              sizeof(training_pattern));
4270                 }
4271         } else {
4272                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4273
4274                 switch (test_pattern_color_space) {
4275                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4276                         color_space = COLOR_SPACE_SRGB;
4277                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4278                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4279                         break;
4280
4281                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4282                         color_space = COLOR_SPACE_YCBCR601;
4283                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4284                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4285                         break;
4286                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4287                         color_space = COLOR_SPACE_YCBCR709;
4288                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4289                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4290                         break;
4291                 default:
4292                         break;
4293                 }
4294
4295                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4296                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4297                                 union dmub_hw_lock_flags hw_locks = { 0 };
4298                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4299
4300                                 hw_locks.bits.lock_dig = 1;
4301                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4302
4303                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4304                                                         true,
4305                                                         &hw_locks,
4306                                                         &inst_flags);
4307                         } else
4308                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4309                                                 pipe_ctx->stream_res.tg);
4310                 }
4311
4312                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4313                 /* update MSA to requested color space */
4314                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4315                                 &pipe_ctx->stream->timing,
4316                                 color_space,
4317                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4318                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4319
4320                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4321                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4322                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4323                         else
4324                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4325                         resource_build_info_frame(pipe_ctx);
4326                         link->dc->hwss.update_info_frame(pipe_ctx);
4327                 }
4328
4329                 /* CRTC Patterns */
4330                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4331                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4332                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4333                                 CRTC_STATE_VACTIVE);
4334                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4335                                 CRTC_STATE_VBLANK);
4336                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4337                                 CRTC_STATE_VACTIVE);
4338
4339                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4340                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4341                                 union dmub_hw_lock_flags hw_locks = { 0 };
4342                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4343
4344                                 hw_locks.bits.lock_dig = 1;
4345                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4346
4347                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4348                                                         false,
4349                                                         &hw_locks,
4350                                                         &inst_flags);
4351                         } else
4352                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4353                                                 pipe_ctx->stream_res.tg);
4354                 }
4355
4356                 /* Set Test Pattern state */
4357                 link->test_pattern_enabled = true;
4358         }
4359
4360         return true;
4361 }
4362
4363 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4364 {
4365         unsigned char mstmCntl;
4366
4367         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4368         if (enable)
4369                 mstmCntl |= DP_MST_EN;
4370         else
4371                 mstmCntl &= (~DP_MST_EN);
4372
4373         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4374 }
4375
4376 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4377 {
4378         union dpcd_edp_config edp_config_set;
4379         bool panel_mode_edp = false;
4380
4381         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4382
4383         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4384
4385                 switch (panel_mode) {
4386                 case DP_PANEL_MODE_EDP:
4387                 case DP_PANEL_MODE_SPECIAL:
4388                         panel_mode_edp = true;
4389                         break;
4390
4391                 default:
4392                                 break;
4393                 }
4394
4395                 /*set edp panel mode in receiver*/
4396                 core_link_read_dpcd(
4397                         link,
4398                         DP_EDP_CONFIGURATION_SET,
4399                         &edp_config_set.raw,
4400                         sizeof(edp_config_set.raw));
4401
4402                 if (edp_config_set.bits.PANEL_MODE_EDP
4403                         != panel_mode_edp) {
4404                         enum dc_status result;
4405
4406                         edp_config_set.bits.PANEL_MODE_EDP =
4407                         panel_mode_edp;
4408                         result = core_link_write_dpcd(
4409                                 link,
4410                                 DP_EDP_CONFIGURATION_SET,
4411                                 &edp_config_set.raw,
4412                                 sizeof(edp_config_set.raw));
4413
4414                         ASSERT(result == DC_OK);
4415                 }
4416         }
4417         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4418                  "eDP panel mode enabled: %d \n",
4419                  link->link_index,
4420                  link->dpcd_caps.panel_mode_edp,
4421                  panel_mode_edp);
4422 }
4423
4424 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4425 {
4426         /* We need to explicitly check that connector
4427          * is not DP. Some Travis_VGA get reported
4428          * by video bios as DP.
4429          */
4430         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4431
4432                 switch (link->dpcd_caps.branch_dev_id) {
4433                 case DP_BRANCH_DEVICE_ID_0022B9:
4434                         /* alternate scrambler reset is required for Travis
4435                          * for the case when external chip does not
4436                          * provide sink device id, alternate scrambler
4437                          * scheme will  be overriden later by querying
4438                          * Encoder features
4439                          */
4440                         if (strncmp(
4441                                 link->dpcd_caps.branch_dev_name,
4442                                 DP_VGA_LVDS_CONVERTER_ID_2,
4443                                 sizeof(
4444                                 link->dpcd_caps.
4445                                 branch_dev_name)) == 0) {
4446                                         return DP_PANEL_MODE_SPECIAL;
4447                         }
4448                         break;
4449                 case DP_BRANCH_DEVICE_ID_00001A:
4450                         /* alternate scrambler reset is required for Travis
4451                          * for the case when external chip does not provide
4452                          * sink device id, alternate scrambler scheme will
4453                          * be overriden later by querying Encoder feature
4454                          */
4455                         if (strncmp(link->dpcd_caps.branch_dev_name,
4456                                 DP_VGA_LVDS_CONVERTER_ID_3,
4457                                 sizeof(
4458                                 link->dpcd_caps.
4459                                 branch_dev_name)) == 0) {
4460                                         return DP_PANEL_MODE_SPECIAL;
4461                         }
4462                         break;
4463                 default:
4464                         break;
4465                 }
4466         }
4467
4468         if (link->dpcd_caps.panel_mode_edp) {
4469                 return DP_PANEL_MODE_EDP;
4470         }
4471
4472         return DP_PANEL_MODE_DEFAULT;
4473 }
4474
4475 void dp_set_fec_ready(struct dc_link *link, bool ready)
4476 {
4477         /* FEC has to be "set ready" before the link training.
4478          * The policy is to always train with FEC
4479          * if the sink supports it and leave it enabled on link.
4480          * If FEC is not supported, disable it.
4481          */
4482         struct link_encoder *link_enc = link->link_enc;
4483         uint8_t fec_config = 0;
4484
4485         if (!dc_link_should_enable_fec(link))
4486                 return;
4487
4488         if (link_enc->funcs->fec_set_ready &&
4489                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4490                 if (ready) {
4491                         fec_config = 1;
4492                         if (core_link_write_dpcd(link,
4493                                         DP_FEC_CONFIGURATION,
4494                                         &fec_config,
4495                                         sizeof(fec_config)) == DC_OK) {
4496                                 link_enc->funcs->fec_set_ready(link_enc, true);
4497                                 link->fec_state = dc_link_fec_ready;
4498                         } else {
4499                                 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4500                                 link->fec_state = dc_link_fec_not_ready;
4501                                 dm_error("dpcd write failed to set fec_ready");
4502                         }
4503                 } else if (link->fec_state == dc_link_fec_ready) {
4504                         fec_config = 0;
4505                         core_link_write_dpcd(link,
4506                                         DP_FEC_CONFIGURATION,
4507                                         &fec_config,
4508                                         sizeof(fec_config));
4509                         link->link_enc->funcs->fec_set_ready(
4510                                         link->link_enc, false);
4511                         link->fec_state = dc_link_fec_not_ready;
4512                 }
4513         }
4514 }
4515
4516 void dp_set_fec_enable(struct dc_link *link, bool enable)
4517 {
4518         struct link_encoder *link_enc = link->link_enc;
4519
4520         if (!dc_link_should_enable_fec(link))
4521                 return;
4522
4523         if (link_enc->funcs->fec_set_enable &&
4524                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4525                 if (link->fec_state == dc_link_fec_ready && enable) {
4526                         /* Accord to DP spec, FEC enable sequence can first
4527                          * be transmitted anytime after 1000 LL codes have
4528                          * been transmitted on the link after link training
4529                          * completion. Using 1 lane RBR should have the maximum
4530                          * time for transmitting 1000 LL codes which is 6.173 us.
4531                          * So use 7 microseconds delay instead.
4532                          */
4533                         udelay(7);
4534                         link_enc->funcs->fec_set_enable(link_enc, true);
4535                         link->fec_state = dc_link_fec_enabled;
4536                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4537                         link_enc->funcs->fec_set_enable(link_enc, false);
4538                         link->fec_state = dc_link_fec_ready;
4539                 }
4540         }
4541 }
4542
4543 void dpcd_set_source_specific_data(struct dc_link *link)
4544 {
4545         if (!link->dc->vendor_signature.is_valid) {
4546                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4547                 struct dpcd_amd_signature amd_signature = {0};
4548                 struct dpcd_amd_device_id amd_device_id = {0};
4549
4550                 amd_device_id.device_id_byte1 =
4551                                 (uint8_t)(link->ctx->asic_id.chip_id);
4552                 amd_device_id.device_id_byte2 =
4553                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4554                 amd_device_id.dce_version =
4555                                 (uint8_t)(link->ctx->dce_version);
4556                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4557                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4558
4559                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4560                                 (uint8_t *)(&amd_signature),
4561                                 sizeof(amd_signature));
4562
4563                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4564                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4565                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4566
4567                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4568                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4569                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4570
4571                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4572                                 (uint8_t *)(&amd_signature),
4573                                 sizeof(amd_signature));
4574                 }
4575
4576                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4577                                 (uint8_t *)(&amd_device_id),
4578                                 sizeof(amd_device_id));
4579
4580                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4581                         link->dc->caps.min_horizontal_blanking_period != 0) {
4582
4583                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4584
4585                         result_write_min_hblank = core_link_write_dpcd(link,
4586                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4587                                 sizeof(hblank_size));
4588                 }
4589                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4590                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4591                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4592                                                         result_write_min_hblank,
4593                                                         link->link_index,
4594                                                         link->ctx->dce_version,
4595                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4596                                                         link->dc->caps.min_horizontal_blanking_period,
4597                                                         link->dpcd_caps.branch_dev_id,
4598                                                         link->dpcd_caps.branch_dev_name[0],
4599                                                         link->dpcd_caps.branch_dev_name[1],
4600                                                         link->dpcd_caps.branch_dev_name[2],
4601                                                         link->dpcd_caps.branch_dev_name[3],
4602                                                         link->dpcd_caps.branch_dev_name[4],
4603                                                         link->dpcd_caps.branch_dev_name[5]);
4604         } else {
4605                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4606                                 link->dc->vendor_signature.data.raw,
4607                                 sizeof(link->dc->vendor_signature.data.raw));
4608         }
4609 }
4610
4611 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4612                 bool isHDR,
4613                 uint32_t backlight_millinits,
4614                 uint32_t transition_time_in_ms)
4615 {
4616         struct dpcd_source_backlight_set dpcd_backlight_set;
4617         uint8_t backlight_control = isHDR ? 1 : 0;
4618
4619         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4620                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4621                 return false;
4622
4623         // OLEDs have no PWM, they can only use AUX
4624         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4625                 backlight_control = 1;
4626
4627         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4628         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4629
4630
4631         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4632                         (uint8_t *)(&dpcd_backlight_set),
4633                         sizeof(dpcd_backlight_set)) != DC_OK)
4634                 return false;
4635
4636         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4637                         &backlight_control, 1) != DC_OK)
4638                 return false;
4639
4640         return true;
4641 }
4642
4643 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4644                 uint32_t *backlight_millinits_avg,
4645                 uint32_t *backlight_millinits_peak)
4646 {
4647         union dpcd_source_backlight_get dpcd_backlight_get;
4648
4649         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4650
4651         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4652                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4653                 return false;
4654
4655         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4656                         dpcd_backlight_get.raw,
4657                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4658                 return false;
4659
4660         *backlight_millinits_avg =
4661                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4662         *backlight_millinits_peak =
4663                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4664
4665         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4666         if (*backlight_millinits_avg == 0 ||
4667                         *backlight_millinits_avg > *backlight_millinits_peak)
4668                 return false;
4669
4670         return true;
4671 }
4672
4673 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4674 {
4675         uint8_t backlight_enable = enable ? 1 : 0;
4676
4677         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4678                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4679                 return false;
4680
4681         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4682                 &backlight_enable, 1) != DC_OK)
4683                 return false;
4684
4685         return true;
4686 }
4687
4688 // we read default from 0x320 because we expect BIOS wrote it there
4689 // regular get_backlight_nit reads from panel set at 0x326
4690 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4691 {
4692         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4693                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4694                 return false;
4695
4696         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4697                 (uint8_t *) backlight_millinits,
4698                 sizeof(uint32_t)) != DC_OK)
4699                 return false;
4700
4701         return true;
4702 }
4703
4704 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4705 {
4706         uint32_t default_backlight;
4707
4708         if (link &&
4709                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4710                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4711                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4712                         default_backlight = 150000;
4713                 // if < 5 nits or > 5000, it might be wrong readback
4714                 if (default_backlight < 5000 || default_backlight > 5000000)
4715                         default_backlight = 150000; //
4716
4717                 return dc_link_set_backlight_level_nits(link, true,
4718                                 default_backlight, 0);
4719         }
4720         return false;
4721 }
4722
4723 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4724 {
4725         struct dc_link_settings link_setting;
4726         uint8_t link_bw_set;
4727         uint8_t link_rate_set;
4728         uint32_t req_bw;
4729         union lane_count_set lane_count_set = { {0} };
4730
4731         ASSERT(link || crtc_timing); // invalid input
4732
4733         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4734                         !link->dc->debug.optimize_edp_link_rate)
4735                 return false;
4736
4737
4738         // Read DPCD 00100h to find if standard link rates are set
4739         core_link_read_dpcd(link, DP_LINK_BW_SET,
4740                                 &link_bw_set, sizeof(link_bw_set));
4741
4742         if (link_bw_set) {
4743                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4744                 return true;
4745         }
4746
4747         // Read DPCD 00115h to find the edp link rate set used
4748         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4749                             &link_rate_set, sizeof(link_rate_set));
4750
4751         // Read DPCD 00101h to find out the number of lanes currently set
4752         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4753                                 &lane_count_set.raw, sizeof(lane_count_set));
4754
4755         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4756
4757         decide_edp_link_settings(link, &link_setting, req_bw);
4758
4759         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4760                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4761                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4762                 return true;
4763         }
4764
4765         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4766         return false;
4767 }
4768
4769