drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17 #include "inc/link_enc_cfg.h"
  18
  19 /*Travis*/
  20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  21 /*Nutmeg*/
  22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  23
  24 #define DC_LOGGER \
  25         link->ctx->logger
  26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  27
  28 #include "link_dpcd.h"
  29
  30         /* maximum pre emphasis level allowed for each voltage swing level*/
  31         static const enum dc_pre_emphasis
  32         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  33                                             PRE_EMPHASIS_LEVEL2,
  34                                             PRE_EMPHASIS_LEVEL1,
  35                                             PRE_EMPHASIS_DISABLED };
  36
  37 enum {
  38         POST_LT_ADJ_REQ_LIMIT = 6,
  39         POST_LT_ADJ_REQ_TIMEOUT = 200
  40 };
  41
  42 static bool decide_fallback_link_setting(
  43                 struct dc_link_settings initial_link_settings,
  44                 struct dc_link_settings *current_link_setting,
  45                 enum link_training_result training_result);
  46 static struct dc_link_settings get_common_supported_link_settings(
  47                 struct dc_link_settings link_setting_a,
  48                 struct dc_link_settings link_setting_b);
  49
  50 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  51                 const struct dc_link_settings *link_settings)
  52 {
  53         union training_aux_rd_interval training_rd_interval;
  54         uint32_t wait_in_micro_secs = 100;
  55
  56         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  57         core_link_read_dpcd(
  58                         link,
  59                         DP_TRAINING_AUX_RD_INTERVAL,
  60                         (uint8_t *)&training_rd_interval,
  61                         sizeof(training_rd_interval));
  62         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  63                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  64         return wait_in_micro_secs;
  65 }
  66
  67 static uint32_t get_eq_training_aux_rd_interval(
  68         struct dc_link *link,
  69         const struct dc_link_settings *link_settings)
  70 {
  71         union training_aux_rd_interval training_rd_interval;
  72         uint32_t wait_in_micro_secs = 400;
  73
  74         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  75         /* overwrite the delay if rev > 1.1*/
  76         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  77                 /* DP 1.2 or later - retrieve delay through
  78                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  79                 core_link_read_dpcd(
  80                         link,
  81                         DP_TRAINING_AUX_RD_INTERVAL,
  82                         (uint8_t *)&training_rd_interval,
  83                         sizeof(training_rd_interval));
  84
  85                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  86                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  87         }
  88
  89         return wait_in_micro_secs;
  90 }
  91
  92 void dp_wait_for_training_aux_rd_interval(
  93         struct dc_link *link,
  94         uint32_t wait_in_micro_secs)
  95 {
  96         udelay(wait_in_micro_secs);
  97
  98         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  99                 __func__,
 100                 wait_in_micro_secs);
 101 }
 102
 103 enum dpcd_training_patterns
 104         dc_dp_training_pattern_to_dpcd_training_pattern(
 105         struct dc_link *link,
 106         enum dc_dp_training_pattern pattern)
 107 {
 108         enum dpcd_training_patterns dpcd_tr_pattern =
 109         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 110
 111         switch (pattern) {
 112         case DP_TRAINING_PATTERN_SEQUENCE_1:
 113                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 114                 break;
 115         case DP_TRAINING_PATTERN_SEQUENCE_2:
 116                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 117                 break;
 118         case DP_TRAINING_PATTERN_SEQUENCE_3:
 119                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 120                 break;
 121         case DP_TRAINING_PATTERN_SEQUENCE_4:
 122                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 123                 break;
 124         case DP_TRAINING_PATTERN_VIDEOIDLE:
 125                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 126                 break;
 127         default:
 128                 ASSERT(0);
 129                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 130                         __func__, pattern);
 131                 break;
 132         }
 133
 134         return dpcd_tr_pattern;
 135 }
 136
 137 static void dpcd_set_training_pattern(
 138         struct dc_link *link,
 139         enum dc_dp_training_pattern training_pattern)
 140 {
 141         union dpcd_training_pattern dpcd_pattern = { {0} };
 142
 143         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 144                         dc_dp_training_pattern_to_dpcd_training_pattern(
 145                                         link, training_pattern);
 146
 147         core_link_write_dpcd(
 148                 link,
 149                 DP_TRAINING_PATTERN_SET,
 150                 &dpcd_pattern.raw,
 151                 1);
 152
 153         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 154                 __func__,
 155                 DP_TRAINING_PATTERN_SET,
 156                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 157 }
 158
 159 static enum dc_dp_training_pattern decide_cr_training_pattern(
 160                 const struct dc_link_settings *link_settings)
 161 {
 162         return DP_TRAINING_PATTERN_SEQUENCE_1;
 163 }
 164
 165 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 166                 const struct dc_link_settings *link_settings)
 167 {
 168         struct link_encoder *link_enc;
 169         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 170         struct encoder_feature_support *features;
 171         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 172
 173         /* Access link encoder capability based on whether it is statically
 174          * or dynamically assigned to a link.
 175          */
 176         if (link->is_dig_mapping_flexible &&
 177                         link->dc->res_pool->funcs->link_encs_assign)
 178                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 179         else
 180                 link_enc = link->link_enc;
 181         ASSERT(link_enc);
 182         features = &link_enc->features;
 183
 184         if (features->flags.bits.IS_TPS3_CAPABLE)
 185                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 186
 187         if (features->flags.bits.IS_TPS4_CAPABLE)
 188                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 189
 190         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 191                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 192                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 193
 194         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 195                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 196                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 197
 198         return DP_TRAINING_PATTERN_SEQUENCE_2;
 199 }
 200
 201 enum dc_status dpcd_set_link_settings(
 202         struct dc_link *link,
 203         const struct link_training_settings *lt_settings)
 204 {
 205         uint8_t rate;
 206         enum dc_status status;
 207
 208         union down_spread_ctrl downspread = { {0} };
 209         union lane_count_set lane_count_set = { {0} };
 210
 211         downspread.raw = (uint8_t)
 212         (lt_settings->link_settings.link_spread);
 213
 214         lane_count_set.bits.LANE_COUNT_SET =
 215         lt_settings->link_settings.lane_count;
 216
 217         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 218         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 219
 220
 221         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 222                         lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 223                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 224                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 225         }
 226
 227         status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 228                 &downspread.raw, sizeof(downspread));
 229
 230         status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 231                 &lane_count_set.raw, 1);
 232
 233         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 234                         lt_settings->link_settings.use_link_rate_set == true) {
 235                 rate = 0;
 236                 /* WA for some MUX chips that will power down with eDP and lose supported
 237                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 238                  * MUX chip gets link rate set back before link training.
 239                  */
 240                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 241                         uint8_t supported_link_rates[16];
 242
 243                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 244                                         supported_link_rates, sizeof(supported_link_rates));
 245                 }
 246                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 247                 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
 248                                 &lt_settings->link_settings.link_rate_set, 1);
 249         } else {
 250                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 251                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 252         }
 253
 254         if (rate) {
 255                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 256                         __func__,
 257                         DP_LINK_BW_SET,
 258                         lt_settings->link_settings.link_rate,
 259                         DP_LANE_COUNT_SET,
 260                         lt_settings->link_settings.lane_count,
 261                         lt_settings->enhanced_framing,
 262                         DP_DOWNSPREAD_CTRL,
 263                         lt_settings->link_settings.link_spread);
 264         } else {
 265                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 266                         __func__,
 267                         DP_LINK_RATE_SET,
 268                         lt_settings->link_settings.link_rate_set,
 269                         DP_LANE_COUNT_SET,
 270                         lt_settings->link_settings.lane_count,
 271                         lt_settings->enhanced_framing,
 272                         DP_DOWNSPREAD_CTRL,
 273                         lt_settings->link_settings.link_spread);
 274         }
 275
 276         return status;
 277 }
 278
 279 uint8_t dc_dp_initialize_scrambling_data_symbols(
 280         struct dc_link *link,
 281         enum dc_dp_training_pattern pattern)
 282 {
 283         uint8_t disable_scrabled_data_symbols = 0;
 284
 285         switch (pattern) {
 286         case DP_TRAINING_PATTERN_SEQUENCE_1:
 287         case DP_TRAINING_PATTERN_SEQUENCE_2:
 288         case DP_TRAINING_PATTERN_SEQUENCE_3:
 289                 disable_scrabled_data_symbols = 1;
 290                 break;
 291         case DP_TRAINING_PATTERN_SEQUENCE_4:
 292                 disable_scrabled_data_symbols = 0;
 293                 break;
 294         default:
 295                 ASSERT(0);
 296                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 297                         __func__, pattern);
 298                 break;
 299         }
 300         return disable_scrabled_data_symbols;
 301 }
 302
 303 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 304 {
 305         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 306 }
 307
 308 static void dpcd_set_lt_pattern_and_lane_settings(
 309         struct dc_link *link,
 310         const struct link_training_settings *lt_settings,
 311         enum dc_dp_training_pattern pattern,
 312         uint32_t offset)
 313 {
 314         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 315
 316         uint32_t dpcd_base_lt_offset;
 317
 318         uint8_t dpcd_lt_buffer[5] = {0};
 319         union dpcd_training_pattern dpcd_pattern = { {0} };
 320         uint32_t lane;
 321         uint32_t size_in_bytes;
 322         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 323         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 324
 325         if (is_repeater(link, offset))
 326                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 327                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 328
 329         /*****************************************************************
 330         * DpcdAddress_TrainingPatternSet
 331         *****************************************************************/
 332         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 333                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 334
 335         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 336                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 337
 338         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 339                 = dpcd_pattern.raw;
 340
 341         if (is_repeater(link, offset)) {
 342                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 343                         __func__,
 344                         offset,
 345                         dpcd_base_lt_offset,
 346                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 347         } else {
 348                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 349                         __func__,
 350                         dpcd_base_lt_offset,
 351                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 352         }
 353         /*****************************************************************
 354         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 355         *****************************************************************/
 356         for (lane = 0; lane <
 357                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 358
 359                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 360                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 361                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 362                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 363
 364                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 365                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 366                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 367                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 368                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 369                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 370         }
 371
 372         /* concatenate everything into one buffer*/
 373
 374         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 375
 376          // 0x00103 - 0x00102
 377         memmove(
 378                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 379                 dpcd_lane,
 380                 size_in_bytes);
 381
 382         if (is_repeater(link, offset)) {
 383                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 384                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 385                         __func__,
 386                         offset,
 387                         dpcd_base_lt_offset,
 388                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 389                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 390                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 391                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 392         } else {
 393                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 394                         __func__,
 395                         dpcd_base_lt_offset,
 396                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 397                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 398                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 399                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 400         }
 401         if (edp_workaround) {
 402                 /* for eDP write in 2 parts because the 5-byte burst is
 403                 * causing issues on some eDP panels (EPR#366724)
 404                 */
 405                 core_link_write_dpcd(
 406                         link,
 407                         DP_TRAINING_PATTERN_SET,
 408                         &dpcd_pattern.raw,
 409                         sizeof(dpcd_pattern.raw));
 410
 411                 core_link_write_dpcd(
 412                         link,
 413                         DP_TRAINING_LANE0_SET,
 414                         (uint8_t *)(dpcd_lane),
 415                         size_in_bytes);
 416
 417                 } else
 418                 /* write it all in (1 + number-of-lanes)-byte burst*/
 419                         core_link_write_dpcd(
 420                                 link,
 421                                 dpcd_base_lt_offset,
 422                                 dpcd_lt_buffer,
 423                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 424
 425         link->cur_lane_setting = lt_settings->lane_settings[0];
 426 }
 427
 428 bool dp_is_cr_done(enum dc_lane_count ln_count,
 429         union lane_status *dpcd_lane_status)
 430 {
 431         uint32_t lane;
 432         /*LANEx_CR_DONE bits All 1's?*/
 433         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 434                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 435                         return false;
 436         }
 437         return true;
 438 }
 439
 440 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
 441                 union lane_status *dpcd_lane_status)
 442 {
 443         bool done = true;
 444         uint32_t lane;
 445         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 446                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 447                         done = false;
 448         return done;
 449 }
 450
 451 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
 452                 union lane_status *dpcd_lane_status)
 453 {
 454         bool locked = true;
 455         uint32_t lane;
 456         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 457                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 458                         locked = false;
 459         return locked;
 460 }
 461
 462 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 463 {
 464         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 465 }
 466
 467 void dp_update_drive_settings(
 468                 struct link_training_settings *dest,
 469                 struct link_training_settings src)
 470 {
 471         uint32_t lane;
 472         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 473                 if (dest->voltage_swing == NULL)
 474                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 475                 else
 476                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 477
 478                 if (dest->pre_emphasis == NULL)
 479                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 480                 else
 481                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 482
 483                 if (dest->post_cursor2 == NULL)
 484                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 485                 else
 486                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 487         }
 488 }
 489
 490 static uint8_t get_nibble_at_index(const uint8_t *buf,
 491         uint32_t index)
 492 {
 493         uint8_t nibble;
 494         nibble = buf[index / 2];
 495
 496         if (index % 2)
 497                 nibble >>= 4;
 498         else
 499                 nibble &= 0x0F;
 500
 501         return nibble;
 502 }
 503
 504 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 505         enum dc_voltage_swing voltage)
 506 {
 507         enum dc_pre_emphasis pre_emphasis;
 508         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 509
 510         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 511                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 512
 513         return pre_emphasis;
 514
 515 }
 516
 517 static void find_max_drive_settings(
 518         const struct link_training_settings *link_training_setting,
 519         struct link_training_settings *max_lt_setting)
 520 {
 521         uint32_t lane;
 522         struct dc_lane_settings max_requested;
 523
 524         max_requested.VOLTAGE_SWING =
 525                 link_training_setting->
 526                 lane_settings[0].VOLTAGE_SWING;
 527         max_requested.PRE_EMPHASIS =
 528                 link_training_setting->
 529                 lane_settings[0].PRE_EMPHASIS;
 530         /*max_requested.postCursor2 =
 531          * link_training_setting->laneSettings[0].postCursor2;*/
 532
 533         /* Determine what the maximum of the requested settings are*/
 534         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 535                         lane++) {
 536                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 537                         max_requested.VOLTAGE_SWING)
 538
 539                         max_requested.VOLTAGE_SWING =
 540                         link_training_setting->
 541                         lane_settings[lane].VOLTAGE_SWING;
 542
 543                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 544                                 max_requested.PRE_EMPHASIS)
 545                         max_requested.PRE_EMPHASIS =
 546                         link_training_setting->
 547                         lane_settings[lane].PRE_EMPHASIS;
 548
 549                 /*
 550                 if (link_training_setting->laneSettings[lane].postCursor2 >
 551                  max_requested.postCursor2)
 552                 {
 553                 max_requested.postCursor2 =
 554                 link_training_setting->laneSettings[lane].postCursor2;
 555                 }
 556                 */
 557         }
 558
 559         /* make sure the requested settings are
 560          * not higher than maximum settings*/
 561         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 562                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 563
 564         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 565                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 566         /*
 567         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 568         max_requested.postCursor2 = PostCursor2_MaxLevel;
 569         */
 570
 571         /* make sure the pre-emphasis matches the voltage swing*/
 572         if (max_requested.PRE_EMPHASIS >
 573                 get_max_pre_emphasis_for_voltage_swing(
 574                         max_requested.VOLTAGE_SWING))
 575                 max_requested.PRE_EMPHASIS =
 576                 get_max_pre_emphasis_for_voltage_swing(
 577                         max_requested.VOLTAGE_SWING);
 578
 579         /*
 580          * Post Cursor2 levels are completely independent from
 581          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 582          * can only be applied to each allowable combination of voltage
 583          * swing and pre-emphasis levels */
 584          /* if ( max_requested.postCursor2 >
 585           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 586           *  max_requested.postCursor2 =
 587           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 588           */
 589
 590         max_lt_setting->link_settings.link_rate =
 591                 link_training_setting->link_settings.link_rate;
 592         max_lt_setting->link_settings.lane_count =
 593         link_training_setting->link_settings.lane_count;
 594         max_lt_setting->link_settings.link_spread =
 595                 link_training_setting->link_settings.link_spread;
 596
 597         for (lane = 0; lane <
 598                 link_training_setting->link_settings.lane_count;
 599                 lane++) {
 600                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 601                         max_requested.VOLTAGE_SWING;
 602                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 603                         max_requested.PRE_EMPHASIS;
 604                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 605                  * max_requested.postCursor2;
 606                  */
 607         }
 608
 609 }
 610
 611 enum dc_status dp_get_lane_status_and_drive_settings(
 612         struct dc_link *link,
 613         const struct link_training_settings *link_training_setting,
 614         union lane_status *ln_status,
 615         union lane_align_status_updated *ln_status_updated,
 616         struct link_training_settings *req_settings,
 617         uint32_t offset)
 618 {
 619         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 620         uint8_t lane_adjust_offset = 4;
 621         unsigned int lane01_adjust_address;
 622         uint8_t dpcd_buf[6] = {0};
 623         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 624         struct link_training_settings request_settings = { {0} };
 625         uint32_t lane;
 626         enum dc_status status;
 627
 628         memset(req_settings, '\0', sizeof(struct link_training_settings));
 629
 630         if (is_repeater(link, offset)) {
 631                 lane01_status_address =
 632                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 633                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 634                 lane_adjust_offset = 3;
 635         }
 636
 637         status = core_link_read_dpcd(
 638                 link,
 639                 lane01_status_address,
 640                 (uint8_t *)(dpcd_buf),
 641                 sizeof(dpcd_buf));
 642
 643         for (lane = 0; lane <
 644                 (uint32_t)(link_training_setting->link_settings.lane_count);
 645                 lane++) {
 646
 647                 ln_status[lane].raw =
 648                         get_nibble_at_index(&dpcd_buf[0], lane);
 649                 dpcd_lane_adjust[lane].raw =
 650                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 651         }
 652
 653         ln_status_updated->raw = dpcd_buf[2];
 654
 655         if (is_repeater(link, offset)) {
 656                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 657                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 658                         __func__,
 659                         offset,
 660                         lane01_status_address, dpcd_buf[0],
 661                         lane01_status_address + 1, dpcd_buf[1]);
 662         } else {
 663                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 664                         __func__,
 665                         lane01_status_address, dpcd_buf[0],
 666                         lane01_status_address + 1, dpcd_buf[1]);
 667         }
 668         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 669
 670         if (is_repeater(link, offset))
 671                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 672                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 673
 674         if (is_repeater(link, offset)) {
 675                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 676                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 677                                         __func__,
 678                                         offset,
 679                                         lane01_adjust_address,
 680                                         dpcd_buf[lane_adjust_offset],
 681                                         lane01_adjust_address + 1,
 682                                         dpcd_buf[lane_adjust_offset + 1]);
 683         } else {
 684                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 685                         __func__,
 686                         lane01_adjust_address,
 687                         dpcd_buf[lane_adjust_offset],
 688                         lane01_adjust_address + 1,
 689                         dpcd_buf[lane_adjust_offset + 1]);
 690         }
 691
 692         /*copy to req_settings*/
 693         request_settings.link_settings.lane_count =
 694                 link_training_setting->link_settings.lane_count;
 695         request_settings.link_settings.link_rate =
 696                 link_training_setting->link_settings.link_rate;
 697         request_settings.link_settings.link_spread =
 698                 link_training_setting->link_settings.link_spread;
 699
 700         for (lane = 0; lane <
 701                 (uint32_t)(link_training_setting->link_settings.lane_count);
 702                 lane++) {
 703
 704                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 705                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 706                                 VOLTAGE_SWING_LANE);
 707                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 708                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 709                                 PRE_EMPHASIS_LANE);
 710         }
 711
 712         /*Note: for postcursor2, read adjusted
 713          * postcursor2 settings from*/
 714         /*DpcdAddress_AdjustRequestPostCursor2 =
 715          *0x020C (not implemented yet)*/
 716
 717         /* we find the maximum of the requested settings across all lanes*/
 718         /* and set this maximum for all lanes*/
 719         find_max_drive_settings(&request_settings, req_settings);
 720
 721         /* if post cursor 2 is needed in the future,
 722          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 723          */
 724
 725         return status;
 726 }
 727
 728 enum dc_status dpcd_set_lane_settings(
 729         struct dc_link *link,
 730         const struct link_training_settings *link_training_setting,
 731         uint32_t offset)
 732 {
 733         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 734         uint32_t lane;
 735         unsigned int lane0_set_address;
 736         enum dc_status status;
 737
 738         lane0_set_address = DP_TRAINING_LANE0_SET;
 739
 740         if (is_repeater(link, offset))
 741                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 742                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 743
 744         for (lane = 0; lane <
 745                 (uint32_t)(link_training_setting->
 746                 link_settings.lane_count);
 747                 lane++) {
 748                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 749                         (uint8_t)(link_training_setting->
 750                         lane_settings[lane].VOLTAGE_SWING);
 751                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 752                         (uint8_t)(link_training_setting->
 753                         lane_settings[lane].PRE_EMPHASIS);
 754                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 755                         (link_training_setting->
 756                         lane_settings[lane].VOLTAGE_SWING ==
 757                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 758                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 759                         (link_training_setting->
 760                         lane_settings[lane].PRE_EMPHASIS ==
 761                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 762         }
 763
 764         status = core_link_write_dpcd(link,
 765                 lane0_set_address,
 766                 (uint8_t *)(dpcd_lane),
 767                 link_training_setting->link_settings.lane_count);
 768
 769         /*
 770         if (LTSettings.link.rate == LinkRate_High2)
 771         {
 772                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 773                 for ( uint32_t lane = 0;
 774                 lane < lane_count_DPMax; lane++)
 775                 {
 776                         dpcd_lane2[lane].bits.post_cursor2_set =
 777                         static_cast<unsigned char>(
 778                         LTSettings.laneSettings[lane].postCursor2);
 779                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 780                 }
 781                 m_pDpcdAccessSrv->WriteDpcdData(
 782                 DpcdAddress_Lane0Set2,
 783                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 784                 LTSettings.link.lanes);
 785         }
 786         */
 787
 788         if (is_repeater(link, offset)) {
 789                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 790                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 791                         __func__,
 792                         offset,
 793                         lane0_set_address,
 794                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 795                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 796                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 797                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 798
 799         } else {
 800                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 801                         __func__,
 802                         lane0_set_address,
 803                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 804                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 805                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 806                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 807         }
 808         link->cur_lane_setting = link_training_setting->lane_settings[0];
 809
 810         return status;
 811 }
 812
 813 bool dp_is_max_vs_reached(
 814         const struct link_training_settings *lt_settings)
 815 {
 816         uint32_t lane;
 817         for (lane = 0; lane <
 818                 (uint32_t)(lt_settings->link_settings.lane_count);
 819                 lane++) {
 820                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 821                         == VOLTAGE_SWING_MAX_LEVEL)
 822                         return true;
 823         }
 824         return false;
 825
 826 }
 827
 828 static bool perform_post_lt_adj_req_sequence(
 829         struct dc_link *link,
 830         struct link_training_settings *lt_settings)
 831 {
 832         enum dc_lane_count lane_count =
 833         lt_settings->link_settings.lane_count;
 834
 835         uint32_t adj_req_count;
 836         uint32_t adj_req_timer;
 837         bool req_drv_setting_changed;
 838         uint32_t lane;
 839
 840         req_drv_setting_changed = false;
 841         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 842         adj_req_count++) {
 843
 844                 req_drv_setting_changed = false;
 845
 846                 for (adj_req_timer = 0;
 847                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 848                         adj_req_timer++) {
 849
 850                         struct link_training_settings req_settings;
 851                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 852                         union lane_align_status_updated
 853                                 dpcd_lane_status_updated;
 854
 855                         dp_get_lane_status_and_drive_settings(
 856                                 link,
 857                                 lt_settings,
 858                                 dpcd_lane_status,
 859                                 &dpcd_lane_status_updated,
 860                                 &req_settings,
 861                                 DPRX);
 862
 863                         if (dpcd_lane_status_updated.bits.
 864                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 865                                 return true;
 866
 867                         if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 868                                 return false;
 869
 870                         if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
 871                                         !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
 872                                         !dp_is_interlane_aligned(dpcd_lane_status_updated))
 873                                 return false;
 874
 875                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 876
 877                                 if (lt_settings->
 878                                 lane_settings[lane].VOLTAGE_SWING !=
 879                                 req_settings.lane_settings[lane].
 880                                 VOLTAGE_SWING ||
 881                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 882                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 883
 884                                         req_drv_setting_changed = true;
 885                                         break;
 886                                 }
 887                         }
 888
 889                         if (req_drv_setting_changed) {
 890                                 dp_update_drive_settings(
 891                                         lt_settings, req_settings);
 892
 893                                 dc_link_dp_set_drive_settings(link,
 894                                                 lt_settings);
 895                                 break;
 896                         }
 897
 898                         msleep(1);
 899                 }
 900
 901                 if (!req_drv_setting_changed) {
 902                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 903                                 __func__);
 904
 905                         ASSERT(0);
 906                         return true;
 907                 }
 908         }
 909         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 910                 __func__);
 911
 912         ASSERT(0);
 913         return true;
 914
 915 }
 916
 917 /* Only used for channel equalization */
 918 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 919 {
 920         unsigned int aux_rd_interval_us = 400;
 921
 922         switch (dpcd_aux_read_interval) {
 923         case 0x01:
 924                 aux_rd_interval_us = 4000;
 925                 break;
 926         case 0x02:
 927                 aux_rd_interval_us = 8000;
 928                 break;
 929         case 0x03:
 930                 aux_rd_interval_us = 12000;
 931                 break;
 932         case 0x04:
 933                 aux_rd_interval_us = 16000;
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return aux_rd_interval_us;
 940 }
 941
 942 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
 943                                         union lane_status *dpcd_lane_status)
 944 {
 945         enum link_training_result result = LINK_TRAINING_SUCCESS;
 946
 947         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 948                 result = LINK_TRAINING_CR_FAIL_LANE0;
 949         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 950                 result = LINK_TRAINING_CR_FAIL_LANE1;
 951         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 952                 result = LINK_TRAINING_CR_FAIL_LANE23;
 953         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 954                 result = LINK_TRAINING_CR_FAIL_LANE23;
 955         return result;
 956 }
 957
 958 static enum link_training_result perform_channel_equalization_sequence(
 959         struct dc_link *link,
 960         struct link_training_settings *lt_settings,
 961         uint32_t offset)
 962 {
 963         struct link_training_settings req_settings;
 964         enum dc_dp_training_pattern tr_pattern;
 965         uint32_t retries_ch_eq;
 966         uint32_t wait_time_microsec;
 967         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 968         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 969         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 970
 971         /* Note: also check that TPS4 is a supported feature*/
 972
 973         tr_pattern = lt_settings->pattern_for_eq;
 974
 975         if (is_repeater(link, offset))
 976                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 977
 978         dp_set_hw_training_pattern(link, tr_pattern, offset);
 979
 980         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 981                 retries_ch_eq++) {
 982
 983                 dp_set_hw_lane_settings(link, lt_settings, offset);
 984
 985                 /* 2. update DPCD*/
 986                 if (!retries_ch_eq)
 987                         /* EPR #361076 - write as a 5-byte burst,
 988                          * but only for the 1-st iteration
 989                          */
 990
 991                         dpcd_set_lt_pattern_and_lane_settings(
 992                                 link,
 993                                 lt_settings,
 994                                 tr_pattern, offset);
 995                 else
 996                         dpcd_set_lane_settings(link, lt_settings, offset);
 997
 998                 /* 3. wait for receiver to lock-on*/
 999                 wait_time_microsec = lt_settings->eq_pattern_time;
1000
1001                 if (is_repeater(link, offset))
1002                         wait_time_microsec =
1003                                         dp_translate_training_aux_read_interval(
1004                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1005
1006                 dp_wait_for_training_aux_rd_interval(
1007                                 link,
1008                                 wait_time_microsec);
1009
1010                 /* 4. Read lane status and requested
1011                  * drive settings as set by the sink*/
1012
1013                 dp_get_lane_status_and_drive_settings(
1014                         link,
1015                         lt_settings,
1016                         dpcd_lane_status,
1017                         &dpcd_lane_status_updated,
1018                         &req_settings,
1019                         offset);
1020
1021                 /* 5. check CR done*/
1022                 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1023                         return LINK_TRAINING_EQ_FAIL_CR;
1024
1025                 /* 6. check CHEQ done*/
1026                 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1027                                 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1028                                 dp_is_interlane_aligned(dpcd_lane_status_updated))
1029                         return LINK_TRAINING_SUCCESS;
1030
1031                 /* 7. update VS/PE/PC2 in lt_settings*/
1032                 dp_update_drive_settings(lt_settings, req_settings);
1033         }
1034
1035         return LINK_TRAINING_EQ_FAIL_EQ;
1036
1037 }
1038
1039 static void start_clock_recovery_pattern_early(struct dc_link *link,
1040                 struct link_training_settings *lt_settings,
1041                 uint32_t offset)
1042 {
1043         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1044                         __func__);
1045         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1046         dp_set_hw_lane_settings(link, lt_settings, offset);
1047         udelay(400);
1048 }
1049
1050 static enum link_training_result perform_clock_recovery_sequence(
1051         struct dc_link *link,
1052         struct link_training_settings *lt_settings,
1053         uint32_t offset)
1054 {
1055         uint32_t retries_cr;
1056         uint32_t retry_count;
1057         uint32_t wait_time_microsec;
1058         struct link_training_settings req_settings;
1059         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1060         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1061         union lane_align_status_updated dpcd_lane_status_updated;
1062
1063         retries_cr = 0;
1064         retry_count = 0;
1065
1066         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1067                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1068
1069         /* najeeb - The synaptics MST hub can put the LT in
1070         * infinite loop by switching the VS
1071         */
1072         /* between level 0 and level 1 continuously, here
1073         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1074         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1075                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1076
1077                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1078                 memset(&dpcd_lane_status_updated, '\0',
1079                 sizeof(dpcd_lane_status_updated));
1080
1081                 /* 1. call HWSS to set lane settings*/
1082                 dp_set_hw_lane_settings(
1083                                 link,
1084                                 lt_settings,
1085                                 offset);
1086
1087                 /* 2. update DPCD of the receiver*/
1088                 if (!retry_count)
1089                         /* EPR #361076 - write as a 5-byte burst,
1090                          * but only for the 1-st iteration.*/
1091                         dpcd_set_lt_pattern_and_lane_settings(
1092                                         link,
1093                                         lt_settings,
1094                                         lt_settings->pattern_for_cr,
1095                                         offset);
1096                 else
1097                         dpcd_set_lane_settings(
1098                                         link,
1099                                         lt_settings,
1100                                         offset);
1101
1102                 /* 3. wait receiver to lock-on*/
1103                 wait_time_microsec = lt_settings->cr_pattern_time;
1104
1105                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1106                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1107
1108                 dp_wait_for_training_aux_rd_interval(
1109                                 link,
1110                                 wait_time_microsec);
1111
1112                 /* 4. Read lane status and requested drive
1113                 * settings as set by the sink
1114                 */
1115                 dp_get_lane_status_and_drive_settings(
1116                                 link,
1117                                 lt_settings,
1118                                 dpcd_lane_status,
1119                                 &dpcd_lane_status_updated,
1120                                 &req_settings,
1121                                 offset);
1122
1123                 /* 5. check CR done*/
1124                 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1125                         return LINK_TRAINING_SUCCESS;
1126
1127                 /* 6. max VS reached*/
1128                 if (dp_is_max_vs_reached(lt_settings))
1129                         break;
1130
1131                 /* 7. same lane settings*/
1132                 /* Note: settings are the same for all lanes,
1133                  * so comparing first lane is sufficient*/
1134                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1135                         req_settings.lane_settings[0].VOLTAGE_SWING)
1136                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1137                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1138                         retries_cr++;
1139                 else
1140                         retries_cr = 0;
1141
1142                 /* 8. update VS/PE/PC2 in lt_settings*/
1143                 dp_update_drive_settings(lt_settings, req_settings);
1144
1145                 retry_count++;
1146         }
1147
1148         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1149                 ASSERT(0);
1150                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1151                         __func__,
1152                         LINK_TRAINING_MAX_CR_RETRY);
1153
1154         }
1155
1156         return dp_get_cr_failure(lane_count, dpcd_lane_status);
1157 }
1158
1159 static inline enum link_training_result dp_transition_to_video_idle(
1160         struct dc_link *link,
1161         struct link_training_settings *lt_settings,
1162         enum link_training_result status)
1163 {
1164         union lane_count_set lane_count_set = { {0} };
1165
1166         /* 4. mainlink output idle pattern*/
1167         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1168
1169         /*
1170          * 5. post training adjust if required
1171          * If the upstream DPTX and downstream DPRX both support TPS4,
1172          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1173          */
1174         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1175                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1176                 /* delay 5ms after Main Link output idle pattern and then check
1177                  * DPCD 0202h.
1178                  */
1179                 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1180                         msleep(5);
1181                         status = dp_check_link_loss_status(link, lt_settings);
1182                 }
1183                 return status;
1184         }
1185
1186         if (status == LINK_TRAINING_SUCCESS &&
1187                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1188                 status = LINK_TRAINING_LQA_FAIL;
1189
1190         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1191         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1192         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1193
1194         core_link_write_dpcd(
1195                 link,
1196                 DP_LANE_COUNT_SET,
1197                 &lane_count_set.raw,
1198                 sizeof(lane_count_set));
1199
1200         return status;
1201 }
1202
1203 enum link_training_result dp_check_link_loss_status(
1204         struct dc_link *link,
1205         const struct link_training_settings *link_training_setting)
1206 {
1207         enum link_training_result status = LINK_TRAINING_SUCCESS;
1208         union lane_status lane_status;
1209         uint8_t dpcd_buf[6] = {0};
1210         uint32_t lane;
1211
1212         core_link_read_dpcd(
1213                         link,
1214                         DP_SINK_COUNT,
1215                         (uint8_t *)(dpcd_buf),
1216                         sizeof(dpcd_buf));
1217
1218         /*parse lane status*/
1219         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1220                 /*
1221                  * check lanes status
1222                  */
1223                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1224
1225                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1226                         !lane_status.bits.CR_DONE_0 ||
1227                         !lane_status.bits.SYMBOL_LOCKED_0) {
1228                         /* if one of the channel equalization, clock
1229                          * recovery or symbol lock is dropped
1230                          * consider it as (link has been
1231                          * dropped) dp sink status has changed
1232                          */
1233                         status = LINK_TRAINING_LINK_LOSS;
1234                         break;
1235                 }
1236         }
1237
1238         return status;
1239 }
1240
1241 static inline void decide_8b_10b_training_settings(
1242          struct dc_link *link,
1243         const struct dc_link_settings *link_setting,
1244         const struct dc_link_training_overrides *overrides,
1245         struct link_training_settings *lt_settings)
1246 {
1247         uint32_t lane;
1248
1249         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1250
1251         /* Initialize link settings */
1252         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1253         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1254
1255         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1256                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1257         else
1258                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1259
1260         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1261                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1262         else
1263                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1264
1265         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1266
1267         /* TODO hard coded to SS for now
1268          * lt_settings.link_settings.link_spread =
1269          * dal_display_path_is_ss_supported(
1270          * path_mode->display_path) ?
1271          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1272          * LINK_SPREAD_DISABLED;
1273          */
1274         /* Initialize link spread */
1275         if (link->dp_ss_off)
1276                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1277         else if (overrides->downspread != NULL)
1278                 lt_settings->link_settings.link_spread
1279                         = *overrides->downspread
1280                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1281                         : LINK_SPREAD_DISABLED;
1282         else
1283                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1284
1285         lt_settings->lttpr_mode = link->lttpr_mode;
1286
1287         /* Initialize lane settings overrides */
1288         if (overrides->voltage_swing != NULL)
1289                 lt_settings->voltage_swing = overrides->voltage_swing;
1290
1291         if (overrides->pre_emphasis != NULL)
1292                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1293
1294         if (overrides->post_cursor2 != NULL)
1295                 lt_settings->post_cursor2 = overrides->post_cursor2;
1296
1297         /* Initialize lane settings (VS/PE/PC2) */
1298         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1299                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1300                         lt_settings->voltage_swing != NULL ?
1301                         *lt_settings->voltage_swing :
1302                         VOLTAGE_SWING_LEVEL0;
1303                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1304                         lt_settings->pre_emphasis != NULL ?
1305                         *lt_settings->pre_emphasis
1306                         : PRE_EMPHASIS_DISABLED;
1307                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1308                         lt_settings->post_cursor2 != NULL ?
1309                         *lt_settings->post_cursor2
1310                         : POST_CURSOR2_DISABLED;
1311         }
1312
1313         /* Initialize training timings */
1314         if (overrides->cr_pattern_time != NULL)
1315                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1316         else
1317                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1318
1319         if (overrides->eq_pattern_time != NULL)
1320                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1321         else
1322                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1323
1324         if (overrides->pattern_for_cr != NULL)
1325                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1326         else
1327                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1328         if (overrides->pattern_for_eq != NULL)
1329                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1330         else
1331                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1332
1333         if (overrides->enhanced_framing != NULL)
1334                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1335         else
1336                 lt_settings->enhanced_framing = 1;
1337
1338         if (link->preferred_training_settings.fec_enable != NULL)
1339                 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1340         else
1341                 lt_settings->should_set_fec_ready = true;
1342 }
1343
1344 void dp_decide_training_settings(
1345                 struct dc_link *link,
1346                 const struct dc_link_settings *link_settings,
1347                 const struct dc_link_training_overrides *overrides,
1348                 struct link_training_settings *lt_settings)
1349 {
1350         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1351                 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1352 }
1353
1354
1355 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1356 {
1357         switch (lttpr_repeater_count) {
1358         case 0x80: // 1 lttpr repeater
1359                 return 1;
1360         case 0x40: // 2 lttpr repeaters
1361                 return 2;
1362         case 0x20: // 3 lttpr repeaters
1363                 return 3;
1364         case 0x10: // 4 lttpr repeaters
1365                 return 4;
1366         case 0x08: // 5 lttpr repeaters
1367                 return 5;
1368         case 0x04: // 6 lttpr repeaters
1369                 return 6;
1370         case 0x02: // 7 lttpr repeaters
1371                 return 7;
1372         case 0x01: // 8 lttpr repeaters
1373                 return 8;
1374         default:
1375                 break;
1376         }
1377         return 0; // invalid value
1378 }
1379
1380 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1381 {
1382         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1383
1384         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1385         return core_link_write_dpcd(link,
1386                         DP_PHY_REPEATER_MODE,
1387                         (uint8_t *)&repeater_mode,
1388                         sizeof(repeater_mode));
1389 }
1390
1391 enum dc_status configure_lttpr_mode_non_transparent(
1392                 struct dc_link *link,
1393                 const struct link_training_settings *lt_settings)
1394 {
1395         /* aux timeout is already set to extended */
1396         /* RESET/SET lttpr mode to enable non transparent mode */
1397         uint8_t repeater_cnt;
1398         uint32_t aux_interval_address;
1399         uint8_t repeater_id;
1400         enum dc_status result = DC_ERROR_UNEXPECTED;
1401         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1402
1403         enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1404
1405         if (encoding == DP_8b_10b_ENCODING) {
1406                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1407                 result = core_link_write_dpcd(link,
1408                                 DP_PHY_REPEATER_MODE,
1409                                 (uint8_t *)&repeater_mode,
1410                                 sizeof(repeater_mode));
1411
1412         }
1413
1414         if (result == DC_OK) {
1415                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1416         }
1417
1418         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1419
1420                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1421
1422                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1423                 result = core_link_write_dpcd(link,
1424                                 DP_PHY_REPEATER_MODE,
1425                                 (uint8_t *)&repeater_mode,
1426                                 sizeof(repeater_mode));
1427
1428                 if (result == DC_OK) {
1429                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1430                 }
1431
1432                 if (encoding == DP_8b_10b_ENCODING) {
1433                         repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1434                         for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1435                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1436                                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1437                                 core_link_read_dpcd(
1438                                         link,
1439                                         aux_interval_address,
1440                                         (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1441                                         sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1442                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1443                         }
1444                 }
1445         }
1446
1447         return result;
1448 }
1449
1450 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1451 {
1452         union dpcd_training_pattern dpcd_pattern = { {0} };
1453
1454         const uint32_t dpcd_base_lt_offset =
1455                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1456                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1457         /* Set training not in progress*/
1458         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1459
1460         core_link_write_dpcd(
1461                 link,
1462                 dpcd_base_lt_offset,
1463                 &dpcd_pattern.raw,
1464                 1);
1465
1466         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1467                 __func__,
1468                 offset,
1469                 dpcd_base_lt_offset,
1470                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1471 }
1472
1473 static void print_status_message(
1474         struct dc_link *link,
1475         const struct link_training_settings *lt_settings,
1476         enum link_training_result status)
1477 {
1478         char *link_rate = "Unknown";
1479         char *lt_result = "Unknown";
1480         char *lt_spread = "Disabled";
1481
1482         switch (lt_settings->link_settings.link_rate) {
1483         case LINK_RATE_LOW:
1484                 link_rate = "RBR";
1485                 break;
1486         case LINK_RATE_RATE_2:
1487                 link_rate = "R2";
1488                 break;
1489         case LINK_RATE_RATE_3:
1490                 link_rate = "R3";
1491                 break;
1492         case LINK_RATE_HIGH:
1493                 link_rate = "HBR";
1494                 break;
1495         case LINK_RATE_RBR2:
1496                 link_rate = "RBR2";
1497                 break;
1498         case LINK_RATE_RATE_6:
1499                 link_rate = "R6";
1500                 break;
1501         case LINK_RATE_HIGH2:
1502                 link_rate = "HBR2";
1503                 break;
1504         case LINK_RATE_HIGH3:
1505                 link_rate = "HBR3";
1506                 break;
1507         default:
1508                 break;
1509         }
1510
1511         switch (status) {
1512         case LINK_TRAINING_SUCCESS:
1513                 lt_result = "pass";
1514                 break;
1515         case LINK_TRAINING_CR_FAIL_LANE0:
1516                 lt_result = "CR failed lane0";
1517                 break;
1518         case LINK_TRAINING_CR_FAIL_LANE1:
1519                 lt_result = "CR failed lane1";
1520                 break;
1521         case LINK_TRAINING_CR_FAIL_LANE23:
1522                 lt_result = "CR failed lane23";
1523                 break;
1524         case LINK_TRAINING_EQ_FAIL_CR:
1525                 lt_result = "CR failed in EQ";
1526                 break;
1527         case LINK_TRAINING_EQ_FAIL_EQ:
1528                 lt_result = "EQ failed";
1529                 break;
1530         case LINK_TRAINING_LQA_FAIL:
1531                 lt_result = "LQA failed";
1532                 break;
1533         case LINK_TRAINING_LINK_LOSS:
1534                 lt_result = "Link loss";
1535                 break;
1536         default:
1537                 break;
1538         }
1539
1540         switch (lt_settings->link_settings.link_spread) {
1541         case LINK_SPREAD_DISABLED:
1542                 lt_spread = "Disabled";
1543                 break;
1544         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1545                 lt_spread = "0.5% 30KHz";
1546                 break;
1547         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1548                 lt_spread = "0.5% 33KHz";
1549                 break;
1550         default:
1551                 break;
1552         }
1553
1554         /* Connectivity log: link training */
1555         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1556                                 link_rate,
1557                                 lt_settings->link_settings.lane_count,
1558                                 lt_result,
1559                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1560                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1561                                 lt_spread);
1562 }
1563
1564 void dc_link_dp_set_drive_settings(
1565         struct dc_link *link,
1566         struct link_training_settings *lt_settings)
1567 {
1568         /* program ASIC PHY settings*/
1569         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1570
1571         /* Notify DP sink the PHY settings from source */
1572         dpcd_set_lane_settings(link, lt_settings, DPRX);
1573 }
1574
1575 bool dc_link_dp_perform_link_training_skip_aux(
1576         struct dc_link *link,
1577         const struct dc_link_settings *link_setting)
1578 {
1579         struct link_training_settings lt_settings;
1580
1581         dp_decide_training_settings(
1582                         link,
1583                         link_setting,
1584                         &link->preferred_training_settings,
1585                         &lt_settings);
1586
1587         /* 1. Perform_clock_recovery_sequence. */
1588
1589         /* transmit training pattern for clock recovery */
1590         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1591
1592         /* call HWSS to set lane settings*/
1593         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1594
1595         /* wait receiver to lock-on*/
1596         dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1597
1598         /* 2. Perform_channel_equalization_sequence. */
1599
1600         /* transmit training pattern for channel equalization. */
1601         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1602
1603         /* call HWSS to set lane settings*/
1604         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1605
1606         /* wait receiver to lock-on. */
1607         dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1608
1609         /* 3. Perform_link_training_int. */
1610
1611         /* Mainlink output idle pattern. */
1612         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1613
1614         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1615
1616         return true;
1617 }
1618
1619 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1620 {
1621         enum dc_status status = DC_OK;
1622
1623         if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1624                 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1625         else
1626                 status = configure_lttpr_mode_transparent(link);
1627
1628         return status;
1629 }
1630
1631 static void dpcd_exit_training_mode(struct dc_link *link)
1632 {
1633
1634         /* clear training pattern set */
1635         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1636 }
1637
1638 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1639                 struct link_training_settings *lt_settings)
1640 {
1641         enum dp_link_encoding encoding =
1642                         dp_get_link_encoding_format(
1643                                         &lt_settings->link_settings);
1644         enum dc_status status;
1645
1646         status = core_link_write_dpcd(
1647                         link,
1648                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1649                         (uint8_t *) &encoding,
1650                         1);
1651         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1652                                         __func__,
1653                                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1654                                         encoding);
1655
1656         return status;
1657 }
1658
1659 static enum link_training_result dp_perform_8b_10b_link_training(
1660                 struct dc_link *link,
1661                 struct link_training_settings *lt_settings)
1662 {
1663         enum link_training_result status = LINK_TRAINING_SUCCESS;
1664
1665         uint8_t repeater_cnt;
1666         uint8_t repeater_id;
1667         uint8_t lane = 0;
1668
1669         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1670                 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
1671
1672         /* 1. set link rate, lane count and spread. */
1673         dpcd_set_link_settings(link, lt_settings);
1674
1675         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1676
1677                 /* 2. perform link training (set link training done
1678                  *  to false is done as well)
1679                  */
1680                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1681
1682                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1683                                 repeater_id--) {
1684                         status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
1685
1686                         if (status != LINK_TRAINING_SUCCESS)
1687                                 break;
1688
1689                         status = perform_channel_equalization_sequence(link,
1690                                         lt_settings,
1691                                         repeater_id);
1692
1693                         if (status != LINK_TRAINING_SUCCESS)
1694                                 break;
1695
1696                         repeater_training_done(link, repeater_id);
1697                 }
1698
1699                 for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
1700                         lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
1701         }
1702
1703         if (status == LINK_TRAINING_SUCCESS) {
1704                 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
1705         if (status == LINK_TRAINING_SUCCESS) {
1706                 status = perform_channel_equalization_sequence(link,
1707                                         lt_settings,
1708                                         DPRX);
1709                 }
1710         }
1711
1712         return status;
1713 }
1714
1715 enum link_training_result dc_link_dp_perform_link_training(
1716         struct dc_link *link,
1717         const struct dc_link_settings *link_settings,
1718         bool skip_video_pattern)
1719 {
1720         enum link_training_result status = LINK_TRAINING_SUCCESS;
1721         struct link_training_settings lt_settings;
1722         enum dp_link_encoding encoding =
1723                         dp_get_link_encoding_format(link_settings);
1724
1725         /* decide training settings */
1726         dp_decide_training_settings(
1727                         link,
1728                         link_settings,
1729                         &link->preferred_training_settings,
1730                         &lt_settings);
1731
1732         /* reset previous training states */
1733         dpcd_exit_training_mode(link);
1734
1735         /* configure link prior to entering training mode */
1736         dpcd_configure_lttpr_mode(link, &lt_settings);
1737         dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1738         dpcd_configure_channel_coding(link, &lt_settings);
1739
1740         /* enter training mode:
1741          * Per DP specs starting from here, DPTX device shall not issue
1742          * Non-LT AUX transactions inside training mode.
1743          */
1744         if (encoding == DP_8b_10b_ENCODING)
1745                 status = dp_perform_8b_10b_link_training(link, &lt_settings);
1746         else
1747                 ASSERT(0);
1748
1749         /* exit training mode and switch to video idle */
1750         dpcd_exit_training_mode(link);
1751         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1752                 status = dp_transition_to_video_idle(link,
1753                                 &lt_settings,
1754                                 status);
1755
1756         /* dump debug data */
1757         print_status_message(link, &lt_settings, status);
1758         if (status != LINK_TRAINING_SUCCESS)
1759                 link->ctx->dc->debug_data.ltFailCount++;
1760         return status;
1761 }
1762
1763 bool perform_link_training_with_retries(
1764         const struct dc_link_settings *link_setting,
1765         bool skip_video_pattern,
1766         int attempts,
1767         struct pipe_ctx *pipe_ctx,
1768         enum signal_type signal,
1769         bool do_fallback)
1770 {
1771         int j;
1772         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1773         struct dc_stream_state *stream = pipe_ctx->stream;
1774         struct dc_link *link = stream->link;
1775         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1776         struct link_encoder *link_enc;
1777         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1778         struct dc_link_settings current_setting = *link_setting;
1779
1780         /* Dynamically assigned link encoders associated with stream rather than
1781          * link.
1782          */
1783         if (link->dc->res_pool->funcs->link_encs_assign)
1784                 link_enc = stream->link_enc;
1785         else
1786                 link_enc = link->link_enc;
1787         ASSERT(link_enc);
1788
1789         /* We need to do this before the link training to ensure the idle pattern in SST
1790          * mode will be sent right after the link training
1791          */
1792         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1793                                                         pipe_ctx->stream_res.stream_enc->id, true);
1794
1795         for (j = 0; j < attempts; ++j) {
1796
1797                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1798                         __func__, (unsigned int)j + 1, attempts);
1799
1800                 dp_enable_link_phy(
1801                         link,
1802                         signal,
1803                         pipe_ctx->clock_source->id,
1804                         &current_setting);
1805
1806                 if (stream->sink_patches.dppowerup_delay > 0) {
1807                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1808
1809                         msleep(delay_dp_power_up_in_ms);
1810                 }
1811
1812 #ifdef CONFIG_DRM_AMD_DC_HDCP
1813                 if (panel_mode == DP_PANEL_MODE_EDP) {
1814                         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1815
1816                         if (cp_psp && cp_psp->funcs.enable_assr) {
1817                                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1818                                         /* since eDP implies ASSR on, change panel
1819                                          * mode to disable ASSR
1820                                          */
1821                                         panel_mode = DP_PANEL_MODE_DEFAULT;
1822                                 }
1823                         } else
1824                                 panel_mode = DP_PANEL_MODE_DEFAULT;
1825                 }
1826 #endif
1827
1828                 dp_set_panel_mode(link, panel_mode);
1829
1830                 if (link->aux_access_disabled) {
1831                         dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
1832                         return true;
1833                 } else {
1834                                 status = dc_link_dp_perform_link_training(
1835                                                                                 link,
1836                                                                                 &current_setting,
1837                                                                                 skip_video_pattern);
1838                         if (status == LINK_TRAINING_SUCCESS)
1839                                 return true;
1840                 }
1841
1842                 /* latest link training still fail, skip delay and keep PHY on
1843                  */
1844                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1845                         break;
1846
1847                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1848                         __func__, (unsigned int)j + 1, attempts);
1849
1850                 dp_disable_link_phy(link, signal);
1851
1852                 /* Abort link training if failure due to sink being unplugged. */
1853                 if (status == LINK_TRAINING_ABORT)
1854                         break;
1855                 else if (do_fallback) {
1856                         decide_fallback_link_setting(*link_setting, &current_setting, status);
1857                         /* Fail link training if reduced link bandwidth no longer meets
1858                          * stream requirements.
1859                          */
1860                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1861                                         dc_link_bandwidth_kbps(link, &current_setting))
1862                                 break;
1863                 }
1864
1865                 msleep(delay_between_attempts);
1866
1867                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1868         }
1869
1870         return false;
1871 }
1872
1873 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1874 {
1875         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1876         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1877
1878         if (dp_cs != NULL) {
1879                 dp_cs_id = dp_cs->id;
1880         } else {
1881                 /*
1882                  * dp clock source is not initialized for some reason.
1883                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1884                  */
1885                 ASSERT(dp_cs);
1886         }
1887
1888         return dp_cs_id;
1889 }
1890
1891 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1892 {
1893         if (mst_enable == false &&
1894                 link->type == dc_connection_mst_branch) {
1895                 /* Disable MST on link. Use only local sink. */
1896                 dp_disable_link_phy_mst(link, link->connector_signal);
1897
1898                 link->type = dc_connection_single;
1899                 link->local_sink = link->remote_sinks[0];
1900                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1901                 dc_sink_retain(link->local_sink);
1902                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1903         } else if (mst_enable == true &&
1904                         link->type == dc_connection_single &&
1905                         link->remote_sinks[0] != NULL) {
1906                 /* Re-enable MST on link. */
1907                 dp_disable_link_phy(link, link->connector_signal);
1908                 dp_enable_mst_on_sink(link, true);
1909
1910                 link->type = dc_connection_mst_branch;
1911                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1912         }
1913 }
1914
1915 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1916 {
1917         /* Begin Sync LT. During this time,
1918          * DPCD:600h must not be powered down.
1919          */
1920         link->sync_lt_in_progress = true;
1921
1922         /*Clear any existing preferred settings.*/
1923         memset(&link->preferred_training_settings, 0,
1924                 sizeof(struct dc_link_training_overrides));
1925         memset(&link->preferred_link_setting, 0,
1926                 sizeof(struct dc_link_settings));
1927
1928         return true;
1929 }
1930
1931 enum link_training_result dc_link_dp_sync_lt_attempt(
1932     struct dc_link *link,
1933     struct dc_link_settings *link_settings,
1934     struct dc_link_training_overrides *lt_overrides)
1935 {
1936         struct link_training_settings lt_settings;
1937         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1938         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1939         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1940         bool fec_enable = false;
1941
1942         dp_decide_training_settings(
1943                 link,
1944                 link_settings,
1945                 lt_overrides,
1946                 &lt_settings);
1947
1948         /* Setup MST Mode */
1949         if (lt_overrides->mst_enable)
1950                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1951
1952         /* Disable link */
1953         dp_disable_link_phy(link, link->connector_signal);
1954
1955         /* Enable link */
1956         dp_cs_id = get_clock_source_id(link);
1957         dp_enable_link_phy(link, link->connector_signal,
1958                 dp_cs_id, link_settings);
1959
1960         /* Set FEC enable */
1961         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1962         dp_set_fec_ready(link, fec_enable);
1963
1964         if (lt_overrides->alternate_scrambler_reset) {
1965                 if (*lt_overrides->alternate_scrambler_reset)
1966                         panel_mode = DP_PANEL_MODE_EDP;
1967                 else
1968                         panel_mode = DP_PANEL_MODE_DEFAULT;
1969         } else
1970                 panel_mode = dp_get_panel_mode(link);
1971
1972         dp_set_panel_mode(link, panel_mode);
1973
1974         /* Attempt to train with given link training settings */
1975         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1976                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1977
1978         /* Set link rate, lane count and spread. */
1979         dpcd_set_link_settings(link, &lt_settings);
1980
1981         /* 2. perform link training (set link training done
1982          *  to false is done as well)
1983          */
1984         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1985         if (lt_status == LINK_TRAINING_SUCCESS) {
1986                 lt_status = perform_channel_equalization_sequence(link,
1987                                                 &lt_settings,
1988                                                 DPRX);
1989         }
1990
1991         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1992         /* 4. print status message*/
1993         print_status_message(link, &lt_settings, lt_status);
1994
1995         return lt_status;
1996 }
1997
1998 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1999 {
2000         /* If input parameter is set, shut down phy.
2001          * Still shouldn't turn off dp_receiver (DPCD:600h)
2002          */
2003         if (link_down == true) {
2004                 dp_disable_link_phy(link, link->connector_signal);
2005                 dp_set_fec_ready(link, false);
2006         }
2007
2008         link->sync_lt_in_progress = false;
2009         return true;
2010 }
2011
2012 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2013 {
2014         if (!max_link_enc_cap) {
2015                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2016                 return false;
2017         }
2018
2019         if (link->link_enc->funcs->get_max_link_cap) {
2020                 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2021                 return true;
2022         }
2023
2024         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2025         max_link_enc_cap->lane_count = 1;
2026         max_link_enc_cap->link_rate = 6;
2027         return false;
2028 }
2029
2030 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2031 {
2032         struct dc_link_settings max_link_cap = {0};
2033
2034         /* get max link encoder capability */
2035         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
2036
2037         /* Lower link settings based on sink's link cap */
2038         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2039                 max_link_cap.lane_count =
2040                                 link->reported_link_cap.lane_count;
2041         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2042                 max_link_cap.link_rate =
2043                                 link->reported_link_cap.link_rate;
2044         if (link->reported_link_cap.link_spread <
2045                         max_link_cap.link_spread)
2046                 max_link_cap.link_spread =
2047                                 link->reported_link_cap.link_spread;
2048         /*
2049          * account for lttpr repeaters cap
2050          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2051          */
2052         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2053                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2054                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2055
2056                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2057                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2058
2059                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2060                                                 __func__,
2061                                                 max_link_cap.lane_count,
2062                                                 max_link_cap.link_rate);
2063         }
2064         return max_link_cap;
2065 }
2066
2067 enum dc_status read_hpd_rx_irq_data(
2068         struct dc_link *link,
2069         union hpd_irq_data *irq_data)
2070 {
2071         static enum dc_status retval;
2072
2073         /* The HW reads 16 bytes from 200h on HPD,
2074          * but if we get an AUX_DEFER, the HW cannot retry
2075          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2076          * fail, so we now explicitly read 6 bytes which is
2077          * the req from the above mentioned test cases.
2078          *
2079          * For DP 1.4 we need to read those from 2002h range.
2080          */
2081         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2082                 retval = core_link_read_dpcd(
2083                         link,
2084                         DP_SINK_COUNT,
2085                         irq_data->raw,
2086                         sizeof(union hpd_irq_data));
2087         else {
2088                 /* Read 14 bytes in a single read and then copy only the required fields.
2089                  * This is more efficient than doing it in two separate AUX reads. */
2090
2091                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2092
2093                 retval = core_link_read_dpcd(
2094                         link,
2095                         DP_SINK_COUNT_ESI,
2096                         tmp,
2097                         sizeof(tmp));
2098
2099                 if (retval != DC_OK)
2100                         return retval;
2101
2102                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2103                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2104                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2105                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2106                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2107                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2108         }
2109
2110         return retval;
2111 }
2112
2113 bool hpd_rx_irq_check_link_loss_status(
2114         struct dc_link *link,
2115         union hpd_irq_data *hpd_irq_dpcd_data)
2116 {
2117         uint8_t irq_reg_rx_power_state = 0;
2118         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2119         union lane_status lane_status;
2120         uint32_t lane;
2121         bool sink_status_changed;
2122         bool return_code;
2123
2124         sink_status_changed = false;
2125         return_code = false;
2126
2127         if (link->cur_link_settings.lane_count == 0)
2128                 return return_code;
2129
2130         /*1. Check that Link Status changed, before re-training.*/
2131
2132         /*parse lane status*/
2133         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2134                 /* check status of lanes 0,1
2135                  * changed DpcdAddress_Lane01Status (0x202)
2136                  */
2137                 lane_status.raw = get_nibble_at_index(
2138                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2139                         lane);
2140
2141                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2142                         !lane_status.bits.CR_DONE_0 ||
2143                         !lane_status.bits.SYMBOL_LOCKED_0) {
2144                         /* if one of the channel equalization, clock
2145                          * recovery or symbol lock is dropped
2146                          * consider it as (link has been
2147                          * dropped) dp sink status has changed
2148                          */
2149                         sink_status_changed = true;
2150                         break;
2151                 }
2152         }
2153
2154         /* Check interlane align.*/
2155         if (sink_status_changed ||
2156                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2157
2158                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2159
2160                 return_code = true;
2161
2162                 /*2. Check that we can handle interrupt: Not in FS DOS,
2163                  *  Not in "Display Timeout" state, Link is trained.
2164                  */
2165                 dpcd_result = core_link_read_dpcd(link,
2166                         DP_SET_POWER,
2167                         &irq_reg_rx_power_state,
2168                         sizeof(irq_reg_rx_power_state));
2169
2170                 if (dpcd_result != DC_OK) {
2171                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2172                                 __func__);
2173                 } else {
2174                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2175                                 return_code = false;
2176                 }
2177         }
2178
2179         return return_code;
2180 }
2181
2182 bool dp_verify_link_cap(
2183         struct dc_link *link,
2184         struct dc_link_settings *known_limit_link_setting,
2185         int *fail_count)
2186 {
2187         struct dc_link_settings max_link_cap = {0};
2188         struct dc_link_settings cur_link_setting = {0};
2189         struct dc_link_settings *cur = &cur_link_setting;
2190         struct dc_link_settings initial_link_settings = {0};
2191         bool success;
2192         bool skip_link_training;
2193         bool skip_video_pattern;
2194         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2195         enum link_training_result status;
2196         union hpd_irq_data irq_data;
2197
2198         if (link->dc->debug.skip_detection_link_training) {
2199                 link->verified_link_cap = *known_limit_link_setting;
2200                 return true;
2201         }
2202
2203         memset(&irq_data, 0, sizeof(irq_data));
2204         success = false;
2205         skip_link_training = false;
2206
2207         max_link_cap = get_max_link_cap(link);
2208
2209         /* Grant extended timeout request */
2210         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2211                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2212
2213                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2214         }
2215
2216         /* TODO implement override and monitor patch later */
2217
2218         /* try to train the link from high to low to
2219          * find the physical link capability
2220          */
2221         /* disable PHY done possible by BIOS, will be done by driver itself */
2222         dp_disable_link_phy(link, link->connector_signal);
2223
2224         dp_cs_id = get_clock_source_id(link);
2225
2226         /* link training starts with the maximum common settings
2227          * supported by both sink and ASIC.
2228          */
2229         initial_link_settings = get_common_supported_link_settings(
2230                         *known_limit_link_setting,
2231                         max_link_cap);
2232         cur_link_setting = initial_link_settings;
2233
2234         /* Temporary Renoir-specific workaround for SWDEV-215184;
2235          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2236          * so add extra cycle of enabling and disabling the PHY before first link training.
2237          */
2238         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2239                         link->dc->debug.usbc_combo_phy_reset_wa) {
2240                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2241                 dp_disable_link_phy(link, link->connector_signal);
2242         }
2243
2244         do {
2245                 skip_video_pattern = true;
2246
2247                 if (cur->link_rate == LINK_RATE_LOW)
2248                         skip_video_pattern = false;
2249
2250                 dp_enable_link_phy(
2251                                 link,
2252                                 link->connector_signal,
2253                                 dp_cs_id,
2254                                 cur);
2255
2256
2257                 if (skip_link_training)
2258                         success = true;
2259                 else {
2260                         status = dc_link_dp_perform_link_training(
2261                                                         link,
2262                                                         cur,
2263                                                         skip_video_pattern);
2264                         if (status == LINK_TRAINING_SUCCESS)
2265                                 success = true;
2266                         else
2267                                 (*fail_count)++;
2268                 }
2269
2270                 if (success) {
2271                         link->verified_link_cap = *cur;
2272                         udelay(1000);
2273                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2274                                 if (hpd_rx_irq_check_link_loss_status(
2275                                                 link,
2276                                                 &irq_data))
2277                                         (*fail_count)++;
2278                 }
2279                 /* always disable the link before trying another
2280                  * setting or before returning we'll enable it later
2281                  * based on the actual mode we're driving
2282                  */
2283                 dp_disable_link_phy(link, link->connector_signal);
2284         } while (!success && decide_fallback_link_setting(
2285                         initial_link_settings, cur, status));
2286
2287         /* Link Training failed for all Link Settings
2288          *  (Lane Count is still unknown)
2289          */
2290         if (!success) {
2291                 /* If all LT fails for all settings,
2292                  * set verified = failed safe (1 lane low)
2293                  */
2294                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2295                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2296
2297                 link->verified_link_cap.link_spread =
2298                 LINK_SPREAD_DISABLED;
2299         }
2300
2301
2302         return success;
2303 }
2304
2305 bool dp_verify_link_cap_with_retries(
2306         struct dc_link *link,
2307         struct dc_link_settings *known_limit_link_setting,
2308         int attempts)
2309 {
2310         int i = 0;
2311         bool success = false;
2312
2313         for (i = 0; i < attempts; i++) {
2314                 int fail_count = 0;
2315                 enum dc_connection_type type = dc_connection_none;
2316
2317                 memset(&link->verified_link_cap, 0,
2318                                 sizeof(struct dc_link_settings));
2319                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2320                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2321                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2322                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2323                         break;
2324                 } else if (dp_verify_link_cap(link,
2325                                 &link->reported_link_cap,
2326                                 &fail_count) && fail_count == 0) {
2327                         success = true;
2328                         break;
2329                 }
2330                 msleep(10);
2331         }
2332         return success;
2333 }
2334
2335 bool dp_verify_mst_link_cap(
2336         struct dc_link *link)
2337 {
2338         struct dc_link_settings max_link_cap = {0};
2339
2340         max_link_cap = get_max_link_cap(link);
2341         link->verified_link_cap = get_common_supported_link_settings(
2342                 link->reported_link_cap,
2343                 max_link_cap);
2344
2345         return true;
2346 }
2347
2348 static struct dc_link_settings get_common_supported_link_settings(
2349                 struct dc_link_settings link_setting_a,
2350                 struct dc_link_settings link_setting_b)
2351 {
2352         struct dc_link_settings link_settings = {0};
2353
2354         link_settings.lane_count =
2355                 (link_setting_a.lane_count <=
2356                         link_setting_b.lane_count) ?
2357                         link_setting_a.lane_count :
2358                         link_setting_b.lane_count;
2359         link_settings.link_rate =
2360                 (link_setting_a.link_rate <=
2361                         link_setting_b.link_rate) ?
2362                         link_setting_a.link_rate :
2363                         link_setting_b.link_rate;
2364         link_settings.link_spread = LINK_SPREAD_DISABLED;
2365
2366         /* in DP compliance test, DPR-120 may have
2367          * a random value in its MAX_LINK_BW dpcd field.
2368          * We map it to the maximum supported link rate that
2369          * is smaller than MAX_LINK_BW in this case.
2370          */
2371         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2372                 link_settings.link_rate = LINK_RATE_HIGH3;
2373         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2374                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2375                 link_settings.link_rate = LINK_RATE_HIGH2;
2376         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2377                         && link_settings.link_rate > LINK_RATE_HIGH) {
2378                 link_settings.link_rate = LINK_RATE_HIGH;
2379         } else if (link_settings.link_rate < LINK_RATE_HIGH
2380                         && link_settings.link_rate > LINK_RATE_LOW) {
2381                 link_settings.link_rate = LINK_RATE_LOW;
2382         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2383                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2384         }
2385
2386         return link_settings;
2387 }
2388
2389 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2390 {
2391         return lane_count <= LANE_COUNT_ONE;
2392 }
2393
2394 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2395 {
2396         return link_rate <= LINK_RATE_LOW;
2397 }
2398
2399 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2400 {
2401         switch (lane_count) {
2402         case LANE_COUNT_FOUR:
2403                 return LANE_COUNT_TWO;
2404         case LANE_COUNT_TWO:
2405                 return LANE_COUNT_ONE;
2406         case LANE_COUNT_ONE:
2407                 return LANE_COUNT_UNKNOWN;
2408         default:
2409                 return LANE_COUNT_UNKNOWN;
2410         }
2411 }
2412
2413 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2414 {
2415         switch (link_rate) {
2416         case LINK_RATE_HIGH3:
2417                 return LINK_RATE_HIGH2;
2418         case LINK_RATE_HIGH2:
2419                 return LINK_RATE_HIGH;
2420         case LINK_RATE_HIGH:
2421                 return LINK_RATE_LOW;
2422         case LINK_RATE_LOW:
2423                 return LINK_RATE_UNKNOWN;
2424         default:
2425                 return LINK_RATE_UNKNOWN;
2426         }
2427 }
2428
2429 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2430 {
2431         switch (lane_count) {
2432         case LANE_COUNT_ONE:
2433                 return LANE_COUNT_TWO;
2434         case LANE_COUNT_TWO:
2435                 return LANE_COUNT_FOUR;
2436         default:
2437                 return LANE_COUNT_UNKNOWN;
2438         }
2439 }
2440
2441 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2442 {
2443         switch (link_rate) {
2444         case LINK_RATE_LOW:
2445                 return LINK_RATE_HIGH;
2446         case LINK_RATE_HIGH:
2447                 return LINK_RATE_HIGH2;
2448         case LINK_RATE_HIGH2:
2449                 return LINK_RATE_HIGH3;
2450         default:
2451                 return LINK_RATE_UNKNOWN;
2452         }
2453 }
2454
2455 /*
2456  * function: set link rate and lane count fallback based
2457  * on current link setting and last link training result
2458  * return value:
2459  *                      true - link setting could be set
2460  *                      false - has reached minimum setting
2461  *                                      and no further fallback could be done
2462  */
2463 static bool decide_fallback_link_setting(
2464                 struct dc_link_settings initial_link_settings,
2465                 struct dc_link_settings *current_link_setting,
2466                 enum link_training_result training_result)
2467 {
2468         if (!current_link_setting)
2469                 return false;
2470
2471         switch (training_result) {
2472         case LINK_TRAINING_CR_FAIL_LANE0:
2473         case LINK_TRAINING_CR_FAIL_LANE1:
2474         case LINK_TRAINING_CR_FAIL_LANE23:
2475         case LINK_TRAINING_LQA_FAIL:
2476         {
2477                 if (!reached_minimum_link_rate
2478                                 (current_link_setting->link_rate)) {
2479                         current_link_setting->link_rate =
2480                                 reduce_link_rate(
2481                                         current_link_setting->link_rate);
2482                 } else if (!reached_minimum_lane_count
2483                                 (current_link_setting->lane_count)) {
2484                         current_link_setting->link_rate =
2485                                 initial_link_settings.link_rate;
2486                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2487                                 return false;
2488                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2489                                 current_link_setting->lane_count =
2490                                                 LANE_COUNT_ONE;
2491                         else if (training_result ==
2492                                         LINK_TRAINING_CR_FAIL_LANE23)
2493                                 current_link_setting->lane_count =
2494                                                 LANE_COUNT_TWO;
2495                         else
2496                                 current_link_setting->lane_count =
2497                                         reduce_lane_count(
2498                                         current_link_setting->lane_count);
2499                 } else {
2500                         return false;
2501                 }
2502                 break;
2503         }
2504         case LINK_TRAINING_EQ_FAIL_EQ:
2505         {
2506                 if (!reached_minimum_lane_count
2507                                 (current_link_setting->lane_count)) {
2508                         current_link_setting->lane_count =
2509                                 reduce_lane_count(
2510                                         current_link_setting->lane_count);
2511                 } else if (!reached_minimum_link_rate
2512                                 (current_link_setting->link_rate)) {
2513                         current_link_setting->link_rate =
2514                                 reduce_link_rate(
2515                                         current_link_setting->link_rate);
2516                 } else {
2517                         return false;
2518                 }
2519                 break;
2520         }
2521         case LINK_TRAINING_EQ_FAIL_CR:
2522         {
2523                 if (!reached_minimum_link_rate
2524                                 (current_link_setting->link_rate)) {
2525                         current_link_setting->link_rate =
2526                                 reduce_link_rate(
2527                                         current_link_setting->link_rate);
2528                 } else {
2529                         return false;
2530                 }
2531                 break;
2532         }
2533         default:
2534                 return false;
2535         }
2536         return true;
2537 }
2538
2539 bool dp_validate_mode_timing(
2540         struct dc_link *link,
2541         const struct dc_crtc_timing *timing)
2542 {
2543         uint32_t req_bw;
2544         uint32_t max_bw;
2545
2546         const struct dc_link_settings *link_setting;
2547
2548         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2549         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2550                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2551                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2552                 return false;
2553
2554         /*always DP fail safe mode*/
2555         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2556                 timing->h_addressable == (uint32_t) 640 &&
2557                 timing->v_addressable == (uint32_t) 480)
2558                 return true;
2559
2560         link_setting = dc_link_get_link_cap(link);
2561
2562         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2563         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2564                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2565                 link_setting = &link->verified_link_cap;
2566         */
2567
2568         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2569         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2570
2571         if (req_bw <= max_bw) {
2572                 /* remember the biggest mode here, during
2573                  * initial link training (to get
2574                  * verified_link_cap), LS sends event about
2575                  * cannot train at reported cap to upper
2576                  * layer and upper layer will re-enumerate modes.
2577                  * this is not necessary if the lower
2578                  * verified_link_cap is enough to drive
2579                  * all the modes */
2580
2581                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2582                 /* if (flags.DYNAMIC_VALIDATION == 1)
2583                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2584                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2585                 return true;
2586         } else
2587                 return false;
2588 }
2589
2590 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2591 {
2592         struct dc_link_settings initial_link_setting = {
2593                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2594         struct dc_link_settings current_link_setting =
2595                         initial_link_setting;
2596         uint32_t link_bw;
2597
2598         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2599                 return false;
2600
2601         /* search for the minimum link setting that:
2602          * 1. is supported according to the link training result
2603          * 2. could support the b/w requested by the timing
2604          */
2605         while (current_link_setting.link_rate <=
2606                         link->verified_link_cap.link_rate) {
2607                 link_bw = dc_link_bandwidth_kbps(
2608                                 link,
2609                                 &current_link_setting);
2610                 if (req_bw <= link_bw) {
2611                         *link_setting = current_link_setting;
2612                         return true;
2613                 }
2614
2615                 if (current_link_setting.lane_count <
2616                                 link->verified_link_cap.lane_count) {
2617                         current_link_setting.lane_count =
2618                                         increase_lane_count(
2619                                                         current_link_setting.lane_count);
2620                 } else {
2621                         current_link_setting.link_rate =
2622                                         increase_link_rate(
2623                                                         current_link_setting.link_rate);
2624                         current_link_setting.lane_count =
2625                                         initial_link_setting.lane_count;
2626                 }
2627         }
2628
2629         return false;
2630 }
2631
2632 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2633 {
2634         struct dc_link_settings initial_link_setting;
2635         struct dc_link_settings current_link_setting;
2636         uint32_t link_bw;
2637
2638         /*
2639          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2640          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2641          */
2642         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2643                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2644                 *link_setting = link->verified_link_cap;
2645                 return true;
2646         }
2647
2648         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2649         initial_link_setting.lane_count = LANE_COUNT_ONE;
2650         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2651         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2652         initial_link_setting.use_link_rate_set = true;
2653         initial_link_setting.link_rate_set = 0;
2654         current_link_setting = initial_link_setting;
2655
2656         /* search for the minimum link setting that:
2657          * 1. is supported according to the link training result
2658          * 2. could support the b/w requested by the timing
2659          */
2660         while (current_link_setting.link_rate <=
2661                         link->verified_link_cap.link_rate) {
2662                 link_bw = dc_link_bandwidth_kbps(
2663                                 link,
2664                                 &current_link_setting);
2665                 if (req_bw <= link_bw) {
2666                         *link_setting = current_link_setting;
2667                         return true;
2668                 }
2669
2670                 if (current_link_setting.lane_count <
2671                                 link->verified_link_cap.lane_count) {
2672                         current_link_setting.lane_count =
2673                                         increase_lane_count(
2674                                                         current_link_setting.lane_count);
2675                 } else {
2676                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2677                                 current_link_setting.link_rate_set++;
2678                                 current_link_setting.link_rate =
2679                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2680                                 current_link_setting.lane_count =
2681                                                                         initial_link_setting.lane_count;
2682                         } else
2683                                 break;
2684                 }
2685         }
2686         return false;
2687 }
2688
2689 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2690 {
2691         *link_setting = link->verified_link_cap;
2692         return true;
2693 }
2694
2695 void decide_link_settings(struct dc_stream_state *stream,
2696         struct dc_link_settings *link_setting)
2697 {
2698         struct dc_link *link;
2699         uint32_t req_bw;
2700
2701         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2702
2703         link = stream->link;
2704
2705         /* if preferred is specified through AMDDP, use it, if it's enough
2706          * to drive the mode
2707          */
2708         if (link->preferred_link_setting.lane_count !=
2709                         LANE_COUNT_UNKNOWN &&
2710                         link->preferred_link_setting.link_rate !=
2711                                         LINK_RATE_UNKNOWN) {
2712                 *link_setting =  link->preferred_link_setting;
2713                 return;
2714         }
2715
2716         /* MST doesn't perform link training for now
2717          * TODO: add MST specific link training routine
2718          */
2719         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2720                 if (decide_mst_link_settings(link, link_setting))
2721                         return;
2722         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2723                 if (decide_edp_link_settings(link, link_setting, req_bw))
2724                         return;
2725         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2726                 return;
2727
2728         BREAK_TO_DEBUGGER();
2729         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2730
2731         *link_setting = link->verified_link_cap;
2732 }
2733
2734 /*************************Short Pulse IRQ***************************/
2735 static bool allow_hpd_rx_irq(const struct dc_link *link)
2736 {
2737         /*
2738          * Don't handle RX IRQ unless one of following is met:
2739          * 1) The link is established (cur_link_settings != unknown)
2740          * 2) We know we're dealing with a branch device, SST or MST
2741          */
2742
2743         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2744                 is_dp_branch_device(link))
2745                 return true;
2746
2747         return false;
2748 }
2749
2750 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2751 {
2752         union dpcd_psr_configuration psr_configuration;
2753
2754         if (!link->psr_settings.psr_feature_enabled)
2755                 return false;
2756
2757         dm_helpers_dp_read_dpcd(
2758                 link->ctx,
2759                 link,
2760                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2761                 &psr_configuration.raw,
2762                 sizeof(psr_configuration.raw));
2763
2764
2765         if (psr_configuration.bits.ENABLE) {
2766                 unsigned char dpcdbuf[3] = {0};
2767                 union psr_error_status psr_error_status;
2768                 union psr_sink_psr_status psr_sink_psr_status;
2769
2770                 dm_helpers_dp_read_dpcd(
2771                         link->ctx,
2772                         link,
2773                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2774                         (unsigned char *) dpcdbuf,
2775                         sizeof(dpcdbuf));
2776
2777                 /*DPCD 2006h   ERROR STATUS*/
2778                 psr_error_status.raw = dpcdbuf[0];
2779                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2780                 psr_sink_psr_status.raw = dpcdbuf[2];
2781
2782                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2783                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2784                                 psr_error_status.bits.VSC_SDP_ERROR) {
2785                         /* Acknowledge and clear error bits */
2786                         dm_helpers_dp_write_dpcd(
2787                                 link->ctx,
2788                                 link,
2789                                 8198,/*DpcdAddress_PSR_Error_Status*/
2790                                 &psr_error_status.raw,
2791                                 sizeof(psr_error_status.raw));
2792
2793                         /* PSR error, disable and re-enable PSR */
2794                         dc_link_set_psr_allow_active(link, false, true, false);
2795                         dc_link_set_psr_allow_active(link, true, true, false);
2796
2797                         return true;
2798                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2799                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2800                         /* No error is detect, PSR is active.
2801                          * We should return with IRQ_HPD handled without
2802                          * checking for loss of sync since PSR would have
2803                          * powered down main link.
2804                          */
2805                         return true;
2806                 }
2807         }
2808         return false;
2809 }
2810
2811 static void dp_test_send_link_training(struct dc_link *link)
2812 {
2813         struct dc_link_settings link_settings = {0};
2814
2815         core_link_read_dpcd(
2816                         link,
2817                         DP_TEST_LANE_COUNT,
2818                         (unsigned char *)(&link_settings.lane_count),
2819                         1);
2820         core_link_read_dpcd(
2821                         link,
2822                         DP_TEST_LINK_RATE,
2823                         (unsigned char *)(&link_settings.link_rate),
2824                         1);
2825
2826         /* Set preferred link settings */
2827         link->verified_link_cap.lane_count = link_settings.lane_count;
2828         link->verified_link_cap.link_rate = link_settings.link_rate;
2829
2830         dp_retrain_link_dp_test(link, &link_settings, false);
2831 }
2832
2833 /* TODO Raven hbr2 compliance eye output is unstable
2834  * (toggling on and off) with debugger break
2835  * This caueses intermittent PHY automation failure
2836  * Need to look into the root cause */
2837 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2838 {
2839         union phy_test_pattern dpcd_test_pattern;
2840         union lane_adjust dpcd_lane_adjustment[2];
2841         unsigned char dpcd_post_cursor_2_adjustment = 0;
2842         unsigned char test_pattern_buffer[
2843                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2844                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2845         unsigned int test_pattern_size = 0;
2846         enum dp_test_pattern test_pattern;
2847         struct dc_link_training_settings link_settings;
2848         union lane_adjust dpcd_lane_adjust;
2849         unsigned int lane;
2850         struct link_training_settings link_training_settings;
2851         int i = 0;
2852
2853         dpcd_test_pattern.raw = 0;
2854         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2855         memset(&link_settings, 0, sizeof(link_settings));
2856
2857         /* get phy test pattern and pattern parameters from DP receiver */
2858         core_link_read_dpcd(
2859                         link,
2860                         DP_PHY_TEST_PATTERN,
2861                         &dpcd_test_pattern.raw,
2862                         sizeof(dpcd_test_pattern));
2863         core_link_read_dpcd(
2864                         link,
2865                         DP_ADJUST_REQUEST_LANE0_1,
2866                         &dpcd_lane_adjustment[0].raw,
2867                         sizeof(dpcd_lane_adjustment));
2868
2869         /*get post cursor 2 parameters
2870          * For DP 1.1a or eariler, this DPCD register's value is 0
2871          * For DP 1.2 or later:
2872          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2873          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2874          */
2875         core_link_read_dpcd(
2876                         link,
2877                         DP_ADJUST_REQUEST_POST_CURSOR2,
2878                         &dpcd_post_cursor_2_adjustment,
2879                         sizeof(dpcd_post_cursor_2_adjustment));
2880
2881         /* translate request */
2882         switch (dpcd_test_pattern.bits.PATTERN) {
2883         case PHY_TEST_PATTERN_D10_2:
2884                 test_pattern = DP_TEST_PATTERN_D102;
2885                 break;
2886         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2887                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2888                 break;
2889         case PHY_TEST_PATTERN_PRBS7:
2890                 test_pattern = DP_TEST_PATTERN_PRBS7;
2891                 break;
2892         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2893                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2894                 break;
2895         case PHY_TEST_PATTERN_CP2520_1:
2896                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2897                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2898                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2899                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2900                 break;
2901         case PHY_TEST_PATTERN_CP2520_2:
2902                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2903                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2904                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2905                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2906                 break;
2907         case PHY_TEST_PATTERN_CP2520_3:
2908                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2909                 break;
2910         default:
2911                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2912         break;
2913         }
2914
2915         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2916                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2917                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2918                 core_link_read_dpcd(
2919                                 link,
2920                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2921                                 test_pattern_buffer,
2922                                 test_pattern_size);
2923         }
2924
2925         /* prepare link training settings */
2926         link_settings.link = link->cur_link_settings;
2927
2928         for (lane = 0; lane <
2929                 (unsigned int)(link->cur_link_settings.lane_count);
2930                 lane++) {
2931                 dpcd_lane_adjust.raw =
2932                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2933                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2934                         (enum dc_voltage_swing)
2935                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2936                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2937                         (enum dc_pre_emphasis)
2938                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2939                 link_settings.lane_settings[lane].POST_CURSOR2 =
2940                         (enum dc_post_cursor2)
2941                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2942         }
2943
2944         for (i = 0; i < 4; i++)
2945                 link_training_settings.lane_settings[i] =
2946                                 link_settings.lane_settings[i];
2947         link_training_settings.link_settings = link_settings.link;
2948         link_training_settings.allow_invalid_msa_timing_param = false;
2949         /*Usage: Measure DP physical lane signal
2950          * by DP SI test equipment automatically.
2951          * PHY test pattern request is generated by equipment via HPD interrupt.
2952          * HPD needs to be active all the time. HPD should be active
2953          * all the time. Do not touch it.
2954          * forward request to DS
2955          */
2956         dc_link_dp_set_test_pattern(
2957                 link,
2958                 test_pattern,
2959                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2960                 &link_training_settings,
2961                 test_pattern_buffer,
2962                 test_pattern_size);
2963 }
2964
2965 static void dp_test_send_link_test_pattern(struct dc_link *link)
2966 {
2967         union link_test_pattern dpcd_test_pattern;
2968         union test_misc dpcd_test_params;
2969         enum dp_test_pattern test_pattern;
2970         enum dp_test_pattern_color_space test_pattern_color_space =
2971                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2972         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2973         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2974         struct pipe_ctx *pipe_ctx = NULL;
2975         int i;
2976
2977         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2978         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2979
2980         for (i = 0; i < MAX_PIPES; i++) {
2981                 if (pipes[i].stream == NULL)
2982                         continue;
2983
2984                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2985                         pipe_ctx = &pipes[i];
2986                         break;
2987                 }
2988         }
2989
2990         if (pipe_ctx == NULL)
2991                 return;
2992
2993         /* get link test pattern and pattern parameters */
2994         core_link_read_dpcd(
2995                         link,
2996                         DP_TEST_PATTERN,
2997                         &dpcd_test_pattern.raw,
2998                         sizeof(dpcd_test_pattern));
2999         core_link_read_dpcd(
3000                         link,
3001                         DP_TEST_MISC0,
3002                         &dpcd_test_params.raw,
3003                         sizeof(dpcd_test_params));
3004
3005         switch (dpcd_test_pattern.bits.PATTERN) {
3006         case LINK_TEST_PATTERN_COLOR_RAMP:
3007                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3008         break;
3009         case LINK_TEST_PATTERN_VERTICAL_BARS:
3010                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3011         break; /* black and white */
3012         case LINK_TEST_PATTERN_COLOR_SQUARES:
3013                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3014                                 TEST_DYN_RANGE_VESA ?
3015                                 DP_TEST_PATTERN_COLOR_SQUARES :
3016                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3017         break;
3018         default:
3019                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3020         break;
3021         }
3022
3023         if (dpcd_test_params.bits.CLR_FORMAT == 0)
3024                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3025         else
3026                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3027                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3028                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
3029
3030         switch (dpcd_test_params.bits.BPC) {
3031         case 0: // 6 bits
3032                 requestColorDepth = COLOR_DEPTH_666;
3033                 break;
3034         case 1: // 8 bits
3035                 requestColorDepth = COLOR_DEPTH_888;
3036                 break;
3037         case 2: // 10 bits
3038                 requestColorDepth = COLOR_DEPTH_101010;
3039                 break;
3040         case 3: // 12 bits
3041                 requestColorDepth = COLOR_DEPTH_121212;
3042                 break;
3043         default:
3044                 break;
3045         }
3046
3047         switch (dpcd_test_params.bits.CLR_FORMAT) {
3048         case 0:
3049                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3050                 break;
3051         case 1:
3052                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3053                 break;
3054         case 2:
3055                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3056                 break;
3057         default:
3058                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3059                 break;
3060         }
3061
3062
3063         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3064                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3065                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3066                                 __func__,
3067                                 pipe_ctx->stream->timing.display_color_depth,
3068                                 requestColorDepth);
3069                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3070         }
3071
3072         dp_update_dsc_config(pipe_ctx);
3073
3074         dc_link_dp_set_test_pattern(
3075                         link,
3076                         test_pattern,
3077                         test_pattern_color_space,
3078                         NULL,
3079                         NULL,
3080                         0);
3081 }
3082
3083 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3084 {
3085         union audio_test_mode            dpcd_test_mode = {0};
3086         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3087         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3088         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3089
3090         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3091         struct pipe_ctx *pipe_ctx = &pipes[0];
3092         unsigned int channel_count;
3093         unsigned int channel = 0;
3094         unsigned int modes = 0;
3095         unsigned int sampling_rate_in_hz = 0;
3096
3097         // get audio test mode and test pattern parameters
3098         core_link_read_dpcd(
3099                 link,
3100                 DP_TEST_AUDIO_MODE,
3101                 &dpcd_test_mode.raw,
3102                 sizeof(dpcd_test_mode));
3103
3104         core_link_read_dpcd(
3105                 link,
3106                 DP_TEST_AUDIO_PATTERN_TYPE,
3107                 &dpcd_pattern_type.value,
3108                 sizeof(dpcd_pattern_type));
3109
3110         channel_count = dpcd_test_mode.bits.channel_count + 1;
3111
3112         // read pattern periods for requested channels when sawTooth pattern is requested
3113         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3114                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3115
3116                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3117                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3118                 // read period for each channel
3119                 for (channel = 0; channel < channel_count; channel++) {
3120                         core_link_read_dpcd(
3121                                                         link,
3122                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3123                                                         &dpcd_pattern_period[channel].raw,
3124                                                         sizeof(dpcd_pattern_period[channel]));
3125                 }
3126         }
3127
3128         // translate sampling rate
3129         switch (dpcd_test_mode.bits.sampling_rate) {
3130         case AUDIO_SAMPLING_RATE_32KHZ:
3131                 sampling_rate_in_hz = 32000;
3132                 break;
3133         case AUDIO_SAMPLING_RATE_44_1KHZ:
3134                 sampling_rate_in_hz = 44100;
3135                 break;
3136         case AUDIO_SAMPLING_RATE_48KHZ:
3137                 sampling_rate_in_hz = 48000;
3138                 break;
3139         case AUDIO_SAMPLING_RATE_88_2KHZ:
3140                 sampling_rate_in_hz = 88200;
3141                 break;
3142         case AUDIO_SAMPLING_RATE_96KHZ:
3143                 sampling_rate_in_hz = 96000;
3144                 break;
3145         case AUDIO_SAMPLING_RATE_176_4KHZ:
3146                 sampling_rate_in_hz = 176400;
3147                 break;
3148         case AUDIO_SAMPLING_RATE_192KHZ:
3149                 sampling_rate_in_hz = 192000;
3150                 break;
3151         default:
3152                 sampling_rate_in_hz = 0;
3153                 break;
3154         }
3155
3156         link->audio_test_data.flags.test_requested = 1;
3157         link->audio_test_data.flags.disable_video = disable_video;
3158         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3159         link->audio_test_data.channel_count = channel_count;
3160         link->audio_test_data.pattern_type = test_pattern;
3161
3162         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3163                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3164                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3165                 }
3166         }
3167 }
3168
3169 static void handle_automated_test(struct dc_link *link)
3170 {
3171         union test_request test_request;
3172         union test_response test_response;
3173
3174         memset(&test_request, 0, sizeof(test_request));
3175         memset(&test_response, 0, sizeof(test_response));
3176
3177         core_link_read_dpcd(
3178                 link,
3179                 DP_TEST_REQUEST,
3180                 &test_request.raw,
3181                 sizeof(union test_request));
3182         if (test_request.bits.LINK_TRAINING) {
3183                 /* ACK first to let DP RX test box monitor LT sequence */
3184                 test_response.bits.ACK = 1;
3185                 core_link_write_dpcd(
3186                         link,
3187                         DP_TEST_RESPONSE,
3188                         &test_response.raw,
3189                         sizeof(test_response));
3190                 dp_test_send_link_training(link);
3191                 /* no acknowledge request is needed again */
3192                 test_response.bits.ACK = 0;
3193         }
3194         if (test_request.bits.LINK_TEST_PATTRN) {
3195                 dp_test_send_link_test_pattern(link);
3196                 test_response.bits.ACK = 1;
3197         }
3198
3199         if (test_request.bits.AUDIO_TEST_PATTERN) {
3200                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3201                 test_response.bits.ACK = 1;
3202         }
3203
3204         if (test_request.bits.PHY_TEST_PATTERN) {
3205                 dp_test_send_phy_test_pattern(link);
3206                 test_response.bits.ACK = 1;
3207         }
3208
3209         /* send request acknowledgment */
3210         if (test_response.bits.ACK)
3211                 core_link_write_dpcd(
3212                         link,
3213                         DP_TEST_RESPONSE,
3214                         &test_response.raw,
3215                         sizeof(test_response));
3216 }
3217
3218 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3219 {
3220         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3221         union device_service_irq device_service_clear = { { 0 } };
3222         enum dc_status result;
3223         bool status = false;
3224         struct pipe_ctx *pipe_ctx;
3225         int i;
3226
3227         if (out_link_loss)
3228                 *out_link_loss = false;
3229         /* For use cases related to down stream connection status change,
3230          * PSR and device auto test, refer to function handle_sst_hpd_irq
3231          * in DAL2.1*/
3232
3233         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3234                 __func__, link->link_index);
3235
3236
3237          /* All the "handle_hpd_irq_xxx()" methods
3238                  * should be called only after
3239                  * dal_dpsst_ls_read_hpd_irq_data
3240                  * Order of calls is important too
3241                  */
3242         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3243         if (out_hpd_irq_dpcd_data)
3244                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3245
3246         if (result != DC_OK) {
3247                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3248                         __func__);
3249                 return false;
3250         }
3251
3252         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3253                 device_service_clear.bits.AUTOMATED_TEST = 1;
3254                 core_link_write_dpcd(
3255                         link,
3256                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3257                         &device_service_clear.raw,
3258                         sizeof(device_service_clear.raw));
3259                 device_service_clear.raw = 0;
3260                 handle_automated_test(link);
3261                 return false;
3262         }
3263
3264         if (!allow_hpd_rx_irq(link)) {
3265                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3266                         __func__, link->link_index);
3267                 return false;
3268         }
3269
3270         if (handle_hpd_irq_psr_sink(link))
3271                 /* PSR-related error was detected and handled */
3272                 return true;
3273
3274         /* If PSR-related error handled, Main link may be off,
3275          * so do not handle as a normal sink status change interrupt.
3276          */
3277
3278         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3279                 return true;
3280
3281         /* check if we have MST msg and return since we poll for it */
3282         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3283                 return false;
3284
3285         /* For now we only handle 'Downstream port status' case.
3286          * If we got sink count changed it means
3287          * Downstream port status changed,
3288          * then DM should call DC to do the detection.
3289          * NOTE: Do not handle link loss on eDP since it is internal link*/
3290         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3291                 hpd_rx_irq_check_link_loss_status(
3292                         link,
3293                         &hpd_irq_dpcd_data)) {
3294                 /* Connectivity log: link loss */
3295                 CONN_DATA_LINK_LOSS(link,
3296                                         hpd_irq_dpcd_data.raw,
3297                                         sizeof(hpd_irq_dpcd_data),
3298                                         "Status: ");
3299
3300                 for (i = 0; i < MAX_PIPES; i++) {
3301                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3302                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3303                                 break;
3304                 }
3305
3306                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3307                         return false;
3308
3309
3310                 for (i = 0; i < MAX_PIPES; i++) {
3311                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3312                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3313                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3314                                 core_link_disable_stream(pipe_ctx);
3315                 }
3316
3317                 for (i = 0; i < MAX_PIPES; i++) {
3318                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3319                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3320                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3321                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3322                 }
3323
3324                 status = false;
3325                 if (out_link_loss)
3326                         *out_link_loss = true;
3327         }
3328
3329         if (link->type == dc_connection_sst_branch &&
3330                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3331                         != link->dpcd_sink_count)
3332                 status = true;
3333
3334         /* reasons for HPD RX:
3335          * 1. Link Loss - ie Re-train the Link
3336          * 2. MST sideband message
3337          * 3. Automated Test - ie. Internal Commit
3338          * 4. CP (copy protection) - (not interesting for DM???)
3339          * 5. DRR
3340          * 6. Downstream Port status changed
3341          * -ie. Detect - this the only one
3342          * which is interesting for DM because
3343          * it must call dc_link_detect.
3344          */
3345         return status;
3346 }
3347
3348 /*query dpcd for version and mst cap addresses*/
3349 bool is_mst_supported(struct dc_link *link)
3350 {
3351         bool mst          = false;
3352         enum dc_status st = DC_OK;
3353         union dpcd_rev rev;
3354         union mstm_cap cap;
3355
3356         if (link->preferred_training_settings.mst_enable &&
3357                 *link->preferred_training_settings.mst_enable == false) {
3358                 return false;
3359         }
3360
3361         rev.raw  = 0;
3362         cap.raw  = 0;
3363
3364         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3365                         sizeof(rev));
3366
3367         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3368
3369                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3370                                 &cap.raw, sizeof(cap));
3371                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3372                         mst = true;
3373         }
3374         return mst;
3375
3376 }
3377
3378 bool is_dp_active_dongle(const struct dc_link *link)
3379 {
3380         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3381                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3382 }
3383
3384 bool is_dp_branch_device(const struct dc_link *link)
3385 {
3386         return link->dpcd_caps.is_branch_dev;
3387 }
3388
3389 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3390 {
3391         switch (bpc) {
3392         case DOWN_STREAM_MAX_8BPC:
3393                 return 8;
3394         case DOWN_STREAM_MAX_10BPC:
3395                 return 10;
3396         case DOWN_STREAM_MAX_12BPC:
3397                 return 12;
3398         case DOWN_STREAM_MAX_16BPC:
3399                 return 16;
3400         default:
3401                 break;
3402         }
3403
3404         return -1;
3405 }
3406
3407 static void read_dp_device_vendor_id(struct dc_link *link)
3408 {
3409         struct dp_device_vendor_id dp_id;
3410
3411         /* read IEEE branch device id */
3412         core_link_read_dpcd(
3413                 link,
3414                 DP_BRANCH_OUI,
3415                 (uint8_t *)&dp_id,
3416                 sizeof(dp_id));
3417
3418         link->dpcd_caps.branch_dev_id =
3419                 (dp_id.ieee_oui[0] << 16) +
3420                 (dp_id.ieee_oui[1] << 8) +
3421                 dp_id.ieee_oui[2];
3422
3423         memmove(
3424                 link->dpcd_caps.branch_dev_name,
3425                 dp_id.ieee_device_id,
3426                 sizeof(dp_id.ieee_device_id));
3427 }
3428
3429
3430
3431 static void get_active_converter_info(
3432         uint8_t data, struct dc_link *link)
3433 {
3434         union dp_downstream_port_present ds_port = { .byte = data };
3435         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3436
3437         /* decode converter info*/
3438         if (!ds_port.fields.PORT_PRESENT) {
3439                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3440                 ddc_service_set_dongle_type(link->ddc,
3441                                 link->dpcd_caps.dongle_type);
3442                 link->dpcd_caps.is_branch_dev = false;
3443                 return;
3444         }
3445
3446         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3447         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3448
3449         switch (ds_port.fields.PORT_TYPE) {
3450         case DOWNSTREAM_VGA:
3451                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3452                 break;
3453         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3454                 /* At this point we don't know is it DVI or HDMI or DP++,
3455                  * assume DVI.*/
3456                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3457                 break;
3458         default:
3459                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3460                 break;
3461         }
3462
3463         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3464                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3465                 union dwnstream_port_caps_byte0 *port_caps =
3466                         (union dwnstream_port_caps_byte0 *)det_caps;
3467                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3468                                 det_caps, sizeof(det_caps)) == DC_OK) {
3469
3470                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3471                         /*Handle DP case as DONGLE_NONE*/
3472                         case DOWN_STREAM_DETAILED_DP:
3473                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3474                                 break;
3475                         case DOWN_STREAM_DETAILED_VGA:
3476                                 link->dpcd_caps.dongle_type =
3477                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3478                                 break;
3479                         case DOWN_STREAM_DETAILED_DVI:
3480                                 link->dpcd_caps.dongle_type =
3481                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3482                                 break;
3483                         case DOWN_STREAM_DETAILED_HDMI:
3484                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3485                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3486                                 link->dpcd_caps.dongle_type =
3487                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3488
3489                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3490                                 if (ds_port.fields.DETAILED_CAPS) {
3491
3492                                         union dwnstream_port_caps_byte3_hdmi
3493                                                 hdmi_caps = {.raw = det_caps[3] };
3494                                         union dwnstream_port_caps_byte2
3495                                                 hdmi_color_caps = {.raw = det_caps[2] };
3496                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3497                                                 det_caps[1] * 2500;
3498
3499                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3500                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3501                                         /*YCBCR capability only for HDMI case*/
3502                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3503                                                         == DOWN_STREAM_DETAILED_HDMI) {
3504                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3505                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3506                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3507                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3508                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3509                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3510                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3511                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3512                                         }
3513
3514                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3515                                                 translate_dpcd_max_bpc(
3516                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3517
3518                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3519                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3520                                 }
3521
3522                                 break;
3523                         }
3524                 }
3525         }
3526
3527         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3528
3529         {
3530                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3531
3532                 core_link_read_dpcd(
3533                         link,
3534                         DP_BRANCH_REVISION_START,
3535                         (uint8_t *)&dp_hw_fw_revision,
3536                         sizeof(dp_hw_fw_revision));
3537
3538                 link->dpcd_caps.branch_hw_revision =
3539                         dp_hw_fw_revision.ieee_hw_rev;
3540
3541                 memmove(
3542                         link->dpcd_caps.branch_fw_revision,
3543                         dp_hw_fw_revision.ieee_fw_rev,
3544                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3545         }
3546 }
3547
3548 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3549                 int length)
3550 {
3551         int retry = 0;
3552
3553         if (!link->dpcd_caps.dpcd_rev.raw) {
3554                 do {
3555                         dp_receiver_power_ctrl(link, true);
3556                         core_link_read_dpcd(link, DP_DPCD_REV,
3557                                                         dpcd_data, length);
3558                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3559                                 DP_DPCD_REV -
3560                                 DP_DPCD_REV];
3561                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3562         }
3563
3564         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3565                 switch (link->dpcd_caps.branch_dev_id) {
3566                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3567                  * all internal circuits including AUX communication preventing
3568                  * reading DPCD table and EDID (spec violation).
3569                  * Encoder will skip DP RX power down on disable_output to
3570                  * keep receiver powered all the time.*/
3571                 case DP_BRANCH_DEVICE_ID_0010FA:
3572                 case DP_BRANCH_DEVICE_ID_0080E1:
3573                 case DP_BRANCH_DEVICE_ID_00E04C:
3574                         link->wa_flags.dp_keep_receiver_powered = true;
3575                         break;
3576
3577                 /* TODO: May need work around for other dongles. */
3578                 default:
3579                         link->wa_flags.dp_keep_receiver_powered = false;
3580                         break;
3581                 }
3582         } else
3583                 link->wa_flags.dp_keep_receiver_powered = false;
3584 }
3585
3586 /* Read additional sink caps defined in source specific DPCD area
3587  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3588  */
3589 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3590 {
3591         uint8_t dpcd_data;
3592
3593         if (!link)
3594                 return false;
3595
3596         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3597                 return false;
3598
3599         link->dpcd_sink_ext_caps.raw = dpcd_data;
3600         return true;
3601 }
3602
3603 bool dp_retrieve_lttpr_cap(struct dc_link *link)
3604 {
3605         uint8_t lttpr_dpcd_data[6];
3606         bool vbios_lttpr_enable = false;
3607         bool vbios_lttpr_interop = false;
3608         struct dc_bios *bios = link->dc->ctx->dc_bios;
3609         enum dc_status status = DC_ERROR_UNEXPECTED;
3610         bool is_lttpr_present = false;
3611
3612         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3613         /* Query BIOS to determine if LTTPR functionality is forced on by system */
3614         if (bios->funcs->get_lttpr_caps) {
3615                 enum bp_result bp_query_result;
3616                 uint8_t is_vbios_lttpr_enable = 0;
3617
3618                 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3619                 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3620         }
3621
3622         if (bios->funcs->get_lttpr_interop) {
3623                 enum bp_result bp_query_result;
3624                 uint8_t is_vbios_interop_enabled = 0;
3625
3626                 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3627                 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3628         }
3629
3630         /*
3631          * Logic to determine LTTPR mode
3632          */
3633         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3634         if (vbios_lttpr_enable && vbios_lttpr_interop)
3635                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3636         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3637                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3638                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3639                 else
3640                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3641         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3642                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3643                         || !link->dc->caps.extended_aux_timeout_support)
3644                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3645                 else
3646                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3647         }
3648
3649         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3650                 /* By reading LTTPR capability, RX assumes that we will enable
3651                  * LTTPR extended aux timeout if LTTPR is present.
3652                  */
3653                 status = core_link_read_dpcd(
3654                                 link,
3655                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3656                                 lttpr_dpcd_data,
3657                                 sizeof(lttpr_dpcd_data));
3658                 if (status != DC_OK) {
3659                         dm_error("%s: Read LTTPR caps data failed.\n", __func__);
3660                         return false;
3661                 }
3662
3663                 link->dpcd_caps.lttpr_caps.revision.raw =
3664                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3665                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3666
3667                 link->dpcd_caps.lttpr_caps.max_link_rate =
3668                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3669                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3670
3671                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3672                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3673                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3674
3675                 link->dpcd_caps.lttpr_caps.max_lane_count =
3676                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3677                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3678
3679                 link->dpcd_caps.lttpr_caps.mode =
3680                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3681                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3682
3683                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3684                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3685                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3686
3687                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3688                 is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
3689                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3690                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3691                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3692                 if (is_lttpr_present) {
3693                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3694                         configure_lttpr_mode_transparent(link);
3695                 } else
3696                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3697         }
3698         return is_lttpr_present;
3699 }
3700
3701 static bool retrieve_link_cap(struct dc_link *link)
3702 {
3703         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3704          * which means size 16 will be good for both of those DPCD register block reads
3705          */
3706         uint8_t dpcd_data[16];
3707         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3708          */
3709         uint8_t dpcd_dprx_data = '\0';
3710         uint8_t dpcd_power_state = '\0';
3711
3712         struct dp_device_vendor_id sink_id;
3713         union down_stream_port_count down_strm_port_count;
3714         union edp_configuration_cap edp_config_cap;
3715         union dp_downstream_port_present ds_port = { 0 };
3716         enum dc_status status = DC_ERROR_UNEXPECTED;
3717         uint32_t read_dpcd_retry_cnt = 3;
3718         int i;
3719         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3720         const uint32_t post_oui_delay = 30; // 30ms
3721         bool is_lttpr_present = false;
3722
3723         memset(dpcd_data, '\0', sizeof(dpcd_data));
3724         memset(&down_strm_port_count,
3725                 '\0', sizeof(union down_stream_port_count));
3726         memset(&edp_config_cap, '\0',
3727                 sizeof(union edp_configuration_cap));
3728
3729         /* if extended timeout is supported in hardware,
3730          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3731          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3732          */
3733         dc_link_aux_try_to_configure_timeout(link->ddc,
3734                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3735
3736         is_lttpr_present = dp_retrieve_lttpr_cap(link);
3737
3738         status = core_link_read_dpcd(link, DP_SET_POWER,
3739                         &dpcd_power_state, sizeof(dpcd_power_state));
3740
3741         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3742          * section 2.3.1.2, if AUX CH may be powered down due to
3743          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3744          * signal and may need up to 1 ms before being able to reply.
3745          */
3746         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3747                 udelay(1000);
3748
3749         dpcd_set_source_specific_data(link);
3750         /* Sink may need to configure internals based on vendor, so allow some
3751          * time before proceeding with possibly vendor specific transactions
3752          */
3753         msleep(post_oui_delay);
3754
3755         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3756                 status = core_link_read_dpcd(
3757                                 link,
3758                                 DP_DPCD_REV,
3759                                 dpcd_data,
3760                                 sizeof(dpcd_data));
3761                 if (status == DC_OK)
3762                         break;
3763         }
3764
3765         if (status != DC_OK) {
3766                 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3767                 return false;
3768         }
3769
3770         if (!is_lttpr_present)
3771                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3772
3773         {
3774                 union training_aux_rd_interval aux_rd_interval;
3775
3776                 aux_rd_interval.raw =
3777                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3778
3779                 link->dpcd_caps.ext_receiver_cap_field_present =
3780                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3781
3782                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3783                         uint8_t ext_cap_data[16];
3784
3785                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3786                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3787                                 status = core_link_read_dpcd(
3788                                 link,
3789                                 DP_DP13_DPCD_REV,
3790                                 ext_cap_data,
3791                                 sizeof(ext_cap_data));
3792                                 if (status == DC_OK) {
3793                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3794                                         break;
3795                                 }
3796                         }
3797                         if (status != DC_OK)
3798                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3799                 }
3800         }
3801
3802         link->dpcd_caps.dpcd_rev.raw =
3803                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3804
3805         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3806                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3807                         status = core_link_read_dpcd(
3808                                         link,
3809                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3810                                         &dpcd_dprx_data,
3811                                         sizeof(dpcd_dprx_data));
3812                         if (status == DC_OK)
3813                                 break;
3814                 }
3815
3816                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3817
3818                 if (status != DC_OK)
3819                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3820         }
3821
3822         else {
3823                 link->dpcd_caps.dprx_feature.raw = 0;
3824         }
3825
3826
3827         /* Error condition checking...
3828          * It is impossible for Sink to report Max Lane Count = 0.
3829          * It is possible for Sink to report Max Link Rate = 0, if it is
3830          * an eDP device that is reporting specialized link rates in the
3831          * SUPPORTED_LINK_RATE table.
3832          */
3833         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3834                 return false;
3835
3836         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3837                                  DP_DPCD_REV];
3838
3839         read_dp_device_vendor_id(link);
3840
3841         get_active_converter_info(ds_port.byte, link);
3842
3843         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3844
3845         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3846                                  DP_DPCD_REV];
3847
3848         link->dpcd_caps.allow_invalid_MSA_timing_param =
3849                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3850
3851         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3852                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3853
3854         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3855                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3856
3857         link->reported_link_cap.lane_count =
3858                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3859         link->reported_link_cap.link_rate = dpcd_data[
3860                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3861         link->reported_link_cap.link_spread =
3862                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3863                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3864
3865         edp_config_cap.raw = dpcd_data[
3866                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3867         link->dpcd_caps.panel_mode_edp =
3868                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3869         link->dpcd_caps.dpcd_display_control_capable =
3870                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3871
3872         link->test_pattern_enabled = false;
3873         link->compliance_test_state.raw = 0;
3874
3875         /* read sink count */
3876         core_link_read_dpcd(link,
3877                         DP_SINK_COUNT,
3878                         &link->dpcd_caps.sink_count.raw,
3879                         sizeof(link->dpcd_caps.sink_count.raw));
3880
3881         /* read sink ieee oui */
3882         core_link_read_dpcd(link,
3883                         DP_SINK_OUI,
3884                         (uint8_t *)(&sink_id),
3885                         sizeof(sink_id));
3886
3887         link->dpcd_caps.sink_dev_id =
3888                         (sink_id.ieee_oui[0] << 16) +
3889                         (sink_id.ieee_oui[1] << 8) +
3890                         (sink_id.ieee_oui[2]);
3891
3892         memmove(
3893                 link->dpcd_caps.sink_dev_id_str,
3894                 sink_id.ieee_device_id,
3895                 sizeof(sink_id.ieee_device_id));
3896
3897         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3898         {
3899                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3900
3901                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3902                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3903                             sizeof(str_mbp_2017))) {
3904                         link->reported_link_cap.link_rate = 0x0c;
3905                 }
3906         }
3907
3908         core_link_read_dpcd(
3909                 link,
3910                 DP_SINK_HW_REVISION_START,
3911                 (uint8_t *)&dp_hw_fw_revision,
3912                 sizeof(dp_hw_fw_revision));
3913
3914         link->dpcd_caps.sink_hw_revision =
3915                 dp_hw_fw_revision.ieee_hw_rev;
3916
3917         memmove(
3918                 link->dpcd_caps.sink_fw_revision,
3919                 dp_hw_fw_revision.ieee_fw_rev,
3920                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3921
3922         memset(&link->dpcd_caps.dsc_caps, '\0',
3923                         sizeof(link->dpcd_caps.dsc_caps));
3924         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3925         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3926         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3927                 status = core_link_read_dpcd(
3928                                 link,
3929                                 DP_FEC_CAPABILITY,
3930                                 &link->dpcd_caps.fec_cap.raw,
3931                                 sizeof(link->dpcd_caps.fec_cap.raw));
3932                 status = core_link_read_dpcd(
3933                                 link,
3934                                 DP_DSC_SUPPORT,
3935                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3936                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3937                 status = core_link_read_dpcd(
3938                                 link,
3939                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3940                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3941                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3942         }
3943
3944         if (!dpcd_read_sink_ext_caps(link))
3945                 link->dpcd_sink_ext_caps.raw = 0;
3946
3947         /* Connectivity log: detection */
3948         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3949
3950         return true;
3951 }
3952
3953 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3954 {
3955         uint8_t dpcd_data[16];
3956         uint32_t read_dpcd_retry_cnt = 3;
3957         enum dc_status status = DC_ERROR_UNEXPECTED;
3958         union dp_downstream_port_present ds_port = { 0 };
3959         union down_stream_port_count down_strm_port_count;
3960         union edp_configuration_cap edp_config_cap;
3961
3962         int i;
3963
3964         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3965                 status = core_link_read_dpcd(
3966                                 link,
3967                                 DP_DPCD_REV,
3968                                 dpcd_data,
3969                                 sizeof(dpcd_data));
3970                 if (status == DC_OK)
3971                         break;
3972         }
3973
3974         link->dpcd_caps.dpcd_rev.raw =
3975                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3976
3977         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3978                 return false;
3979
3980         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3981                         DP_DPCD_REV];
3982
3983         get_active_converter_info(ds_port.byte, link);
3984
3985         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3986                         DP_DPCD_REV];
3987
3988         link->dpcd_caps.allow_invalid_MSA_timing_param =
3989                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3990
3991         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3992                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3993
3994         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3995                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3996
3997         link->reported_link_cap.lane_count =
3998                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3999         link->reported_link_cap.link_rate = dpcd_data[
4000                 DP_MAX_LINK_RATE - DP_DPCD_REV];
4001         link->reported_link_cap.link_spread =
4002                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
4003                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
4004
4005         edp_config_cap.raw = dpcd_data[
4006                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4007         link->dpcd_caps.panel_mode_edp =
4008                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
4009         link->dpcd_caps.dpcd_display_control_capable =
4010                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4011
4012         return true;
4013 }
4014
4015 bool detect_dp_sink_caps(struct dc_link *link)
4016 {
4017         return retrieve_link_cap(link);
4018
4019         /* dc init_hw has power encoder using default
4020          * signal for connector. For native DP, no
4021          * need to power up encoder again. If not native
4022          * DP, hw_init may need check signal or power up
4023          * encoder here.
4024          */
4025         /* TODO save sink caps in link->sink */
4026 }
4027
4028 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
4029 {
4030         enum dc_link_rate link_rate;
4031         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4032         switch (link_rate_in_khz) {
4033         case 1620000:
4034                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
4035                 break;
4036         case 2160000:
4037                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
4038                 break;
4039         case 2430000:
4040                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
4041                 break;
4042         case 2700000:
4043                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
4044                 break;
4045         case 3240000:
4046                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
4047                 break;
4048         case 4320000:
4049                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
4050                 break;
4051         case 5400000:
4052                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
4053                 break;
4054         case 8100000:
4055                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
4056                 break;
4057         default:
4058                 link_rate = LINK_RATE_UNKNOWN;
4059                 break;
4060         }
4061         return link_rate;
4062 }
4063
4064 void detect_edp_sink_caps(struct dc_link *link)
4065 {
4066         uint8_t supported_link_rates[16];
4067         uint32_t entry;
4068         uint32_t link_rate_in_khz;
4069         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4070         uint8_t backlight_adj_cap;
4071
4072         retrieve_link_cap(link);
4073         link->dpcd_caps.edp_supported_link_rates_count = 0;
4074         memset(supported_link_rates, 0, sizeof(supported_link_rates));
4075
4076         /*
4077          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4078          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4079          */
4080         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4081                         (link->dc->debug.optimize_edp_link_rate ||
4082                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4083                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4084                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4085                                                         supported_link_rates, sizeof(supported_link_rates));
4086
4087                 for (entry = 0; entry < 16; entry += 2) {
4088                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4089                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4090                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4091                                                                                 supported_link_rates[entry]) * 200;
4092
4093                         if (link_rate_in_khz != 0) {
4094                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4095                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4096                                 link->dpcd_caps.edp_supported_link_rates_count++;
4097
4098                                 if (link->reported_link_cap.link_rate < link_rate)
4099                                         link->reported_link_cap.link_rate = link_rate;
4100                         }
4101                 }
4102         }
4103         link->verified_link_cap = link->reported_link_cap;
4104
4105         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4106                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4107
4108         link->dpcd_caps.dynamic_backlight_capable_edp =
4109                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4110
4111         dc_link_set_default_brightness_aux(link);
4112 }
4113
4114 void dc_link_dp_enable_hpd(const struct dc_link *link)
4115 {
4116         struct link_encoder *encoder = link->link_enc;
4117
4118         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4119                 encoder->funcs->enable_hpd(encoder);
4120 }
4121
4122 void dc_link_dp_disable_hpd(const struct dc_link *link)
4123 {
4124         struct link_encoder *encoder = link->link_enc;
4125
4126         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4127                 encoder->funcs->disable_hpd(encoder);
4128 }
4129
4130 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4131 {
4132         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4133                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4134                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4135                 return true;
4136         else
4137                 return false;
4138 }
4139
4140 static void set_crtc_test_pattern(struct dc_link *link,
4141                                 struct pipe_ctx *pipe_ctx,
4142                                 enum dp_test_pattern test_pattern,
4143                                 enum dp_test_pattern_color_space test_pattern_color_space)
4144 {
4145         enum controller_dp_test_pattern controller_test_pattern;
4146         enum dc_color_depth color_depth = pipe_ctx->
4147                 stream->timing.display_color_depth;
4148         struct bit_depth_reduction_params params;
4149         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4150         int width = pipe_ctx->stream->timing.h_addressable +
4151                 pipe_ctx->stream->timing.h_border_left +
4152                 pipe_ctx->stream->timing.h_border_right;
4153         int height = pipe_ctx->stream->timing.v_addressable +
4154                 pipe_ctx->stream->timing.v_border_bottom +
4155                 pipe_ctx->stream->timing.v_border_top;
4156
4157         memset(&params, 0, sizeof(params));
4158
4159         switch (test_pattern) {
4160         case DP_TEST_PATTERN_COLOR_SQUARES:
4161                 controller_test_pattern =
4162                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4163         break;
4164         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4165                 controller_test_pattern =
4166                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4167         break;
4168         case DP_TEST_PATTERN_VERTICAL_BARS:
4169                 controller_test_pattern =
4170                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4171         break;
4172         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4173                 controller_test_pattern =
4174                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4175         break;
4176         case DP_TEST_PATTERN_COLOR_RAMP:
4177                 controller_test_pattern =
4178                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4179         break;
4180         default:
4181                 controller_test_pattern =
4182                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4183         break;
4184         }
4185
4186         switch (test_pattern) {
4187         case DP_TEST_PATTERN_COLOR_SQUARES:
4188         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4189         case DP_TEST_PATTERN_VERTICAL_BARS:
4190         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4191         case DP_TEST_PATTERN_COLOR_RAMP:
4192         {
4193                 /* disable bit depth reduction */
4194                 pipe_ctx->stream->bit_depth_params = params;
4195                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4196                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4197                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4198                                 controller_test_pattern, color_depth);
4199                 else if (link->dc->hwss.set_disp_pattern_generator) {
4200                         struct pipe_ctx *odm_pipe;
4201                         enum controller_dp_color_space controller_color_space;
4202                         int opp_cnt = 1;
4203                         int offset = 0;
4204                         int dpg_width = width;
4205
4206                         switch (test_pattern_color_space) {
4207                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4208                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4209                                 break;
4210                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4211                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4212                                 break;
4213                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4214                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4215                                 break;
4216                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4217                         default:
4218                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4219                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4220                                 ASSERT(0);
4221                                 break;
4222                         }
4223
4224                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4225                                 opp_cnt++;
4226                         dpg_width = width / opp_cnt;
4227                         offset = dpg_width;
4228
4229                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4230                                         pipe_ctx,
4231                                         controller_test_pattern,
4232                                         controller_color_space,
4233                                         color_depth,
4234                                         NULL,
4235                                         dpg_width,
4236                                         height,
4237                                         0);
4238
4239                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4240                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4241
4242                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4243                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4244                                                 odm_pipe,
4245                                                 controller_test_pattern,
4246                                                 controller_color_space,
4247                                                 color_depth,
4248                                                 NULL,
4249                                                 dpg_width,
4250                                                 height,
4251                                                 offset);
4252                                 offset += offset;
4253                         }
4254                 }
4255         }
4256         break;
4257         case DP_TEST_PATTERN_VIDEO_MODE:
4258         {
4259                 /* restore bitdepth reduction */
4260                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4261                 pipe_ctx->stream->bit_depth_params = params;
4262                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4263                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4264                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4265                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4266                                 color_depth);
4267                 else if (link->dc->hwss.set_disp_pattern_generator) {
4268                         struct pipe_ctx *odm_pipe;
4269                         int opp_cnt = 1;
4270                         int dpg_width = width;
4271
4272                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4273                                 opp_cnt++;
4274
4275                         dpg_width = width / opp_cnt;
4276                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4277                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4278
4279                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4280                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4281                                                 odm_pipe,
4282                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4283                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4284                                                 color_depth,
4285                                                 NULL,
4286                                                 dpg_width,
4287                                                 height,
4288                                                 0);
4289                         }
4290                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4291                                         pipe_ctx,
4292                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4293                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4294                                         color_depth,
4295                                         NULL,
4296                                         dpg_width,
4297                                         height,
4298                                         0);
4299                 }
4300         }
4301         break;
4302
4303         default:
4304         break;
4305         }
4306 }
4307
4308 bool dc_link_dp_set_test_pattern(
4309         struct dc_link *link,
4310         enum dp_test_pattern test_pattern,
4311         enum dp_test_pattern_color_space test_pattern_color_space,
4312         const struct link_training_settings *p_link_settings,
4313         const unsigned char *p_custom_pattern,
4314         unsigned int cust_pattern_size)
4315 {
4316         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4317         struct pipe_ctx *pipe_ctx = NULL;
4318         unsigned int lane;
4319         unsigned int i;
4320         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4321         union dpcd_training_pattern training_pattern;
4322         enum dpcd_phy_test_patterns pattern;
4323
4324         memset(&training_pattern, 0, sizeof(training_pattern));
4325
4326         for (i = 0; i < MAX_PIPES; i++) {
4327                 if (pipes[i].stream == NULL)
4328                         continue;
4329
4330                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4331                         pipe_ctx = &pipes[i];
4332                         break;
4333                 }
4334         }
4335
4336         if (pipe_ctx == NULL)
4337                 return false;
4338
4339         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4340         if (link->test_pattern_enabled && test_pattern ==
4341                         DP_TEST_PATTERN_VIDEO_MODE) {
4342                 /* Set CRTC Test Pattern */
4343                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4344                 dp_set_hw_test_pattern(link, test_pattern,
4345                                 (uint8_t *)p_custom_pattern,
4346                                 (uint32_t)cust_pattern_size);
4347
4348                 /* Unblank Stream */
4349                 link->dc->hwss.unblank_stream(
4350                         pipe_ctx,
4351                         &link->verified_link_cap);
4352                 /* TODO:m_pHwss->MuteAudioEndpoint
4353                  * (pPathMode->pDisplayPath, false);
4354                  */
4355
4356                 /* Reset Test Pattern state */
4357                 link->test_pattern_enabled = false;
4358
4359                 return true;
4360         }
4361
4362         /* Check for PHY Test Patterns */
4363         if (is_dp_phy_pattern(test_pattern)) {
4364                 /* Set DPCD Lane Settings before running test pattern */
4365                 if (p_link_settings != NULL) {
4366                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4367                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4368                 }
4369
4370                 /* Blank stream if running test pattern */
4371                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4372                         /*TODO:
4373                          * m_pHwss->
4374                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4375                          */
4376                         /* Blank stream */
4377                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4378                 }
4379
4380                 dp_set_hw_test_pattern(link, test_pattern,
4381                                 (uint8_t *)p_custom_pattern,
4382                                 (uint32_t)cust_pattern_size);
4383
4384                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4385                         /* Set Test Pattern state */
4386                         link->test_pattern_enabled = true;
4387                         if (p_link_settings != NULL)
4388                                 dpcd_set_link_settings(link,
4389                                                 p_link_settings);
4390                 }
4391
4392                 switch (test_pattern) {
4393                 case DP_TEST_PATTERN_VIDEO_MODE:
4394                         pattern = PHY_TEST_PATTERN_NONE;
4395                         break;
4396                 case DP_TEST_PATTERN_D102:
4397                         pattern = PHY_TEST_PATTERN_D10_2;
4398                         break;
4399                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4400                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4401                         break;
4402                 case DP_TEST_PATTERN_PRBS7:
4403                         pattern = PHY_TEST_PATTERN_PRBS7;
4404                         break;
4405                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4406                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4407                         break;
4408                 case DP_TEST_PATTERN_CP2520_1:
4409                         pattern = PHY_TEST_PATTERN_CP2520_1;
4410                         break;
4411                 case DP_TEST_PATTERN_CP2520_2:
4412                         pattern = PHY_TEST_PATTERN_CP2520_2;
4413                         break;
4414                 case DP_TEST_PATTERN_CP2520_3:
4415                         pattern = PHY_TEST_PATTERN_CP2520_3;
4416                         break;
4417                 default:
4418                         return false;
4419                 }
4420
4421                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4422                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4423                         return false;
4424
4425                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4426                         /* tell receiver that we are sending qualification
4427                          * pattern DP 1.2 or later - DP receiver's link quality
4428                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4429                          * register (0x10B~0x10E)\
4430                          */
4431                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4432                                 link_qual_pattern[lane] =
4433                                                 (unsigned char)(pattern);
4434
4435                         core_link_write_dpcd(link,
4436                                         DP_LINK_QUAL_LANE0_SET,
4437                                         link_qual_pattern,
4438                                         sizeof(link_qual_pattern));
4439                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4440                            link->dpcd_caps.dpcd_rev.raw == 0) {
4441                         /* tell receiver that we are sending qualification
4442                          * pattern DP 1.1a or earlier - DP receiver's link
4443                          * quality pattern is set using
4444                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4445                          * register (0x102). We will use v_1.3 when we are
4446                          * setting test pattern for DP 1.1.
4447                          */
4448                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4449                                             &training_pattern.raw,
4450                                             sizeof(training_pattern));
4451                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4452                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4453                                              &training_pattern.raw,
4454                                              sizeof(training_pattern));
4455                 }
4456         } else {
4457                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4458
4459                 switch (test_pattern_color_space) {
4460                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4461                         color_space = COLOR_SPACE_SRGB;
4462                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4463                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4464                         break;
4465
4466                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4467                         color_space = COLOR_SPACE_YCBCR601;
4468                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4469                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4470                         break;
4471                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4472                         color_space = COLOR_SPACE_YCBCR709;
4473                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4474                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4475                         break;
4476                 default:
4477                         break;
4478                 }
4479
4480                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4481                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4482                                 union dmub_hw_lock_flags hw_locks = { 0 };
4483                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4484
4485                                 hw_locks.bits.lock_dig = 1;
4486                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4487
4488                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4489                                                         true,
4490                                                         &hw_locks,
4491                                                         &inst_flags);
4492                         } else
4493                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4494                                                 pipe_ctx->stream_res.tg);
4495                 }
4496
4497                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4498                 /* update MSA to requested color space */
4499                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4500                                 &pipe_ctx->stream->timing,
4501                                 color_space,
4502                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4503                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4504
4505                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4506                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4507                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4508                         else
4509                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4510                         resource_build_info_frame(pipe_ctx);
4511                         link->dc->hwss.update_info_frame(pipe_ctx);
4512                 }
4513
4514                 /* CRTC Patterns */
4515                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4516                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4517                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4518                                 CRTC_STATE_VACTIVE);
4519                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4520                                 CRTC_STATE_VBLANK);
4521                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4522                                 CRTC_STATE_VACTIVE);
4523
4524                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4525                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4526                                 union dmub_hw_lock_flags hw_locks = { 0 };
4527                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4528
4529                                 hw_locks.bits.lock_dig = 1;
4530                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4531
4532                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4533                                                         false,
4534                                                         &hw_locks,
4535                                                         &inst_flags);
4536                         } else
4537                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4538                                                 pipe_ctx->stream_res.tg);
4539                 }
4540
4541                 /* Set Test Pattern state */
4542                 link->test_pattern_enabled = true;
4543         }
4544
4545         return true;
4546 }
4547
4548 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4549 {
4550         unsigned char mstmCntl;
4551
4552         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4553         if (enable)
4554                 mstmCntl |= DP_MST_EN;
4555         else
4556                 mstmCntl &= (~DP_MST_EN);
4557
4558         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4559 }
4560
4561 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4562 {
4563         union dpcd_edp_config edp_config_set;
4564         bool panel_mode_edp = false;
4565
4566         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4567
4568         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4569
4570                 switch (panel_mode) {
4571                 case DP_PANEL_MODE_EDP:
4572                 case DP_PANEL_MODE_SPECIAL:
4573                         panel_mode_edp = true;
4574                         break;
4575
4576                 default:
4577                                 break;
4578                 }
4579
4580                 /*set edp panel mode in receiver*/
4581                 core_link_read_dpcd(
4582                         link,
4583                         DP_EDP_CONFIGURATION_SET,
4584                         &edp_config_set.raw,
4585                         sizeof(edp_config_set.raw));
4586
4587                 if (edp_config_set.bits.PANEL_MODE_EDP
4588                         != panel_mode_edp) {
4589                         enum dc_status result;
4590
4591                         edp_config_set.bits.PANEL_MODE_EDP =
4592                         panel_mode_edp;
4593                         result = core_link_write_dpcd(
4594                                 link,
4595                                 DP_EDP_CONFIGURATION_SET,
4596                                 &edp_config_set.raw,
4597                                 sizeof(edp_config_set.raw));
4598
4599                         ASSERT(result == DC_OK);
4600                 }
4601         }
4602         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4603                  "eDP panel mode enabled: %d \n",
4604                  link->link_index,
4605                  link->dpcd_caps.panel_mode_edp,
4606                  panel_mode_edp);
4607 }
4608
4609 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4610 {
4611         /* We need to explicitly check that connector
4612          * is not DP. Some Travis_VGA get reported
4613          * by video bios as DP.
4614          */
4615         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4616
4617                 switch (link->dpcd_caps.branch_dev_id) {
4618                 case DP_BRANCH_DEVICE_ID_0022B9:
4619                         /* alternate scrambler reset is required for Travis
4620                          * for the case when external chip does not
4621                          * provide sink device id, alternate scrambler
4622                          * scheme will  be overriden later by querying
4623                          * Encoder features
4624                          */
4625                         if (strncmp(
4626                                 link->dpcd_caps.branch_dev_name,
4627                                 DP_VGA_LVDS_CONVERTER_ID_2,
4628                                 sizeof(
4629                                 link->dpcd_caps.
4630                                 branch_dev_name)) == 0) {
4631                                         return DP_PANEL_MODE_SPECIAL;
4632                         }
4633                         break;
4634                 case DP_BRANCH_DEVICE_ID_00001A:
4635                         /* alternate scrambler reset is required for Travis
4636                          * for the case when external chip does not provide
4637                          * sink device id, alternate scrambler scheme will
4638                          * be overriden later by querying Encoder feature
4639                          */
4640                         if (strncmp(link->dpcd_caps.branch_dev_name,
4641                                 DP_VGA_LVDS_CONVERTER_ID_3,
4642                                 sizeof(
4643                                 link->dpcd_caps.
4644                                 branch_dev_name)) == 0) {
4645                                         return DP_PANEL_MODE_SPECIAL;
4646                         }
4647                         break;
4648                 default:
4649                         break;
4650                 }
4651         }
4652
4653         if (link->dpcd_caps.panel_mode_edp) {
4654                 return DP_PANEL_MODE_EDP;
4655         }
4656
4657         return DP_PANEL_MODE_DEFAULT;
4658 }
4659
4660 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
4661 {
4662         /* FEC has to be "set ready" before the link training.
4663          * The policy is to always train with FEC
4664          * if the sink supports it and leave it enabled on link.
4665          * If FEC is not supported, disable it.
4666          */
4667         struct link_encoder *link_enc = NULL;
4668         enum dc_status status = DC_OK;
4669         uint8_t fec_config = 0;
4670
4671         /* Access link encoder based on whether it is statically
4672          * or dynamically assigned to a link.
4673          */
4674         if (link->is_dig_mapping_flexible &&
4675                         link->dc->res_pool->funcs->link_encs_assign)
4676                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4677         else
4678                 link_enc = link->link_enc;
4679         ASSERT(link_enc);
4680
4681         if (!dc_link_should_enable_fec(link))
4682                 return status;
4683
4684         if (link_enc->funcs->fec_set_ready &&
4685                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4686                 if (ready) {
4687                         fec_config = 1;
4688                         status = core_link_write_dpcd(link,
4689                                         DP_FEC_CONFIGURATION,
4690                                         &fec_config,
4691                                         sizeof(fec_config));
4692                         if (status == DC_OK) {
4693                                 link_enc->funcs->fec_set_ready(link_enc, true);
4694                                 link->fec_state = dc_link_fec_ready;
4695                         } else {
4696                                 link_enc->funcs->fec_set_ready(link->link_enc, false);
4697                                 link->fec_state = dc_link_fec_not_ready;
4698                                 dm_error("dpcd write failed to set fec_ready");
4699                         }
4700                 } else if (link->fec_state == dc_link_fec_ready) {
4701                         fec_config = 0;
4702                         status = core_link_write_dpcd(link,
4703                                         DP_FEC_CONFIGURATION,
4704                                         &fec_config,
4705                                         sizeof(fec_config));
4706                         link_enc->funcs->fec_set_ready(link_enc, false);
4707                         link->fec_state = dc_link_fec_not_ready;
4708                 }
4709         }
4710
4711         return status;
4712 }
4713
4714 void dp_set_fec_enable(struct dc_link *link, bool enable)
4715 {
4716         struct link_encoder *link_enc = NULL;
4717
4718         /* Access link encoder based on whether it is statically
4719          * or dynamically assigned to a link.
4720          */
4721         if (link->is_dig_mapping_flexible &&
4722                         link->dc->res_pool->funcs->link_encs_assign)
4723                 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4724                                 link->dc->current_state, link);
4725         else
4726                 link_enc = link->link_enc;
4727         ASSERT(link_enc);
4728
4729         if (!dc_link_should_enable_fec(link))
4730                 return;
4731
4732         if (link_enc->funcs->fec_set_enable &&
4733                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4734                 if (link->fec_state == dc_link_fec_ready && enable) {
4735                         /* Accord to DP spec, FEC enable sequence can first
4736                          * be transmitted anytime after 1000 LL codes have
4737                          * been transmitted on the link after link training
4738                          * completion. Using 1 lane RBR should have the maximum
4739                          * time for transmitting 1000 LL codes which is 6.173 us.
4740                          * So use 7 microseconds delay instead.
4741                          */
4742                         udelay(7);
4743                         link_enc->funcs->fec_set_enable(link_enc, true);
4744                         link->fec_state = dc_link_fec_enabled;
4745                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4746                         link_enc->funcs->fec_set_enable(link_enc, false);
4747                         link->fec_state = dc_link_fec_ready;
4748                 }
4749         }
4750 }
4751
4752 void dpcd_set_source_specific_data(struct dc_link *link)
4753 {
4754         if (!link->dc->vendor_signature.is_valid) {
4755                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4756                 struct dpcd_amd_signature amd_signature = {0};
4757                 struct dpcd_amd_device_id amd_device_id = {0};
4758
4759                 amd_device_id.device_id_byte1 =
4760                                 (uint8_t)(link->ctx->asic_id.chip_id);
4761                 amd_device_id.device_id_byte2 =
4762                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4763                 amd_device_id.dce_version =
4764                                 (uint8_t)(link->ctx->dce_version);
4765                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4766                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4767
4768                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4769                                 (uint8_t *)(&amd_signature),
4770                                 sizeof(amd_signature));
4771
4772                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4773                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4774                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4775
4776                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4777                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4778                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4779
4780                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4781                                 (uint8_t *)(&amd_signature),
4782                                 sizeof(amd_signature));
4783                 }
4784
4785                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4786                                 (uint8_t *)(&amd_device_id),
4787                                 sizeof(amd_device_id));
4788
4789                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4790                         link->dc->caps.min_horizontal_blanking_period != 0) {
4791
4792                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4793
4794                         result_write_min_hblank = core_link_write_dpcd(link,
4795                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4796                                 sizeof(hblank_size));
4797                 }
4798                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4799                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4800                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4801                                                         result_write_min_hblank,
4802                                                         link->link_index,
4803                                                         link->ctx->dce_version,
4804                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4805                                                         link->dc->caps.min_horizontal_blanking_period,
4806                                                         link->dpcd_caps.branch_dev_id,
4807                                                         link->dpcd_caps.branch_dev_name[0],
4808                                                         link->dpcd_caps.branch_dev_name[1],
4809                                                         link->dpcd_caps.branch_dev_name[2],
4810                                                         link->dpcd_caps.branch_dev_name[3],
4811                                                         link->dpcd_caps.branch_dev_name[4],
4812                                                         link->dpcd_caps.branch_dev_name[5]);
4813         } else {
4814                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4815                                 link->dc->vendor_signature.data.raw,
4816                                 sizeof(link->dc->vendor_signature.data.raw));
4817         }
4818 }
4819
4820 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4821                 bool isHDR,
4822                 uint32_t backlight_millinits,
4823                 uint32_t transition_time_in_ms)
4824 {
4825         struct dpcd_source_backlight_set dpcd_backlight_set;
4826         uint8_t backlight_control = isHDR ? 1 : 0;
4827
4828         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4829                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4830                 return false;
4831
4832         // OLEDs have no PWM, they can only use AUX
4833         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4834                 backlight_control = 1;
4835
4836         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4837         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4838
4839
4840         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4841                         (uint8_t *)(&dpcd_backlight_set),
4842                         sizeof(dpcd_backlight_set)) != DC_OK)
4843                 return false;
4844
4845         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4846                         &backlight_control, 1) != DC_OK)
4847                 return false;
4848
4849         return true;
4850 }
4851
4852 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4853                 uint32_t *backlight_millinits_avg,
4854                 uint32_t *backlight_millinits_peak)
4855 {
4856         union dpcd_source_backlight_get dpcd_backlight_get;
4857
4858         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4859
4860         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4861                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4862                 return false;
4863
4864         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4865                         dpcd_backlight_get.raw,
4866                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4867                 return false;
4868
4869         *backlight_millinits_avg =
4870                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4871         *backlight_millinits_peak =
4872                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4873
4874         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4875         if (*backlight_millinits_avg == 0 ||
4876                         *backlight_millinits_avg > *backlight_millinits_peak)
4877                 return false;
4878
4879         return true;
4880 }
4881
4882 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4883 {
4884         uint8_t backlight_enable = enable ? 1 : 0;
4885
4886         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4887                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4888                 return false;
4889
4890         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4891                 &backlight_enable, 1) != DC_OK)
4892                 return false;
4893
4894         return true;
4895 }
4896
4897 // we read default from 0x320 because we expect BIOS wrote it there
4898 // regular get_backlight_nit reads from panel set at 0x326
4899 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4900 {
4901         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4902                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4903                 return false;
4904
4905         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4906                 (uint8_t *) backlight_millinits,
4907                 sizeof(uint32_t)) != DC_OK)
4908                 return false;
4909
4910         return true;
4911 }
4912
4913 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4914 {
4915         uint32_t default_backlight;
4916
4917         if (link &&
4918                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4919                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4920                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4921                         default_backlight = 150000;
4922                 // if < 5 nits or > 5000, it might be wrong readback
4923                 if (default_backlight < 5000 || default_backlight > 5000000)
4924                         default_backlight = 150000; //
4925
4926                 return dc_link_set_backlight_level_nits(link, true,
4927                                 default_backlight, 0);
4928         }
4929         return false;
4930 }
4931
4932 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4933 {
4934         struct dc_link_settings link_setting;
4935         uint8_t link_bw_set;
4936         uint8_t link_rate_set;
4937         uint32_t req_bw;
4938         union lane_count_set lane_count_set = { {0} };
4939
4940         ASSERT(link || crtc_timing); // invalid input
4941
4942         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4943                         !link->dc->debug.optimize_edp_link_rate)
4944                 return false;
4945
4946
4947         // Read DPCD 00100h to find if standard link rates are set
4948         core_link_read_dpcd(link, DP_LINK_BW_SET,
4949                                 &link_bw_set, sizeof(link_bw_set));
4950
4951         if (link_bw_set) {
4952                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4953                 return true;
4954         }
4955
4956         // Read DPCD 00115h to find the edp link rate set used
4957         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4958                             &link_rate_set, sizeof(link_rate_set));
4959
4960         // Read DPCD 00101h to find out the number of lanes currently set
4961         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4962                                 &lane_count_set.raw, sizeof(lane_count_set));
4963
4964         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4965
4966         decide_edp_link_settings(link, &link_setting, req_bw);
4967
4968         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4969                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4970                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4971                 return true;
4972         }
4973
4974         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4975         return false;
4976 }
4977
4978 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4979 {
4980         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4981                         (link_settings->link_rate <= LINK_RATE_HIGH3))
4982                 return DP_8b_10b_ENCODING;
4983         return DP_UNKNOWN_ENCODING;
4984 }
4985