drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17
  18 /*Travis*/
  19 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  20 /*Nutmeg*/
  21 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  22
  23 #define DC_LOGGER \
  24         link->ctx->logger
  25 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  26
  27 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
  28
  29         /* maximum pre emphasis level allowed for each voltage swing level*/
  30         static const enum dc_pre_emphasis
  31         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  32                                             PRE_EMPHASIS_LEVEL2,
  33                                             PRE_EMPHASIS_LEVEL1,
  34                                             PRE_EMPHASIS_DISABLED };
  35
  36 enum {
  37         POST_LT_ADJ_REQ_LIMIT = 6,
  38         POST_LT_ADJ_REQ_TIMEOUT = 200
  39 };
  40
  41 enum {
  42         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  43         /* to avoid infinite loop where-in the receiver
  44          * switches between different VS
  45          */
  46         LINK_TRAINING_MAX_CR_RETRY = 100
  47 };
  48
  49 static bool decide_fallback_link_setting(
  50                 struct dc_link_settings initial_link_settings,
  51                 struct dc_link_settings *current_link_setting,
  52                 enum link_training_result training_result);
  53 static struct dc_link_settings get_common_supported_link_settings(
  54                 struct dc_link_settings link_setting_a,
  55                 struct dc_link_settings link_setting_b);
  56
  57 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  58                 const struct dc_link_settings *link_settings)
  59 {
  60         union training_aux_rd_interval training_rd_interval;
  61         uint32_t wait_in_micro_secs = 100;
  62
  63         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  64         core_link_read_dpcd(
  65                         link,
  66                         DP_TRAINING_AUX_RD_INTERVAL,
  67                         (uint8_t *)&training_rd_interval,
  68                         sizeof(training_rd_interval));
  69         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  70                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  71         return wait_in_micro_secs;
  72 }
  73
  74 static uint32_t get_eq_training_aux_rd_interval(
  75         struct dc_link *link,
  76         const struct dc_link_settings *link_settings)
  77 {
  78         union training_aux_rd_interval training_rd_interval;
  79         uint32_t wait_in_micro_secs = 400;
  80
  81         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  82         /* overwrite the delay if rev > 1.1*/
  83         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  84                 /* DP 1.2 or later - retrieve delay through
  85                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  86                 core_link_read_dpcd(
  87                         link,
  88                         DP_TRAINING_AUX_RD_INTERVAL,
  89                         (uint8_t *)&training_rd_interval,
  90                         sizeof(training_rd_interval));
  91
  92                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  93                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  94         }
  95
  96         return wait_in_micro_secs;
  97 }
  98
  99 static void wait_for_training_aux_rd_interval(
 100         struct dc_link *link,
 101         uint32_t wait_in_micro_secs)
 102 {
 103         udelay(wait_in_micro_secs);
 104
 105         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 106                 __func__,
 107                 wait_in_micro_secs);
 108 }
 109
 110 static void dpcd_set_training_pattern(
 111         struct dc_link *link,
 112         union dpcd_training_pattern dpcd_pattern)
 113 {
 114         core_link_write_dpcd(
 115                 link,
 116                 DP_TRAINING_PATTERN_SET,
 117                 &dpcd_pattern.raw,
 118                 1);
 119
 120         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 121                 __func__,
 122                 DP_TRAINING_PATTERN_SET,
 123                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 124 }
 125
 126 static enum dc_dp_training_pattern decide_cr_training_pattern(
 127                 const struct dc_link_settings *link_settings)
 128 {
 129         enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
 130
 131         return pattern;
 132 }
 133
 134 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 135                 const struct dc_link_settings *link_settings)
 136 {
 137         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 138         struct encoder_feature_support *features = &link->link_enc->features;
 139         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 140
 141         if (features->flags.bits.IS_TPS3_CAPABLE)
 142                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 143
 144         if (features->flags.bits.IS_TPS4_CAPABLE)
 145                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 146
 147         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 148                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 149                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 150
 151         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 152                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 153                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 154
 155         return DP_TRAINING_PATTERN_SEQUENCE_2;
 156 }
 157
 158 static void dpcd_set_link_settings(
 159         struct dc_link *link,
 160         const struct link_training_settings *lt_settings)
 161 {
 162         uint8_t rate;
 163
 164         union down_spread_ctrl downspread = { {0} };
 165         union lane_count_set lane_count_set = { {0} };
 166
 167         downspread.raw = (uint8_t)
 168         (lt_settings->link_settings.link_spread);
 169
 170         lane_count_set.bits.LANE_COUNT_SET =
 171         lt_settings->link_settings.lane_count;
 172
 173         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 174         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 175
 176
 177         if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 178                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 179                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 180         }
 181
 182         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 183                 &downspread.raw, sizeof(downspread));
 184
 185         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 186                 &lane_count_set.raw, 1);
 187
 188         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 189                         lt_settings->link_settings.use_link_rate_set == true) {
 190                 rate = 0;
 191                 /* WA for some MUX chips that will power down with eDP and lose supported
 192                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 193                  * MUX chip gets link rate set back before link training.
 194                  */
 195                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 196                         uint8_t supported_link_rates[16];
 197
 198                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 199                                         supported_link_rates, sizeof(supported_link_rates));
 200                 }
 201                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 202                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 203                                 &lt_settings->link_settings.link_rate_set, 1);
 204         } else {
 205                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 206                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 207         }
 208
 209         if (rate) {
 210                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 211                         __func__,
 212                         DP_LINK_BW_SET,
 213                         lt_settings->link_settings.link_rate,
 214                         DP_LANE_COUNT_SET,
 215                         lt_settings->link_settings.lane_count,
 216                         lt_settings->enhanced_framing,
 217                         DP_DOWNSPREAD_CTRL,
 218                         lt_settings->link_settings.link_spread);
 219         } else {
 220                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 221                         __func__,
 222                         DP_LINK_RATE_SET,
 223                         lt_settings->link_settings.link_rate_set,
 224                         DP_LANE_COUNT_SET,
 225                         lt_settings->link_settings.lane_count,
 226                         lt_settings->enhanced_framing,
 227                         DP_DOWNSPREAD_CTRL,
 228                         lt_settings->link_settings.link_spread);
 229         }
 230 }
 231
 232 static enum dpcd_training_patterns
 233         dc_dp_training_pattern_to_dpcd_training_pattern(
 234         struct dc_link *link,
 235         enum dc_dp_training_pattern pattern)
 236 {
 237         enum dpcd_training_patterns dpcd_tr_pattern =
 238         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 239
 240         switch (pattern) {
 241         case DP_TRAINING_PATTERN_SEQUENCE_1:
 242                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 243                 break;
 244         case DP_TRAINING_PATTERN_SEQUENCE_2:
 245                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 246                 break;
 247         case DP_TRAINING_PATTERN_SEQUENCE_3:
 248                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 249                 break;
 250         case DP_TRAINING_PATTERN_SEQUENCE_4:
 251                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 252                 break;
 253         default:
 254                 ASSERT(0);
 255                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 256                         __func__, pattern);
 257                 break;
 258         }
 259
 260         return dpcd_tr_pattern;
 261 }
 262
 263 static uint8_t dc_dp_initialize_scrambling_data_symbols(
 264         struct dc_link *link,
 265         enum dc_dp_training_pattern pattern)
 266 {
 267         uint8_t disable_scrabled_data_symbols = 0;
 268
 269         switch (pattern) {
 270         case DP_TRAINING_PATTERN_SEQUENCE_1:
 271         case DP_TRAINING_PATTERN_SEQUENCE_2:
 272         case DP_TRAINING_PATTERN_SEQUENCE_3:
 273                 disable_scrabled_data_symbols = 1;
 274                 break;
 275         case DP_TRAINING_PATTERN_SEQUENCE_4:
 276                 disable_scrabled_data_symbols = 0;
 277                 break;
 278         default:
 279                 ASSERT(0);
 280                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 281                         __func__, pattern);
 282                 break;
 283         }
 284         return disable_scrabled_data_symbols;
 285 }
 286
 287 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 288 {
 289         return (link->lttpr_non_transparent_mode && offset != 0);
 290 }
 291
 292 static void dpcd_set_lt_pattern_and_lane_settings(
 293         struct dc_link *link,
 294         const struct link_training_settings *lt_settings,
 295         enum dc_dp_training_pattern pattern,
 296         uint32_t offset)
 297 {
 298         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 299
 300         uint32_t dpcd_base_lt_offset;
 301
 302         uint8_t dpcd_lt_buffer[5] = {0};
 303         union dpcd_training_pattern dpcd_pattern = { {0} };
 304         uint32_t lane;
 305         uint32_t size_in_bytes;
 306         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 307         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 308
 309         if (is_repeater(link, offset))
 310                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 311                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 312
 313         /*****************************************************************
 314         * DpcdAddress_TrainingPatternSet
 315         *****************************************************************/
 316         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 317                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 318
 319         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 320                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 321
 322         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 323                 = dpcd_pattern.raw;
 324
 325         if (is_repeater(link, offset)) {
 326                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 327                         __func__,
 328                         offset,
 329                         dpcd_base_lt_offset,
 330                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 331         } else {
 332                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 333                         __func__,
 334                         dpcd_base_lt_offset,
 335                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 336         }
 337         /*****************************************************************
 338         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 339         *****************************************************************/
 340         for (lane = 0; lane <
 341                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 342
 343                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 344                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 345                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 346                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 347
 348                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 349                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 350                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 351                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 352                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 353                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 354         }
 355
 356         /* concatenate everything into one buffer*/
 357
 358         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 359
 360          // 0x00103 - 0x00102
 361         memmove(
 362                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 363                 dpcd_lane,
 364                 size_in_bytes);
 365
 366         if (is_repeater(link, offset)) {
 367                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 368                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 369                         __func__,
 370                         offset,
 371                         dpcd_base_lt_offset,
 372                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 373                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 374                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 375                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 376         } else {
 377                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 378                         __func__,
 379                         dpcd_base_lt_offset,
 380                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 381                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 382                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 383                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 384         }
 385         if (edp_workaround) {
 386                 /* for eDP write in 2 parts because the 5-byte burst is
 387                 * causing issues on some eDP panels (EPR#366724)
 388                 */
 389                 core_link_write_dpcd(
 390                         link,
 391                         DP_TRAINING_PATTERN_SET,
 392                         &dpcd_pattern.raw,
 393                         sizeof(dpcd_pattern.raw));
 394
 395                 core_link_write_dpcd(
 396                         link,
 397                         DP_TRAINING_LANE0_SET,
 398                         (uint8_t *)(dpcd_lane),
 399                         size_in_bytes);
 400
 401                 } else
 402                 /* write it all in (1 + number-of-lanes)-byte burst*/
 403                         core_link_write_dpcd(
 404                                 link,
 405                                 dpcd_base_lt_offset,
 406                                 dpcd_lt_buffer,
 407                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 408
 409         link->cur_lane_setting = lt_settings->lane_settings[0];
 410 }
 411
 412 static bool is_cr_done(enum dc_lane_count ln_count,
 413         union lane_status *dpcd_lane_status)
 414 {
 415         uint32_t lane;
 416         /*LANEx_CR_DONE bits All 1's?*/
 417         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 418                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 419                         return false;
 420         }
 421         return true;
 422 }
 423
 424 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 425         union lane_status *dpcd_lane_status,
 426         union lane_align_status_updated *lane_status_updated)
 427 {
 428         uint32_t lane;
 429         if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
 430                 return false;
 431         else {
 432                 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 433                         if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
 434                                 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 435                                 return false;
 436                 }
 437         }
 438         return true;
 439 }
 440
 441 static void update_drive_settings(
 442                 struct link_training_settings *dest,
 443                 struct link_training_settings src)
 444 {
 445         uint32_t lane;
 446         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 447                 if (dest->voltage_swing == NULL)
 448                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 449                 else
 450                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 451
 452                 if (dest->pre_emphasis == NULL)
 453                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 454                 else
 455                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 456
 457                 if (dest->post_cursor2 == NULL)
 458                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 459                 else
 460                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 461         }
 462 }
 463
 464 static uint8_t get_nibble_at_index(const uint8_t *buf,
 465         uint32_t index)
 466 {
 467         uint8_t nibble;
 468         nibble = buf[index / 2];
 469
 470         if (index % 2)
 471                 nibble >>= 4;
 472         else
 473                 nibble &= 0x0F;
 474
 475         return nibble;
 476 }
 477
 478 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 479         enum dc_voltage_swing voltage)
 480 {
 481         enum dc_pre_emphasis pre_emphasis;
 482         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 483
 484         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 485                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 486
 487         return pre_emphasis;
 488
 489 }
 490
 491 static void find_max_drive_settings(
 492         const struct link_training_settings *link_training_setting,
 493         struct link_training_settings *max_lt_setting)
 494 {
 495         uint32_t lane;
 496         struct dc_lane_settings max_requested;
 497
 498         max_requested.VOLTAGE_SWING =
 499                 link_training_setting->
 500                 lane_settings[0].VOLTAGE_SWING;
 501         max_requested.PRE_EMPHASIS =
 502                 link_training_setting->
 503                 lane_settings[0].PRE_EMPHASIS;
 504         /*max_requested.postCursor2 =
 505          * link_training_setting->laneSettings[0].postCursor2;*/
 506
 507         /* Determine what the maximum of the requested settings are*/
 508         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 509                         lane++) {
 510                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 511                         max_requested.VOLTAGE_SWING)
 512
 513                         max_requested.VOLTAGE_SWING =
 514                         link_training_setting->
 515                         lane_settings[lane].VOLTAGE_SWING;
 516
 517                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 518                                 max_requested.PRE_EMPHASIS)
 519                         max_requested.PRE_EMPHASIS =
 520                         link_training_setting->
 521                         lane_settings[lane].PRE_EMPHASIS;
 522
 523                 /*
 524                 if (link_training_setting->laneSettings[lane].postCursor2 >
 525                  max_requested.postCursor2)
 526                 {
 527                 max_requested.postCursor2 =
 528                 link_training_setting->laneSettings[lane].postCursor2;
 529                 }
 530                 */
 531         }
 532
 533         /* make sure the requested settings are
 534          * not higher than maximum settings*/
 535         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 536                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 537
 538         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 539                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 540         /*
 541         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 542         max_requested.postCursor2 = PostCursor2_MaxLevel;
 543         */
 544
 545         /* make sure the pre-emphasis matches the voltage swing*/
 546         if (max_requested.PRE_EMPHASIS >
 547                 get_max_pre_emphasis_for_voltage_swing(
 548                         max_requested.VOLTAGE_SWING))
 549                 max_requested.PRE_EMPHASIS =
 550                 get_max_pre_emphasis_for_voltage_swing(
 551                         max_requested.VOLTAGE_SWING);
 552
 553         /*
 554          * Post Cursor2 levels are completely independent from
 555          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 556          * can only be applied to each allowable combination of voltage
 557          * swing and pre-emphasis levels */
 558          /* if ( max_requested.postCursor2 >
 559           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 560           *  max_requested.postCursor2 =
 561           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 562           */
 563
 564         max_lt_setting->link_settings.link_rate =
 565                 link_training_setting->link_settings.link_rate;
 566         max_lt_setting->link_settings.lane_count =
 567         link_training_setting->link_settings.lane_count;
 568         max_lt_setting->link_settings.link_spread =
 569                 link_training_setting->link_settings.link_spread;
 570
 571         for (lane = 0; lane <
 572                 link_training_setting->link_settings.lane_count;
 573                 lane++) {
 574                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 575                         max_requested.VOLTAGE_SWING;
 576                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 577                         max_requested.PRE_EMPHASIS;
 578                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 579                  * max_requested.postCursor2;
 580                  */
 581         }
 582
 583 }
 584
 585 static void get_lane_status_and_drive_settings(
 586         struct dc_link *link,
 587         const struct link_training_settings *link_training_setting,
 588         union lane_status *ln_status,
 589         union lane_align_status_updated *ln_status_updated,
 590         struct link_training_settings *req_settings,
 591         uint32_t offset)
 592 {
 593         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 594         uint8_t lane_adjust_offset = 4;
 595         unsigned int lane01_adjust_address;
 596         uint8_t dpcd_buf[6] = {0};
 597         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 598         struct link_training_settings request_settings = { {0} };
 599         uint32_t lane;
 600
 601         memset(req_settings, '\0', sizeof(struct link_training_settings));
 602
 603         if (is_repeater(link, offset)) {
 604                 lane01_status_address =
 605                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 606                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 607                 lane_adjust_offset = 3;
 608         }
 609
 610         core_link_read_dpcd(
 611                 link,
 612                 lane01_status_address,
 613                 (uint8_t *)(dpcd_buf),
 614                 sizeof(dpcd_buf));
 615
 616         for (lane = 0; lane <
 617                 (uint32_t)(link_training_setting->link_settings.lane_count);
 618                 lane++) {
 619
 620                 ln_status[lane].raw =
 621                         get_nibble_at_index(&dpcd_buf[0], lane);
 622                 dpcd_lane_adjust[lane].raw =
 623                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 624         }
 625
 626         ln_status_updated->raw = dpcd_buf[2];
 627
 628         if (is_repeater(link, offset)) {
 629                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 630                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 631                         __func__,
 632                         offset,
 633                         lane01_status_address, dpcd_buf[0],
 634                         lane01_status_address + 1, dpcd_buf[1]);
 635         } else {
 636                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 637                         __func__,
 638                         lane01_status_address, dpcd_buf[0],
 639                         lane01_status_address + 1, dpcd_buf[1]);
 640         }
 641         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 642
 643         if (is_repeater(link, offset))
 644                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 645                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 646
 647         if (is_repeater(link, offset)) {
 648                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 649                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 650                                         __func__,
 651                                         offset,
 652                                         lane01_adjust_address,
 653                                         dpcd_buf[lane_adjust_offset],
 654                                         lane01_adjust_address + 1,
 655                                         dpcd_buf[lane_adjust_offset + 1]);
 656         } else {
 657                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 658                         __func__,
 659                         lane01_adjust_address,
 660                         dpcd_buf[lane_adjust_offset],
 661                         lane01_adjust_address + 1,
 662                         dpcd_buf[lane_adjust_offset + 1]);
 663         }
 664
 665         /*copy to req_settings*/
 666         request_settings.link_settings.lane_count =
 667                 link_training_setting->link_settings.lane_count;
 668         request_settings.link_settings.link_rate =
 669                 link_training_setting->link_settings.link_rate;
 670         request_settings.link_settings.link_spread =
 671                 link_training_setting->link_settings.link_spread;
 672
 673         for (lane = 0; lane <
 674                 (uint32_t)(link_training_setting->link_settings.lane_count);
 675                 lane++) {
 676
 677                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 678                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 679                                 VOLTAGE_SWING_LANE);
 680                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 681                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 682                                 PRE_EMPHASIS_LANE);
 683         }
 684
 685         /*Note: for postcursor2, read adjusted
 686          * postcursor2 settings from*/
 687         /*DpcdAddress_AdjustRequestPostCursor2 =
 688          *0x020C (not implemented yet)*/
 689
 690         /* we find the maximum of the requested settings across all lanes*/
 691         /* and set this maximum for all lanes*/
 692         find_max_drive_settings(&request_settings, req_settings);
 693
 694         /* if post cursor 2 is needed in the future,
 695          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 696          */
 697
 698 }
 699
 700 static void dpcd_set_lane_settings(
 701         struct dc_link *link,
 702         const struct link_training_settings *link_training_setting,
 703         uint32_t offset)
 704 {
 705         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 706         uint32_t lane;
 707         unsigned int lane0_set_address;
 708
 709         lane0_set_address = DP_TRAINING_LANE0_SET;
 710
 711         if (is_repeater(link, offset))
 712                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 713                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 714
 715         for (lane = 0; lane <
 716                 (uint32_t)(link_training_setting->
 717                 link_settings.lane_count);
 718                 lane++) {
 719                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 720                         (uint8_t)(link_training_setting->
 721                         lane_settings[lane].VOLTAGE_SWING);
 722                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 723                         (uint8_t)(link_training_setting->
 724                         lane_settings[lane].PRE_EMPHASIS);
 725                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 726                         (link_training_setting->
 727                         lane_settings[lane].VOLTAGE_SWING ==
 728                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 729                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 730                         (link_training_setting->
 731                         lane_settings[lane].PRE_EMPHASIS ==
 732                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 733         }
 734
 735         core_link_write_dpcd(link,
 736                 lane0_set_address,
 737                 (uint8_t *)(dpcd_lane),
 738                 link_training_setting->link_settings.lane_count);
 739
 740         /*
 741         if (LTSettings.link.rate == LinkRate_High2)
 742         {
 743                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 744                 for ( uint32_t lane = 0;
 745                 lane < lane_count_DPMax; lane++)
 746                 {
 747                         dpcd_lane2[lane].bits.post_cursor2_set =
 748                         static_cast<unsigned char>(
 749                         LTSettings.laneSettings[lane].postCursor2);
 750                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 751                 }
 752                 m_pDpcdAccessSrv->WriteDpcdData(
 753                 DpcdAddress_Lane0Set2,
 754                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 755                 LTSettings.link.lanes);
 756         }
 757         */
 758
 759         if (is_repeater(link, offset)) {
 760                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 761                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 762                         __func__,
 763                         offset,
 764                         lane0_set_address,
 765                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 766                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 767                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 768                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 769
 770         } else {
 771                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 772                         __func__,
 773                         lane0_set_address,
 774                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 775                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 776                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 777                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 778         }
 779         link->cur_lane_setting = link_training_setting->lane_settings[0];
 780
 781 }
 782
 783 static bool is_max_vs_reached(
 784         const struct link_training_settings *lt_settings)
 785 {
 786         uint32_t lane;
 787         for (lane = 0; lane <
 788                 (uint32_t)(lt_settings->link_settings.lane_count);
 789                 lane++) {
 790                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 791                         == VOLTAGE_SWING_MAX_LEVEL)
 792                         return true;
 793         }
 794         return false;
 795
 796 }
 797
 798 static bool perform_post_lt_adj_req_sequence(
 799         struct dc_link *link,
 800         struct link_training_settings *lt_settings)
 801 {
 802         enum dc_lane_count lane_count =
 803         lt_settings->link_settings.lane_count;
 804
 805         uint32_t adj_req_count;
 806         uint32_t adj_req_timer;
 807         bool req_drv_setting_changed;
 808         uint32_t lane;
 809
 810         req_drv_setting_changed = false;
 811         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 812         adj_req_count++) {
 813
 814                 req_drv_setting_changed = false;
 815
 816                 for (adj_req_timer = 0;
 817                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 818                         adj_req_timer++) {
 819
 820                         struct link_training_settings req_settings;
 821                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 822                         union lane_align_status_updated
 823                                 dpcd_lane_status_updated;
 824
 825                         get_lane_status_and_drive_settings(
 826                         link,
 827                         lt_settings,
 828                         dpcd_lane_status,
 829                         &dpcd_lane_status_updated,
 830                         &req_settings,
 831                         DPRX);
 832
 833                         if (dpcd_lane_status_updated.bits.
 834                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 835                                 return true;
 836
 837                         if (!is_cr_done(lane_count, dpcd_lane_status))
 838                                 return false;
 839
 840                         if (!is_ch_eq_done(
 841                                 lane_count,
 842                                 dpcd_lane_status,
 843                                 &dpcd_lane_status_updated))
 844                                 return false;
 845
 846                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 847
 848                                 if (lt_settings->
 849                                 lane_settings[lane].VOLTAGE_SWING !=
 850                                 req_settings.lane_settings[lane].
 851                                 VOLTAGE_SWING ||
 852                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 853                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 854
 855                                         req_drv_setting_changed = true;
 856                                         break;
 857                                 }
 858                         }
 859
 860                         if (req_drv_setting_changed) {
 861                                 update_drive_settings(
 862                                         lt_settings, req_settings);
 863
 864                                 dc_link_dp_set_drive_settings(link,
 865                                                 lt_settings);
 866                                 break;
 867                         }
 868
 869                         msleep(1);
 870                 }
 871
 872                 if (!req_drv_setting_changed) {
 873                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 874                                 __func__);
 875
 876                         ASSERT(0);
 877                         return true;
 878                 }
 879         }
 880         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 881                 __func__);
 882
 883         ASSERT(0);
 884         return true;
 885
 886 }
 887
 888 /* Only used for channel equalization */
 889 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 890 {
 891         unsigned int aux_rd_interval_us = 400;
 892
 893         switch (dpcd_aux_read_interval) {
 894         case 0x01:
 895                 aux_rd_interval_us = 400;
 896                 break;
 897         case 0x02:
 898                 aux_rd_interval_us = 4000;
 899                 break;
 900         case 0x03:
 901                 aux_rd_interval_us = 8000;
 902                 break;
 903         case 0x04:
 904                 aux_rd_interval_us = 16000;
 905                 break;
 906         default:
 907                 break;
 908         }
 909
 910         return aux_rd_interval_us;
 911 }
 912
 913 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 914                                         union lane_status *dpcd_lane_status)
 915 {
 916         enum link_training_result result = LINK_TRAINING_SUCCESS;
 917
 918         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 919                 result = LINK_TRAINING_CR_FAIL_LANE0;
 920         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 921                 result = LINK_TRAINING_CR_FAIL_LANE1;
 922         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 923                 result = LINK_TRAINING_CR_FAIL_LANE23;
 924         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 925                 result = LINK_TRAINING_CR_FAIL_LANE23;
 926         return result;
 927 }
 928
 929 static enum link_training_result perform_channel_equalization_sequence(
 930         struct dc_link *link,
 931         struct link_training_settings *lt_settings,
 932         uint32_t offset)
 933 {
 934         struct link_training_settings req_settings;
 935         enum dc_dp_training_pattern tr_pattern;
 936         uint32_t retries_ch_eq;
 937         uint32_t wait_time_microsec;
 938         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 939         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 940         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 941
 942         /* Note: also check that TPS4 is a supported feature*/
 943
 944         tr_pattern = lt_settings->pattern_for_eq;
 945
 946         if (is_repeater(link, offset))
 947                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 948
 949         dp_set_hw_training_pattern(link, tr_pattern, offset);
 950
 951         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 952                 retries_ch_eq++) {
 953
 954                 dp_set_hw_lane_settings(link, lt_settings, offset);
 955
 956                 /* 2. update DPCD*/
 957                 if (!retries_ch_eq)
 958                         /* EPR #361076 - write as a 5-byte burst,
 959                          * but only for the 1-st iteration
 960                          */
 961
 962                         dpcd_set_lt_pattern_and_lane_settings(
 963                                 link,
 964                                 lt_settings,
 965                                 tr_pattern, offset);
 966                 else
 967                         dpcd_set_lane_settings(link, lt_settings, offset);
 968
 969                 /* 3. wait for receiver to lock-on*/
 970                 wait_time_microsec = lt_settings->eq_pattern_time;
 971
 972                 if (is_repeater(link, offset))
 973                         wait_time_microsec =
 974                                         translate_training_aux_read_interval(
 975                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 976
 977                 wait_for_training_aux_rd_interval(
 978                                 link,
 979                                 wait_time_microsec);
 980
 981                 /* 4. Read lane status and requested
 982                  * drive settings as set by the sink*/
 983
 984                 get_lane_status_and_drive_settings(
 985                         link,
 986                         lt_settings,
 987                         dpcd_lane_status,
 988                         &dpcd_lane_status_updated,
 989                         &req_settings,
 990                         offset);
 991
 992                 /* 5. check CR done*/
 993                 if (!is_cr_done(lane_count, dpcd_lane_status))
 994                         return LINK_TRAINING_EQ_FAIL_CR;
 995
 996                 /* 6. check CHEQ done*/
 997                 if (is_ch_eq_done(lane_count,
 998                         dpcd_lane_status,
 999                         &dpcd_lane_status_updated))
1000                         return LINK_TRAINING_SUCCESS;
1001
1002                 /* 7. update VS/PE/PC2 in lt_settings*/
1003                 update_drive_settings(lt_settings, req_settings);
1004         }
1005
1006         return LINK_TRAINING_EQ_FAIL_EQ;
1007
1008 }
1009 #define TRAINING_AUX_RD_INTERVAL 100 //us
1010
1011 static void start_clock_recovery_pattern_early(struct dc_link *link,
1012                 struct link_training_settings *lt_settings,
1013                 uint32_t offset)
1014 {
1015         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1016                         __func__);
1017         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1018         dp_set_hw_lane_settings(link, lt_settings, offset);
1019         udelay(400);
1020 }
1021
1022 static enum link_training_result perform_clock_recovery_sequence(
1023         struct dc_link *link,
1024         struct link_training_settings *lt_settings,
1025         uint32_t offset)
1026 {
1027         uint32_t retries_cr;
1028         uint32_t retry_count;
1029         uint32_t wait_time_microsec;
1030         struct link_training_settings req_settings;
1031         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1032         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1033         union lane_align_status_updated dpcd_lane_status_updated;
1034
1035         retries_cr = 0;
1036         retry_count = 0;
1037
1038         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1039                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1040
1041         /* najeeb - The synaptics MST hub can put the LT in
1042         * infinite loop by switching the VS
1043         */
1044         /* between level 0 and level 1 continuously, here
1045         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1046         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1047                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1048
1049                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1050                 memset(&dpcd_lane_status_updated, '\0',
1051                 sizeof(dpcd_lane_status_updated));
1052
1053                 /* 1. call HWSS to set lane settings*/
1054                 dp_set_hw_lane_settings(
1055                                 link,
1056                                 lt_settings,
1057                                 offset);
1058
1059                 /* 2. update DPCD of the receiver*/
1060                 if (!retry_count)
1061                         /* EPR #361076 - write as a 5-byte burst,
1062                          * but only for the 1-st iteration.*/
1063                         dpcd_set_lt_pattern_and_lane_settings(
1064                                         link,
1065                                         lt_settings,
1066                                         lt_settings->pattern_for_cr,
1067                                         offset);
1068                 else
1069                         dpcd_set_lane_settings(
1070                                         link,
1071                                         lt_settings,
1072                                         offset);
1073
1074                 /* 3. wait receiver to lock-on*/
1075                 wait_time_microsec = lt_settings->cr_pattern_time;
1076
1077                 if (link->lttpr_non_transparent_mode)
1078                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1079
1080                 wait_for_training_aux_rd_interval(
1081                                 link,
1082                                 wait_time_microsec);
1083
1084                 /* 4. Read lane status and requested drive
1085                 * settings as set by the sink
1086                 */
1087                 get_lane_status_and_drive_settings(
1088                                 link,
1089                                 lt_settings,
1090                                 dpcd_lane_status,
1091                                 &dpcd_lane_status_updated,
1092                                 &req_settings,
1093                                 offset);
1094
1095                 /* 5. check CR done*/
1096                 if (is_cr_done(lane_count, dpcd_lane_status))
1097                         return LINK_TRAINING_SUCCESS;
1098
1099                 /* 6. max VS reached*/
1100                 if (is_max_vs_reached(lt_settings))
1101                         break;
1102
1103                 /* 7. same voltage*/
1104                 /* Note: VS same for all lanes,
1105                 * so comparing first lane is sufficient*/
1106                 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
1107                         req_settings.lane_settings[0].VOLTAGE_SWING)
1108                         retries_cr++;
1109                 else
1110                         retries_cr = 0;
1111
1112                 /* 8. update VS/PE/PC2 in lt_settings*/
1113                 update_drive_settings(lt_settings, req_settings);
1114
1115                 retry_count++;
1116         }
1117
1118         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1119                 ASSERT(0);
1120                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1121                         __func__,
1122                         LINK_TRAINING_MAX_CR_RETRY);
1123
1124         }
1125
1126         return get_cr_failure(lane_count, dpcd_lane_status);
1127 }
1128
1129 static inline enum link_training_result perform_link_training_int(
1130         struct dc_link *link,
1131         struct link_training_settings *lt_settings,
1132         enum link_training_result status)
1133 {
1134         union lane_count_set lane_count_set = { {0} };
1135         union dpcd_training_pattern dpcd_pattern = { {0} };
1136
1137         /* 3. set training not in progress*/
1138         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1139         dpcd_set_training_pattern(link, dpcd_pattern);
1140
1141         /* 4. mainlink output idle pattern*/
1142         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1143
1144         /*
1145          * 5. post training adjust if required
1146          * If the upstream DPTX and downstream DPRX both support TPS4,
1147          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1148          */
1149         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1150                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
1151                 return status;
1152
1153         if (status == LINK_TRAINING_SUCCESS &&
1154                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1155                 status = LINK_TRAINING_LQA_FAIL;
1156
1157         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1158         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1159         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1160
1161         core_link_write_dpcd(
1162                 link,
1163                 DP_LANE_COUNT_SET,
1164                 &lane_count_set.raw,
1165                 sizeof(lane_count_set));
1166
1167         return status;
1168 }
1169
1170 static enum link_training_result check_link_loss_status(
1171         struct dc_link *link,
1172         const struct link_training_settings *link_training_setting)
1173 {
1174         enum link_training_result status = LINK_TRAINING_SUCCESS;
1175         union lane_status lane_status;
1176         uint8_t dpcd_buf[6] = {0};
1177         uint32_t lane;
1178
1179         core_link_read_dpcd(
1180                         link,
1181                         DP_SINK_COUNT,
1182                         (uint8_t *)(dpcd_buf),
1183                         sizeof(dpcd_buf));
1184
1185         /*parse lane status*/
1186         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1187                 /*
1188                  * check lanes status
1189                  */
1190                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1191
1192                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1193                         !lane_status.bits.CR_DONE_0 ||
1194                         !lane_status.bits.SYMBOL_LOCKED_0) {
1195                         /* if one of the channel equalization, clock
1196                          * recovery or symbol lock is dropped
1197                          * consider it as (link has been
1198                          * dropped) dp sink status has changed
1199                          */
1200                         status = LINK_TRAINING_LINK_LOSS;
1201                         break;
1202                 }
1203         }
1204
1205         return status;
1206 }
1207
1208 static void initialize_training_settings(
1209          struct dc_link *link,
1210         const struct dc_link_settings *link_setting,
1211         const struct dc_link_training_overrides *overrides,
1212         struct link_training_settings *lt_settings)
1213 {
1214         uint32_t lane;
1215
1216         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1217
1218         /* Initialize link settings */
1219         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1220         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1221
1222         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1223                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1224         else
1225                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1226
1227         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1228                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1229         else
1230                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1231
1232         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1233
1234         /* TODO hard coded to SS for now
1235          * lt_settings.link_settings.link_spread =
1236          * dal_display_path_is_ss_supported(
1237          * path_mode->display_path) ?
1238          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1239          * LINK_SPREAD_DISABLED;
1240          */
1241         /* Initialize link spread */
1242         if (link->dp_ss_off)
1243                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1244         else if (overrides->downspread != NULL)
1245                 lt_settings->link_settings.link_spread
1246                         = *overrides->downspread
1247                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1248                         : LINK_SPREAD_DISABLED;
1249         else
1250                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1251
1252         /* Initialize lane settings overrides */
1253         if (overrides->voltage_swing != NULL)
1254                 lt_settings->voltage_swing = overrides->voltage_swing;
1255
1256         if (overrides->pre_emphasis != NULL)
1257                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1258
1259         if (overrides->post_cursor2 != NULL)
1260                 lt_settings->post_cursor2 = overrides->post_cursor2;
1261
1262         /* Initialize lane settings (VS/PE/PC2) */
1263         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1264                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1265                         lt_settings->voltage_swing != NULL ?
1266                         *lt_settings->voltage_swing :
1267                         VOLTAGE_SWING_LEVEL0;
1268                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1269                         lt_settings->pre_emphasis != NULL ?
1270                         *lt_settings->pre_emphasis
1271                         : PRE_EMPHASIS_DISABLED;
1272                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1273                         lt_settings->post_cursor2 != NULL ?
1274                         *lt_settings->post_cursor2
1275                         : POST_CURSOR2_DISABLED;
1276         }
1277
1278         /* Initialize training timings */
1279         if (overrides->cr_pattern_time != NULL)
1280                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1281         else
1282                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1283
1284         if (overrides->eq_pattern_time != NULL)
1285                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1286         else
1287                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1288
1289         if (overrides->pattern_for_cr != NULL)
1290                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1291         else
1292                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1293         if (overrides->pattern_for_eq != NULL)
1294                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1295         else
1296                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1297
1298         if (overrides->enhanced_framing != NULL)
1299                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1300         else
1301                 lt_settings->enhanced_framing = 1;
1302 }
1303
1304 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1305 {
1306         switch (lttpr_repeater_count) {
1307         case 0x80: // 1 lttpr repeater
1308                 return 1;
1309         case 0x40: // 2 lttpr repeaters
1310                 return 2;
1311         case 0x20: // 3 lttpr repeaters
1312                 return 3;
1313         case 0x10: // 4 lttpr repeaters
1314                 return 4;
1315         case 0x08: // 5 lttpr repeaters
1316                 return 5;
1317         case 0x04: // 6 lttpr repeaters
1318                 return 6;
1319         case 0x02: // 7 lttpr repeaters
1320                 return 7;
1321         case 0x01: // 8 lttpr repeaters
1322                 return 8;
1323         default:
1324                 break;
1325         }
1326         return 0; // invalid value
1327 }
1328
1329 static void configure_lttpr_mode(struct dc_link *link)
1330 {
1331         /* aux timeout is already set to extended */
1332         /* RESET/SET lttpr mode to enable non transparent mode */
1333         uint8_t repeater_cnt;
1334         uint32_t aux_interval_address;
1335         uint8_t repeater_id;
1336         enum dc_status result = DC_ERROR_UNEXPECTED;
1337         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1338
1339         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1340         result = core_link_write_dpcd(link,
1341                         DP_PHY_REPEATER_MODE,
1342                         (uint8_t *)&repeater_mode,
1343                         sizeof(repeater_mode));
1344
1345         if (result == DC_OK) {
1346                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1347         }
1348
1349         if (link->lttpr_non_transparent_mode) {
1350
1351                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1352
1353                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1354                 result = core_link_write_dpcd(link,
1355                                 DP_PHY_REPEATER_MODE,
1356                                 (uint8_t *)&repeater_mode,
1357                                 sizeof(repeater_mode));
1358
1359                 if (result == DC_OK) {
1360                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1361                 }
1362
1363                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1364                 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1365                         aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1366                                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1367                         core_link_read_dpcd(
1368                                 link,
1369                                 aux_interval_address,
1370                                 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1371                                 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1372                         link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1373                 }
1374         }
1375 }
1376
1377 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1378 {
1379         union dpcd_training_pattern dpcd_pattern = { {0} };
1380
1381         const uint32_t dpcd_base_lt_offset =
1382                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1383                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1384         /* Set training not in progress*/
1385         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1386
1387         core_link_write_dpcd(
1388                 link,
1389                 dpcd_base_lt_offset,
1390                 &dpcd_pattern.raw,
1391                 1);
1392
1393         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1394                 __func__,
1395                 offset,
1396                 dpcd_base_lt_offset,
1397                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1398 }
1399
1400 static void print_status_message(
1401         struct dc_link *link,
1402         const struct link_training_settings *lt_settings,
1403         enum link_training_result status)
1404 {
1405         char *link_rate = "Unknown";
1406         char *lt_result = "Unknown";
1407         char *lt_spread = "Disabled";
1408
1409         switch (lt_settings->link_settings.link_rate) {
1410         case LINK_RATE_LOW:
1411                 link_rate = "RBR";
1412                 break;
1413         case LINK_RATE_RATE_2:
1414                 link_rate = "R2";
1415                 break;
1416         case LINK_RATE_RATE_3:
1417                 link_rate = "R3";
1418                 break;
1419         case LINK_RATE_HIGH:
1420                 link_rate = "HBR";
1421                 break;
1422         case LINK_RATE_RBR2:
1423                 link_rate = "RBR2";
1424                 break;
1425         case LINK_RATE_RATE_6:
1426                 link_rate = "R6";
1427                 break;
1428         case LINK_RATE_HIGH2:
1429                 link_rate = "HBR2";
1430                 break;
1431         case LINK_RATE_HIGH3:
1432                 link_rate = "HBR3";
1433                 break;
1434         default:
1435                 break;
1436         }
1437
1438         switch (status) {
1439         case LINK_TRAINING_SUCCESS:
1440                 lt_result = "pass";
1441                 break;
1442         case LINK_TRAINING_CR_FAIL_LANE0:
1443                 lt_result = "CR failed lane0";
1444                 break;
1445         case LINK_TRAINING_CR_FAIL_LANE1:
1446                 lt_result = "CR failed lane1";
1447                 break;
1448         case LINK_TRAINING_CR_FAIL_LANE23:
1449                 lt_result = "CR failed lane23";
1450                 break;
1451         case LINK_TRAINING_EQ_FAIL_CR:
1452                 lt_result = "CR failed in EQ";
1453                 break;
1454         case LINK_TRAINING_EQ_FAIL_EQ:
1455                 lt_result = "EQ failed";
1456                 break;
1457         case LINK_TRAINING_LQA_FAIL:
1458                 lt_result = "LQA failed";
1459                 break;
1460         case LINK_TRAINING_LINK_LOSS:
1461                 lt_result = "Link loss";
1462                 break;
1463         default:
1464                 break;
1465         }
1466
1467         switch (lt_settings->link_settings.link_spread) {
1468         case LINK_SPREAD_DISABLED:
1469                 lt_spread = "Disabled";
1470                 break;
1471         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1472                 lt_spread = "0.5% 30KHz";
1473                 break;
1474         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1475                 lt_spread = "0.5% 33KHz";
1476                 break;
1477         default:
1478                 break;
1479         }
1480
1481         /* Connectivity log: link training */
1482         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1483                                 link_rate,
1484                                 lt_settings->link_settings.lane_count,
1485                                 lt_result,
1486                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1487                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1488                                 lt_spread);
1489 }
1490
1491 void dc_link_dp_set_drive_settings(
1492         struct dc_link *link,
1493         struct link_training_settings *lt_settings)
1494 {
1495         /* program ASIC PHY settings*/
1496         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1497
1498         /* Notify DP sink the PHY settings from source */
1499         dpcd_set_lane_settings(link, lt_settings, DPRX);
1500 }
1501
1502 bool dc_link_dp_perform_link_training_skip_aux(
1503         struct dc_link *link,
1504         const struct dc_link_settings *link_setting)
1505 {
1506         struct link_training_settings lt_settings;
1507
1508         initialize_training_settings(
1509                         link,
1510                         link_setting,
1511                         &link->preferred_training_settings,
1512                         &lt_settings);
1513
1514         /* 1. Perform_clock_recovery_sequence. */
1515
1516         /* transmit training pattern for clock recovery */
1517         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1518
1519         /* call HWSS to set lane settings*/
1520         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1521
1522         /* wait receiver to lock-on*/
1523         wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1524
1525         /* 2. Perform_channel_equalization_sequence. */
1526
1527         /* transmit training pattern for channel equalization. */
1528         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1529
1530         /* call HWSS to set lane settings*/
1531         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1532
1533         /* wait receiver to lock-on. */
1534         wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1535
1536         /* 3. Perform_link_training_int. */
1537
1538         /* Mainlink output idle pattern. */
1539         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1540
1541         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1542
1543         return true;
1544 }
1545
1546 enum link_training_result dc_link_dp_perform_link_training(
1547         struct dc_link *link,
1548         const struct dc_link_settings *link_setting,
1549         bool skip_video_pattern)
1550 {
1551         enum link_training_result status = LINK_TRAINING_SUCCESS;
1552         struct link_training_settings lt_settings;
1553
1554         bool fec_enable;
1555         uint8_t repeater_cnt;
1556         uint8_t repeater_id;
1557
1558         initialize_training_settings(
1559                         link,
1560                         link_setting,
1561                         &link->preferred_training_settings,
1562                         &lt_settings);
1563
1564         /* Configure lttpr mode */
1565         if (link->lttpr_non_transparent_mode)
1566                 configure_lttpr_mode(link);
1567
1568         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1569                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1570
1571         /* 1. set link rate, lane count and spread. */
1572         dpcd_set_link_settings(link, &lt_settings);
1573
1574         if (link->preferred_training_settings.fec_enable != NULL)
1575                 fec_enable = *link->preferred_training_settings.fec_enable;
1576         else
1577                 fec_enable = true;
1578
1579         dp_set_fec_ready(link, fec_enable);
1580
1581         if (link->lttpr_non_transparent_mode) {
1582
1583                 /* 2. perform link training (set link training done
1584                  *  to false is done as well)
1585                  */
1586                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1587
1588                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1589                                 repeater_id--) {
1590                         status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1591
1592                         if (status != LINK_TRAINING_SUCCESS)
1593                                 break;
1594
1595                         status = perform_channel_equalization_sequence(link,
1596                                         &lt_settings,
1597                                         repeater_id);
1598
1599                         if (status != LINK_TRAINING_SUCCESS)
1600                                 break;
1601
1602                         repeater_training_done(link, repeater_id);
1603                 }
1604         }
1605
1606         if (status == LINK_TRAINING_SUCCESS) {
1607                 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1608         if (status == LINK_TRAINING_SUCCESS) {
1609                 status = perform_channel_equalization_sequence(link,
1610                                         &lt_settings,
1611                                         DPRX);
1612                 }
1613         }
1614
1615         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1616                 status = perform_link_training_int(link,
1617                                 &lt_settings,
1618                                 status);
1619         }
1620
1621         /* delay 5ms after Main Link output idle pattern and then check
1622          * DPCD 0202h.
1623          */
1624         if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1625                 msleep(5);
1626                 status = check_link_loss_status(link, &lt_settings);
1627         }
1628
1629         /* 6. print status message*/
1630         print_status_message(link, &lt_settings, status);
1631
1632         if (status != LINK_TRAINING_SUCCESS)
1633                 link->ctx->dc->debug_data.ltFailCount++;
1634
1635         return status;
1636 }
1637
1638 bool perform_link_training_with_retries(
1639         const struct dc_link_settings *link_setting,
1640         bool skip_video_pattern,
1641         int attempts,
1642         struct pipe_ctx *pipe_ctx,
1643         enum signal_type signal)
1644 {
1645         uint8_t j;
1646         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1647         struct dc_stream_state *stream = pipe_ctx->stream;
1648         struct dc_link *link = stream->link;
1649         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1650
1651         /* We need to do this before the link training to ensure the idle pattern in SST
1652          * mode will be sent right after the link training
1653          */
1654         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1655                                                         pipe_ctx->stream_res.stream_enc->id, true);
1656
1657         for (j = 0; j < attempts; ++j) {
1658
1659                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1660                         __func__, (unsigned int)j + 1, attempts);
1661
1662                 dp_enable_link_phy(
1663                         link,
1664                         signal,
1665                         pipe_ctx->clock_source->id,
1666                         link_setting);
1667
1668                 if (stream->sink_patches.dppowerup_delay > 0) {
1669                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1670
1671                         msleep(delay_dp_power_up_in_ms);
1672                 }
1673
1674                 dp_set_panel_mode(link, panel_mode);
1675
1676                 if (link->aux_access_disabled) {
1677                         dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1678                         return true;
1679                 } else if (dc_link_dp_perform_link_training(
1680                                 link,
1681                                 link_setting,
1682                                 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1683                         return true;
1684
1685                 /* latest link training still fail, skip delay and keep PHY on
1686                  */
1687                 if (j == (attempts - 1))
1688                         break;
1689
1690                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1691                         __func__, (unsigned int)j + 1, attempts);
1692
1693                 dp_disable_link_phy(link, signal);
1694
1695                 msleep(delay_between_attempts);
1696
1697                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1698         }
1699
1700         return false;
1701 }
1702
1703 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1704 {
1705         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1706         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1707
1708         if (dp_cs != NULL) {
1709                 dp_cs_id = dp_cs->id;
1710         } else {
1711                 /*
1712                  * dp clock source is not initialized for some reason.
1713                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1714                  */
1715                 ASSERT(dp_cs);
1716         }
1717
1718         return dp_cs_id;
1719 }
1720
1721 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1722 {
1723         if (mst_enable == false &&
1724                 link->type == dc_connection_mst_branch) {
1725                 /* Disable MST on link. Use only local sink. */
1726                 dp_disable_link_phy_mst(link, link->connector_signal);
1727
1728                 link->type = dc_connection_single;
1729                 link->local_sink = link->remote_sinks[0];
1730                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1731         } else if (mst_enable == true &&
1732                         link->type == dc_connection_single &&
1733                         link->remote_sinks[0] != NULL) {
1734                 /* Re-enable MST on link. */
1735                 dp_disable_link_phy(link, link->connector_signal);
1736                 dp_enable_mst_on_sink(link, true);
1737
1738                 link->type = dc_connection_mst_branch;
1739                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1740         }
1741 }
1742
1743 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1744 {
1745         /* Begin Sync LT. During this time,
1746          * DPCD:600h must not be powered down.
1747          */
1748         link->sync_lt_in_progress = true;
1749
1750         /*Clear any existing preferred settings.*/
1751         memset(&link->preferred_training_settings, 0,
1752                 sizeof(struct dc_link_training_overrides));
1753         memset(&link->preferred_link_setting, 0,
1754                 sizeof(struct dc_link_settings));
1755
1756         return true;
1757 }
1758
1759 enum link_training_result dc_link_dp_sync_lt_attempt(
1760     struct dc_link *link,
1761     struct dc_link_settings *link_settings,
1762     struct dc_link_training_overrides *lt_overrides)
1763 {
1764         struct link_training_settings lt_settings;
1765         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1766         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1767         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1768         bool fec_enable = false;
1769
1770         initialize_training_settings(
1771                 link,
1772                 link_settings,
1773                 lt_overrides,
1774                 &lt_settings);
1775
1776         /* Setup MST Mode */
1777         if (lt_overrides->mst_enable)
1778                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1779
1780         /* Disable link */
1781         dp_disable_link_phy(link, link->connector_signal);
1782
1783         /* Enable link */
1784         dp_cs_id = get_clock_source_id(link);
1785         dp_enable_link_phy(link, link->connector_signal,
1786                 dp_cs_id, link_settings);
1787
1788         /* Set FEC enable */
1789         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1790         dp_set_fec_ready(link, fec_enable);
1791
1792         if (lt_overrides->alternate_scrambler_reset) {
1793                 if (*lt_overrides->alternate_scrambler_reset)
1794                         panel_mode = DP_PANEL_MODE_EDP;
1795                 else
1796                         panel_mode = DP_PANEL_MODE_DEFAULT;
1797         } else
1798                 panel_mode = dp_get_panel_mode(link);
1799
1800         dp_set_panel_mode(link, panel_mode);
1801
1802         /* Attempt to train with given link training settings */
1803         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1804                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1805
1806         /* Set link rate, lane count and spread. */
1807         dpcd_set_link_settings(link, &lt_settings);
1808
1809         /* 2. perform link training (set link training done
1810          *  to false is done as well)
1811          */
1812         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1813         if (lt_status == LINK_TRAINING_SUCCESS) {
1814                 lt_status = perform_channel_equalization_sequence(link,
1815                                                 &lt_settings,
1816                                                 DPRX);
1817         }
1818
1819         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1820         /* 4. print status message*/
1821         print_status_message(link, &lt_settings, lt_status);
1822
1823         return lt_status;
1824 }
1825
1826 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1827 {
1828         /* If input parameter is set, shut down phy.
1829          * Still shouldn't turn off dp_receiver (DPCD:600h)
1830          */
1831         if (link_down == true) {
1832                 dp_disable_link_phy(link, link->connector_signal);
1833                 dp_set_fec_ready(link, false);
1834         }
1835
1836         link->sync_lt_in_progress = false;
1837         return true;
1838 }
1839
1840 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1841 {
1842         struct dc_link_settings max_link_cap = {0};
1843
1844         /* get max link encoder capability */
1845         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1846
1847         /* Lower link settings based on sink's link cap */
1848         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1849                 max_link_cap.lane_count =
1850                                 link->reported_link_cap.lane_count;
1851         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1852                 max_link_cap.link_rate =
1853                                 link->reported_link_cap.link_rate;
1854         if (link->reported_link_cap.link_spread <
1855                         max_link_cap.link_spread)
1856                 max_link_cap.link_spread =
1857                                 link->reported_link_cap.link_spread;
1858         /*
1859          * account for lttpr repeaters cap
1860          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1861          */
1862         if (link->lttpr_non_transparent_mode) {
1863                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1864                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1865
1866                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1867                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1868
1869                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
1870                                                 __func__,
1871                                                 max_link_cap.lane_count,
1872                                                 max_link_cap.link_rate);
1873         }
1874         return max_link_cap;
1875 }
1876
1877 enum dc_status read_hpd_rx_irq_data(
1878         struct dc_link *link,
1879         union hpd_irq_data *irq_data)
1880 {
1881         static enum dc_status retval;
1882
1883         /* The HW reads 16 bytes from 200h on HPD,
1884          * but if we get an AUX_DEFER, the HW cannot retry
1885          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1886          * fail, so we now explicitly read 6 bytes which is
1887          * the req from the above mentioned test cases.
1888          *
1889          * For DP 1.4 we need to read those from 2002h range.
1890          */
1891         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1892                 retval = core_link_read_dpcd(
1893                         link,
1894                         DP_SINK_COUNT,
1895                         irq_data->raw,
1896                         sizeof(union hpd_irq_data));
1897         else {
1898                 /* Read 14 bytes in a single read and then copy only the required fields.
1899                  * This is more efficient than doing it in two separate AUX reads. */
1900
1901                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1902
1903                 retval = core_link_read_dpcd(
1904                         link,
1905                         DP_SINK_COUNT_ESI,
1906                         tmp,
1907                         sizeof(tmp));
1908
1909                 if (retval != DC_OK)
1910                         return retval;
1911
1912                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1913                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1914                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1915                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1916                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1917                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1918         }
1919
1920         return retval;
1921 }
1922
1923 static bool hpd_rx_irq_check_link_loss_status(
1924         struct dc_link *link,
1925         union hpd_irq_data *hpd_irq_dpcd_data)
1926 {
1927         uint8_t irq_reg_rx_power_state = 0;
1928         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1929         union lane_status lane_status;
1930         uint32_t lane;
1931         bool sink_status_changed;
1932         bool return_code;
1933
1934         sink_status_changed = false;
1935         return_code = false;
1936
1937         if (link->cur_link_settings.lane_count == 0)
1938                 return return_code;
1939
1940         /*1. Check that Link Status changed, before re-training.*/
1941
1942         /*parse lane status*/
1943         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1944                 /* check status of lanes 0,1
1945                  * changed DpcdAddress_Lane01Status (0x202)
1946                  */
1947                 lane_status.raw = get_nibble_at_index(
1948                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1949                         lane);
1950
1951                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1952                         !lane_status.bits.CR_DONE_0 ||
1953                         !lane_status.bits.SYMBOL_LOCKED_0) {
1954                         /* if one of the channel equalization, clock
1955                          * recovery or symbol lock is dropped
1956                          * consider it as (link has been
1957                          * dropped) dp sink status has changed
1958                          */
1959                         sink_status_changed = true;
1960                         break;
1961                 }
1962         }
1963
1964         /* Check interlane align.*/
1965         if (sink_status_changed ||
1966                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1967
1968                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1969
1970                 return_code = true;
1971
1972                 /*2. Check that we can handle interrupt: Not in FS DOS,
1973                  *  Not in "Display Timeout" state, Link is trained.
1974                  */
1975                 dpcd_result = core_link_read_dpcd(link,
1976                         DP_SET_POWER,
1977                         &irq_reg_rx_power_state,
1978                         sizeof(irq_reg_rx_power_state));
1979
1980                 if (dpcd_result != DC_OK) {
1981                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1982                                 __func__);
1983                 } else {
1984                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1985                                 return_code = false;
1986                 }
1987         }
1988
1989         return return_code;
1990 }
1991
1992 bool dp_verify_link_cap(
1993         struct dc_link *link,
1994         struct dc_link_settings *known_limit_link_setting,
1995         int *fail_count)
1996 {
1997         struct dc_link_settings max_link_cap = {0};
1998         struct dc_link_settings cur_link_setting = {0};
1999         struct dc_link_settings *cur = &cur_link_setting;
2000         struct dc_link_settings initial_link_settings = {0};
2001         bool success;
2002         bool skip_link_training;
2003         bool skip_video_pattern;
2004         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2005         enum link_training_result status;
2006         union hpd_irq_data irq_data;
2007
2008         if (link->dc->debug.skip_detection_link_training) {
2009                 link->verified_link_cap = *known_limit_link_setting;
2010                 return true;
2011         }
2012
2013         memset(&irq_data, 0, sizeof(irq_data));
2014         success = false;
2015         skip_link_training = false;
2016
2017         max_link_cap = get_max_link_cap(link);
2018
2019         /* Grant extended timeout request */
2020         if (link->lttpr_non_transparent_mode && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2021                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2022
2023                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2024         }
2025
2026         /* TODO implement override and monitor patch later */
2027
2028         /* try to train the link from high to low to
2029          * find the physical link capability
2030          */
2031         /* disable PHY done possible by BIOS, will be done by driver itself */
2032         dp_disable_link_phy(link, link->connector_signal);
2033
2034         dp_cs_id = get_clock_source_id(link);
2035
2036         /* link training starts with the maximum common settings
2037          * supported by both sink and ASIC.
2038          */
2039         initial_link_settings = get_common_supported_link_settings(
2040                         *known_limit_link_setting,
2041                         max_link_cap);
2042         cur_link_setting = initial_link_settings;
2043
2044         /* Temporary Renoir-specific workaround for SWDEV-215184;
2045          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2046          * so add extra cycle of enabling and disabling the PHY before first link training.
2047          */
2048         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2049                         link->dc->debug.usbc_combo_phy_reset_wa) {
2050                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2051                 dp_disable_link_phy(link, link->connector_signal);
2052         }
2053
2054         do {
2055                 skip_video_pattern = true;
2056
2057                 if (cur->link_rate == LINK_RATE_LOW)
2058                         skip_video_pattern = false;
2059
2060                 dp_enable_link_phy(
2061                                 link,
2062                                 link->connector_signal,
2063                                 dp_cs_id,
2064                                 cur);
2065
2066
2067                 if (skip_link_training)
2068                         success = true;
2069                 else {
2070                         status = dc_link_dp_perform_link_training(
2071                                                         link,
2072                                                         cur,
2073                                                         skip_video_pattern);
2074                         if (status == LINK_TRAINING_SUCCESS)
2075                                 success = true;
2076                         else
2077                                 (*fail_count)++;
2078                 }
2079
2080                 if (success) {
2081                         link->verified_link_cap = *cur;
2082                         udelay(1000);
2083                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2084                                 if (hpd_rx_irq_check_link_loss_status(
2085                                                 link,
2086                                                 &irq_data))
2087                                         (*fail_count)++;
2088                 }
2089                 /* always disable the link before trying another
2090                  * setting or before returning we'll enable it later
2091                  * based on the actual mode we're driving
2092                  */
2093                 dp_disable_link_phy(link, link->connector_signal);
2094         } while (!success && decide_fallback_link_setting(
2095                         initial_link_settings, cur, status));
2096
2097         /* Link Training failed for all Link Settings
2098          *  (Lane Count is still unknown)
2099          */
2100         if (!success) {
2101                 /* If all LT fails for all settings,
2102                  * set verified = failed safe (1 lane low)
2103                  */
2104                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2105                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2106
2107                 link->verified_link_cap.link_spread =
2108                 LINK_SPREAD_DISABLED;
2109         }
2110
2111
2112         return success;
2113 }
2114
2115 bool dp_verify_link_cap_with_retries(
2116         struct dc_link *link,
2117         struct dc_link_settings *known_limit_link_setting,
2118         int attempts)
2119 {
2120         uint8_t i = 0;
2121         bool success = false;
2122
2123         for (i = 0; i < attempts; i++) {
2124                 int fail_count = 0;
2125                 enum dc_connection_type type = dc_connection_none;
2126
2127                 memset(&link->verified_link_cap, 0,
2128                                 sizeof(struct dc_link_settings));
2129                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2130                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2131                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2132                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2133                         break;
2134                 } else if (dp_verify_link_cap(link,
2135                                 &link->reported_link_cap,
2136                                 &fail_count) && fail_count == 0) {
2137                         success = true;
2138                         break;
2139                 }
2140                 msleep(10);
2141         }
2142         return success;
2143 }
2144
2145 bool dp_verify_mst_link_cap(
2146         struct dc_link *link)
2147 {
2148         struct dc_link_settings max_link_cap = {0};
2149
2150         max_link_cap = get_max_link_cap(link);
2151         link->verified_link_cap = get_common_supported_link_settings(
2152                 link->reported_link_cap,
2153                 max_link_cap);
2154
2155         return true;
2156 }
2157
2158 static struct dc_link_settings get_common_supported_link_settings(
2159                 struct dc_link_settings link_setting_a,
2160                 struct dc_link_settings link_setting_b)
2161 {
2162         struct dc_link_settings link_settings = {0};
2163
2164         link_settings.lane_count =
2165                 (link_setting_a.lane_count <=
2166                         link_setting_b.lane_count) ?
2167                         link_setting_a.lane_count :
2168                         link_setting_b.lane_count;
2169         link_settings.link_rate =
2170                 (link_setting_a.link_rate <=
2171                         link_setting_b.link_rate) ?
2172                         link_setting_a.link_rate :
2173                         link_setting_b.link_rate;
2174         link_settings.link_spread = LINK_SPREAD_DISABLED;
2175
2176         /* in DP compliance test, DPR-120 may have
2177          * a random value in its MAX_LINK_BW dpcd field.
2178          * We map it to the maximum supported link rate that
2179          * is smaller than MAX_LINK_BW in this case.
2180          */
2181         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2182                 link_settings.link_rate = LINK_RATE_HIGH3;
2183         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2184                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2185                 link_settings.link_rate = LINK_RATE_HIGH2;
2186         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2187                         && link_settings.link_rate > LINK_RATE_HIGH) {
2188                 link_settings.link_rate = LINK_RATE_HIGH;
2189         } else if (link_settings.link_rate < LINK_RATE_HIGH
2190                         && link_settings.link_rate > LINK_RATE_LOW) {
2191                 link_settings.link_rate = LINK_RATE_LOW;
2192         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2193                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2194         }
2195
2196         return link_settings;
2197 }
2198
2199 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2200 {
2201         return lane_count <= LANE_COUNT_ONE;
2202 }
2203
2204 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2205 {
2206         return link_rate <= LINK_RATE_LOW;
2207 }
2208
2209 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2210 {
2211         switch (lane_count) {
2212         case LANE_COUNT_FOUR:
2213                 return LANE_COUNT_TWO;
2214         case LANE_COUNT_TWO:
2215                 return LANE_COUNT_ONE;
2216         case LANE_COUNT_ONE:
2217                 return LANE_COUNT_UNKNOWN;
2218         default:
2219                 return LANE_COUNT_UNKNOWN;
2220         }
2221 }
2222
2223 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2224 {
2225         switch (link_rate) {
2226         case LINK_RATE_HIGH3:
2227                 return LINK_RATE_HIGH2;
2228         case LINK_RATE_HIGH2:
2229                 return LINK_RATE_HIGH;
2230         case LINK_RATE_HIGH:
2231                 return LINK_RATE_LOW;
2232         case LINK_RATE_LOW:
2233                 return LINK_RATE_UNKNOWN;
2234         default:
2235                 return LINK_RATE_UNKNOWN;
2236         }
2237 }
2238
2239 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2240 {
2241         switch (lane_count) {
2242         case LANE_COUNT_ONE:
2243                 return LANE_COUNT_TWO;
2244         case LANE_COUNT_TWO:
2245                 return LANE_COUNT_FOUR;
2246         default:
2247                 return LANE_COUNT_UNKNOWN;
2248         }
2249 }
2250
2251 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2252 {
2253         switch (link_rate) {
2254         case LINK_RATE_LOW:
2255                 return LINK_RATE_HIGH;
2256         case LINK_RATE_HIGH:
2257                 return LINK_RATE_HIGH2;
2258         case LINK_RATE_HIGH2:
2259                 return LINK_RATE_HIGH3;
2260         default:
2261                 return LINK_RATE_UNKNOWN;
2262         }
2263 }
2264
2265 /*
2266  * function: set link rate and lane count fallback based
2267  * on current link setting and last link training result
2268  * return value:
2269  *                      true - link setting could be set
2270  *                      false - has reached minimum setting
2271  *                                      and no further fallback could be done
2272  */
2273 static bool decide_fallback_link_setting(
2274                 struct dc_link_settings initial_link_settings,
2275                 struct dc_link_settings *current_link_setting,
2276                 enum link_training_result training_result)
2277 {
2278         if (!current_link_setting)
2279                 return false;
2280
2281         switch (training_result) {
2282         case LINK_TRAINING_CR_FAIL_LANE0:
2283         case LINK_TRAINING_CR_FAIL_LANE1:
2284         case LINK_TRAINING_CR_FAIL_LANE23:
2285         case LINK_TRAINING_LQA_FAIL:
2286         {
2287                 if (!reached_minimum_link_rate
2288                                 (current_link_setting->link_rate)) {
2289                         current_link_setting->link_rate =
2290                                 reduce_link_rate(
2291                                         current_link_setting->link_rate);
2292                 } else if (!reached_minimum_lane_count
2293                                 (current_link_setting->lane_count)) {
2294                         current_link_setting->link_rate =
2295                                 initial_link_settings.link_rate;
2296                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2297                                 return false;
2298                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2299                                 current_link_setting->lane_count =
2300                                                 LANE_COUNT_ONE;
2301                         else if (training_result ==
2302                                         LINK_TRAINING_CR_FAIL_LANE23)
2303                                 current_link_setting->lane_count =
2304                                                 LANE_COUNT_TWO;
2305                         else
2306                                 current_link_setting->lane_count =
2307                                         reduce_lane_count(
2308                                         current_link_setting->lane_count);
2309                 } else {
2310                         return false;
2311                 }
2312                 break;
2313         }
2314         case LINK_TRAINING_EQ_FAIL_EQ:
2315         {
2316                 if (!reached_minimum_lane_count
2317                                 (current_link_setting->lane_count)) {
2318                         current_link_setting->lane_count =
2319                                 reduce_lane_count(
2320                                         current_link_setting->lane_count);
2321                 } else if (!reached_minimum_link_rate
2322                                 (current_link_setting->link_rate)) {
2323                         current_link_setting->link_rate =
2324                                 reduce_link_rate(
2325                                         current_link_setting->link_rate);
2326                 } else {
2327                         return false;
2328                 }
2329                 break;
2330         }
2331         case LINK_TRAINING_EQ_FAIL_CR:
2332         {
2333                 if (!reached_minimum_link_rate
2334                                 (current_link_setting->link_rate)) {
2335                         current_link_setting->link_rate =
2336                                 reduce_link_rate(
2337                                         current_link_setting->link_rate);
2338                 } else {
2339                         return false;
2340                 }
2341                 break;
2342         }
2343         default:
2344                 return false;
2345         }
2346         return true;
2347 }
2348
2349 bool dp_validate_mode_timing(
2350         struct dc_link *link,
2351         const struct dc_crtc_timing *timing)
2352 {
2353         uint32_t req_bw;
2354         uint32_t max_bw;
2355
2356         const struct dc_link_settings *link_setting;
2357
2358         /*always DP fail safe mode*/
2359         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2360                 timing->h_addressable == (uint32_t) 640 &&
2361                 timing->v_addressable == (uint32_t) 480)
2362                 return true;
2363
2364         link_setting = dc_link_get_link_cap(link);
2365
2366         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2367         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2368                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2369                 link_setting = &link->verified_link_cap;
2370         */
2371
2372         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2373         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2374
2375         if (req_bw <= max_bw) {
2376                 /* remember the biggest mode here, during
2377                  * initial link training (to get
2378                  * verified_link_cap), LS sends event about
2379                  * cannot train at reported cap to upper
2380                  * layer and upper layer will re-enumerate modes.
2381                  * this is not necessary if the lower
2382                  * verified_link_cap is enough to drive
2383                  * all the modes */
2384
2385                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2386                 /* if (flags.DYNAMIC_VALIDATION == 1)
2387                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2388                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2389                 return true;
2390         } else
2391                 return false;
2392 }
2393
2394 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2395 {
2396         struct dc_link_settings initial_link_setting = {
2397                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2398         struct dc_link_settings current_link_setting =
2399                         initial_link_setting;
2400         uint32_t link_bw;
2401
2402         /* search for the minimum link setting that:
2403          * 1. is supported according to the link training result
2404          * 2. could support the b/w requested by the timing
2405          */
2406         while (current_link_setting.link_rate <=
2407                         link->verified_link_cap.link_rate) {
2408                 link_bw = dc_link_bandwidth_kbps(
2409                                 link,
2410                                 &current_link_setting);
2411                 if (req_bw <= link_bw) {
2412                         *link_setting = current_link_setting;
2413                         return true;
2414                 }
2415
2416                 if (current_link_setting.lane_count <
2417                                 link->verified_link_cap.lane_count) {
2418                         current_link_setting.lane_count =
2419                                         increase_lane_count(
2420                                                         current_link_setting.lane_count);
2421                 } else {
2422                         current_link_setting.link_rate =
2423                                         increase_link_rate(
2424                                                         current_link_setting.link_rate);
2425                         current_link_setting.lane_count =
2426                                         initial_link_setting.lane_count;
2427                 }
2428         }
2429
2430         return false;
2431 }
2432
2433 static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2434 {
2435         struct dc_link_settings initial_link_setting;
2436         struct dc_link_settings current_link_setting;
2437         uint32_t link_bw;
2438
2439         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2440                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2441                 *link_setting = link->verified_link_cap;
2442                 return true;
2443         }
2444
2445         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2446         initial_link_setting.lane_count = LANE_COUNT_ONE;
2447         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2448         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2449         initial_link_setting.use_link_rate_set = true;
2450         initial_link_setting.link_rate_set = 0;
2451         current_link_setting = initial_link_setting;
2452
2453         /* search for the minimum link setting that:
2454          * 1. is supported according to the link training result
2455          * 2. could support the b/w requested by the timing
2456          */
2457         while (current_link_setting.link_rate <=
2458                         link->verified_link_cap.link_rate) {
2459                 link_bw = dc_link_bandwidth_kbps(
2460                                 link,
2461                                 &current_link_setting);
2462                 if (req_bw <= link_bw) {
2463                         *link_setting = current_link_setting;
2464                         return true;
2465                 }
2466
2467                 if (current_link_setting.lane_count <
2468                                 link->verified_link_cap.lane_count) {
2469                         current_link_setting.lane_count =
2470                                         increase_lane_count(
2471                                                         current_link_setting.lane_count);
2472                 } else {
2473                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2474                                 current_link_setting.link_rate_set++;
2475                                 current_link_setting.link_rate =
2476                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2477                                 current_link_setting.lane_count =
2478                                                                         initial_link_setting.lane_count;
2479                         } else
2480                                 break;
2481                 }
2482         }
2483         return false;
2484 }
2485
2486 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2487 {
2488         *link_setting = link->verified_link_cap;
2489         return true;
2490 }
2491
2492 void decide_link_settings(struct dc_stream_state *stream,
2493         struct dc_link_settings *link_setting)
2494 {
2495         struct dc_link *link;
2496         uint32_t req_bw;
2497
2498         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2499
2500         link = stream->link;
2501
2502         /* if preferred is specified through AMDDP, use it, if it's enough
2503          * to drive the mode
2504          */
2505         if (link->preferred_link_setting.lane_count !=
2506                         LANE_COUNT_UNKNOWN &&
2507                         link->preferred_link_setting.link_rate !=
2508                                         LINK_RATE_UNKNOWN) {
2509                 *link_setting =  link->preferred_link_setting;
2510                 return;
2511         }
2512
2513         /* MST doesn't perform link training for now
2514          * TODO: add MST specific link training routine
2515          */
2516         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2517                 if (decide_mst_link_settings(link, link_setting))
2518                         return;
2519         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2520                 if (decide_edp_link_settings(link, link_setting, req_bw))
2521                         return;
2522         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2523                 return;
2524
2525         BREAK_TO_DEBUGGER();
2526         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2527
2528         *link_setting = link->verified_link_cap;
2529 }
2530
2531 /*************************Short Pulse IRQ***************************/
2532 static bool allow_hpd_rx_irq(const struct dc_link *link)
2533 {
2534         /*
2535          * Don't handle RX IRQ unless one of following is met:
2536          * 1) The link is established (cur_link_settings != unknown)
2537          * 2) We kicked off MST detection
2538          * 3) We know we're dealing with an active dongle
2539          */
2540
2541         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2542                 (link->type == dc_connection_mst_branch) ||
2543                 is_dp_active_dongle(link))
2544                 return true;
2545
2546         return false;
2547 }
2548
2549 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2550 {
2551         union dpcd_psr_configuration psr_configuration;
2552
2553         if (!link->psr_settings.psr_feature_enabled)
2554                 return false;
2555
2556         dm_helpers_dp_read_dpcd(
2557                 link->ctx,
2558                 link,
2559                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2560                 &psr_configuration.raw,
2561                 sizeof(psr_configuration.raw));
2562
2563
2564         if (psr_configuration.bits.ENABLE) {
2565                 unsigned char dpcdbuf[3] = {0};
2566                 union psr_error_status psr_error_status;
2567                 union psr_sink_psr_status psr_sink_psr_status;
2568
2569                 dm_helpers_dp_read_dpcd(
2570                         link->ctx,
2571                         link,
2572                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2573                         (unsigned char *) dpcdbuf,
2574                         sizeof(dpcdbuf));
2575
2576                 /*DPCD 2006h   ERROR STATUS*/
2577                 psr_error_status.raw = dpcdbuf[0];
2578                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2579                 psr_sink_psr_status.raw = dpcdbuf[2];
2580
2581                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2582                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2583                                 psr_error_status.bits.VSC_SDP_ERROR) {
2584                         /* Acknowledge and clear error bits */
2585                         dm_helpers_dp_write_dpcd(
2586                                 link->ctx,
2587                                 link,
2588                                 8198,/*DpcdAddress_PSR_Error_Status*/
2589                                 &psr_error_status.raw,
2590                                 sizeof(psr_error_status.raw));
2591
2592                         /* PSR error, disable and re-enable PSR */
2593                         dc_link_set_psr_allow_active(link, false, true, false);
2594                         dc_link_set_psr_allow_active(link, true, true, false);
2595
2596                         return true;
2597                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2598                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2599                         /* No error is detect, PSR is active.
2600                          * We should return with IRQ_HPD handled without
2601                          * checking for loss of sync since PSR would have
2602                          * powered down main link.
2603                          */
2604                         return true;
2605                 }
2606         }
2607         return false;
2608 }
2609
2610 static void dp_test_send_link_training(struct dc_link *link)
2611 {
2612         struct dc_link_settings link_settings = {0};
2613
2614         core_link_read_dpcd(
2615                         link,
2616                         DP_TEST_LANE_COUNT,
2617                         (unsigned char *)(&link_settings.lane_count),
2618                         1);
2619         core_link_read_dpcd(
2620                         link,
2621                         DP_TEST_LINK_RATE,
2622                         (unsigned char *)(&link_settings.link_rate),
2623                         1);
2624
2625         /* Set preferred link settings */
2626         link->verified_link_cap.lane_count = link_settings.lane_count;
2627         link->verified_link_cap.link_rate = link_settings.link_rate;
2628
2629         dp_retrain_link_dp_test(link, &link_settings, false);
2630 }
2631
2632 /* TODO Raven hbr2 compliance eye output is unstable
2633  * (toggling on and off) with debugger break
2634  * This caueses intermittent PHY automation failure
2635  * Need to look into the root cause */
2636 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2637 {
2638         union phy_test_pattern dpcd_test_pattern;
2639         union lane_adjust dpcd_lane_adjustment[2];
2640         unsigned char dpcd_post_cursor_2_adjustment = 0;
2641         unsigned char test_80_bit_pattern[
2642                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2643                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2644         enum dp_test_pattern test_pattern;
2645         struct dc_link_training_settings link_settings;
2646         union lane_adjust dpcd_lane_adjust;
2647         unsigned int lane;
2648         struct link_training_settings link_training_settings;
2649         int i = 0;
2650
2651         dpcd_test_pattern.raw = 0;
2652         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2653         memset(&link_settings, 0, sizeof(link_settings));
2654
2655         /* get phy test pattern and pattern parameters from DP receiver */
2656         core_link_read_dpcd(
2657                         link,
2658                         DP_PHY_TEST_PATTERN,
2659                         &dpcd_test_pattern.raw,
2660                         sizeof(dpcd_test_pattern));
2661         core_link_read_dpcd(
2662                         link,
2663                         DP_ADJUST_REQUEST_LANE0_1,
2664                         &dpcd_lane_adjustment[0].raw,
2665                         sizeof(dpcd_lane_adjustment));
2666
2667         /*get post cursor 2 parameters
2668          * For DP 1.1a or eariler, this DPCD register's value is 0
2669          * For DP 1.2 or later:
2670          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2671          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2672          */
2673         core_link_read_dpcd(
2674                         link,
2675                         DP_ADJUST_REQUEST_POST_CURSOR2,
2676                         &dpcd_post_cursor_2_adjustment,
2677                         sizeof(dpcd_post_cursor_2_adjustment));
2678
2679         /* translate request */
2680         switch (dpcd_test_pattern.bits.PATTERN) {
2681         case PHY_TEST_PATTERN_D10_2:
2682                 test_pattern = DP_TEST_PATTERN_D102;
2683                 break;
2684         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2685                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2686                 break;
2687         case PHY_TEST_PATTERN_PRBS7:
2688                 test_pattern = DP_TEST_PATTERN_PRBS7;
2689                 break;
2690         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2691                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2692                 break;
2693         case PHY_TEST_PATTERN_CP2520_1:
2694                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2695                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2696                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2697                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2698                 break;
2699         case PHY_TEST_PATTERN_CP2520_2:
2700                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2701                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2702                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2703                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2704                 break;
2705         case PHY_TEST_PATTERN_CP2520_3:
2706                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2707                 break;
2708         default:
2709                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2710         break;
2711         }
2712
2713         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2714                 core_link_read_dpcd(
2715                                 link,
2716                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2717                                 test_80_bit_pattern,
2718                                 sizeof(test_80_bit_pattern));
2719
2720         /* prepare link training settings */
2721         link_settings.link = link->cur_link_settings;
2722
2723         for (lane = 0; lane <
2724                 (unsigned int)(link->cur_link_settings.lane_count);
2725                 lane++) {
2726                 dpcd_lane_adjust.raw =
2727                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2728                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2729                         (enum dc_voltage_swing)
2730                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2731                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2732                         (enum dc_pre_emphasis)
2733                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2734                 link_settings.lane_settings[lane].POST_CURSOR2 =
2735                         (enum dc_post_cursor2)
2736                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2737         }
2738
2739         for (i = 0; i < 4; i++)
2740                 link_training_settings.lane_settings[i] =
2741                                 link_settings.lane_settings[i];
2742         link_training_settings.link_settings = link_settings.link;
2743         link_training_settings.allow_invalid_msa_timing_param = false;
2744         /*Usage: Measure DP physical lane signal
2745          * by DP SI test equipment automatically.
2746          * PHY test pattern request is generated by equipment via HPD interrupt.
2747          * HPD needs to be active all the time. HPD should be active
2748          * all the time. Do not touch it.
2749          * forward request to DS
2750          */
2751         dc_link_dp_set_test_pattern(
2752                 link,
2753                 test_pattern,
2754                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2755                 &link_training_settings,
2756                 test_80_bit_pattern,
2757                 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2758                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2759 }
2760
2761 static void dp_test_send_link_test_pattern(struct dc_link *link)
2762 {
2763         union link_test_pattern dpcd_test_pattern;
2764         union test_misc dpcd_test_params;
2765         enum dp_test_pattern test_pattern;
2766         enum dp_test_pattern_color_space test_pattern_color_space =
2767                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2768
2769         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2770         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2771
2772         /* get link test pattern and pattern parameters */
2773         core_link_read_dpcd(
2774                         link,
2775                         DP_TEST_PATTERN,
2776                         &dpcd_test_pattern.raw,
2777                         sizeof(dpcd_test_pattern));
2778         core_link_read_dpcd(
2779                         link,
2780                         DP_TEST_MISC0,
2781                         &dpcd_test_params.raw,
2782                         sizeof(dpcd_test_params));
2783
2784         switch (dpcd_test_pattern.bits.PATTERN) {
2785         case LINK_TEST_PATTERN_COLOR_RAMP:
2786                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2787         break;
2788         case LINK_TEST_PATTERN_VERTICAL_BARS:
2789                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2790         break; /* black and white */
2791         case LINK_TEST_PATTERN_COLOR_SQUARES:
2792                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2793                                 TEST_DYN_RANGE_VESA ?
2794                                 DP_TEST_PATTERN_COLOR_SQUARES :
2795                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2796         break;
2797         default:
2798                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2799         break;
2800         }
2801
2802         if (dpcd_test_params.bits.CLR_FORMAT == 0)
2803                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2804         else
2805                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2806                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2807                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2808
2809         dc_link_dp_set_test_pattern(
2810                         link,
2811                         test_pattern,
2812                         test_pattern_color_space,
2813                         NULL,
2814                         NULL,
2815                         0);
2816 }
2817
2818 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2819 {
2820         union audio_test_mode            dpcd_test_mode = {0};
2821         struct audio_test_pattern_type   dpcd_pattern_type = {0};
2822         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2823         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2824
2825         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2826         struct pipe_ctx *pipe_ctx = &pipes[0];
2827         unsigned int channel_count;
2828         unsigned int channel = 0;
2829         unsigned int modes = 0;
2830         unsigned int sampling_rate_in_hz = 0;
2831
2832         // get audio test mode and test pattern parameters
2833         core_link_read_dpcd(
2834                 link,
2835                 DP_TEST_AUDIO_MODE,
2836                 &dpcd_test_mode.raw,
2837                 sizeof(dpcd_test_mode));
2838
2839         core_link_read_dpcd(
2840                 link,
2841                 DP_TEST_AUDIO_PATTERN_TYPE,
2842                 &dpcd_pattern_type.value,
2843                 sizeof(dpcd_pattern_type));
2844
2845         channel_count = dpcd_test_mode.bits.channel_count + 1;
2846
2847         // read pattern periods for requested channels when sawTooth pattern is requested
2848         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2849                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2850
2851                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2852                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2853                 // read period for each channel
2854                 for (channel = 0; channel < channel_count; channel++) {
2855                         core_link_read_dpcd(
2856                                                         link,
2857                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
2858                                                         &dpcd_pattern_period[channel].raw,
2859                                                         sizeof(dpcd_pattern_period[channel]));
2860                 }
2861         }
2862
2863         // translate sampling rate
2864         switch (dpcd_test_mode.bits.sampling_rate) {
2865         case AUDIO_SAMPLING_RATE_32KHZ:
2866                 sampling_rate_in_hz = 32000;
2867                 break;
2868         case AUDIO_SAMPLING_RATE_44_1KHZ:
2869                 sampling_rate_in_hz = 44100;
2870                 break;
2871         case AUDIO_SAMPLING_RATE_48KHZ:
2872                 sampling_rate_in_hz = 48000;
2873                 break;
2874         case AUDIO_SAMPLING_RATE_88_2KHZ:
2875                 sampling_rate_in_hz = 88200;
2876                 break;
2877         case AUDIO_SAMPLING_RATE_96KHZ:
2878                 sampling_rate_in_hz = 96000;
2879                 break;
2880         case AUDIO_SAMPLING_RATE_176_4KHZ:
2881                 sampling_rate_in_hz = 176400;
2882                 break;
2883         case AUDIO_SAMPLING_RATE_192KHZ:
2884                 sampling_rate_in_hz = 192000;
2885                 break;
2886         default:
2887                 sampling_rate_in_hz = 0;
2888                 break;
2889         }
2890
2891         link->audio_test_data.flags.test_requested = 1;
2892         link->audio_test_data.flags.disable_video = disable_video;
2893         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2894         link->audio_test_data.channel_count = channel_count;
2895         link->audio_test_data.pattern_type = test_pattern;
2896
2897         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
2898                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
2899                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
2900                 }
2901         }
2902 }
2903
2904 static void handle_automated_test(struct dc_link *link)
2905 {
2906         union test_request test_request;
2907         union test_response test_response;
2908
2909         memset(&test_request, 0, sizeof(test_request));
2910         memset(&test_response, 0, sizeof(test_response));
2911
2912         core_link_read_dpcd(
2913                 link,
2914                 DP_TEST_REQUEST,
2915                 &test_request.raw,
2916                 sizeof(union test_request));
2917         if (test_request.bits.LINK_TRAINING) {
2918                 /* ACK first to let DP RX test box monitor LT sequence */
2919                 test_response.bits.ACK = 1;
2920                 core_link_write_dpcd(
2921                         link,
2922                         DP_TEST_RESPONSE,
2923                         &test_response.raw,
2924                         sizeof(test_response));
2925                 dp_test_send_link_training(link);
2926                 /* no acknowledge request is needed again */
2927                 test_response.bits.ACK = 0;
2928         }
2929         if (test_request.bits.LINK_TEST_PATTRN) {
2930                 dp_test_send_link_test_pattern(link);
2931                 test_response.bits.ACK = 1;
2932         }
2933
2934         if (test_request.bits.AUDIO_TEST_PATTERN) {
2935                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
2936                 test_response.bits.ACK = 1;
2937         }
2938
2939         if (test_request.bits.PHY_TEST_PATTERN) {
2940                 dp_test_send_phy_test_pattern(link);
2941                 test_response.bits.ACK = 1;
2942         }
2943
2944         /* send request acknowledgment */
2945         if (test_response.bits.ACK)
2946                 core_link_write_dpcd(
2947                         link,
2948                         DP_TEST_RESPONSE,
2949                         &test_response.raw,
2950                         sizeof(test_response));
2951 }
2952
2953 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2954 {
2955         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2956         union device_service_irq device_service_clear = { { 0 } };
2957         enum dc_status result;
2958         bool status = false;
2959         struct pipe_ctx *pipe_ctx;
2960         int i;
2961
2962         if (out_link_loss)
2963                 *out_link_loss = false;
2964         /* For use cases related to down stream connection status change,
2965          * PSR and device auto test, refer to function handle_sst_hpd_irq
2966          * in DAL2.1*/
2967
2968         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2969                 __func__, link->link_index);
2970
2971
2972          /* All the "handle_hpd_irq_xxx()" methods
2973                  * should be called only after
2974                  * dal_dpsst_ls_read_hpd_irq_data
2975                  * Order of calls is important too
2976                  */
2977         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2978         if (out_hpd_irq_dpcd_data)
2979                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2980
2981         if (result != DC_OK) {
2982                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2983                         __func__);
2984                 return false;
2985         }
2986
2987         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2988                 device_service_clear.bits.AUTOMATED_TEST = 1;
2989                 core_link_write_dpcd(
2990                         link,
2991                         DP_DEVICE_SERVICE_IRQ_VECTOR,
2992                         &device_service_clear.raw,
2993                         sizeof(device_service_clear.raw));
2994                 device_service_clear.raw = 0;
2995                 handle_automated_test(link);
2996                 return false;
2997         }
2998
2999         if (!allow_hpd_rx_irq(link)) {
3000                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3001                         __func__, link->link_index);
3002                 return false;
3003         }
3004
3005         if (handle_hpd_irq_psr_sink(link))
3006                 /* PSR-related error was detected and handled */
3007                 return true;
3008
3009         /* If PSR-related error handled, Main link may be off,
3010          * so do not handle as a normal sink status change interrupt.
3011          */
3012
3013         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3014                 return true;
3015
3016         /* check if we have MST msg and return since we poll for it */
3017         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3018                 return false;
3019
3020         /* For now we only handle 'Downstream port status' case.
3021          * If we got sink count changed it means
3022          * Downstream port status changed,
3023          * then DM should call DC to do the detection.
3024          * NOTE: Do not handle link loss on eDP since it is internal link*/
3025         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3026                 hpd_rx_irq_check_link_loss_status(
3027                         link,
3028                         &hpd_irq_dpcd_data)) {
3029                 /* Connectivity log: link loss */
3030                 CONN_DATA_LINK_LOSS(link,
3031                                         hpd_irq_dpcd_data.raw,
3032                                         sizeof(hpd_irq_dpcd_data),
3033                                         "Status: ");
3034
3035                 for (i = 0; i < MAX_PIPES; i++) {
3036                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3037                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3038                                 break;
3039                 }
3040
3041                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3042                         return false;
3043
3044
3045                 for (i = 0; i < MAX_PIPES; i++) {
3046                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3047                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3048                                         pipe_ctx->stream->link == link)
3049                                 core_link_disable_stream(pipe_ctx);
3050                 }
3051
3052                 for (i = 0; i < MAX_PIPES; i++) {
3053                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3054                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3055                                         pipe_ctx->stream->link == link)
3056                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3057                 }
3058
3059                 status = false;
3060                 if (out_link_loss)
3061                         *out_link_loss = true;
3062         }
3063
3064         if (link->type == dc_connection_active_dongle &&
3065                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3066                         != link->dpcd_sink_count)
3067                 status = true;
3068
3069         /* reasons for HPD RX:
3070          * 1. Link Loss - ie Re-train the Link
3071          * 2. MST sideband message
3072          * 3. Automated Test - ie. Internal Commit
3073          * 4. CP (copy protection) - (not interesting for DM???)
3074          * 5. DRR
3075          * 6. Downstream Port status changed
3076          * -ie. Detect - this the only one
3077          * which is interesting for DM because
3078          * it must call dc_link_detect.
3079          */
3080         return status;
3081 }
3082
3083 /*query dpcd for version and mst cap addresses*/
3084 bool is_mst_supported(struct dc_link *link)
3085 {
3086         bool mst          = false;
3087         enum dc_status st = DC_OK;
3088         union dpcd_rev rev;
3089         union mstm_cap cap;
3090
3091         if (link->preferred_training_settings.mst_enable &&
3092                 *link->preferred_training_settings.mst_enable == false) {
3093                 return false;
3094         }
3095
3096         rev.raw  = 0;
3097         cap.raw  = 0;
3098
3099         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3100                         sizeof(rev));
3101
3102         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3103
3104                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3105                                 &cap.raw, sizeof(cap));
3106                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3107                         mst = true;
3108         }
3109         return mst;
3110
3111 }
3112
3113 bool is_dp_active_dongle(const struct dc_link *link)
3114 {
3115         return link->dpcd_caps.is_branch_dev;
3116 }
3117
3118 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3119 {
3120         switch (bpc) {
3121         case DOWN_STREAM_MAX_8BPC:
3122                 return 8;
3123         case DOWN_STREAM_MAX_10BPC:
3124                 return 10;
3125         case DOWN_STREAM_MAX_12BPC:
3126                 return 12;
3127         case DOWN_STREAM_MAX_16BPC:
3128                 return 16;
3129         default:
3130                 break;
3131         }
3132
3133         return -1;
3134 }
3135
3136 static void read_dp_device_vendor_id(struct dc_link *link)
3137 {
3138         struct dp_device_vendor_id dp_id;
3139
3140         /* read IEEE branch device id */
3141         core_link_read_dpcd(
3142                 link,
3143                 DP_BRANCH_OUI,
3144                 (uint8_t *)&dp_id,
3145                 sizeof(dp_id));
3146
3147         link->dpcd_caps.branch_dev_id =
3148                 (dp_id.ieee_oui[0] << 16) +
3149                 (dp_id.ieee_oui[1] << 8) +
3150                 dp_id.ieee_oui[2];
3151
3152         memmove(
3153                 link->dpcd_caps.branch_dev_name,
3154                 dp_id.ieee_device_id,
3155                 sizeof(dp_id.ieee_device_id));
3156 }
3157
3158
3159
3160 static void get_active_converter_info(
3161         uint8_t data, struct dc_link *link)
3162 {
3163         union dp_downstream_port_present ds_port = { .byte = data };
3164         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3165
3166         /* decode converter info*/
3167         if (!ds_port.fields.PORT_PRESENT) {
3168                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3169                 ddc_service_set_dongle_type(link->ddc,
3170                                 link->dpcd_caps.dongle_type);
3171                 link->dpcd_caps.is_branch_dev = false;
3172                 return;
3173         }
3174
3175         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3176         if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
3177                 link->dpcd_caps.is_branch_dev = false;
3178         }
3179
3180         else {
3181                 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3182         }
3183
3184         switch (ds_port.fields.PORT_TYPE) {
3185         case DOWNSTREAM_VGA:
3186                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3187                 break;
3188         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3189                 /* At this point we don't know is it DVI or HDMI or DP++,
3190                  * assume DVI.*/
3191                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3192                 break;
3193         default:
3194                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3195                 break;
3196         }
3197
3198         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3199                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3200                 union dwnstream_port_caps_byte0 *port_caps =
3201                         (union dwnstream_port_caps_byte0 *)det_caps;
3202                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3203                                 det_caps, sizeof(det_caps)) == DC_OK) {
3204
3205                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3206                         /*Handle DP case as DONGLE_NONE*/
3207                         case DOWN_STREAM_DETAILED_DP:
3208                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3209                                 break;
3210                         case DOWN_STREAM_DETAILED_VGA:
3211                                 link->dpcd_caps.dongle_type =
3212                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3213                                 break;
3214                         case DOWN_STREAM_DETAILED_DVI:
3215                                 link->dpcd_caps.dongle_type =
3216                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3217                                 break;
3218                         case DOWN_STREAM_DETAILED_HDMI:
3219                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3220                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3221                                 link->dpcd_caps.dongle_type =
3222                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3223
3224                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3225                                 if (ds_port.fields.DETAILED_CAPS) {
3226
3227                                         union dwnstream_port_caps_byte3_hdmi
3228                                                 hdmi_caps = {.raw = det_caps[3] };
3229                                         union dwnstream_port_caps_byte2
3230                                                 hdmi_color_caps = {.raw = det_caps[2] };
3231                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3232                                                 det_caps[1] * 2500;
3233
3234                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3235                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3236                                         /*YCBCR capability only for HDMI case*/
3237                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3238                                                         == DOWN_STREAM_DETAILED_HDMI) {
3239                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3240                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3241                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3242                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3243                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3244                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3245                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3246                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3247                                         }
3248
3249                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3250                                                 translate_dpcd_max_bpc(
3251                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3252
3253                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3254                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3255                                 }
3256
3257                                 break;
3258                         }
3259                 }
3260         }
3261
3262         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3263
3264         {
3265                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3266
3267                 core_link_read_dpcd(
3268                         link,
3269                         DP_BRANCH_REVISION_START,
3270                         (uint8_t *)&dp_hw_fw_revision,
3271                         sizeof(dp_hw_fw_revision));
3272
3273                 link->dpcd_caps.branch_hw_revision =
3274                         dp_hw_fw_revision.ieee_hw_rev;
3275
3276                 memmove(
3277                         link->dpcd_caps.branch_fw_revision,
3278                         dp_hw_fw_revision.ieee_fw_rev,
3279                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3280         }
3281 }
3282
3283 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3284                 int length)
3285 {
3286         int retry = 0;
3287
3288         if (!link->dpcd_caps.dpcd_rev.raw) {
3289                 do {
3290                         dp_receiver_power_ctrl(link, true);
3291                         core_link_read_dpcd(link, DP_DPCD_REV,
3292                                                         dpcd_data, length);
3293                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3294                                 DP_DPCD_REV -
3295                                 DP_DPCD_REV];
3296                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3297         }
3298
3299         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3300                 switch (link->dpcd_caps.branch_dev_id) {
3301                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3302                  * all internal circuits including AUX communication preventing
3303                  * reading DPCD table and EDID (spec violation).
3304                  * Encoder will skip DP RX power down on disable_output to
3305                  * keep receiver powered all the time.*/
3306                 case DP_BRANCH_DEVICE_ID_0010FA:
3307                 case DP_BRANCH_DEVICE_ID_0080E1:
3308                 case DP_BRANCH_DEVICE_ID_00E04C:
3309                         link->wa_flags.dp_keep_receiver_powered = true;
3310                         break;
3311
3312                 /* TODO: May need work around for other dongles. */
3313                 default:
3314                         link->wa_flags.dp_keep_receiver_powered = false;
3315                         break;
3316                 }
3317         } else
3318                 link->wa_flags.dp_keep_receiver_powered = false;
3319 }
3320
3321 /* Read additional sink caps defined in source specific DPCD area
3322  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3323  */
3324 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3325 {
3326         uint8_t dpcd_data;
3327
3328         if (!link)
3329                 return false;
3330
3331         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3332                 return false;
3333
3334         link->dpcd_sink_ext_caps.raw = dpcd_data;
3335         return true;
3336 }
3337
3338 static bool retrieve_link_cap(struct dc_link *link)
3339 {
3340         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3341          * which means size 16 will be good for both of those DPCD register block reads
3342          */
3343         uint8_t dpcd_data[16];
3344         uint8_t lttpr_dpcd_data[6];
3345
3346         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3347          */
3348         uint8_t dpcd_dprx_data = '\0';
3349         uint8_t dpcd_power_state = '\0';
3350
3351         struct dp_device_vendor_id sink_id;
3352         union down_stream_port_count down_strm_port_count;
3353         union edp_configuration_cap edp_config_cap;
3354         union dp_downstream_port_present ds_port = { 0 };
3355         enum dc_status status = DC_ERROR_UNEXPECTED;
3356         uint32_t read_dpcd_retry_cnt = 3;
3357         int i;
3358         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3359         bool is_lttpr_present = false;
3360         const uint32_t post_oui_delay = 30; // 30ms
3361
3362         memset(dpcd_data, '\0', sizeof(dpcd_data));
3363         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3364         memset(&down_strm_port_count,
3365                 '\0', sizeof(union down_stream_port_count));
3366         memset(&edp_config_cap, '\0',
3367                 sizeof(union edp_configuration_cap));
3368
3369         /* if extended timeout is supported in hardware,
3370          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3371          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3372          */
3373         dc_link_aux_try_to_configure_timeout(link->ddc,
3374                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3375
3376         status = core_link_read_dpcd(link, DP_SET_POWER,
3377                                 &dpcd_power_state, sizeof(dpcd_power_state));
3378
3379         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3380          * section 2.3.1.2, if AUX CH may be powered down due to
3381          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3382          * signal and may need up to 1 ms before being able to reply.
3383          */
3384         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3385                 udelay(1000);
3386
3387         dpcd_set_source_specific_data(link);
3388         /* Sink may need to configure internals based on vendor, so allow some
3389          * time before proceeding with possibly vendor specific transactions
3390          */
3391         msleep(post_oui_delay);
3392
3393         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3394                 status = core_link_read_dpcd(
3395                                 link,
3396                                 DP_DPCD_REV,
3397                                 dpcd_data,
3398                                 sizeof(dpcd_data));
3399                 if (status == DC_OK)
3400                         break;
3401         }
3402
3403         if (status != DC_OK) {
3404                 dm_error("%s: Read dpcd data failed.\n", __func__);
3405                 return false;
3406         }
3407
3408         if (link->dc->caps.extended_aux_timeout_support &&
3409                         link->dc->config.allow_lttpr_non_transparent_mode) {
3410                 /* By reading LTTPR capability, RX assumes that we will enable
3411                  * LTTPR non transparent if LTTPR is present.
3412                  * Therefore, only query LTTPR capability when both LTTPR
3413                  * extended aux timeout and
3414                  * non transparent mode is supported by hardware
3415                  */
3416                 status = core_link_read_dpcd(
3417                                 link,
3418                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3419                                 lttpr_dpcd_data,
3420                                 sizeof(lttpr_dpcd_data));
3421
3422                 link->dpcd_caps.lttpr_caps.revision.raw =
3423                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3424                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3425
3426                 link->dpcd_caps.lttpr_caps.max_link_rate =
3427                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3428                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3429
3430                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3431                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3432                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3433
3434                 link->dpcd_caps.lttpr_caps.max_lane_count =
3435                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3436                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3437
3438                 link->dpcd_caps.lttpr_caps.mode =
3439                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3440                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3441
3442                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3443                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3444                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3445
3446                 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3447                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3448                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3449                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3450                 if (is_lttpr_present)
3451                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3452         }
3453
3454         /* decide lttpr non transparent mode */
3455         link->lttpr_non_transparent_mode = is_lttpr_present;
3456
3457         if (!is_lttpr_present)
3458                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3459
3460
3461         {
3462                 union training_aux_rd_interval aux_rd_interval;
3463
3464                 aux_rd_interval.raw =
3465                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3466
3467                 link->dpcd_caps.ext_receiver_cap_field_present =
3468                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3469
3470                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3471                         uint8_t ext_cap_data[16];
3472
3473                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3474                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3475                                 status = core_link_read_dpcd(
3476                                 link,
3477                                 DP_DP13_DPCD_REV,
3478                                 ext_cap_data,
3479                                 sizeof(ext_cap_data));
3480                                 if (status == DC_OK) {
3481                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3482                                         break;
3483                                 }
3484                         }
3485                         if (status != DC_OK)
3486                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3487                 }
3488         }
3489
3490         link->dpcd_caps.dpcd_rev.raw =
3491                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3492
3493         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3494                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3495                         status = core_link_read_dpcd(
3496                                         link,
3497                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3498                                         &dpcd_dprx_data,
3499                                         sizeof(dpcd_dprx_data));
3500                         if (status == DC_OK)
3501                                 break;
3502                 }
3503
3504                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3505
3506                 if (status != DC_OK)
3507                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3508         }
3509
3510         else {
3511                 link->dpcd_caps.dprx_feature.raw = 0;
3512         }
3513
3514
3515         /* Error condition checking...
3516          * It is impossible for Sink to report Max Lane Count = 0.
3517          * It is possible for Sink to report Max Link Rate = 0, if it is
3518          * an eDP device that is reporting specialized link rates in the
3519          * SUPPORTED_LINK_RATE table.
3520          */
3521         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3522                 return false;
3523
3524         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3525                                  DP_DPCD_REV];
3526
3527         read_dp_device_vendor_id(link);
3528
3529         get_active_converter_info(ds_port.byte, link);
3530
3531         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3532
3533         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3534                                  DP_DPCD_REV];
3535
3536         link->dpcd_caps.allow_invalid_MSA_timing_param =
3537                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3538
3539         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3540                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3541
3542         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3543                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3544
3545         link->reported_link_cap.lane_count =
3546                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3547         link->reported_link_cap.link_rate = dpcd_data[
3548                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3549         link->reported_link_cap.link_spread =
3550                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3551                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3552
3553         edp_config_cap.raw = dpcd_data[
3554                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3555         link->dpcd_caps.panel_mode_edp =
3556                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3557         link->dpcd_caps.dpcd_display_control_capable =
3558                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3559
3560         link->test_pattern_enabled = false;
3561         link->compliance_test_state.raw = 0;
3562
3563         /* read sink count */
3564         core_link_read_dpcd(link,
3565                         DP_SINK_COUNT,
3566                         &link->dpcd_caps.sink_count.raw,
3567                         sizeof(link->dpcd_caps.sink_count.raw));
3568
3569         /* read sink ieee oui */
3570         core_link_read_dpcd(link,
3571                         DP_SINK_OUI,
3572                         (uint8_t *)(&sink_id),
3573                         sizeof(sink_id));
3574
3575         link->dpcd_caps.sink_dev_id =
3576                         (sink_id.ieee_oui[0] << 16) +
3577                         (sink_id.ieee_oui[1] << 8) +
3578                         (sink_id.ieee_oui[2]);
3579
3580         memmove(
3581                 link->dpcd_caps.sink_dev_id_str,
3582                 sink_id.ieee_device_id,
3583                 sizeof(sink_id.ieee_device_id));
3584
3585         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3586         {
3587                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3588
3589                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3590                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3591                             sizeof(str_mbp_2017))) {
3592                         link->reported_link_cap.link_rate = 0x0c;
3593                 }
3594         }
3595
3596         core_link_read_dpcd(
3597                 link,
3598                 DP_SINK_HW_REVISION_START,
3599                 (uint8_t *)&dp_hw_fw_revision,
3600                 sizeof(dp_hw_fw_revision));
3601
3602         link->dpcd_caps.sink_hw_revision =
3603                 dp_hw_fw_revision.ieee_hw_rev;
3604
3605         memmove(
3606                 link->dpcd_caps.sink_fw_revision,
3607                 dp_hw_fw_revision.ieee_fw_rev,
3608                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3609
3610         memset(&link->dpcd_caps.dsc_caps, '\0',
3611                         sizeof(link->dpcd_caps.dsc_caps));
3612         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3613         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3614         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3615                 status = core_link_read_dpcd(
3616                                 link,
3617                                 DP_FEC_CAPABILITY,
3618                                 &link->dpcd_caps.fec_cap.raw,
3619                                 sizeof(link->dpcd_caps.fec_cap.raw));
3620                 status = core_link_read_dpcd(
3621                                 link,
3622                                 DP_DSC_SUPPORT,
3623                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3624                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3625                 status = core_link_read_dpcd(
3626                                 link,
3627                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3628                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3629                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3630         }
3631
3632         if (!dpcd_read_sink_ext_caps(link))
3633                 link->dpcd_sink_ext_caps.raw = 0;
3634
3635         /* Connectivity log: detection */
3636         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3637
3638         return true;
3639 }
3640
3641 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3642 {
3643         uint8_t dpcd_data[16];
3644         uint32_t read_dpcd_retry_cnt = 3;
3645         enum dc_status status = DC_ERROR_UNEXPECTED;
3646         union dp_downstream_port_present ds_port = { 0 };
3647         union down_stream_port_count down_strm_port_count;
3648         union edp_configuration_cap edp_config_cap;
3649
3650         int i;
3651
3652         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3653                 status = core_link_read_dpcd(
3654                                 link,
3655                                 DP_DPCD_REV,
3656                                 dpcd_data,
3657                                 sizeof(dpcd_data));
3658                 if (status == DC_OK)
3659                         break;
3660         }
3661
3662         link->dpcd_caps.dpcd_rev.raw =
3663                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3664
3665         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3666                 return false;
3667
3668         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3669                         DP_DPCD_REV];
3670
3671         get_active_converter_info(ds_port.byte, link);
3672
3673         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3674                         DP_DPCD_REV];
3675
3676         link->dpcd_caps.allow_invalid_MSA_timing_param =
3677                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3678
3679         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3680                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3681
3682         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3683                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3684
3685         link->reported_link_cap.lane_count =
3686                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3687         link->reported_link_cap.link_rate = dpcd_data[
3688                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3689         link->reported_link_cap.link_spread =
3690                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3691                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3692
3693         edp_config_cap.raw = dpcd_data[
3694                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3695         link->dpcd_caps.panel_mode_edp =
3696                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3697         link->dpcd_caps.dpcd_display_control_capable =
3698                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3699
3700         return true;
3701 }
3702
3703 bool detect_dp_sink_caps(struct dc_link *link)
3704 {
3705         return retrieve_link_cap(link);
3706
3707         /* dc init_hw has power encoder using default
3708          * signal for connector. For native DP, no
3709          * need to power up encoder again. If not native
3710          * DP, hw_init may need check signal or power up
3711          * encoder here.
3712          */
3713         /* TODO save sink caps in link->sink */
3714 }
3715
3716 enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3717 {
3718         enum dc_link_rate link_rate;
3719         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3720         switch (link_rate_in_khz) {
3721         case 1620000:
3722                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
3723                 break;
3724         case 2160000:
3725                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
3726                 break;
3727         case 2430000:
3728                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
3729                 break;
3730         case 2700000:
3731                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
3732                 break;
3733         case 3240000:
3734                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
3735                 break;
3736         case 4320000:
3737                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
3738                 break;
3739         case 5400000:
3740                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
3741                 break;
3742         case 8100000:
3743                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
3744                 break;
3745         default:
3746                 link_rate = LINK_RATE_UNKNOWN;
3747                 break;
3748         }
3749         return link_rate;
3750 }
3751
3752 void detect_edp_sink_caps(struct dc_link *link)
3753 {
3754         uint8_t supported_link_rates[16];
3755         uint32_t entry;
3756         uint32_t link_rate_in_khz;
3757         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3758         uint8_t backlight_adj_cap;
3759
3760         retrieve_link_cap(link);
3761         link->dpcd_caps.edp_supported_link_rates_count = 0;
3762         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3763
3764         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3765                         (link->dc->config.optimize_edp_link_rate ||
3766                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3767                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3768                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3769                                                         supported_link_rates, sizeof(supported_link_rates));
3770
3771                 for (entry = 0; entry < 16; entry += 2) {
3772                         // DPCD register reports per-lane link rate = 16-bit link rate capability
3773                         // value X 200 kHz. Need multiplier to find link rate in kHz.
3774                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3775                                                                                 supported_link_rates[entry]) * 200;
3776
3777                         if (link_rate_in_khz != 0) {
3778                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
3779                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3780                                 link->dpcd_caps.edp_supported_link_rates_count++;
3781
3782                                 if (link->reported_link_cap.link_rate < link_rate)
3783                                         link->reported_link_cap.link_rate = link_rate;
3784                         }
3785                 }
3786         }
3787         link->verified_link_cap = link->reported_link_cap;
3788
3789         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
3790                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
3791
3792         link->dpcd_caps.dynamic_backlight_capable_edp =
3793                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
3794
3795         dc_link_set_default_brightness_aux(link);
3796 }
3797
3798 void dc_link_dp_enable_hpd(const struct dc_link *link)
3799 {
3800         struct link_encoder *encoder = link->link_enc;
3801
3802         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3803                 encoder->funcs->enable_hpd(encoder);
3804 }
3805
3806 void dc_link_dp_disable_hpd(const struct dc_link *link)
3807 {
3808         struct link_encoder *encoder = link->link_enc;
3809
3810         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3811                 encoder->funcs->disable_hpd(encoder);
3812 }
3813
3814 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3815 {
3816         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3817                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3818                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
3819                 return true;
3820         else
3821                 return false;
3822 }
3823
3824 static void set_crtc_test_pattern(struct dc_link *link,
3825                                 struct pipe_ctx *pipe_ctx,
3826                                 enum dp_test_pattern test_pattern,
3827                                 enum dp_test_pattern_color_space test_pattern_color_space)
3828 {
3829         enum controller_dp_test_pattern controller_test_pattern;
3830         enum dc_color_depth color_depth = pipe_ctx->
3831                 stream->timing.display_color_depth;
3832         struct bit_depth_reduction_params params;
3833         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3834         int width = pipe_ctx->stream->timing.h_addressable +
3835                 pipe_ctx->stream->timing.h_border_left +
3836                 pipe_ctx->stream->timing.h_border_right;
3837         int height = pipe_ctx->stream->timing.v_addressable +
3838                 pipe_ctx->stream->timing.v_border_bottom +
3839                 pipe_ctx->stream->timing.v_border_top;
3840
3841         memset(&params, 0, sizeof(params));
3842
3843         switch (test_pattern) {
3844         case DP_TEST_PATTERN_COLOR_SQUARES:
3845                 controller_test_pattern =
3846                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3847         break;
3848         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3849                 controller_test_pattern =
3850                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3851         break;
3852         case DP_TEST_PATTERN_VERTICAL_BARS:
3853                 controller_test_pattern =
3854                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3855         break;
3856         case DP_TEST_PATTERN_HORIZONTAL_BARS:
3857                 controller_test_pattern =
3858                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3859         break;
3860         case DP_TEST_PATTERN_COLOR_RAMP:
3861                 controller_test_pattern =
3862                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3863         break;
3864         default:
3865                 controller_test_pattern =
3866                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3867         break;
3868         }
3869
3870         switch (test_pattern) {
3871         case DP_TEST_PATTERN_COLOR_SQUARES:
3872         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3873         case DP_TEST_PATTERN_VERTICAL_BARS:
3874         case DP_TEST_PATTERN_HORIZONTAL_BARS:
3875         case DP_TEST_PATTERN_COLOR_RAMP:
3876         {
3877                 /* disable bit depth reduction */
3878                 pipe_ctx->stream->bit_depth_params = params;
3879                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
3880                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3881                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3882                                 controller_test_pattern, color_depth);
3883                 else if (link->dc->hwss.set_disp_pattern_generator) {
3884                         struct pipe_ctx *odm_pipe;
3885                         enum controller_dp_color_space controller_color_space;
3886                         int opp_cnt = 1;
3887                         int offset = 0;
3888                         int dpg_width = width;
3889
3890                         switch (test_pattern_color_space) {
3891                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3892                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
3893                                 break;
3894                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3895                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
3896                                 break;
3897                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3898                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
3899                                 break;
3900                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
3901                         default:
3902                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
3903                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
3904                                 ASSERT(0);
3905                                 break;
3906                         }
3907
3908                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3909                                 opp_cnt++;
3910                         dpg_width = width / opp_cnt;
3911                         offset = dpg_width;
3912
3913                         link->dc->hwss.set_disp_pattern_generator(link->dc,
3914                                         pipe_ctx,
3915                                         controller_test_pattern,
3916                                         controller_color_space,
3917                                         color_depth,
3918                                         NULL,
3919                                         dpg_width,
3920                                         height,
3921                                         0);
3922
3923                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3924                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3925
3926                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3927                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
3928                                                 odm_pipe,
3929                                                 controller_test_pattern,
3930                                                 controller_color_space,
3931                                                 color_depth,
3932                                                 NULL,
3933                                                 dpg_width,
3934                                                 height,
3935                                                 offset);
3936                                 offset += offset;
3937                         }
3938                 }
3939         }
3940         break;
3941         case DP_TEST_PATTERN_VIDEO_MODE:
3942         {
3943                 /* restore bitdepth reduction */
3944                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
3945                 pipe_ctx->stream->bit_depth_params = params;
3946                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
3947                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3948                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3949                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3950                                 color_depth);
3951                 else if (link->dc->hwss.set_disp_pattern_generator) {
3952                         struct pipe_ctx *odm_pipe;
3953                         int opp_cnt = 1;
3954                         int dpg_width = width;
3955
3956                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3957                                 opp_cnt++;
3958
3959                         dpg_width = width / opp_cnt;
3960                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3961                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3962
3963                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3964                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
3965                                                 odm_pipe,
3966                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3967                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3968                                                 color_depth,
3969                                                 NULL,
3970                                                 dpg_width,
3971                                                 height,
3972                                                 0);
3973                         }
3974                         link->dc->hwss.set_disp_pattern_generator(link->dc,
3975                                         pipe_ctx,
3976                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3977                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3978                                         color_depth,
3979                                         NULL,
3980                                         dpg_width,
3981                                         height,
3982                                         0);
3983                 }
3984         }
3985         break;
3986
3987         default:
3988         break;
3989         }
3990 }
3991
3992 bool dc_link_dp_set_test_pattern(
3993         struct dc_link *link,
3994         enum dp_test_pattern test_pattern,
3995         enum dp_test_pattern_color_space test_pattern_color_space,
3996         const struct link_training_settings *p_link_settings,
3997         const unsigned char *p_custom_pattern,
3998         unsigned int cust_pattern_size)
3999 {
4000         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4001         struct pipe_ctx *pipe_ctx = &pipes[0];
4002         unsigned int lane;
4003         unsigned int i;
4004         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4005         union dpcd_training_pattern training_pattern;
4006         enum dpcd_phy_test_patterns pattern;
4007
4008         memset(&training_pattern, 0, sizeof(training_pattern));
4009
4010         for (i = 0; i < MAX_PIPES; i++) {
4011                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4012                         pipe_ctx = &pipes[i];
4013                         break;
4014                 }
4015         }
4016
4017         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4018         if (link->test_pattern_enabled && test_pattern ==
4019                         DP_TEST_PATTERN_VIDEO_MODE) {
4020                 /* Set CRTC Test Pattern */
4021                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4022                 dp_set_hw_test_pattern(link, test_pattern,
4023                                 (uint8_t *)p_custom_pattern,
4024                                 (uint32_t)cust_pattern_size);
4025
4026                 /* Unblank Stream */
4027                 link->dc->hwss.unblank_stream(
4028                         pipe_ctx,
4029                         &link->verified_link_cap);
4030                 /* TODO:m_pHwss->MuteAudioEndpoint
4031                  * (pPathMode->pDisplayPath, false);
4032                  */
4033
4034                 /* Reset Test Pattern state */
4035                 link->test_pattern_enabled = false;
4036
4037                 return true;
4038         }
4039
4040         /* Check for PHY Test Patterns */
4041         if (is_dp_phy_pattern(test_pattern)) {
4042                 /* Set DPCD Lane Settings before running test pattern */
4043                 if (p_link_settings != NULL) {
4044                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4045                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4046                 }
4047
4048                 /* Blank stream if running test pattern */
4049                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4050                         /*TODO:
4051                          * m_pHwss->
4052                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4053                          */
4054                         /* Blank stream */
4055                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4056                 }
4057
4058                 dp_set_hw_test_pattern(link, test_pattern,
4059                                 (uint8_t *)p_custom_pattern,
4060                                 (uint32_t)cust_pattern_size);
4061
4062                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4063                         /* Set Test Pattern state */
4064                         link->test_pattern_enabled = true;
4065                         if (p_link_settings != NULL)
4066                                 dpcd_set_link_settings(link,
4067                                                 p_link_settings);
4068                 }
4069
4070                 switch (test_pattern) {
4071                 case DP_TEST_PATTERN_VIDEO_MODE:
4072                         pattern = PHY_TEST_PATTERN_NONE;
4073                         break;
4074                 case DP_TEST_PATTERN_D102:
4075                         pattern = PHY_TEST_PATTERN_D10_2;
4076                         break;
4077                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4078                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4079                         break;
4080                 case DP_TEST_PATTERN_PRBS7:
4081                         pattern = PHY_TEST_PATTERN_PRBS7;
4082                         break;
4083                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4084                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4085                         break;
4086                 case DP_TEST_PATTERN_CP2520_1:
4087                         pattern = PHY_TEST_PATTERN_CP2520_1;
4088                         break;
4089                 case DP_TEST_PATTERN_CP2520_2:
4090                         pattern = PHY_TEST_PATTERN_CP2520_2;
4091                         break;
4092                 case DP_TEST_PATTERN_CP2520_3:
4093                         pattern = PHY_TEST_PATTERN_CP2520_3;
4094                         break;
4095                 default:
4096                         return false;
4097                 }
4098
4099                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4100                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4101                         return false;
4102
4103                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4104                         /* tell receiver that we are sending qualification
4105                          * pattern DP 1.2 or later - DP receiver's link quality
4106                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4107                          * register (0x10B~0x10E)\
4108                          */
4109                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4110                                 link_qual_pattern[lane] =
4111                                                 (unsigned char)(pattern);
4112
4113                         core_link_write_dpcd(link,
4114                                         DP_LINK_QUAL_LANE0_SET,
4115                                         link_qual_pattern,
4116                                         sizeof(link_qual_pattern));
4117                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4118                            link->dpcd_caps.dpcd_rev.raw == 0) {
4119                         /* tell receiver that we are sending qualification
4120                          * pattern DP 1.1a or earlier - DP receiver's link
4121                          * quality pattern is set using
4122                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4123                          * register (0x102). We will use v_1.3 when we are
4124                          * setting test pattern for DP 1.1.
4125                          */
4126                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4127                                             &training_pattern.raw,
4128                                             sizeof(training_pattern));
4129                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4130                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4131                                              &training_pattern.raw,
4132                                              sizeof(training_pattern));
4133                 }
4134         } else {
4135                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4136
4137                 switch (test_pattern_color_space) {
4138                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4139                         color_space = COLOR_SPACE_SRGB;
4140                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4141                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4142                         break;
4143
4144                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4145                         color_space = COLOR_SPACE_YCBCR601;
4146                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4147                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4148                         break;
4149                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4150                         color_space = COLOR_SPACE_YCBCR709;
4151                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4152                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4153                         break;
4154                 default:
4155                         break;
4156                 }
4157
4158                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4159                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4160                                 union dmub_hw_lock_flags hw_locks = { 0 };
4161                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4162
4163                                 hw_locks.bits.lock_dig = 1;
4164                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4165
4166                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4167                                                         true,
4168                                                         &hw_locks,
4169                                                         &inst_flags);
4170                         } else
4171                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4172                                                 pipe_ctx->stream_res.tg);
4173                 }
4174
4175                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4176                 /* update MSA to requested color space */
4177                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4178                                 &pipe_ctx->stream->timing,
4179                                 color_space,
4180                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4181                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4182
4183                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4184                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4185                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4186                         else
4187                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4188                         resource_build_info_frame(pipe_ctx);
4189                         link->dc->hwss.update_info_frame(pipe_ctx);
4190                 }
4191
4192                 /* CRTC Patterns */
4193                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4194                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4195                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4196                                 CRTC_STATE_VACTIVE);
4197                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4198                                 CRTC_STATE_VBLANK);
4199                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4200                                 CRTC_STATE_VACTIVE);
4201
4202                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4203                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4204                                 union dmub_hw_lock_flags hw_locks = { 0 };
4205                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4206
4207                                 hw_locks.bits.lock_dig = 1;
4208                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4209
4210                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4211                                                         false,
4212                                                         &hw_locks,
4213                                                         &inst_flags);
4214                         } else
4215                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4216                                                 pipe_ctx->stream_res.tg);
4217                 }
4218
4219                 /* Set Test Pattern state */
4220                 link->test_pattern_enabled = true;
4221         }
4222
4223         return true;
4224 }
4225
4226 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4227 {
4228         unsigned char mstmCntl;
4229
4230         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4231         if (enable)
4232                 mstmCntl |= DP_MST_EN;
4233         else
4234                 mstmCntl &= (~DP_MST_EN);
4235
4236         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4237 }
4238
4239 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4240 {
4241         union dpcd_edp_config edp_config_set;
4242         bool panel_mode_edp = false;
4243
4244         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4245
4246         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4247
4248                 switch (panel_mode) {
4249                 case DP_PANEL_MODE_EDP:
4250                 case DP_PANEL_MODE_SPECIAL:
4251                         panel_mode_edp = true;
4252                         break;
4253
4254                 default:
4255                                 break;
4256                 }
4257
4258                 /*set edp panel mode in receiver*/
4259                 core_link_read_dpcd(
4260                         link,
4261                         DP_EDP_CONFIGURATION_SET,
4262                         &edp_config_set.raw,
4263                         sizeof(edp_config_set.raw));
4264
4265                 if (edp_config_set.bits.PANEL_MODE_EDP
4266                         != panel_mode_edp) {
4267                         enum dc_status result = DC_ERROR_UNEXPECTED;
4268
4269                         edp_config_set.bits.PANEL_MODE_EDP =
4270                         panel_mode_edp;
4271                         result = core_link_write_dpcd(
4272                                 link,
4273                                 DP_EDP_CONFIGURATION_SET,
4274                                 &edp_config_set.raw,
4275                                 sizeof(edp_config_set.raw));
4276
4277                         ASSERT(result == DC_OK);
4278                 }
4279         }
4280         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4281                  "eDP panel mode enabled: %d \n",
4282                  link->link_index,
4283                  link->dpcd_caps.panel_mode_edp,
4284                  panel_mode_edp);
4285 }
4286
4287 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4288 {
4289         /* We need to explicitly check that connector
4290          * is not DP. Some Travis_VGA get reported
4291          * by video bios as DP.
4292          */
4293         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4294
4295                 switch (link->dpcd_caps.branch_dev_id) {
4296                 case DP_BRANCH_DEVICE_ID_0022B9:
4297                         /* alternate scrambler reset is required for Travis
4298                          * for the case when external chip does not
4299                          * provide sink device id, alternate scrambler
4300                          * scheme will  be overriden later by querying
4301                          * Encoder features
4302                          */
4303                         if (strncmp(
4304                                 link->dpcd_caps.branch_dev_name,
4305                                 DP_VGA_LVDS_CONVERTER_ID_2,
4306                                 sizeof(
4307                                 link->dpcd_caps.
4308                                 branch_dev_name)) == 0) {
4309                                         return DP_PANEL_MODE_SPECIAL;
4310                         }
4311                         break;
4312                 case DP_BRANCH_DEVICE_ID_00001A:
4313                         /* alternate scrambler reset is required for Travis
4314                          * for the case when external chip does not provide
4315                          * sink device id, alternate scrambler scheme will
4316                          * be overriden later by querying Encoder feature
4317                          */
4318                         if (strncmp(link->dpcd_caps.branch_dev_name,
4319                                 DP_VGA_LVDS_CONVERTER_ID_3,
4320                                 sizeof(
4321                                 link->dpcd_caps.
4322                                 branch_dev_name)) == 0) {
4323                                         return DP_PANEL_MODE_SPECIAL;
4324                         }
4325                         break;
4326                 default:
4327                         break;
4328                 }
4329         }
4330
4331         if (link->dpcd_caps.panel_mode_edp) {
4332                 return DP_PANEL_MODE_EDP;
4333         }
4334
4335         return DP_PANEL_MODE_DEFAULT;
4336 }
4337
4338 void dp_set_fec_ready(struct dc_link *link, bool ready)
4339 {
4340         /* FEC has to be "set ready" before the link training.
4341          * The policy is to always train with FEC
4342          * if the sink supports it and leave it enabled on link.
4343          * If FEC is not supported, disable it.
4344          */
4345         struct link_encoder *link_enc = link->link_enc;
4346         uint8_t fec_config = 0;
4347
4348         if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4349                 return;
4350
4351         if (link_enc->funcs->fec_set_ready &&
4352                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4353                 if (ready) {
4354                         fec_config = 1;
4355                         if (core_link_write_dpcd(link,
4356                                         DP_FEC_CONFIGURATION,
4357                                         &fec_config,
4358                                         sizeof(fec_config)) == DC_OK) {
4359                                 link_enc->funcs->fec_set_ready(link_enc, true);
4360                                 link->fec_state = dc_link_fec_ready;
4361                         } else {
4362                                 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4363                                 link->fec_state = dc_link_fec_not_ready;
4364                                 dm_error("dpcd write failed to set fec_ready");
4365                         }
4366                 } else if (link->fec_state == dc_link_fec_ready) {
4367                         fec_config = 0;
4368                         core_link_write_dpcd(link,
4369                                         DP_FEC_CONFIGURATION,
4370                                         &fec_config,
4371                                         sizeof(fec_config));
4372                         link->link_enc->funcs->fec_set_ready(
4373                                         link->link_enc, false);
4374                         link->fec_state = dc_link_fec_not_ready;
4375                 }
4376         }
4377 }
4378
4379 void dp_set_fec_enable(struct dc_link *link, bool enable)
4380 {
4381         struct link_encoder *link_enc = link->link_enc;
4382
4383         if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4384                 return;
4385
4386         if (link_enc->funcs->fec_set_enable &&
4387                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4388                 if (link->fec_state == dc_link_fec_ready && enable) {
4389                         /* Accord to DP spec, FEC enable sequence can first
4390                          * be transmitted anytime after 1000 LL codes have
4391                          * been transmitted on the link after link training
4392                          * completion. Using 1 lane RBR should have the maximum
4393                          * time for transmitting 1000 LL codes which is 6.173 us.
4394                          * So use 7 microseconds delay instead.
4395                          */
4396                         udelay(7);
4397                         link_enc->funcs->fec_set_enable(link_enc, true);
4398                         link->fec_state = dc_link_fec_enabled;
4399                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4400                         link_enc->funcs->fec_set_enable(link_enc, false);
4401                         link->fec_state = dc_link_fec_ready;
4402                 }
4403         }
4404 }
4405
4406 void dpcd_set_source_specific_data(struct dc_link *link)
4407 {
4408         if (!link->dc->vendor_signature.is_valid) {
4409                 enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;
4410                 struct dpcd_amd_signature amd_signature;
4411                 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4412                 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4413                 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4414                 amd_signature.device_id_byte1 =
4415                                 (uint8_t)(link->ctx->asic_id.chip_id);
4416                 amd_signature.device_id_byte2 =
4417                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4418                 memset(&amd_signature.zero, 0, 4);
4419                 amd_signature.dce_version =
4420                                 (uint8_t)(link->ctx->dce_version);
4421                 amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
4422                 amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
4423
4424                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4425                                 (uint8_t *)(&amd_signature),
4426                                 sizeof(amd_signature));
4427
4428                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4429                         link->dc->caps.min_horizontal_blanking_period != 0) {
4430
4431                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4432
4433                         result_write_min_hblank = core_link_write_dpcd(link,
4434                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4435                                 sizeof(hblank_size));
4436                 }
4437                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4438                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4439                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4440                                                         result_write_min_hblank,
4441                                                         link->link_index,
4442                                                         link->ctx->dce_version,
4443                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4444                                                         link->dc->caps.min_horizontal_blanking_period,
4445                                                         link->dpcd_caps.branch_dev_id,
4446                                                         link->dpcd_caps.branch_dev_name[0],
4447                                                         link->dpcd_caps.branch_dev_name[1],
4448                                                         link->dpcd_caps.branch_dev_name[2],
4449                                                         link->dpcd_caps.branch_dev_name[3],
4450                                                         link->dpcd_caps.branch_dev_name[4],
4451                                                         link->dpcd_caps.branch_dev_name[5]);
4452         } else {
4453                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4454                                 link->dc->vendor_signature.data.raw,
4455                                 sizeof(link->dc->vendor_signature.data.raw));
4456         }
4457 }
4458
4459 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4460                 bool isHDR,
4461                 uint32_t backlight_millinits,
4462                 uint32_t transition_time_in_ms)
4463 {
4464         struct dpcd_source_backlight_set dpcd_backlight_set;
4465         uint8_t backlight_control = isHDR ? 1 : 0;
4466
4467         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4468                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4469                 return false;
4470
4471         // OLEDs have no PWM, they can only use AUX
4472         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4473                 backlight_control = 1;
4474
4475         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4476         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4477
4478
4479         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4480                         (uint8_t *)(&dpcd_backlight_set),
4481                         sizeof(dpcd_backlight_set)) != DC_OK)
4482                 return false;
4483
4484         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4485                         &backlight_control, 1) != DC_OK)
4486                 return false;
4487
4488         return true;
4489 }
4490
4491 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4492                 uint32_t *backlight_millinits_avg,
4493                 uint32_t *backlight_millinits_peak)
4494 {
4495         union dpcd_source_backlight_get dpcd_backlight_get;
4496
4497         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4498
4499         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4500                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4501                 return false;
4502
4503         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4504                         dpcd_backlight_get.raw,
4505                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4506                 return false;
4507
4508         *backlight_millinits_avg =
4509                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4510         *backlight_millinits_peak =
4511                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4512
4513         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4514         if (*backlight_millinits_avg == 0 ||
4515                         *backlight_millinits_avg > *backlight_millinits_peak)
4516                 return false;
4517
4518         return true;
4519 }
4520
4521 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4522 {
4523         uint8_t backlight_enable = enable ? 1 : 0;
4524
4525         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4526                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4527                 return false;
4528
4529         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4530                 &backlight_enable, 1) != DC_OK)
4531                 return false;
4532
4533         return true;
4534 }
4535
4536 // we read default from 0x320 because we expect BIOS wrote it there
4537 // regular get_backlight_nit reads from panel set at 0x326
4538 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4539 {
4540         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4541                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4542                 return false;
4543
4544         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4545                 (uint8_t *) backlight_millinits,
4546                 sizeof(uint32_t)) != DC_OK)
4547                 return false;
4548
4549         return true;
4550 }
4551
4552 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4553 {
4554         uint32_t default_backlight;
4555
4556         if (link &&
4557                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4558                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4559                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4560                         default_backlight = 150000;
4561                 // if < 5 nits or > 5000, it might be wrong readback
4562                 if (default_backlight < 5000 || default_backlight > 5000000)
4563                         default_backlight = 150000; //
4564
4565                 return dc_link_set_backlight_level_nits(link, true,
4566                                 default_backlight, 0);
4567         }
4568         return false;
4569 }