drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atom.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48
  49 #define DC_LOGGER_INIT(logger)
  50
  51
  52 #define LINK_INFO(...) \
  53         DC_LOG_HW_HOTPLUG(  \
  54                 __VA_ARGS__)
  55
  56 #define RETIMER_REDRIVER_INFO(...) \
  57         DC_LOG_RETIMER_REDRIVER(  \
  58                 __VA_ARGS__)
  59 /*******************************************************************************
  60  * Private structures
  61  ******************************************************************************/
  62
  63 enum {
  64         PEAK_FACTOR_X1000 = 1006,
  65         /*
  66         * Some receivers fail to train on first try and are good
  67         * on subsequent tries. 2 retries should be plenty. If we
  68         * don't have a successful training then we don't expect to
  69         * ever get one.
  70         */
  71         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  72 };
  73
  74 /*******************************************************************************
  75  * Private functions
  76  ******************************************************************************/
  77 static void destruct(struct dc_link *link)
  78 {
  79         int i;
  80
  81         if (link->hpd_gpio != NULL) {
  82                 dal_gpio_destroy_irq(&link->hpd_gpio);
  83                 link->hpd_gpio = NULL;
  84         }
  85
  86         if (link->ddc)
  87                 dal_ddc_service_destroy(&link->ddc);
  88
  89         if(link->link_enc)
  90                 link->link_enc->funcs->destroy(&link->link_enc);
  91
  92         if (link->local_sink)
  93                 dc_sink_release(link->local_sink);
  94
  95         for (i = 0; i < link->sink_count; ++i)
  96                 dc_sink_release(link->remote_sinks[i]);
  97 }
  98
  99 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 100                 struct graphics_object_id link_id,
 101                 struct gpio_service *gpio_service)
 102 {
 103         enum bp_result bp_result;
 104         struct graphics_object_hpd_info hpd_info;
 105         struct gpio_pin_info pin_info;
 106
 107         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 108                 return NULL;
 109
 110         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 111                 hpd_info.hpd_int_gpio_uid, &pin_info);
 112
 113         if (bp_result != BP_RESULT_OK) {
 114                 ASSERT(bp_result == BP_RESULT_NORECORD);
 115                 return NULL;
 116         }
 117
 118         return dal_gpio_service_create_irq(
 119                 gpio_service,
 120                 pin_info.offset,
 121                 pin_info.mask);
 122 }
 123
 124 /*
 125  *  Function: program_hpd_filter
 126  *
 127  *  @brief
 128  *     Programs HPD filter on associated HPD line
 129  *
 130  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 131  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 132  *
 133  *  @return
 134  *     true on success, false otherwise
 135  */
 136 static bool program_hpd_filter(
 137         const struct dc_link *link)
 138 {
 139         bool result = false;
 140
 141         struct gpio *hpd;
 142
 143         int delay_on_connect_in_ms = 0;
 144         int delay_on_disconnect_in_ms = 0;
 145
 146         if (link->is_hpd_filter_disabled)
 147                 return false;
 148         /* Verify feature is supported */
 149         switch (link->connector_signal) {
 150         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 151         case SIGNAL_TYPE_DVI_DUAL_LINK:
 152         case SIGNAL_TYPE_HDMI_TYPE_A:
 153                 /* Program hpd filter */
 154                 delay_on_connect_in_ms = 500;
 155                 delay_on_disconnect_in_ms = 100;
 156                 break;
 157         case SIGNAL_TYPE_DISPLAY_PORT:
 158         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 159                 /* Program hpd filter to allow DP signal to settle */
 160                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 161                  *      only 100ms on DELL U2413
 162                  * 0:   some passive dongle still show aux mode instead of i2c
 163                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 164                  *      also see intermittent i2c read issues.
 165                  */
 166                 delay_on_connect_in_ms = 80;
 167                 delay_on_disconnect_in_ms = 0;
 168                 break;
 169         case SIGNAL_TYPE_LVDS:
 170         case SIGNAL_TYPE_EDP:
 171         default:
 172                 /* Don't program hpd filter */
 173                 return false;
 174         }
 175
 176         /* Obtain HPD handle */
 177         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 178
 179         if (!hpd)
 180                 return result;
 181
 182         /* Setup HPD filtering */
 183         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 184                 struct gpio_hpd_config config;
 185
 186                 config.delay_on_connect = delay_on_connect_in_ms;
 187                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 188
 189                 dal_irq_setup_hpd_filter(hpd, &config);
 190
 191                 dal_gpio_close(hpd);
 192
 193                 result = true;
 194         } else {
 195                 ASSERT_CRITICAL(false);
 196         }
 197
 198         /* Release HPD handle */
 199         dal_gpio_destroy_irq(&hpd);
 200
 201         return result;
 202 }
 203
 204 /**
 205  * dc_link_detect_sink() - Determine if there is a sink connected
 206  *
 207  * @type: Returned connection type
 208  * Does not detect downstream devices, such as MST sinks
 209  * or display connected through active dongles
 210  */
 211 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 212 {
 213         uint32_t is_hpd_high = 0;
 214         struct gpio *hpd_pin;
 215
 216         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 217                 *type = dc_connection_single;
 218                 return true;
 219         }
 220
 221         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 222                 /*in case it is not on*/
 223                 link->dc->hwss.edp_power_control(link, true);
 224                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 225         }
 226
 227         /* todo: may need to lock gpio access */
 228         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 229         if (hpd_pin == NULL)
 230                 goto hpd_gpio_failure;
 231
 232         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 233         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 234         dal_gpio_close(hpd_pin);
 235         dal_gpio_destroy_irq(&hpd_pin);
 236
 237         if (is_hpd_high) {
 238                 *type = dc_connection_single;
 239                 /* TODO: need to do the actual detection */
 240         } else {
 241                 *type = dc_connection_none;
 242         }
 243
 244         return true;
 245
 246 hpd_gpio_failure:
 247         return false;
 248 }
 249
 250 static enum ddc_transaction_type get_ddc_transaction_type(
 251                 enum signal_type sink_signal)
 252 {
 253         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 254
 255         switch (sink_signal) {
 256         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 257         case SIGNAL_TYPE_DVI_DUAL_LINK:
 258         case SIGNAL_TYPE_HDMI_TYPE_A:
 259         case SIGNAL_TYPE_LVDS:
 260         case SIGNAL_TYPE_RGB:
 261                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 262                 break;
 263
 264         case SIGNAL_TYPE_DISPLAY_PORT:
 265         case SIGNAL_TYPE_EDP:
 266                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 267                 break;
 268
 269         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 270                 /* MST does not use I2COverAux, but there is the
 271                  * SPECIAL use case for "immediate dwnstrm device
 272                  * access" (EPR#370830). */
 273                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 274                 break;
 275
 276         default:
 277                 break;
 278         }
 279
 280         return transaction_type;
 281 }
 282
 283 static enum signal_type get_basic_signal_type(
 284         struct graphics_object_id encoder,
 285         struct graphics_object_id downstream)
 286 {
 287         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 288                 switch (downstream.id) {
 289                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 290                         switch (encoder.id) {
 291                         case ENCODER_ID_INTERNAL_DAC1:
 292                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 293                         case ENCODER_ID_INTERNAL_DAC2:
 294                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 295                                 return SIGNAL_TYPE_RGB;
 296                         default:
 297                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 298                         }
 299                 break;
 300                 case CONNECTOR_ID_DUAL_LINK_DVII:
 301                 {
 302                         switch (encoder.id) {
 303                         case ENCODER_ID_INTERNAL_DAC1:
 304                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 305                         case ENCODER_ID_INTERNAL_DAC2:
 306                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 307                                 return SIGNAL_TYPE_RGB;
 308                         default:
 309                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 310                         }
 311                 }
 312                 break;
 313                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 314                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 315                 case CONNECTOR_ID_DUAL_LINK_DVID:
 316                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 317                 case CONNECTOR_ID_VGA:
 318                         return SIGNAL_TYPE_RGB;
 319                 case CONNECTOR_ID_HDMI_TYPE_A:
 320                         return SIGNAL_TYPE_HDMI_TYPE_A;
 321                 case CONNECTOR_ID_LVDS:
 322                         return SIGNAL_TYPE_LVDS;
 323                 case CONNECTOR_ID_DISPLAY_PORT:
 324                         return SIGNAL_TYPE_DISPLAY_PORT;
 325                 case CONNECTOR_ID_EDP:
 326                         return SIGNAL_TYPE_EDP;
 327                 default:
 328                         return SIGNAL_TYPE_NONE;
 329                 }
 330         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 331                 switch (downstream.id) {
 332                 case ENCODER_ID_EXTERNAL_NUTMEG:
 333                 case ENCODER_ID_EXTERNAL_TRAVIS:
 334                         return SIGNAL_TYPE_DISPLAY_PORT;
 335                 default:
 336                         return SIGNAL_TYPE_NONE;
 337                 }
 338         }
 339
 340         return SIGNAL_TYPE_NONE;
 341 }
 342
 343 /**
 344  * dc_link_is_dp_sink_present() - Check if there is a native DP
 345  * or passive DP-HDMI dongle connected
 346  */
 347 bool dc_link_is_dp_sink_present(struct dc_link *link)
 348 {
 349         enum gpio_result gpio_result;
 350         uint32_t clock_pin = 0;
 351         uint8_t retry = 0;
 352         struct ddc *ddc;
 353
 354         enum connector_id connector_id =
 355                 dal_graphics_object_id_get_connector_id(link->link_id);
 356
 357         bool present =
 358                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 359                 (connector_id == CONNECTOR_ID_EDP));
 360
 361         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 362
 363         if (!ddc) {
 364                 BREAK_TO_DEBUGGER();
 365                 return present;
 366         }
 367
 368         /* Open GPIO and set it to I2C mode */
 369         /* Note: this GpioMode_Input will be converted
 370          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 371          * which indicates we need additional delay */
 372
 373         if (GPIO_RESULT_OK != dal_ddc_open(
 374                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 375                 dal_gpio_destroy_ddc(&ddc);
 376
 377                 return present;
 378         }
 379
 380         /*
 381          * Read GPIO: DP sink is present if both clock and data pins are zero
 382          *
 383          * [W/A] plug-unplug DP cable, sometimes customer board has
 384          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 385          * then monitor can't br light up. Add retry 3 times
 386          * But in real passive dongle, it need additional 3ms to detect
 387          */
 388         do {
 389                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 390                 ASSERT(gpio_result == GPIO_RESULT_OK);
 391                 if (clock_pin)
 392                         udelay(1000);
 393                 else
 394                         break;
 395         } while (retry++ < 3);
 396
 397         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 398
 399         dal_ddc_close(ddc);
 400
 401         return present;
 402 }
 403
 404 /*
 405  * @brief
 406  * Detect output sink type
 407  */
 408 static enum signal_type link_detect_sink(
 409         struct dc_link *link,
 410         enum dc_detect_reason reason)
 411 {
 412         enum signal_type result = get_basic_signal_type(
 413                 link->link_enc->id, link->link_id);
 414
 415         /* Internal digital encoder will detect only dongles
 416          * that require digital signal */
 417
 418         /* Detection mechanism is different
 419          * for different native connectors.
 420          * LVDS connector supports only LVDS signal;
 421          * PCIE is a bus slot, the actual connector needs to be detected first;
 422          * eDP connector supports only eDP signal;
 423          * HDMI should check straps for audio */
 424
 425         /* PCIE detects the actual connector on add-on board */
 426
 427         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 428                 /* ZAZTODO implement PCIE add-on card detection */
 429         }
 430
 431         switch (link->link_id.id) {
 432         case CONNECTOR_ID_HDMI_TYPE_A: {
 433                 /* check audio support:
 434                  * if native HDMI is not supported, switch to DVI */
 435                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 436
 437                 if (!aud_support->hdmi_audio_native)
 438                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 439                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 440         }
 441         break;
 442         case CONNECTOR_ID_DISPLAY_PORT: {
 443                 /* DP HPD short pulse. Passive DP dongle will not
 444                  * have short pulse
 445                  */
 446                 if (reason != DETECT_REASON_HPDRX) {
 447                         /* Check whether DP signal detected: if not -
 448                          * we assume signal is DVI; it could be corrected
 449                          * to HDMI after dongle detection
 450                          */
 451                         if (!dm_helpers_is_dp_sink_present(link))
 452                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 453                 }
 454         }
 455         break;
 456         default:
 457         break;
 458         }
 459
 460         return result;
 461 }
 462
 463 static enum signal_type decide_signal_from_strap_and_dongle_type(
 464                 enum display_dongle_type dongle_type,
 465                 struct audio_support *audio_support)
 466 {
 467         enum signal_type signal = SIGNAL_TYPE_NONE;
 468
 469         switch (dongle_type) {
 470         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 471                 if (audio_support->hdmi_audio_on_dongle)
 472                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 473                 else
 474                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 475                 break;
 476         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 477                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 478                 break;
 479         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 480                 if (audio_support->hdmi_audio_native)
 481                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 482                 else
 483                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 484                 break;
 485         default:
 486                 signal = SIGNAL_TYPE_NONE;
 487                 break;
 488         }
 489
 490         return signal;
 491 }
 492
 493 static enum signal_type dp_passive_dongle_detection(
 494                 struct ddc_service *ddc,
 495                 struct display_sink_capability *sink_cap,
 496                 struct audio_support *audio_support)
 497 {
 498         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 499                                                 ddc, sink_cap);
 500         return decide_signal_from_strap_and_dongle_type(
 501                         sink_cap->dongle_type,
 502                         audio_support);
 503 }
 504
 505 static void link_disconnect_sink(struct dc_link *link)
 506 {
 507         if (link->local_sink) {
 508                 dc_sink_release(link->local_sink);
 509                 link->local_sink = NULL;
 510         }
 511
 512         link->dpcd_sink_count = 0;
 513 }
 514
 515 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 516 {
 517         dc_sink_release(link->local_sink);
 518         link->local_sink = prev_sink;
 519 }
 520
 521
 522 static void read_current_link_settings_on_detect(struct dc_link *link)
 523 {
 524         union lane_count_set lane_count_set = { {0} };
 525         uint8_t link_bw_set;
 526         uint8_t link_rate_set;
 527         uint32_t read_dpcd_retry_cnt = 10;
 528         enum dc_status status = DC_ERROR_UNEXPECTED;
 529         int i;
 530         union max_down_spread max_down_spread = { {0} };
 531
 532         // Read DPCD 00101h to find out the number of lanes currently set
 533         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 534                 status = core_link_read_dpcd(
 535                                 link,
 536                                 DP_LANE_COUNT_SET,
 537                                 &lane_count_set.raw,
 538                                 sizeof(lane_count_set));
 539                 /* First DPCD read after VDD ON can fail if the particular board
 540                  * does not have HPD pin wired correctly. So if DPCD read fails,
 541                  * which it should never happen, retry a few times. Target worst
 542                  * case scenario of 80 ms.
 543                  */
 544                 if (status == DC_OK) {
 545                         link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
 546                         break;
 547                 }
 548
 549                 msleep(8);
 550         }
 551
 552         // Read DPCD 00100h to find if standard link rates are set
 553         core_link_read_dpcd(link, DP_LINK_BW_SET,
 554                         &link_bw_set, sizeof(link_bw_set));
 555
 556         if (link_bw_set == 0) {
 557                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 558                         /* If standard link rates are not being used,
 559                          * Read DPCD 00115h to find the edp link rate set used
 560                          */
 561                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 562                                         &link_rate_set, sizeof(link_rate_set));
 563
 564                         // edp_supported_link_rates_count = 0 for DP
 565                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 566                                 link->cur_link_settings.link_rate =
 567                                                 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 568                                 link->cur_link_settings.link_rate_set = link_rate_set;
 569                                 link->cur_link_settings.use_link_rate_set = true;
 570                         }
 571                 } else {
 572                         // Link Rate not found. Seamless boot may not work.
 573                         ASSERT(false);
 574                 }
 575         } else {
 576                 link->cur_link_settings.link_rate = link_bw_set;
 577                 link->cur_link_settings.use_link_rate_set = false;
 578         }
 579         // Read DPCD 00003h to find the max down spread.
 580         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 581                         &max_down_spread.raw, sizeof(max_down_spread));
 582         link->cur_link_settings.link_spread =
 583                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 584                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 585 }
 586
 587 static bool detect_dp(
 588         struct dc_link *link,
 589         struct display_sink_capability *sink_caps,
 590         bool *converter_disable_audio,
 591         struct audio_support *audio_support,
 592         enum dc_detect_reason reason)
 593 {
 594         bool boot = false;
 595         sink_caps->signal = link_detect_sink(link, reason);
 596         sink_caps->transaction_type =
 597                 get_ddc_transaction_type(sink_caps->signal);
 598
 599         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 600                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 601                 if (!detect_dp_sink_caps(link))
 602                         return false;
 603
 604                 if (is_mst_supported(link)) {
 605                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 606                         link->type = dc_connection_mst_branch;
 607
 608                         dal_ddc_service_set_transaction_type(
 609                                                         link->ddc,
 610                                                         sink_caps->transaction_type);
 611
 612                         /*
 613                          * This call will initiate MST topology discovery. Which
 614                          * will detect MST ports and add new DRM connector DRM
 615                          * framework. Then read EDID via remote i2c over aux. In
 616                          * the end, will notify DRM detect result and save EDID
 617                          * into DRM framework.
 618                          *
 619                          * .detect is called by .fill_modes.
 620                          * .fill_modes is called by user mode ioctl
 621                          * DRM_IOCTL_MODE_GETCONNECTOR.
 622                          *
 623                          * .get_modes is called by .fill_modes.
 624                          *
 625                          * call .get_modes, AMDGPU DM implementation will create
 626                          * new dc_sink and add to dc_link. For long HPD plug
 627                          * in/out, MST has its own handle.
 628                          *
 629                          * Therefore, just after dc_create, link->sink is not
 630                          * created for MST until user mode app calls
 631                          * DRM_IOCTL_MODE_GETCONNECTOR.
 632                          *
 633                          * Need check ->sink usages in case ->sink = NULL
 634                          * TODO: s3 resume check
 635                          */
 636                         if (reason == DETECT_REASON_BOOT)
 637                                 boot = true;
 638
 639                         dm_helpers_dp_update_branch_info(
 640                                 link->ctx,
 641                                 link);
 642
 643                         if (!dm_helpers_dp_mst_start_top_mgr(
 644                                 link->ctx,
 645                                 link, boot)) {
 646                                 /* MST not supported */
 647                                 link->type = dc_connection_single;
 648                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 649                         }
 650                 }
 651
 652                 if (link->type != dc_connection_mst_branch &&
 653                         is_dp_active_dongle(link)) {
 654                         /* DP active dongles */
 655                         link->type = dc_connection_active_dongle;
 656                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 657                                 /*
 658                                  * active dongle unplug processing for short irq
 659                                  */
 660                                 link_disconnect_sink(link);
 661                                 return true;
 662                         }
 663
 664                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 665                                 *converter_disable_audio = true;
 666                 }
 667         } else {
 668                 /* DP passive dongles */
 669                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 670                                 sink_caps,
 671                                 audio_support);
 672         }
 673
 674         return true;
 675 }
 676
 677 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 678 {
 679         if (old_edid->length != new_edid->length)
 680                 return false;
 681
 682         if (new_edid->length == 0)
 683                 return false;
 684
 685         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 686 }
 687
 688 static bool wait_for_alt_mode(struct dc_link *link)
 689 {
 690
 691         /**
 692          * something is terribly wrong if time out is > 200ms. (5Hz)
 693          * 500 microseconds * 400 tries us 200 ms
 694          **/
 695         unsigned int sleep_time_in_microseconds = 500;
 696         unsigned int tries_allowed = 400;
 697         bool is_in_alt_mode;
 698         unsigned long long enter_timestamp;
 699         unsigned long long finish_timestamp;
 700         unsigned long long time_taken_in_ns;
 701         int tries_taken;
 702
 703         DC_LOGGER_INIT(link->ctx->logger);
 704
 705         if (link->link_enc->funcs->is_in_alt_mode == NULL)
 706                 return true;
 707
 708         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 709         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 710
 711         if (is_in_alt_mode)
 712                 return true;
 713
 714         enter_timestamp = dm_get_timestamp(link->ctx);
 715
 716         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 717                 udelay(sleep_time_in_microseconds);
 718                 /* ask the link if alt mode is enabled, if so return ok */
 719                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 720
 721                         finish_timestamp = dm_get_timestamp(link->ctx);
 722                         time_taken_in_ns = dm_get_elapse_time_in_ns(
 723                                 link->ctx, finish_timestamp, enter_timestamp);
 724                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 725                                        div_u64(time_taken_in_ns, 1000000));
 726                         return true;
 727                 }
 728
 729         }
 730         finish_timestamp = dm_get_timestamp(link->ctx);
 731         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 732                                                     enter_timestamp);
 733         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 734                         div_u64(time_taken_in_ns, 1000000));
 735         return false;
 736 }
 737
 738 /**
 739  * dc_link_detect() - Detect if a sink is attached to a given link
 740  *
 741  * link->local_sink is created or destroyed as needed.
 742  *
 743  * This does not create remote sinks but will trigger DM
 744  * to start MST detection if a branch is detected.
 745  */
 746 bool dc_link_detect_helper(struct dc_link *link, enum dc_detect_reason reason)
 747 {
 748         struct dc_sink_init_data sink_init_data = { 0 };
 749         struct display_sink_capability sink_caps = { 0 };
 750         uint8_t i;
 751         bool converter_disable_audio = false;
 752         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 753         bool same_edid = false;
 754         enum dc_edid_status edid_status;
 755         struct dc_context *dc_ctx = link->ctx;
 756         struct dc_sink *sink = NULL;
 757         struct dc_sink *prev_sink = NULL;
 758         struct dpcd_caps prev_dpcd_caps;
 759         bool same_dpcd = true;
 760         enum dc_connection_type new_connection_type = dc_connection_none;
 761         bool perform_dp_seamless_boot = false;
 762
 763         DC_LOGGER_INIT(link->ctx->logger);
 764
 765         if (dc_is_virtual_signal(link->connector_signal))
 766                 return false;
 767
 768         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 769                         link->connector_signal == SIGNAL_TYPE_EDP) &&
 770                         link->local_sink)
 771                 return true;
 772
 773         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 774                 BREAK_TO_DEBUGGER();
 775                 return false;
 776         }
 777
 778         prev_sink = link->local_sink;
 779         if (prev_sink != NULL) {
 780                 dc_sink_retain(prev_sink);
 781                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 782         }
 783         link_disconnect_sink(link);
 784
 785         if (new_connection_type != dc_connection_none) {
 786                 link->type = new_connection_type;
 787                 link->link_state_valid = false;
 788
 789                 /* From Disconnected-to-Connected. */
 790                 switch (link->connector_signal) {
 791                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 792                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 793                         if (aud_support->hdmi_audio_native)
 794                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 795                         else
 796                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 797                         break;
 798                 }
 799
 800                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 801                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 802                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 803                         break;
 804                 }
 805
 806                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 807                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 808                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 809                         break;
 810                 }
 811
 812                 case SIGNAL_TYPE_LVDS: {
 813                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 814                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 815                         break;
 816                 }
 817
 818                 case SIGNAL_TYPE_EDP: {
 819                         read_current_link_settings_on_detect(link);
 820                         detect_edp_sink_caps(link);
 821                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 822                         sink_caps.signal = SIGNAL_TYPE_EDP;
 823                         break;
 824                 }
 825
 826                 case SIGNAL_TYPE_DISPLAY_PORT: {
 827
 828                         /* wa HPD high coming too early*/
 829                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 830
 831                                 /* if alt mode times out, return false */
 832                                 if (wait_for_alt_mode(link) == false) {
 833                                         return false;
 834                                 }
 835                         }
 836
 837                         if (!detect_dp(
 838                                 link,
 839                                 &sink_caps,
 840                                 &converter_disable_audio,
 841                                 aud_support, reason)) {
 842                                 if (prev_sink != NULL)
 843                                         dc_sink_release(prev_sink);
 844                                 return false;
 845                         }
 846
 847                         // Check if dpcp block is the same
 848                         if (prev_sink != NULL) {
 849                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 850                                         same_dpcd = false;
 851                         }
 852                         /* Active dongle plug in without display or downstream unplug*/
 853                         if (link->type == dc_connection_active_dongle &&
 854                                 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 855                                 if (prev_sink != NULL) {
 856                                         /* Downstream unplug */
 857                                         dc_sink_release(prev_sink);
 858                                 } else {
 859                                         /* Empty dongle plug in */
 860                                         dp_verify_link_cap_with_retries(link,
 861                                                         &link->reported_link_cap,
 862                                                         LINK_TRAINING_MAX_VERIFY_RETRY);
 863                                 }
 864                                 return true;
 865                         }
 866
 867                         if (link->type == dc_connection_mst_branch) {
 868                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 869                                         link->link_index);
 870                                 /* Need to setup mst link_cap struct here
 871                                  * otherwise dc_link_detect() will leave mst link_cap
 872                                  * empty which leads to allocate_mst_payload() has "0"
 873                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 874                                  */
 875                                 dp_verify_mst_link_cap(link);
 876
 877                                 if (prev_sink != NULL)
 878                                         dc_sink_release(prev_sink);
 879                                 return false;
 880                         }
 881
 882                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 883                         if (reason == DETECT_REASON_BOOT &&
 884                                         dc_ctx->dc->config.power_down_display_on_boot == false &&
 885                                         link->link_status.link_active == true)
 886                                 perform_dp_seamless_boot = true;
 887
 888                         if (perform_dp_seamless_boot) {
 889                                 read_current_link_settings_on_detect(link);
 890                                 link->verified_link_cap = link->reported_link_cap;
 891                         }
 892
 893                         break;
 894                 }
 895
 896                 default:
 897                         DC_ERROR("Invalid connector type! signal:%d\n",
 898                                 link->connector_signal);
 899                         if (prev_sink != NULL)
 900                                 dc_sink_release(prev_sink);
 901                         return false;
 902                 } /* switch() */
 903
 904                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 905                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 906                                         bits.SINK_COUNT;
 907                 else
 908                         link->dpcd_sink_count = 1;
 909
 910                 dal_ddc_service_set_transaction_type(
 911                                                 link->ddc,
 912                                                 sink_caps.transaction_type);
 913
 914                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 915                                 link->ddc);
 916
 917                 sink_init_data.link = link;
 918                 sink_init_data.sink_signal = sink_caps.signal;
 919
 920                 sink = dc_sink_create(&sink_init_data);
 921                 if (!sink) {
 922                         DC_ERROR("Failed to create sink!\n");
 923                         if (prev_sink != NULL)
 924                                 dc_sink_release(prev_sink);
 925                         return false;
 926                 }
 927
 928                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 929                 sink->converter_disable_audio = converter_disable_audio;
 930
 931                 /* dc_sink_create returns a new reference */
 932                 link->local_sink = sink;
 933
 934                 edid_status = dm_helpers_read_local_edid(
 935                                 link->ctx,
 936                                 link,
 937                                 sink);
 938
 939                 switch (edid_status) {
 940                 case EDID_BAD_CHECKSUM:
 941                         DC_LOG_ERROR("EDID checksum invalid.\n");
 942                         break;
 943                 case EDID_NO_RESPONSE:
 944                         DC_LOG_ERROR("No EDID read.\n");
 945
 946                         /*
 947                          * Abort detection for non-DP connectors if we have
 948                          * no EDID
 949                          *
 950                          * DP needs to report as connected if HDP is high
 951                          * even if we have no EDID in order to go to
 952                          * fail-safe mode
 953                          */
 954                         if (dc_is_hdmi_signal(link->connector_signal) ||
 955                             dc_is_dvi_signal(link->connector_signal)) {
 956                                 if (prev_sink != NULL)
 957                                         dc_sink_release(prev_sink);
 958
 959                                 return false;
 960                         }
 961                 default:
 962                         break;
 963                 }
 964
 965                 // Check if edid is the same
 966                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 967                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 968
 969                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 970                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
 971                         reason != DETECT_REASON_HPDRX) {
 972                         /*
 973                          * TODO debug why Dell 2413 doesn't like
 974                          *  two link trainings
 975                          */
 976
 977                         // verify link cap for SST non-seamless boot
 978                         if (!perform_dp_seamless_boot)
 979                                 dp_verify_link_cap_with_retries(link,
 980                                                 &link->reported_link_cap,
 981                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 982                 } else {
 983                         // If edid is the same, then discard new sink and revert back to original sink
 984                         if (same_edid) {
 985                                 link_disconnect_remap(prev_sink, link);
 986                                 sink = prev_sink;
 987                                 prev_sink = NULL;
 988
 989                         }
 990                 }
 991
 992                 /* HDMI-DVI Dongle */
 993                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 994                                 !sink->edid_caps.edid_hdmi)
 995                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 996
 997                 /* Connectivity log: detection */
 998                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
 999                         CONN_DATA_DETECT(link,
1000                                         &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1001                                         DC_EDID_BLOCK_SIZE,
1002                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
1003                 }
1004
1005                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1006                         "manufacturer_id = %X, "
1007                         "product_id = %X, "
1008                         "serial_number = %X, "
1009                         "manufacture_week = %d, "
1010                         "manufacture_year = %d, "
1011                         "display_name = %s, "
1012                         "speaker_flag = %d, "
1013                         "audio_mode_count = %d\n",
1014                         __func__,
1015                         sink->edid_caps.manufacturer_id,
1016                         sink->edid_caps.product_id,
1017                         sink->edid_caps.serial_number,
1018                         sink->edid_caps.manufacture_week,
1019                         sink->edid_caps.manufacture_year,
1020                         sink->edid_caps.display_name,
1021                         sink->edid_caps.speaker_flags,
1022                         sink->edid_caps.audio_mode_count);
1023
1024                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1025                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1026                                 "format_code = %d, "
1027                                 "channel_count = %d, "
1028                                 "sample_rate = %d, "
1029                                 "sample_size = %d\n",
1030                                 __func__,
1031                                 i,
1032                                 sink->edid_caps.audio_modes[i].format_code,
1033                                 sink->edid_caps.audio_modes[i].channel_count,
1034                                 sink->edid_caps.audio_modes[i].sample_rate,
1035                                 sink->edid_caps.audio_modes[i].sample_size);
1036                 }
1037
1038         } else {
1039                 /* From Connected-to-Disconnected. */
1040                 if (link->type == dc_connection_mst_branch) {
1041                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1042                                 link->link_index);
1043
1044                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1045
1046                         link->mst_stream_alloc_table.stream_count = 0;
1047                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
1048                 }
1049
1050                 link->type = dc_connection_none;
1051                 sink_caps.signal = SIGNAL_TYPE_NONE;
1052                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1053                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1054                  *  the dongle is still there and limits the number of modes we can emulate.
1055                  *  Clear dongle_max_pix_clk on disconnect to fix this
1056                  */
1057                 link->dongle_max_pix_clk = 0;
1058         }
1059
1060         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1061                 link->link_index, sink,
1062                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
1063                         "Disconnected":"Connected"), prev_sink,
1064                         same_dpcd, same_edid);
1065
1066         if (prev_sink != NULL)
1067                 dc_sink_release(prev_sink);
1068
1069         return true;
1070
1071 }
1072
1073 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1074 {
1075         const struct dc *dc = link->dc;
1076         bool ret;
1077
1078         /* get out of low power state */
1079         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1080
1081         ret = dc_link_detect_helper(link, reason);
1082
1083         /* Go back to power optimized state */
1084         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1085
1086         return ret;
1087 }
1088
1089 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1090 {
1091         uint32_t state;
1092
1093         dal_gpio_lock_pin(dc_link->hpd_gpio);
1094         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1095         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1096
1097         return state;
1098 }
1099
1100 static enum hpd_source_id get_hpd_line(
1101                 struct dc_link *link)
1102 {
1103         struct gpio *hpd;
1104         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1105
1106         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1107
1108         if (hpd) {
1109                 switch (dal_irq_get_source(hpd)) {
1110                 case DC_IRQ_SOURCE_HPD1:
1111                         hpd_id = HPD_SOURCEID1;
1112                 break;
1113                 case DC_IRQ_SOURCE_HPD2:
1114                         hpd_id = HPD_SOURCEID2;
1115                 break;
1116                 case DC_IRQ_SOURCE_HPD3:
1117                         hpd_id = HPD_SOURCEID3;
1118                 break;
1119                 case DC_IRQ_SOURCE_HPD4:
1120                         hpd_id = HPD_SOURCEID4;
1121                 break;
1122                 case DC_IRQ_SOURCE_HPD5:
1123                         hpd_id = HPD_SOURCEID5;
1124                 break;
1125                 case DC_IRQ_SOURCE_HPD6:
1126                         hpd_id = HPD_SOURCEID6;
1127                 break;
1128                 default:
1129                         BREAK_TO_DEBUGGER();
1130                 break;
1131                 }
1132
1133                 dal_gpio_destroy_irq(&hpd);
1134         }
1135
1136         return hpd_id;
1137 }
1138
1139 static enum channel_id get_ddc_line(struct dc_link *link)
1140 {
1141         struct ddc *ddc;
1142         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1143
1144         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1145
1146         if (ddc) {
1147                 switch (dal_ddc_get_line(ddc)) {
1148                 case GPIO_DDC_LINE_DDC1:
1149                         channel = CHANNEL_ID_DDC1;
1150                         break;
1151                 case GPIO_DDC_LINE_DDC2:
1152                         channel = CHANNEL_ID_DDC2;
1153                         break;
1154                 case GPIO_DDC_LINE_DDC3:
1155                         channel = CHANNEL_ID_DDC3;
1156                         break;
1157                 case GPIO_DDC_LINE_DDC4:
1158                         channel = CHANNEL_ID_DDC4;
1159                         break;
1160                 case GPIO_DDC_LINE_DDC5:
1161                         channel = CHANNEL_ID_DDC5;
1162                         break;
1163                 case GPIO_DDC_LINE_DDC6:
1164                         channel = CHANNEL_ID_DDC6;
1165                         break;
1166                 case GPIO_DDC_LINE_DDC_VGA:
1167                         channel = CHANNEL_ID_DDC_VGA;
1168                         break;
1169                 case GPIO_DDC_LINE_I2C_PAD:
1170                         channel = CHANNEL_ID_I2C_PAD;
1171                         break;
1172                 default:
1173                         BREAK_TO_DEBUGGER();
1174                         break;
1175                 }
1176         }
1177
1178         return channel;
1179 }
1180
1181 static enum transmitter translate_encoder_to_transmitter(
1182         struct graphics_object_id encoder)
1183 {
1184         switch (encoder.id) {
1185         case ENCODER_ID_INTERNAL_UNIPHY:
1186                 switch (encoder.enum_id) {
1187                 case ENUM_ID_1:
1188                         return TRANSMITTER_UNIPHY_A;
1189                 case ENUM_ID_2:
1190                         return TRANSMITTER_UNIPHY_B;
1191                 default:
1192                         return TRANSMITTER_UNKNOWN;
1193                 }
1194         break;
1195         case ENCODER_ID_INTERNAL_UNIPHY1:
1196                 switch (encoder.enum_id) {
1197                 case ENUM_ID_1:
1198                         return TRANSMITTER_UNIPHY_C;
1199                 case ENUM_ID_2:
1200                         return TRANSMITTER_UNIPHY_D;
1201                 default:
1202                         return TRANSMITTER_UNKNOWN;
1203                 }
1204         break;
1205         case ENCODER_ID_INTERNAL_UNIPHY2:
1206                 switch (encoder.enum_id) {
1207                 case ENUM_ID_1:
1208                         return TRANSMITTER_UNIPHY_E;
1209                 case ENUM_ID_2:
1210                         return TRANSMITTER_UNIPHY_F;
1211                 default:
1212                         return TRANSMITTER_UNKNOWN;
1213                 }
1214         break;
1215         case ENCODER_ID_INTERNAL_UNIPHY3:
1216                 switch (encoder.enum_id) {
1217                 case ENUM_ID_1:
1218                         return TRANSMITTER_UNIPHY_G;
1219                 default:
1220                         return TRANSMITTER_UNKNOWN;
1221                 }
1222         break;
1223         case ENCODER_ID_EXTERNAL_NUTMEG:
1224                 switch (encoder.enum_id) {
1225                 case ENUM_ID_1:
1226                         return TRANSMITTER_NUTMEG_CRT;
1227                 default:
1228                         return TRANSMITTER_UNKNOWN;
1229                 }
1230         break;
1231         case ENCODER_ID_EXTERNAL_TRAVIS:
1232                 switch (encoder.enum_id) {
1233                 case ENUM_ID_1:
1234                         return TRANSMITTER_TRAVIS_CRT;
1235                 case ENUM_ID_2:
1236                         return TRANSMITTER_TRAVIS_LCD;
1237                 default:
1238                         return TRANSMITTER_UNKNOWN;
1239                 }
1240         break;
1241         default:
1242                 return TRANSMITTER_UNKNOWN;
1243         }
1244 }
1245
1246 static bool construct(
1247         struct dc_link *link,
1248         const struct link_init_data *init_params)
1249 {
1250         uint8_t i;
1251         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1252         struct dc_context *dc_ctx = init_params->ctx;
1253         struct encoder_init_data enc_init_data = { 0 };
1254         struct integrated_info info = {{{ 0 }}};
1255         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1256         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1257         DC_LOGGER_INIT(dc_ctx->logger);
1258
1259         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1260         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1261
1262         link->link_status.dpcd_caps = &link->dpcd_caps;
1263
1264         link->dc = init_params->dc;
1265         link->ctx = dc_ctx;
1266         link->link_index = init_params->link_index;
1267
1268         memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides));
1269         memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings));
1270
1271         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1272
1273         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1274                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1275                          __func__, init_params->connector_index,
1276                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1277                 goto create_fail;
1278         }
1279
1280         if (link->dc->res_pool->funcs->link_init)
1281                 link->dc->res_pool->funcs->link_init(link);
1282
1283         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1284         if (link->hpd_gpio != NULL) {
1285                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1286                 dal_gpio_unlock_pin(link->hpd_gpio);
1287                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1288         }
1289
1290         switch (link->link_id.id) {
1291         case CONNECTOR_ID_HDMI_TYPE_A:
1292                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1293
1294                 break;
1295         case CONNECTOR_ID_SINGLE_LINK_DVID:
1296         case CONNECTOR_ID_SINGLE_LINK_DVII:
1297                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1298                 break;
1299         case CONNECTOR_ID_DUAL_LINK_DVID:
1300         case CONNECTOR_ID_DUAL_LINK_DVII:
1301                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1302                 break;
1303         case CONNECTOR_ID_DISPLAY_PORT:
1304                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1305
1306                 if (link->hpd_gpio != NULL)
1307                         link->irq_source_hpd_rx =
1308                                         dal_irq_get_rx_source(link->hpd_gpio);
1309
1310                 break;
1311         case CONNECTOR_ID_EDP:
1312                 link->connector_signal = SIGNAL_TYPE_EDP;
1313
1314                 if (link->hpd_gpio != NULL) {
1315                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1316                         link->irq_source_hpd_rx =
1317                                         dal_irq_get_rx_source(link->hpd_gpio);
1318                 }
1319                 break;
1320         case CONNECTOR_ID_LVDS:
1321                 link->connector_signal = SIGNAL_TYPE_LVDS;
1322                 break;
1323         default:
1324                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1325                 goto create_fail;
1326         }
1327
1328         /* TODO: #DAL3 Implement id to str function.*/
1329         LINK_INFO("Connector[%d] description:"
1330                         "signal %d\n",
1331                         init_params->connector_index,
1332                         link->connector_signal);
1333
1334         ddc_service_init_data.ctx = link->ctx;
1335         ddc_service_init_data.id = link->link_id;
1336         ddc_service_init_data.link = link;
1337         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1338
1339         if (link->ddc == NULL) {
1340                 DC_ERROR("Failed to create ddc_service!\n");
1341                 goto ddc_create_fail;
1342         }
1343
1344         link->ddc_hw_inst =
1345                 dal_ddc_get_line(
1346                         dal_ddc_service_get_ddc_pin(link->ddc));
1347
1348         enc_init_data.ctx = dc_ctx;
1349         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1350         enc_init_data.connector = link->link_id;
1351         enc_init_data.channel = get_ddc_line(link);
1352         enc_init_data.hpd_source = get_hpd_line(link);
1353
1354         link->hpd_src = enc_init_data.hpd_source;
1355
1356         enc_init_data.transmitter =
1357                         translate_encoder_to_transmitter(enc_init_data.encoder);
1358         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1359                                                                 &enc_init_data);
1360
1361         if (link->link_enc == NULL) {
1362                 DC_ERROR("Failed to create link encoder!\n");
1363                 goto link_enc_create_fail;
1364         }
1365
1366         link->link_enc_hw_inst = link->link_enc->transmitter;
1367
1368         for (i = 0; i < 4; i++) {
1369                 if (BP_RESULT_OK !=
1370                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1371                         DC_ERROR("Failed to find device tag!\n");
1372                         goto device_tag_fail;
1373                 }
1374
1375                 /* Look for device tag that matches connector signal,
1376                  * CRT for rgb, LCD for other supported signal tyes
1377                  */
1378                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1379                         continue;
1380                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1381                         && link->connector_signal != SIGNAL_TYPE_RGB)
1382                         continue;
1383                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1384                         && link->connector_signal == SIGNAL_TYPE_RGB)
1385                         continue;
1386                 break;
1387         }
1388
1389         if (bios->integrated_info)
1390                 info = *bios->integrated_info;
1391
1392         /* Look for channel mapping corresponding to connector and device tag */
1393         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1394                 struct external_display_path *path =
1395                         &info.ext_disp_conn_info.path[i];
1396                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1397                         && path->device_connector_id.id == link->link_id.id
1398                         && path->device_connector_id.type == link->link_id.type) {
1399
1400                         if (link->device_tag.acpi_device != 0
1401                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1402                                 link->ddi_channel_mapping = path->channel_mapping;
1403                                 link->chip_caps = path->caps;
1404                         } else if (path->device_tag ==
1405                                         link->device_tag.dev_id.raw_device_tag) {
1406                                 link->ddi_channel_mapping = path->channel_mapping;
1407                                 link->chip_caps = path->caps;
1408                         }
1409                         break;
1410                 }
1411         }
1412
1413         /*
1414          * TODO check if GPIO programmed correctly
1415          *
1416          * If GPIO isn't programmed correctly HPD might not rise or drain
1417          * fast enough, leading to bounces.
1418          */
1419         program_hpd_filter(link);
1420
1421         return true;
1422 device_tag_fail:
1423         link->link_enc->funcs->destroy(&link->link_enc);
1424 link_enc_create_fail:
1425         dal_ddc_service_destroy(&link->ddc);
1426 ddc_create_fail:
1427 create_fail:
1428
1429         if (link->hpd_gpio != NULL) {
1430                 dal_gpio_destroy_irq(&link->hpd_gpio);
1431                 link->hpd_gpio = NULL;
1432         }
1433
1434         return false;
1435 }
1436
1437 /*******************************************************************************
1438  * Public functions
1439  ******************************************************************************/
1440 struct dc_link *link_create(const struct link_init_data *init_params)
1441 {
1442         struct dc_link *link =
1443                         kzalloc(sizeof(*link), GFP_KERNEL);
1444
1445         if (NULL == link)
1446                 goto alloc_fail;
1447
1448         if (false == construct(link, init_params))
1449                 goto construct_fail;
1450
1451         return link;
1452
1453 construct_fail:
1454         kfree(link);
1455
1456 alloc_fail:
1457         return NULL;
1458 }
1459
1460 void link_destroy(struct dc_link **link)
1461 {
1462         destruct(*link);
1463         kfree(*link);
1464         *link = NULL;
1465 }
1466
1467 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1468 {
1469         struct dc_stream_state *stream = pipe_ctx->stream;
1470         struct dc_link *link = stream->link;
1471         union down_spread_ctrl old_downspread;
1472         union down_spread_ctrl new_downspread;
1473
1474         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1475                         &old_downspread.raw, sizeof(old_downspread));
1476
1477         new_downspread.raw = old_downspread.raw;
1478
1479         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1480                         (stream->ignore_msa_timing_param) ? 1 : 0;
1481
1482         if (new_downspread.raw != old_downspread.raw) {
1483                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1484                         &new_downspread.raw, sizeof(new_downspread));
1485         }
1486 }
1487
1488 static enum dc_status enable_link_dp(
1489                 struct dc_state *state,
1490                 struct pipe_ctx *pipe_ctx)
1491 {
1492         struct dc_stream_state *stream = pipe_ctx->stream;
1493         enum dc_status status;
1494         bool skip_video_pattern;
1495         struct dc_link *link = stream->link;
1496         struct dc_link_settings link_settings = {0};
1497         enum dp_panel_mode panel_mode;
1498 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1499         bool fec_enable;
1500 #endif
1501         int i;
1502         bool apply_seamless_boot_optimization = false;
1503
1504         // check for seamless boot
1505         for (i = 0; i < state->stream_count; i++) {
1506                 if (state->streams[i]->apply_seamless_boot_optimization) {
1507                         apply_seamless_boot_optimization = true;
1508                         break;
1509                 }
1510         }
1511
1512         /* get link settings for video mode timing */
1513         decide_link_settings(stream, &link_settings);
1514
1515         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1516                 /* If link settings are different than current and link already enabled
1517                  * then need to disable before programming to new rate.
1518                  */
1519                 if (link->link_status.link_active &&
1520                         (link->cur_link_settings.lane_count != link_settings.lane_count ||
1521                          link->cur_link_settings.link_rate != link_settings.link_rate)) {
1522                         dp_disable_link_phy(link, pipe_ctx->stream->signal);
1523                 }
1524
1525                 /*in case it is not on*/
1526                 link->dc->hwss.edp_power_control(link, true);
1527                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1528         }
1529
1530         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1531                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1532         if (!apply_seamless_boot_optimization)
1533                 state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
1534
1535         dp_enable_link_phy(
1536                 link,
1537                 pipe_ctx->stream->signal,
1538                 pipe_ctx->clock_source->id,
1539                 &link_settings);
1540
1541         if (stream->sink_patches.dppowerup_delay > 0) {
1542                 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1543
1544                 msleep(delay_dp_power_up_in_ms);
1545         }
1546
1547         panel_mode = dp_get_panel_mode(link);
1548         dp_set_panel_mode(link, panel_mode);
1549
1550         skip_video_pattern = true;
1551
1552         if (link_settings.link_rate == LINK_RATE_LOW)
1553                         skip_video_pattern = false;
1554
1555         if (link->aux_access_disabled) {
1556                 dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
1557
1558                 link->cur_link_settings = link_settings;
1559                 status = DC_OK;
1560         } else if (perform_link_training_with_retries(
1561                         link,
1562                         &link_settings,
1563                         skip_video_pattern,
1564                         LINK_TRAINING_ATTEMPTS)) {
1565                 link->cur_link_settings = link_settings;
1566                 status = DC_OK;
1567         }
1568         else
1569                 status = DC_FAIL_DP_LINK_TRAINING;
1570
1571 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1572         if (link->preferred_training_settings.fec_enable != NULL)
1573                 fec_enable = *link->preferred_training_settings.fec_enable;
1574         else
1575                 fec_enable = true;
1576
1577         dp_set_fec_enable(link, fec_enable);
1578 #endif
1579         return status;
1580 }
1581
1582 static enum dc_status enable_link_edp(
1583                 struct dc_state *state,
1584                 struct pipe_ctx *pipe_ctx)
1585 {
1586         enum dc_status status;
1587
1588         status = enable_link_dp(state, pipe_ctx);
1589
1590         return status;
1591 }
1592
1593 static enum dc_status enable_link_dp_mst(
1594                 struct dc_state *state,
1595                 struct pipe_ctx *pipe_ctx)
1596 {
1597         struct dc_link *link = pipe_ctx->stream->link;
1598
1599         /* sink signal type after MST branch is MST. Multiple MST sinks
1600          * share one link. Link DP PHY is enable or training only once.
1601          */
1602         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1603                 return DC_OK;
1604
1605         /* clear payload table */
1606         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1607
1608         /* to make sure the pending down rep can be processed
1609          * before enabling the link
1610          */
1611         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1612
1613         /* set the sink to MST mode before enabling the link */
1614         dp_enable_mst_on_sink(link, true);
1615
1616         return enable_link_dp(state, pipe_ctx);
1617 }
1618
1619 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1620                 enum engine_id eng_id,
1621                 struct ext_hdmi_settings *settings)
1622 {
1623         bool result = false;
1624         int i = 0;
1625         struct integrated_info *integrated_info =
1626                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1627
1628         if (integrated_info == NULL)
1629                 return false;
1630
1631         /*
1632          * Get retimer settings from sbios for passing SI eye test for DCE11
1633          * The setting values are varied based on board revision and port id
1634          * Therefore the setting values of each ports is passed by sbios.
1635          */
1636
1637         // Check if current bios contains ext Hdmi settings
1638         if (integrated_info->gpu_cap_info & 0x20) {
1639                 switch (eng_id) {
1640                 case ENGINE_ID_DIGA:
1641                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1642                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1643                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1644                         memmove(settings->reg_settings,
1645                                         integrated_info->dp0_ext_hdmi_reg_settings,
1646                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1647                         memmove(settings->reg_settings_6g,
1648                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1649                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1650                         result = true;
1651                         break;
1652                 case ENGINE_ID_DIGB:
1653                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1654                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1655                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1656                         memmove(settings->reg_settings,
1657                                         integrated_info->dp1_ext_hdmi_reg_settings,
1658                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1659                         memmove(settings->reg_settings_6g,
1660                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1661                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1662                         result = true;
1663                         break;
1664                 case ENGINE_ID_DIGC:
1665                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1666                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1667                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1668                         memmove(settings->reg_settings,
1669                                         integrated_info->dp2_ext_hdmi_reg_settings,
1670                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1671                         memmove(settings->reg_settings_6g,
1672                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1673                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1674                         result = true;
1675                         break;
1676                 case ENGINE_ID_DIGD:
1677                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1678                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1679                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1680                         memmove(settings->reg_settings,
1681                                         integrated_info->dp3_ext_hdmi_reg_settings,
1682                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1683                         memmove(settings->reg_settings_6g,
1684                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1685                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1686                         result = true;
1687                         break;
1688                 default:
1689                         break;
1690                 }
1691
1692                 if (result == true) {
1693                         // Validate settings from bios integrated info table
1694                         if (settings->slv_addr == 0)
1695                                 return false;
1696                         if (settings->reg_num > 9)
1697                                 return false;
1698                         if (settings->reg_num_6g > 3)
1699                                 return false;
1700
1701                         for (i = 0; i < settings->reg_num; i++) {
1702                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1703                                         return false;
1704                         }
1705
1706                         for (i = 0; i < settings->reg_num_6g; i++) {
1707                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1708                                         return false;
1709                         }
1710                 }
1711         }
1712
1713         return result;
1714 }
1715
1716 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1717                 uint8_t address, uint8_t *buffer, uint32_t length)
1718 {
1719         struct i2c_command cmd = {0};
1720         struct i2c_payload payload = {0};
1721
1722         memset(&payload, 0, sizeof(payload));
1723         memset(&cmd, 0, sizeof(cmd));
1724
1725         cmd.number_of_payloads = 1;
1726         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1727         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1728
1729         payload.address = address;
1730         payload.data = buffer;
1731         payload.length = length;
1732         payload.write = true;
1733         cmd.payloads = &payload;
1734
1735         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1736                         pipe_ctx->stream->link, &cmd))
1737                 return true;
1738
1739         return false;
1740 }
1741
1742 static void write_i2c_retimer_setting(
1743                 struct pipe_ctx *pipe_ctx,
1744                 bool is_vga_mode,
1745                 bool is_over_340mhz,
1746                 struct ext_hdmi_settings *settings)
1747 {
1748         uint8_t slave_address = (settings->slv_addr >> 1);
1749         uint8_t buffer[2];
1750         const uint8_t apply_rx_tx_change = 0x4;
1751         uint8_t offset = 0xA;
1752         uint8_t value = 0;
1753         int i = 0;
1754         bool i2c_success = false;
1755         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1756
1757         memset(&buffer, 0, sizeof(buffer));
1758
1759         /* Start Ext-Hdmi programming*/
1760
1761         for (i = 0; i < settings->reg_num; i++) {
1762                 /* Apply 3G settings */
1763                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1764
1765                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1766                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1767                         i2c_success = i2c_write(pipe_ctx, slave_address,
1768                                                 buffer, sizeof(buffer));
1769                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1770                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1771                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1772
1773                         if (!i2c_success)
1774                                 /* Write failure */
1775                                 ASSERT(i2c_success);
1776
1777                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1778                          * needs to be set to 1 on every 0xA-0xC write.
1779                          */
1780                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1781                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1782                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1783
1784                                 /* Query current value from offset 0xA */
1785                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1786                                         value = settings->reg_settings[i].i2c_reg_val;
1787                                 else {
1788                                         i2c_success =
1789                                                 dal_ddc_service_query_ddc_data(
1790                                                 pipe_ctx->stream->link->ddc,
1791                                                 slave_address, &offset, 1, &value, 1);
1792                                         if (!i2c_success)
1793                                                 /* Write failure */
1794                                                 ASSERT(i2c_success);
1795                                 }
1796
1797                                 buffer[0] = offset;
1798                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1799                                 buffer[1] = value | apply_rx_tx_change;
1800                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1801                                                 buffer, sizeof(buffer));
1802                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1803                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1804                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1805                                 if (!i2c_success)
1806                                         /* Write failure */
1807                                         ASSERT(i2c_success);
1808                         }
1809                 }
1810         }
1811
1812         /* Apply 3G settings */
1813         if (is_over_340mhz) {
1814                 for (i = 0; i < settings->reg_num_6g; i++) {
1815                         /* Apply 3G settings */
1816                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1817
1818                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1819                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1820                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1821                                                         buffer, sizeof(buffer));
1822                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1823                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1824                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1825
1826                                 if (!i2c_success)
1827                                         /* Write failure */
1828                                         ASSERT(i2c_success);
1829
1830                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1831                                  * needs to be set to 1 on every 0xA-0xC write.
1832                                  */
1833                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1834                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1835                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1836
1837                                         /* Query current value from offset 0xA */
1838                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1839                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1840                                         else {
1841                                                 i2c_success =
1842                                                                 dal_ddc_service_query_ddc_data(
1843                                                                 pipe_ctx->stream->link->ddc,
1844                                                                 slave_address, &offset, 1, &value, 1);
1845                                                 if (!i2c_success)
1846                                                         /* Write failure */
1847                                                         ASSERT(i2c_success);
1848                                         }
1849
1850                                         buffer[0] = offset;
1851                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1852                                         buffer[1] = value | apply_rx_tx_change;
1853                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1854                                                         buffer, sizeof(buffer));
1855                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1856                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1857                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1858                                         if (!i2c_success)
1859                                                 /* Write failure */
1860                                                 ASSERT(i2c_success);
1861                                 }
1862                         }
1863                 }
1864         }
1865
1866         if (is_vga_mode) {
1867                 /* Program additional settings if using 640x480 resolution */
1868
1869                 /* Write offset 0xFF to 0x01 */
1870                 buffer[0] = 0xff;
1871                 buffer[1] = 0x01;
1872                 i2c_success = i2c_write(pipe_ctx, slave_address,
1873                                 buffer, sizeof(buffer));
1874                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1875                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1876                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1877                 if (!i2c_success)
1878                         /* Write failure */
1879                         ASSERT(i2c_success);
1880
1881                 /* Write offset 0x00 to 0x23 */
1882                 buffer[0] = 0x00;
1883                 buffer[1] = 0x23;
1884                 i2c_success = i2c_write(pipe_ctx, slave_address,
1885                                 buffer, sizeof(buffer));
1886                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1887                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1888                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1889                 if (!i2c_success)
1890                         /* Write failure */
1891                         ASSERT(i2c_success);
1892
1893                 /* Write offset 0xff to 0x00 */
1894                 buffer[0] = 0xff;
1895                 buffer[1] = 0x00;
1896                 i2c_success = i2c_write(pipe_ctx, slave_address,
1897                                 buffer, sizeof(buffer));
1898                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1899                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1900                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1901                 if (!i2c_success)
1902                         /* Write failure */
1903                         ASSERT(i2c_success);
1904
1905         }
1906 }
1907
1908 static void write_i2c_default_retimer_setting(
1909                 struct pipe_ctx *pipe_ctx,
1910                 bool is_vga_mode,
1911                 bool is_over_340mhz)
1912 {
1913         uint8_t slave_address = (0xBA >> 1);
1914         uint8_t buffer[2];
1915         bool i2c_success = false;
1916         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1917
1918         memset(&buffer, 0, sizeof(buffer));
1919
1920         /* Program Slave Address for tuning single integrity */
1921         /* Write offset 0x0A to 0x13 */
1922         buffer[0] = 0x0A;
1923         buffer[1] = 0x13;
1924         i2c_success = i2c_write(pipe_ctx, slave_address,
1925                         buffer, sizeof(buffer));
1926         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1927                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1928                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1929         if (!i2c_success)
1930                 /* Write failure */
1931                 ASSERT(i2c_success);
1932
1933         /* Write offset 0x0A to 0x17 */
1934         buffer[0] = 0x0A;
1935         buffer[1] = 0x17;
1936         i2c_success = i2c_write(pipe_ctx, slave_address,
1937                         buffer, sizeof(buffer));
1938         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1939                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1940                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1941         if (!i2c_success)
1942                 /* Write failure */
1943                 ASSERT(i2c_success);
1944
1945         /* Write offset 0x0B to 0xDA or 0xD8 */
1946         buffer[0] = 0x0B;
1947         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1948         i2c_success = i2c_write(pipe_ctx, slave_address,
1949                         buffer, sizeof(buffer));
1950         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1951                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1952                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1953         if (!i2c_success)
1954                 /* Write failure */
1955                 ASSERT(i2c_success);
1956
1957         /* Write offset 0x0A to 0x17 */
1958         buffer[0] = 0x0A;
1959         buffer[1] = 0x17;
1960         i2c_success = i2c_write(pipe_ctx, slave_address,
1961                         buffer, sizeof(buffer));
1962         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1963                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1964                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1965         if (!i2c_success)
1966                 /* Write failure */
1967                 ASSERT(i2c_success);
1968
1969         /* Write offset 0x0C to 0x1D or 0x91 */
1970         buffer[0] = 0x0C;
1971         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1972         i2c_success = i2c_write(pipe_ctx, slave_address,
1973                         buffer, sizeof(buffer));
1974         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1975                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1976                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1977         if (!i2c_success)
1978                 /* Write failure */
1979                 ASSERT(i2c_success);
1980
1981         /* Write offset 0x0A to 0x17 */
1982         buffer[0] = 0x0A;
1983         buffer[1] = 0x17;
1984         i2c_success = i2c_write(pipe_ctx, slave_address,
1985                         buffer, sizeof(buffer));
1986         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1987                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1988                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1989         if (!i2c_success)
1990                 /* Write failure */
1991                 ASSERT(i2c_success);
1992
1993
1994         if (is_vga_mode) {
1995                 /* Program additional settings if using 640x480 resolution */
1996
1997                 /* Write offset 0xFF to 0x01 */
1998                 buffer[0] = 0xff;
1999                 buffer[1] = 0x01;
2000                 i2c_success = i2c_write(pipe_ctx, slave_address,
2001                                 buffer, sizeof(buffer));
2002                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2003                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2004                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2005                 if (!i2c_success)
2006                         /* Write failure */
2007                         ASSERT(i2c_success);
2008
2009                 /* Write offset 0x00 to 0x23 */
2010                 buffer[0] = 0x00;
2011                 buffer[1] = 0x23;
2012                 i2c_success = i2c_write(pipe_ctx, slave_address,
2013                                 buffer, sizeof(buffer));
2014                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2015                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2016                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2017                 if (!i2c_success)
2018                         /* Write failure */
2019                         ASSERT(i2c_success);
2020
2021                 /* Write offset 0xff to 0x00 */
2022                 buffer[0] = 0xff;
2023                 buffer[1] = 0x00;
2024                 i2c_success = i2c_write(pipe_ctx, slave_address,
2025                                 buffer, sizeof(buffer));
2026                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2027                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2028                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2029                 if (!i2c_success)
2030                         /* Write failure */
2031                         ASSERT(i2c_success);
2032         }
2033 }
2034
2035 static void write_i2c_redriver_setting(
2036                 struct pipe_ctx *pipe_ctx,
2037                 bool is_over_340mhz)
2038 {
2039         uint8_t slave_address = (0xF0 >> 1);
2040         uint8_t buffer[16];
2041         bool i2c_success = false;
2042         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2043
2044         memset(&buffer, 0, sizeof(buffer));
2045
2046         // Program Slave Address for tuning single integrity
2047         buffer[3] = 0x4E;
2048         buffer[4] = 0x4E;
2049         buffer[5] = 0x4E;
2050         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2051
2052         i2c_success = i2c_write(pipe_ctx, slave_address,
2053                                         buffer, sizeof(buffer));
2054         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2055                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2056                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2057                 i2c_success = %d\n",
2058                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2059
2060         if (!i2c_success)
2061                 /* Write failure */
2062                 ASSERT(i2c_success);
2063 }
2064
2065 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2066 {
2067         struct dc_stream_state *stream = pipe_ctx->stream;
2068         struct dc_link *link = stream->link;
2069         enum dc_color_depth display_color_depth;
2070         enum engine_id eng_id;
2071         struct ext_hdmi_settings settings = {0};
2072         bool is_over_340mhz = false;
2073         bool is_vga_mode = (stream->timing.h_addressable == 640)
2074                         && (stream->timing.v_addressable == 480);
2075
2076         if (stream->phy_pix_clk == 0)
2077                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2078         if (stream->phy_pix_clk > 340000)
2079                 is_over_340mhz = true;
2080
2081         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2082                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2083                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2084                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2085                         /* DP159, Retimer settings */
2086                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2087
2088                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2089                                 write_i2c_retimer_setting(pipe_ctx,
2090                                                 is_vga_mode, is_over_340mhz, &settings);
2091                         } else {
2092                                 write_i2c_default_retimer_setting(pipe_ctx,
2093                                                 is_vga_mode, is_over_340mhz);
2094                         }
2095                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2096                         /* PI3EQX1204, Redriver settings */
2097                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2098                 }
2099         }
2100
2101         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2102                 dal_ddc_service_write_scdc_data(
2103                         stream->link->ddc,
2104                         stream->phy_pix_clk,
2105                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2106
2107         memset(&stream->link->cur_link_settings, 0,
2108                         sizeof(struct dc_link_settings));
2109
2110         display_color_depth = stream->timing.display_color_depth;
2111         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2112                 display_color_depth = COLOR_DEPTH_888;
2113
2114         link->link_enc->funcs->enable_tmds_output(
2115                         link->link_enc,
2116                         pipe_ctx->clock_source->id,
2117                         display_color_depth,
2118                         pipe_ctx->stream->signal,
2119                         stream->phy_pix_clk);
2120
2121         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2122                 dal_ddc_service_read_scdc_data(link->ddc);
2123 }
2124
2125 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2126 {
2127         struct dc_stream_state *stream = pipe_ctx->stream;
2128         struct dc_link *link = stream->link;
2129
2130         if (stream->phy_pix_clk == 0)
2131                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2132
2133         memset(&stream->link->cur_link_settings, 0,
2134                         sizeof(struct dc_link_settings));
2135
2136         link->link_enc->funcs->enable_lvds_output(
2137                         link->link_enc,
2138                         pipe_ctx->clock_source->id,
2139                         stream->phy_pix_clk);
2140
2141 }
2142
2143 /****************************enable_link***********************************/
2144 static enum dc_status enable_link(
2145                 struct dc_state *state,
2146                 struct pipe_ctx *pipe_ctx)
2147 {
2148         enum dc_status status = DC_ERROR_UNEXPECTED;
2149         switch (pipe_ctx->stream->signal) {
2150         case SIGNAL_TYPE_DISPLAY_PORT:
2151                 status = enable_link_dp(state, pipe_ctx);
2152                 break;
2153         case SIGNAL_TYPE_EDP:
2154                 status = enable_link_edp(state, pipe_ctx);
2155                 break;
2156         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2157                 status = enable_link_dp_mst(state, pipe_ctx);
2158                 msleep(200);
2159                 break;
2160         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2161         case SIGNAL_TYPE_DVI_DUAL_LINK:
2162         case SIGNAL_TYPE_HDMI_TYPE_A:
2163                 enable_link_hdmi(pipe_ctx);
2164                 status = DC_OK;
2165                 break;
2166         case SIGNAL_TYPE_LVDS:
2167                 enable_link_lvds(pipe_ctx);
2168                 status = DC_OK;
2169                 break;
2170         case SIGNAL_TYPE_VIRTUAL:
2171                 status = DC_OK;
2172                 break;
2173         default:
2174                 break;
2175         }
2176
2177         if (status == DC_OK)
2178                 pipe_ctx->stream->link->link_status.link_active = true;
2179
2180         return status;
2181 }
2182
2183 static void disable_link(struct dc_link *link, enum signal_type signal)
2184 {
2185         /*
2186          * TODO: implement call for dp_set_hw_test_pattern
2187          * it is needed for compliance testing
2188          */
2189
2190         /* here we need to specify that encoder output settings
2191          * need to be calculated as for the set mode,
2192          * it will lead to querying dynamic link capabilities
2193          * which should be done before enable output */
2194
2195         if (dc_is_dp_signal(signal)) {
2196                 /* SST DP, eDP */
2197                 if (dc_is_dp_sst_signal(signal))
2198                         dp_disable_link_phy(link, signal);
2199                 else
2200                         dp_disable_link_phy_mst(link, signal);
2201 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2202
2203                 if (dc_is_dp_sst_signal(signal) ||
2204                                 link->mst_stream_alloc_table.stream_count == 0) {
2205                         dp_set_fec_enable(link, false);
2206                         dp_set_fec_ready(link, false);
2207                 }
2208 #endif
2209         } else {
2210                 if (signal != SIGNAL_TYPE_VIRTUAL)
2211                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2212         }
2213
2214         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2215                 /* MST disable link only when no stream use the link */
2216                 if (link->mst_stream_alloc_table.stream_count <= 0)
2217                         link->link_status.link_active = false;
2218         } else {
2219                 link->link_status.link_active = false;
2220         }
2221 }
2222
2223 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2224 {
2225
2226         uint32_t pxl_clk = timing->pix_clk_100hz;
2227
2228         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2229                 pxl_clk /= 2;
2230         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2231                 pxl_clk = pxl_clk * 2 / 3;
2232
2233         if (timing->display_color_depth == COLOR_DEPTH_101010)
2234                 pxl_clk = pxl_clk * 10 / 8;
2235         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2236                 pxl_clk = pxl_clk * 12 / 8;
2237
2238         return pxl_clk;
2239 }
2240
2241 static bool dp_active_dongle_validate_timing(
2242                 const struct dc_crtc_timing *timing,
2243                 const struct dpcd_caps *dpcd_caps)
2244 {
2245         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2246
2247         switch (dpcd_caps->dongle_type) {
2248         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2249         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2250         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2251                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2252                         return true;
2253                 else
2254                         return false;
2255         default:
2256                 break;
2257         }
2258
2259         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2260                 dongle_caps->extendedCapValid == false)
2261                 return true;
2262
2263         /* Check Pixel Encoding */
2264         switch (timing->pixel_encoding) {
2265         case PIXEL_ENCODING_RGB:
2266         case PIXEL_ENCODING_YCBCR444:
2267                 break;
2268         case PIXEL_ENCODING_YCBCR422:
2269                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2270                         return false;
2271                 break;
2272         case PIXEL_ENCODING_YCBCR420:
2273                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2274                         return false;
2275                 break;
2276         default:
2277                 /* Invalid Pixel Encoding*/
2278                 return false;
2279         }
2280
2281         switch (timing->display_color_depth) {
2282         case COLOR_DEPTH_666:
2283         case COLOR_DEPTH_888:
2284                 /*888 and 666 should always be supported*/
2285                 break;
2286         case COLOR_DEPTH_101010:
2287                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2288                         return false;
2289                 break;
2290         case COLOR_DEPTH_121212:
2291                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2292                         return false;
2293                 break;
2294         case COLOR_DEPTH_141414:
2295         case COLOR_DEPTH_161616:
2296         default:
2297                 /* These color depths are currently not supported */
2298                 return false;
2299         }
2300
2301         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2302                 return false;
2303
2304         return true;
2305 }
2306
2307 enum dc_status dc_link_validate_mode_timing(
2308                 const struct dc_stream_state *stream,
2309                 struct dc_link *link,
2310                 const struct dc_crtc_timing *timing)
2311 {
2312         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2313         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2314
2315         /* A hack to avoid failing any modes for EDID override feature on
2316          * topology change such as lower quality cable for DP or different dongle
2317          */
2318         if (link->remote_sinks[0])
2319                 return DC_OK;
2320
2321         /* Passive Dongle */
2322         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2323                 return DC_EXCEED_DONGLE_CAP;
2324
2325         /* Active Dongle*/
2326         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2327                 return DC_EXCEED_DONGLE_CAP;
2328
2329         switch (stream->signal) {
2330         case SIGNAL_TYPE_EDP:
2331         case SIGNAL_TYPE_DISPLAY_PORT:
2332                 if (!dp_validate_mode_timing(
2333                                 link,
2334                                 timing))
2335                         return DC_NO_DP_LINK_BANDWIDTH;
2336                 break;
2337
2338         default:
2339                 break;
2340         }
2341
2342         return DC_OK;
2343 }
2344
2345 int dc_link_get_backlight_level(const struct dc_link *link)
2346 {
2347         struct abm *abm = link->ctx->dc->res_pool->abm;
2348
2349         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2350                 return DC_ERROR_UNEXPECTED;
2351
2352         return (int) abm->funcs->get_current_backlight(abm);
2353 }
2354
2355 bool dc_link_set_backlight_level(const struct dc_link *link,
2356                 uint32_t backlight_pwm_u16_16,
2357                 uint32_t frame_ramp)
2358 {
2359         struct dc  *core_dc = link->ctx->dc;
2360         struct abm *abm = core_dc->res_pool->abm;
2361         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2362         unsigned int controller_id = 0;
2363         bool use_smooth_brightness = true;
2364         int i;
2365         DC_LOGGER_INIT(link->ctx->logger);
2366
2367         if ((dmcu == NULL) ||
2368                 (abm == NULL) ||
2369                 (abm->funcs->set_backlight_level_pwm == NULL))
2370                 return false;
2371
2372         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2373
2374         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2375                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2376
2377         if (dc_is_embedded_signal(link->connector_signal)) {
2378                 for (i = 0; i < MAX_PIPES; i++) {
2379                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2380                                 if (core_dc->current_state->res_ctx.
2381                                                 pipe_ctx[i].stream->link
2382                                                 == link) {
2383                                         /* DMCU -1 for all controller id values,
2384                                          * therefore +1 here
2385                                          */
2386                                         controller_id =
2387                                                 core_dc->current_state->
2388                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2389                                                 1;
2390
2391                                         /* Disable brightness ramping when the display is blanked
2392                                          * as it can hang the DMCU
2393                                          */
2394                                         if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
2395                                                 frame_ramp = 0;
2396                                 }
2397                         }
2398                 }
2399                 abm->funcs->set_backlight_level_pwm(
2400                                 abm,
2401                                 backlight_pwm_u16_16,
2402                                 frame_ramp,
2403                                 controller_id,
2404                                 use_smooth_brightness);
2405         }
2406
2407         return true;
2408 }
2409
2410 bool dc_link_set_abm_disable(const struct dc_link *link)
2411 {
2412         struct dc  *core_dc = link->ctx->dc;
2413         struct abm *abm = core_dc->res_pool->abm;
2414
2415         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2416                 return false;
2417
2418         abm->funcs->set_abm_immediate_disable(abm);
2419
2420         return true;
2421 }
2422
2423 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
2424 {
2425         struct dc  *core_dc = link->ctx->dc;
2426         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2427
2428
2429
2430         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_feature_enabled)
2431                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2432
2433         link->psr_allow_active = allow_active;
2434
2435         return true;
2436 }
2437
2438 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2439 {
2440         return &link->link_status;
2441 }
2442
2443 void core_link_resume(struct dc_link *link)
2444 {
2445         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2446                 program_hpd_filter(link);
2447 }
2448
2449 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2450 {
2451         struct fixed31_32 mbytes_per_sec;
2452         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2453                         &stream->link->cur_link_settings);
2454         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2455
2456         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2457
2458         return dc_fixpt_div_int(mbytes_per_sec, 54);
2459 }
2460
2461 static int get_color_depth(enum dc_color_depth color_depth)
2462 {
2463         switch (color_depth) {
2464         case COLOR_DEPTH_666: return 6;
2465         case COLOR_DEPTH_888: return 8;
2466         case COLOR_DEPTH_101010: return 10;
2467         case COLOR_DEPTH_121212: return 12;
2468         case COLOR_DEPTH_141414: return 14;
2469         case COLOR_DEPTH_161616: return 16;
2470         default: return 0;
2471         }
2472 }
2473
2474 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2475 {
2476         uint32_t bpc;
2477         uint64_t kbps;
2478         struct fixed31_32 peak_kbps;
2479         uint32_t numerator;
2480         uint32_t denominator;
2481
2482         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2483         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2484
2485         /*
2486          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2487          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2488          * common multiplier to render an integer PBN for all link rate/lane
2489          * counts combinations
2490          * calculate
2491          * peak_kbps *= (1006/1000)
2492          * peak_kbps *= (64/54)
2493          * peak_kbps *= 8    convert to bytes
2494          */
2495
2496         numerator = 64 * PEAK_FACTOR_X1000;
2497         denominator = 54 * 8 * 1000 * 1000;
2498         kbps *= numerator;
2499         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2500
2501         return peak_kbps;
2502 }
2503
2504 static void update_mst_stream_alloc_table(
2505         struct dc_link *link,
2506         struct stream_encoder *stream_enc,
2507         const struct dp_mst_stream_allocation_table *proposed_table)
2508 {
2509         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2510                         { 0 } };
2511         struct link_mst_stream_allocation *dc_alloc;
2512
2513         int i;
2514         int j;
2515
2516         /* if DRM proposed_table has more than one new payload */
2517         ASSERT(proposed_table->stream_count -
2518                         link->mst_stream_alloc_table.stream_count < 2);
2519
2520         /* copy proposed_table to link, add stream encoder */
2521         for (i = 0; i < proposed_table->stream_count; i++) {
2522
2523                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2524                         dc_alloc =
2525                         &link->mst_stream_alloc_table.stream_allocations[j];
2526
2527                         if (dc_alloc->vcp_id ==
2528                                 proposed_table->stream_allocations[i].vcp_id) {
2529
2530                                 work_table[i] = *dc_alloc;
2531                                 break; /* exit j loop */
2532                         }
2533                 }
2534
2535                 /* new vcp_id */
2536                 if (j == link->mst_stream_alloc_table.stream_count) {
2537                         work_table[i].vcp_id =
2538                                 proposed_table->stream_allocations[i].vcp_id;
2539                         work_table[i].slot_count =
2540                                 proposed_table->stream_allocations[i].slot_count;
2541                         work_table[i].stream_enc = stream_enc;
2542                 }
2543         }
2544
2545         /* update link->mst_stream_alloc_table with work_table */
2546         link->mst_stream_alloc_table.stream_count =
2547                         proposed_table->stream_count;
2548         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2549                 link->mst_stream_alloc_table.stream_allocations[i] =
2550                                 work_table[i];
2551 }
2552
2553 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2554  * because stream_encoder is not exposed to dm
2555  */
2556 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2557 {
2558         struct dc_stream_state *stream = pipe_ctx->stream;
2559         struct dc_link *link = stream->link;
2560         struct link_encoder *link_encoder = link->link_enc;
2561         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2562         struct dp_mst_stream_allocation_table proposed_table = {0};
2563         struct fixed31_32 avg_time_slots_per_mtp;
2564         struct fixed31_32 pbn;
2565         struct fixed31_32 pbn_per_slot;
2566         uint8_t i;
2567         enum act_return_status ret;
2568         DC_LOGGER_INIT(link->ctx->logger);
2569
2570         /* enable_link_dp_mst already check link->enabled_stream_count
2571          * and stream is in link->stream[]. This is called during set mode,
2572          * stream_enc is available.
2573          */
2574
2575         /* get calculate VC payload for stream: stream_alloc */
2576         if (dm_helpers_dp_mst_write_payload_allocation_table(
2577                 stream->ctx,
2578                 stream,
2579                 &proposed_table,
2580                 true)) {
2581                 update_mst_stream_alloc_table(
2582                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2583         }
2584         else
2585                 DC_LOG_WARNING("Failed to update"
2586                                 "MST allocation table for"
2587                                 "pipe idx:%d\n",
2588                                 pipe_ctx->pipe_idx);
2589
2590         DC_LOG_MST("%s  "
2591                         "stream_count: %d: \n ",
2592                         __func__,
2593                         link->mst_stream_alloc_table.stream_count);
2594
2595         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2596                 DC_LOG_MST("stream_enc[%d]: %p      "
2597                 "stream[%d].vcp_id: %d      "
2598                 "stream[%d].slot_count: %d\n",
2599                 i,
2600                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2601                 i,
2602                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2603                 i,
2604                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2605         }
2606
2607         ASSERT(proposed_table.stream_count > 0);
2608
2609         /* program DP source TX for payload */
2610         link_encoder->funcs->update_mst_stream_allocation_table(
2611                 link_encoder,
2612                 &link->mst_stream_alloc_table);
2613
2614         /* send down message */
2615         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2616                         stream->ctx,
2617                         stream);
2618
2619         if (ret != ACT_LINK_LOST) {
2620                 dm_helpers_dp_mst_send_payload_allocation(
2621                                 stream->ctx,
2622                                 stream,
2623                                 true);
2624         }
2625
2626         /* slot X.Y for only current stream */
2627         pbn_per_slot = get_pbn_per_slot(stream);
2628         pbn = get_pbn_from_timing(pipe_ctx);
2629         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2630
2631         stream_encoder->funcs->set_mst_bandwidth(
2632                 stream_encoder,
2633                 avg_time_slots_per_mtp);
2634
2635         return DC_OK;
2636
2637 }
2638
2639 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2640 {
2641         struct dc_stream_state *stream = pipe_ctx->stream;
2642         struct dc_link *link = stream->link;
2643         struct link_encoder *link_encoder = link->link_enc;
2644         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2645         struct dp_mst_stream_allocation_table proposed_table = {0};
2646         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2647         uint8_t i;
2648         bool mst_mode = (link->type == dc_connection_mst_branch);
2649         DC_LOGGER_INIT(link->ctx->logger);
2650
2651         /* deallocate_mst_payload is called before disable link. When mode or
2652          * disable/enable monitor, new stream is created which is not in link
2653          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2654          * should not done. For new mode set, map_resources will get engine
2655          * for new stream, so stream_enc->id should be validated until here.
2656          */
2657
2658         /* slot X.Y */
2659         stream_encoder->funcs->set_mst_bandwidth(
2660                 stream_encoder,
2661                 avg_time_slots_per_mtp);
2662
2663         /* TODO: which component is responsible for remove payload table? */
2664         if (mst_mode) {
2665                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2666                                 stream->ctx,
2667                                 stream,
2668                                 &proposed_table,
2669                                 false)) {
2670
2671                         update_mst_stream_alloc_table(
2672                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2673                 }
2674                 else {
2675                                 DC_LOG_WARNING("Failed to update"
2676                                                 "MST allocation table for"
2677                                                 "pipe idx:%d\n",
2678                                                 pipe_ctx->pipe_idx);
2679                 }
2680         }
2681
2682         DC_LOG_MST("%s"
2683                         "stream_count: %d: ",
2684                         __func__,
2685                         link->mst_stream_alloc_table.stream_count);
2686
2687         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2688                 DC_LOG_MST("stream_enc[%d]: %p      "
2689                 "stream[%d].vcp_id: %d      "
2690                 "stream[%d].slot_count: %d\n",
2691                 i,
2692                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2693                 i,
2694                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2695                 i,
2696                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2697         }
2698
2699         link_encoder->funcs->update_mst_stream_allocation_table(
2700                 link_encoder,
2701                 &link->mst_stream_alloc_table);
2702
2703         if (mst_mode) {
2704                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2705                         stream->ctx,
2706                         stream);
2707
2708                 dm_helpers_dp_mst_send_payload_allocation(
2709                         stream->ctx,
2710                         stream,
2711                         false);
2712         }
2713
2714         return DC_OK;
2715 }
2716 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2717 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
2718 {
2719         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
2720         if (cp_psp && cp_psp->funcs.update_stream_config) {
2721                 struct cp_psp_stream_config config;
2722
2723                 memset(&config, 0, sizeof(config));
2724
2725                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
2726                 config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->id;
2727                 config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
2728                 config.dpms_off = dpms_off;
2729                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
2730                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
2731         }
2732 }
2733 #endif
2734
2735 void core_link_enable_stream(
2736                 struct dc_state *state,
2737                 struct pipe_ctx *pipe_ctx)
2738 {
2739         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2740         struct dc_stream_state *stream = pipe_ctx->stream;
2741         enum dc_status status;
2742         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2743
2744         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
2745                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2746                 return;
2747
2748         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
2749                 stream->link->link_enc->funcs->setup(
2750                         stream->link->link_enc,
2751                         pipe_ctx->stream->signal);
2752                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2753                         pipe_ctx->stream_res.stream_enc,
2754                         pipe_ctx->stream_res.tg->inst,
2755                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2756         }
2757
2758         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2759                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2760                         pipe_ctx->stream_res.stream_enc,
2761                         &stream->timing,
2762                         stream->output_color_space,
2763                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
2764
2765         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
2766                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2767                         pipe_ctx->stream_res.stream_enc,
2768                         &stream->timing,
2769                         stream->phy_pix_clk,
2770                         pipe_ctx->stream_res.audio != NULL);
2771
2772         pipe_ctx->stream->link->link_state_valid = true;
2773
2774         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2775                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2776                         pipe_ctx->stream_res.stream_enc,
2777                         &stream->timing,
2778                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2779                         true : false);
2780
2781         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2782                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2783                         pipe_ctx->stream_res.stream_enc,
2784                         &stream->timing);
2785
2786         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2787                 bool apply_edp_fast_boot_optimization =
2788                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
2789
2790                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2791
2792                 resource_build_info_frame(pipe_ctx);
2793                 core_dc->hwss.update_info_frame(pipe_ctx);
2794
2795                 /* Do not touch link on seamless boot optimization. */
2796                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
2797                         pipe_ctx->stream->dpms_off = false;
2798 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2799                         update_psp_stream_config(pipe_ctx, false);
2800 #endif
2801                         return;
2802                 }
2803
2804                 /* eDP lit up by bios already, no need to enable again. */
2805                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2806                                         apply_edp_fast_boot_optimization) {
2807                         pipe_ctx->stream->dpms_off = false;
2808 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2809                         update_psp_stream_config(pipe_ctx, false);
2810 #endif
2811                         return;
2812                 }
2813
2814                 if (pipe_ctx->stream->dpms_off)
2815                         return;
2816
2817                 status = enable_link(state, pipe_ctx);
2818
2819                 if (status != DC_OK) {
2820                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2821                         pipe_ctx->stream->link->link_index,
2822                         status);
2823
2824                         /* Abort stream enable *unless* the failure was due to
2825                          * DP link training - some DP monitors will recover and
2826                          * show the stream anyway. But MST displays can't proceed
2827                          * without link training.
2828                          */
2829                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2830                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2831                                 BREAK_TO_DEBUGGER();
2832                                 return;
2833                         }
2834                 }
2835
2836                 core_dc->hwss.enable_audio_stream(pipe_ctx);
2837
2838                 /* turn off otg test pattern if enable */
2839                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2840                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2841                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2842                                         COLOR_DEPTH_UNDEFINED);
2843
2844 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2845                 if (pipe_ctx->stream->timing.flags.DSC) {
2846                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2847                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2848                                 dp_set_dsc_enable(pipe_ctx, true);
2849                 }
2850 #endif
2851                 core_dc->hwss.enable_stream(pipe_ctx);
2852
2853 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2854                 /* Set DPS PPS SDP (AKA "info frames") */
2855                 if (pipe_ctx->stream->timing.flags.DSC) {
2856                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2857                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2858                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
2859                 }
2860 #endif
2861
2862                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2863                         dc_link_allocate_mst_payload(pipe_ctx);
2864
2865                 core_dc->hwss.unblank_stream(pipe_ctx,
2866                         &pipe_ctx->stream->link->cur_link_settings);
2867
2868                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2869                         enable_stream_features(pipe_ctx);
2870 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2871                 update_psp_stream_config(pipe_ctx, false);
2872 #endif
2873         }
2874 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2875         else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
2876                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2877                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
2878                         dp_set_dsc_enable(pipe_ctx, true);
2879
2880         }
2881 #endif
2882 }
2883
2884 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
2885 {
2886         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2887         struct dc_stream_state *stream = pipe_ctx->stream;
2888         struct dc_link *link = stream->sink->link;
2889
2890         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
2891                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2892                 return;
2893
2894 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2895         update_psp_stream_config(pipe_ctx, true);
2896 #endif
2897
2898         core_dc->hwss.blank_stream(pipe_ctx);
2899
2900         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2901                 deallocate_mst_payload(pipe_ctx);
2902
2903         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2904                 struct ext_hdmi_settings settings = {0};
2905                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
2906
2907                 unsigned short masked_chip_caps = link->chip_caps &
2908                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2909                 //Need to inform that sink is going to use legacy HDMI mode.
2910                 dal_ddc_service_write_scdc_data(
2911                         link->ddc,
2912                         165000,//vbios only handles 165Mhz.
2913                         false);
2914                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2915                         /* DP159, Retimer settings */
2916                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
2917                                 write_i2c_retimer_setting(pipe_ctx,
2918                                                 false, false, &settings);
2919                         else
2920                                 write_i2c_default_retimer_setting(pipe_ctx,
2921                                                 false, false);
2922                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2923                         /* PI3EQX1204, Redriver settings */
2924                         write_i2c_redriver_setting(pipe_ctx, false);
2925                 }
2926         }
2927         core_dc->hwss.disable_stream(pipe_ctx);
2928
2929         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
2930 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2931         if (pipe_ctx->stream->timing.flags.DSC) {
2932                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2933                         dp_set_dsc_enable(pipe_ctx, false);
2934         }
2935 #endif
2936 }
2937
2938 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2939 {
2940         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2941
2942         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
2943                 return;
2944
2945         core_dc->hwss.set_avmute(pipe_ctx, enable);
2946 }
2947
2948 /**
2949  *****************************************************************************
2950  *  Function: dc_link_enable_hpd_filter
2951  *
2952  *  @brief
2953  *     If enable is true, programs HPD filter on associated HPD line using
2954  *     delay_on_disconnect/delay_on_connect values dependent on
2955  *     link->connector_signal
2956  *
2957  *     If enable is false, programs HPD filter on associated HPD line with no
2958  *     delays on connect or disconnect
2959  *
2960  *  @param [in] link: pointer to the dc link
2961  *  @param [in] enable: boolean specifying whether to enable hbd
2962  *****************************************************************************
2963  */
2964 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2965 {
2966         struct gpio *hpd;
2967
2968         if (enable) {
2969                 link->is_hpd_filter_disabled = false;
2970                 program_hpd_filter(link);
2971         } else {
2972                 link->is_hpd_filter_disabled = true;
2973                 /* Obtain HPD handle */
2974                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2975
2976                 if (!hpd)
2977                         return;
2978
2979                 /* Setup HPD filtering */
2980                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2981                         struct gpio_hpd_config config;
2982
2983                         config.delay_on_connect = 0;
2984                         config.delay_on_disconnect = 0;
2985
2986                         dal_irq_setup_hpd_filter(hpd, &config);
2987
2988                         dal_gpio_close(hpd);
2989                 } else {
2990                         ASSERT_CRITICAL(false);
2991                 }
2992                 /* Release HPD handle */
2993                 dal_gpio_destroy_irq(&hpd);
2994         }
2995 }
2996
2997 uint32_t dc_bandwidth_in_kbps_from_timing(
2998         const struct dc_crtc_timing *timing)
2999 {
3000         uint32_t bits_per_channel = 0;
3001         uint32_t kbps;
3002
3003 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3004         if (timing->flags.DSC) {
3005                 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
3006                 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
3007                 return kbps;
3008         }
3009 #endif
3010
3011         switch (timing->display_color_depth) {
3012         case COLOR_DEPTH_666:
3013                 bits_per_channel = 6;
3014                 break;
3015         case COLOR_DEPTH_888:
3016                 bits_per_channel = 8;
3017                 break;
3018         case COLOR_DEPTH_101010:
3019                 bits_per_channel = 10;
3020                 break;
3021         case COLOR_DEPTH_121212:
3022                 bits_per_channel = 12;
3023                 break;
3024         case COLOR_DEPTH_141414:
3025                 bits_per_channel = 14;
3026                 break;
3027         case COLOR_DEPTH_161616:
3028                 bits_per_channel = 16;
3029                 break;
3030         default:
3031                 break;
3032         }
3033
3034         ASSERT(bits_per_channel != 0);
3035
3036         kbps = timing->pix_clk_100hz / 10;
3037         kbps *= bits_per_channel;
3038
3039         if (timing->flags.Y_ONLY != 1) {
3040                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3041                 kbps *= 3;
3042                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3043                         kbps /= 2;
3044                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3045                         kbps = kbps * 2 / 3;
3046         }
3047
3048         return kbps;
3049
3050 }
3051
3052 void dc_link_set_drive_settings(struct dc *dc,
3053                                 struct link_training_settings *lt_settings,
3054                                 const struct dc_link *link)
3055 {
3056
3057         int i;
3058
3059         for (i = 0; i < dc->link_count; i++) {
3060                 if (dc->links[i] == link)
3061                         break;
3062         }
3063
3064         if (i >= dc->link_count)
3065                 ASSERT_CRITICAL(false);
3066
3067         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3068 }
3069
3070 void dc_link_perform_link_training(struct dc *dc,
3071                                    struct dc_link_settings *link_setting,
3072                                    bool skip_video_pattern)
3073 {
3074         int i;
3075
3076         for (i = 0; i < dc->link_count; i++)
3077                 dc_link_dp_perform_link_training(
3078                         dc->links[i],
3079                         link_setting,
3080                         skip_video_pattern);
3081 }
3082
3083 void dc_link_set_preferred_link_settings(struct dc *dc,
3084                                          struct dc_link_settings *link_setting,
3085                                          struct dc_link *link)
3086 {
3087         int i;
3088         struct pipe_ctx *pipe;
3089         struct dc_stream_state *link_stream;
3090         struct dc_link_settings store_settings = *link_setting;
3091
3092         link->preferred_link_setting = store_settings;
3093
3094         /* Retrain with preferred link settings only relevant for
3095          * DP signal type
3096          * Check for non-DP signal or if passive dongle present
3097          */
3098         if (!dc_is_dp_signal(link->connector_signal) ||
3099                 link->dongle_max_pix_clk > 0)
3100                 return;
3101
3102         for (i = 0; i < MAX_PIPES; i++) {
3103                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3104                 if (pipe->stream && pipe->stream->link) {
3105                         if (pipe->stream->link == link) {
3106                                 link_stream = pipe->stream;
3107                                 break;
3108                         }
3109                 }
3110         }
3111
3112         /* Stream not found */
3113         if (i == MAX_PIPES)
3114                 return;
3115
3116         /* Cannot retrain link if backend is off */
3117         if (link_stream->dpms_off)
3118                 return;
3119
3120         decide_link_settings(link_stream, &store_settings);
3121
3122         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3123                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3124                 dp_retrain_link_dp_test(link, &store_settings, false);
3125 }
3126
3127 void dc_link_set_preferred_training_settings(struct dc *dc,
3128                                                  struct dc_link_settings *link_setting,
3129                                                  struct dc_link_training_overrides *lt_overrides,
3130                                                  struct dc_link *link,
3131                                                  bool skip_immediate_retrain)
3132 {
3133         if (lt_overrides != NULL)
3134                 link->preferred_training_settings = *lt_overrides;
3135         else
3136                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3137
3138         if (link_setting != NULL) {
3139                 link->preferred_link_setting = *link_setting;
3140         } else {
3141                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3142                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3143         }
3144
3145         /* Retrain now, or wait until next stream update to apply */
3146         if (skip_immediate_retrain == false)
3147                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3148 }
3149
3150 void dc_link_enable_hpd(const struct dc_link *link)
3151 {
3152         dc_link_dp_enable_hpd(link);
3153 }
3154
3155 void dc_link_disable_hpd(const struct dc_link *link)
3156 {
3157         dc_link_dp_disable_hpd(link);
3158 }
3159
3160 void dc_link_set_test_pattern(struct dc_link *link,
3161                               enum dp_test_pattern test_pattern,
3162                               const struct link_training_settings *p_link_settings,
3163                               const unsigned char *p_custom_pattern,
3164                               unsigned int cust_pattern_size)
3165 {
3166         if (link != NULL)
3167                 dc_link_dp_set_test_pattern(
3168                         link,
3169                         test_pattern,
3170                         p_link_settings,
3171                         p_custom_pattern,
3172                         cust_pattern_size);
3173 }
3174
3175 uint32_t dc_link_bandwidth_kbps(
3176         const struct dc_link *link,
3177         const struct dc_link_settings *link_setting)
3178 {
3179         uint32_t link_bw_kbps =
3180                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3181
3182         link_bw_kbps *= 8;   /* 8 bits per byte*/
3183         link_bw_kbps *= link_setting->lane_count;
3184
3185 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3186         if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
3187                 /* Account for FEC overhead.
3188                  * We have to do it based on caps,
3189                  * and not based on FEC being set ready,
3190                  * because FEC is set ready too late in
3191                  * the process to correctly be picked up
3192                  * by mode enumeration.
3193                  *
3194                  * There's enough zeros at the end of 'kbps'
3195                  * that make the below operation 100% precise
3196                  * for our purposes.
3197                  * 'long long' makes it work even for HDMI 2.1
3198                  * max bandwidth (and much, much bigger bandwidths
3199                  * than that, actually).
3200                  *
3201                  * NOTE: Reducing link BW by 3% may not be precise
3202                  * because it may be a stream BT that increases by 3%, and so
3203                  * 1/1.03 = 0.970873 factor should have been used instead,
3204                  * but the difference is minimal and is in a safe direction,
3205                  * which all works well around potential ambiguity of DP 1.4a spec.
3206                  */
3207                 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
3208                                                link_bw_kbps, 32);
3209         }
3210 #endif
3211
3212         return link_bw_kbps;
3213
3214 }
3215
3216 const struct dc_link_settings *dc_link_get_link_cap(
3217                 const struct dc_link *link)
3218 {
3219         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3220                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3221                 return &link->preferred_link_setting;
3222         return &link->verified_link_cap;
3223 }