drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atom.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/inc/dmub_cmd_dal.h"
  50 #include "inc/hw/panel.h"
  51
  52 #define DC_LOGGER_INIT(logger)
  53
  54 #define LINK_INFO(...) \
  55         DC_LOG_HW_HOTPLUG(  \
  56                 __VA_ARGS__)
  57
  58 #define RETIMER_REDRIVER_INFO(...) \
  59         DC_LOG_RETIMER_REDRIVER(  \
  60                 __VA_ARGS__)
  61 /*******************************************************************************
  62  * Private structures
  63  ******************************************************************************/
  64
  65 enum {
  66         PEAK_FACTOR_X1000 = 1006,
  67         /*
  68          * Some receivers fail to train on first try and are good
  69          * on subsequent tries. 2 retries should be plenty. If we
  70          * don't have a successful training then we don't expect to
  71          * ever get one.
  72          */
  73         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  74 };
  75
  76 /*******************************************************************************
  77  * Private functions
  78  ******************************************************************************/
  79 static void dc_link_destruct(struct dc_link *link)
  80 {
  81         int i;
  82
  83         if (link->hpd_gpio) {
  84                 dal_gpio_destroy_irq(&link->hpd_gpio);
  85                 link->hpd_gpio = NULL;
  86         }
  87
  88         if (link->ddc)
  89                 dal_ddc_service_destroy(&link->ddc);
  90
  91         if (link->link_enc)
  92                 link->link_enc->funcs->destroy(&link->link_enc);
  93
  94         if (link->local_sink)
  95                 dc_sink_release(link->local_sink);
  96
  97         for (i = 0; i < link->sink_count; ++i)
  98                 dc_sink_release(link->remote_sinks[i]);
  99 }
 100
 101 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 102                           struct graphics_object_id link_id,
 103                           struct gpio_service *gpio_service)
 104 {
 105         enum bp_result bp_result;
 106         struct graphics_object_hpd_info hpd_info;
 107         struct gpio_pin_info pin_info;
 108
 109         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 110                 return NULL;
 111
 112         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 113                 hpd_info.hpd_int_gpio_uid, &pin_info);
 114
 115         if (bp_result != BP_RESULT_OK) {
 116                 ASSERT(bp_result == BP_RESULT_NORECORD);
 117                 return NULL;
 118         }
 119
 120         return dal_gpio_service_create_irq(gpio_service,
 121                                            pin_info.offset,
 122                                            pin_info.mask);
 123 }
 124
 125 /*
 126  *  Function: program_hpd_filter
 127  *
 128  *  @brief
 129  *     Programs HPD filter on associated HPD line
 130  *
 131  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 132  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 133  *
 134  *  @return
 135  *     true on success, false otherwise
 136  */
 137 static bool program_hpd_filter(const struct dc_link *link)
 138 {
 139         bool result = false;
 140         struct gpio *hpd;
 141         int delay_on_connect_in_ms = 0;
 142         int delay_on_disconnect_in_ms = 0;
 143
 144         if (link->is_hpd_filter_disabled)
 145                 return false;
 146         /* Verify feature is supported */
 147         switch (link->connector_signal) {
 148         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 149         case SIGNAL_TYPE_DVI_DUAL_LINK:
 150         case SIGNAL_TYPE_HDMI_TYPE_A:
 151                 /* Program hpd filter */
 152                 delay_on_connect_in_ms = 500;
 153                 delay_on_disconnect_in_ms = 100;
 154                 break;
 155         case SIGNAL_TYPE_DISPLAY_PORT:
 156         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 157                 /* Program hpd filter to allow DP signal to settle */
 158                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 159                  * only 100ms on DELL U2413
 160                  * 0: some passive dongle still show aux mode instead of i2c
 161                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 162                  * also see intermittent i2c read issues.
 163                  */
 164                 delay_on_connect_in_ms = 80;
 165                 delay_on_disconnect_in_ms = 0;
 166                 break;
 167         case SIGNAL_TYPE_LVDS:
 168         case SIGNAL_TYPE_EDP:
 169         default:
 170                 /* Don't program hpd filter */
 171                 return false;
 172         }
 173
 174         /* Obtain HPD handle */
 175         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 176                            link->ctx->gpio_service);
 177
 178         if (!hpd)
 179                 return result;
 180
 181         /* Setup HPD filtering */
 182         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 183                 struct gpio_hpd_config config;
 184
 185                 config.delay_on_connect = delay_on_connect_in_ms;
 186                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 187
 188                 dal_irq_setup_hpd_filter(hpd, &config);
 189
 190                 dal_gpio_close(hpd);
 191
 192                 result = true;
 193         } else {
 194                 ASSERT_CRITICAL(false);
 195         }
 196
 197         /* Release HPD handle */
 198         dal_gpio_destroy_irq(&hpd);
 199
 200         return result;
 201 }
 202
 203 /**
 204  * dc_link_detect_sink() - Determine if there is a sink connected
 205  *
 206  * @type: Returned connection type
 207  * Does not detect downstream devices, such as MST sinks
 208  * or display connected through active dongles
 209  */
 210 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 211 {
 212         uint32_t is_hpd_high = 0;
 213         struct gpio *hpd_pin;
 214
 215         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 216                 *type = dc_connection_single;
 217                 return true;
 218         }
 219
 220         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 221                 /*in case it is not on*/
 222                 link->dc->hwss.edp_power_control(link, true);
 223                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 224         }
 225
 226         /* todo: may need to lock gpio access */
 227         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 228                                link->ctx->gpio_service);
 229         if (!hpd_pin)
 230                 goto hpd_gpio_failure;
 231
 232         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 233         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 234         dal_gpio_close(hpd_pin);
 235         dal_gpio_destroy_irq(&hpd_pin);
 236
 237         if (is_hpd_high) {
 238                 *type = dc_connection_single;
 239                 /* TODO: need to do the actual detection */
 240         } else {
 241                 *type = dc_connection_none;
 242         }
 243
 244         return true;
 245
 246 hpd_gpio_failure:
 247         return false;
 248 }
 249
 250 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 251 {
 252         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 253
 254         switch (sink_signal) {
 255         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 256         case SIGNAL_TYPE_DVI_DUAL_LINK:
 257         case SIGNAL_TYPE_HDMI_TYPE_A:
 258         case SIGNAL_TYPE_LVDS:
 259         case SIGNAL_TYPE_RGB:
 260                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 261                 break;
 262
 263         case SIGNAL_TYPE_DISPLAY_PORT:
 264         case SIGNAL_TYPE_EDP:
 265                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 266                 break;
 267
 268         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 269                 /* MST does not use I2COverAux, but there is the
 270                  * SPECIAL use case for "immediate dwnstrm device
 271                  * access" (EPR#370830).
 272                  */
 273                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 274                 break;
 275
 276         default:
 277                 break;
 278         }
 279
 280         return transaction_type;
 281 }
 282
 283 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 284                                               struct graphics_object_id downstream)
 285 {
 286         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 287                 switch (downstream.id) {
 288                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 289                         switch (encoder.id) {
 290                         case ENCODER_ID_INTERNAL_DAC1:
 291                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 292                         case ENCODER_ID_INTERNAL_DAC2:
 293                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 294                                 return SIGNAL_TYPE_RGB;
 295                         default:
 296                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 297                         }
 298                 break;
 299                 case CONNECTOR_ID_DUAL_LINK_DVII:
 300                 {
 301                         switch (encoder.id) {
 302                         case ENCODER_ID_INTERNAL_DAC1:
 303                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 304                         case ENCODER_ID_INTERNAL_DAC2:
 305                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 306                                 return SIGNAL_TYPE_RGB;
 307                         default:
 308                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 309                         }
 310                 }
 311                 break;
 312                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 313                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 314                 case CONNECTOR_ID_DUAL_LINK_DVID:
 315                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 316                 case CONNECTOR_ID_VGA:
 317                         return SIGNAL_TYPE_RGB;
 318                 case CONNECTOR_ID_HDMI_TYPE_A:
 319                         return SIGNAL_TYPE_HDMI_TYPE_A;
 320                 case CONNECTOR_ID_LVDS:
 321                         return SIGNAL_TYPE_LVDS;
 322                 case CONNECTOR_ID_DISPLAY_PORT:
 323                         return SIGNAL_TYPE_DISPLAY_PORT;
 324                 case CONNECTOR_ID_EDP:
 325                         return SIGNAL_TYPE_EDP;
 326                 default:
 327                         return SIGNAL_TYPE_NONE;
 328                 }
 329         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 330                 switch (downstream.id) {
 331                 case ENCODER_ID_EXTERNAL_NUTMEG:
 332                 case ENCODER_ID_EXTERNAL_TRAVIS:
 333                         return SIGNAL_TYPE_DISPLAY_PORT;
 334                 default:
 335                         return SIGNAL_TYPE_NONE;
 336                 }
 337         }
 338
 339         return SIGNAL_TYPE_NONE;
 340 }
 341
 342 /**
 343  * dc_link_is_dp_sink_present() - Check if there is a native DP
 344  * or passive DP-HDMI dongle connected
 345  */
 346 bool dc_link_is_dp_sink_present(struct dc_link *link)
 347 {
 348         enum gpio_result gpio_result;
 349         uint32_t clock_pin = 0;
 350         uint8_t retry = 0;
 351         struct ddc *ddc;
 352
 353         enum connector_id connector_id =
 354                 dal_graphics_object_id_get_connector_id(link->link_id);
 355
 356         bool present =
 357                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 358                 (connector_id == CONNECTOR_ID_EDP));
 359
 360         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 361
 362         if (!ddc) {
 363                 BREAK_TO_DEBUGGER();
 364                 return present;
 365         }
 366
 367         /* Open GPIO and set it to I2C mode */
 368         /* Note: this GpioMode_Input will be converted
 369          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 370          * which indicates we need additional delay
 371          */
 372
 373         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 374                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 375                 dal_ddc_close(ddc);
 376
 377                 return present;
 378         }
 379
 380         /*
 381          * Read GPIO: DP sink is present if both clock and data pins are zero
 382          *
 383          * [W/A] plug-unplug DP cable, sometimes customer board has
 384          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 385          * then monitor can't br light up. Add retry 3 times
 386          * But in real passive dongle, it need additional 3ms to detect
 387          */
 388         do {
 389                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 390                 ASSERT(gpio_result == GPIO_RESULT_OK);
 391                 if (clock_pin)
 392                         udelay(1000);
 393                 else
 394                         break;
 395         } while (retry++ < 3);
 396
 397         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 398
 399         dal_ddc_close(ddc);
 400
 401         return present;
 402 }
 403
 404 /*
 405  * @brief
 406  * Detect output sink type
 407  */
 408 static enum signal_type link_detect_sink(struct dc_link *link,
 409                                          enum dc_detect_reason reason)
 410 {
 411         enum signal_type result = get_basic_signal_type(link->link_enc->id,
 412                                                         link->link_id);
 413
 414         /* Internal digital encoder will detect only dongles
 415          * that require digital signal
 416          */
 417
 418         /* Detection mechanism is different
 419          * for different native connectors.
 420          * LVDS connector supports only LVDS signal;
 421          * PCIE is a bus slot, the actual connector needs to be detected first;
 422          * eDP connector supports only eDP signal;
 423          * HDMI should check straps for audio
 424          */
 425
 426         /* PCIE detects the actual connector on add-on board */
 427         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 428                 /* ZAZTODO implement PCIE add-on card detection */
 429         }
 430
 431         switch (link->link_id.id) {
 432         case CONNECTOR_ID_HDMI_TYPE_A: {
 433                 /* check audio support:
 434                  * if native HDMI is not supported, switch to DVI
 435                  */
 436                 struct audio_support *aud_support =
 437                                         &link->dc->res_pool->audio_support;
 438
 439                 if (!aud_support->hdmi_audio_native)
 440                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 441                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 442         }
 443         break;
 444         case CONNECTOR_ID_DISPLAY_PORT: {
 445                 /* DP HPD short pulse. Passive DP dongle will not
 446                  * have short pulse
 447                  */
 448                 if (reason != DETECT_REASON_HPDRX) {
 449                         /* Check whether DP signal detected: if not -
 450                          * we assume signal is DVI; it could be corrected
 451                          * to HDMI after dongle detection
 452                          */
 453                         if (!dm_helpers_is_dp_sink_present(link))
 454                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 455                 }
 456         }
 457         break;
 458         default:
 459         break;
 460         }
 461
 462         return result;
 463 }
 464
 465 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 466                                                                  struct audio_support *audio_support)
 467 {
 468         enum signal_type signal = SIGNAL_TYPE_NONE;
 469
 470         switch (dongle_type) {
 471         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 472                 if (audio_support->hdmi_audio_on_dongle)
 473                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 474                 else
 475                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 476                 break;
 477         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 478                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 479                 break;
 480         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 481                 if (audio_support->hdmi_audio_native)
 482                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 483                 else
 484                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 485                 break;
 486         default:
 487                 signal = SIGNAL_TYPE_NONE;
 488                 break;
 489         }
 490
 491         return signal;
 492 }
 493
 494 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 495                                                     struct display_sink_capability *sink_cap,
 496                                                     struct audio_support *audio_support)
 497 {
 498         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 499
 500         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 501                                                         audio_support);
 502 }
 503
 504 static void link_disconnect_sink(struct dc_link *link)
 505 {
 506         if (link->local_sink) {
 507                 dc_sink_release(link->local_sink);
 508                 link->local_sink = NULL;
 509         }
 510
 511         link->dpcd_sink_count = 0;
 512 }
 513
 514 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 515 {
 516         dc_sink_release(link->local_sink);
 517         link->local_sink = prev_sink;
 518 }
 519
 520 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 521 bool dc_link_is_hdcp14(struct dc_link *link)
 522 {
 523         bool ret = false;
 524
 525         switch (link->connector_signal) {
 526         case SIGNAL_TYPE_DISPLAY_PORT:
 527         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 528                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 529                 break;
 530         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 531         case SIGNAL_TYPE_DVI_DUAL_LINK:
 532         case SIGNAL_TYPE_HDMI_TYPE_A:
 533         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 534          * we can poll for bksv but some displays have an issue with this. Since its so rare
 535          * for a display to not be 1.4 capable, this assumtion is ok
 536          */
 537                 ret = true;
 538                 break;
 539         default:
 540                 break;
 541         }
 542         return ret;
 543 }
 544
 545 bool dc_link_is_hdcp22(struct dc_link *link)
 546 {
 547         bool ret = false;
 548
 549         switch (link->connector_signal) {
 550         case SIGNAL_TYPE_DISPLAY_PORT:
 551         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 552                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 553                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 554                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 555                 break;
 556         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 557         case SIGNAL_TYPE_DVI_DUAL_LINK:
 558         case SIGNAL_TYPE_HDMI_TYPE_A:
 559                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 560                 break;
 561         default:
 562                 break;
 563         }
 564
 565         return ret;
 566 }
 567
 568 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 569 {
 570         struct hdcp_protection_message msg22;
 571         struct hdcp_protection_message msg14;
 572
 573         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 574         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 575         memset(link->hdcp_caps.rx_caps.raw, 0,
 576                 sizeof(link->hdcp_caps.rx_caps.raw));
 577
 578         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 579                         link->ddc->transaction_type ==
 580                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 581                         link->connector_signal == SIGNAL_TYPE_EDP) {
 582                 msg22.data = link->hdcp_caps.rx_caps.raw;
 583                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 584                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 585         } else {
 586                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 587                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 588                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 589         }
 590         msg22.version = HDCP_VERSION_22;
 591         msg22.link = HDCP_LINK_PRIMARY;
 592         msg22.max_retries = 5;
 593         dc_process_hdcp_msg(signal, link, &msg22);
 594
 595         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 596                 enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED;
 597
 598                 msg14.data = &link->hdcp_caps.bcaps.raw;
 599                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 600                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 601                 msg14.version = HDCP_VERSION_14;
 602                 msg14.link = HDCP_LINK_PRIMARY;
 603                 msg14.max_retries = 5;
 604
 605                 status = dc_process_hdcp_msg(signal, link, &msg14);
 606         }
 607
 608 }
 609 #endif
 610
 611 static void read_current_link_settings_on_detect(struct dc_link *link)
 612 {
 613         union lane_count_set lane_count_set = { {0} };
 614         uint8_t link_bw_set;
 615         uint8_t link_rate_set;
 616         uint32_t read_dpcd_retry_cnt = 10;
 617         enum dc_status status = DC_ERROR_UNEXPECTED;
 618         int i;
 619         union max_down_spread max_down_spread = { {0} };
 620
 621         // Read DPCD 00101h to find out the number of lanes currently set
 622         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 623                 status = core_link_read_dpcd(link,
 624                                              DP_LANE_COUNT_SET,
 625                                              &lane_count_set.raw,
 626                                              sizeof(lane_count_set));
 627                 /* First DPCD read after VDD ON can fail if the particular board
 628                  * does not have HPD pin wired correctly. So if DPCD read fails,
 629                  * which it should never happen, retry a few times. Target worst
 630                  * case scenario of 80 ms.
 631                  */
 632                 if (status == DC_OK) {
 633                         link->cur_link_settings.lane_count =
 634                                         lane_count_set.bits.LANE_COUNT_SET;
 635                         break;
 636                 }
 637
 638                 msleep(8);
 639         }
 640
 641         // Read DPCD 00100h to find if standard link rates are set
 642         core_link_read_dpcd(link, DP_LINK_BW_SET,
 643                             &link_bw_set, sizeof(link_bw_set));
 644
 645         if (link_bw_set == 0) {
 646                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 647                         /* If standard link rates are not being used,
 648                          * Read DPCD 00115h to find the edp link rate set used
 649                          */
 650                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 651                                             &link_rate_set, sizeof(link_rate_set));
 652
 653                         // edp_supported_link_rates_count = 0 for DP
 654                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 655                                 link->cur_link_settings.link_rate =
 656                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 657                                 link->cur_link_settings.link_rate_set = link_rate_set;
 658                                 link->cur_link_settings.use_link_rate_set = true;
 659                         }
 660                 } else {
 661                         // Link Rate not found. Seamless boot may not work.
 662                         ASSERT(false);
 663                 }
 664         } else {
 665                 link->cur_link_settings.link_rate = link_bw_set;
 666                 link->cur_link_settings.use_link_rate_set = false;
 667         }
 668         // Read DPCD 00003h to find the max down spread.
 669         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 670                             &max_down_spread.raw, sizeof(max_down_spread));
 671         link->cur_link_settings.link_spread =
 672                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 673                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 674 }
 675
 676 static bool detect_dp(struct dc_link *link,
 677                       struct display_sink_capability *sink_caps,
 678                       bool *converter_disable_audio,
 679                       struct audio_support *audio_support,
 680                       enum dc_detect_reason reason)
 681 {
 682         bool boot = false;
 683
 684         sink_caps->signal = link_detect_sink(link, reason);
 685         sink_caps->transaction_type =
 686                 get_ddc_transaction_type(sink_caps->signal);
 687
 688         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 689                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 690
 691                 dpcd_set_source_specific_data(link);
 692
 693                 if (!detect_dp_sink_caps(link))
 694                         return false;
 695
 696                 if (is_mst_supported(link)) {
 697                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 698                         link->type = dc_connection_mst_branch;
 699
 700                         dal_ddc_service_set_transaction_type(link->ddc,
 701                                                              sink_caps->transaction_type);
 702
 703 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 704                         /* In case of fallback to SST when topology discovery below fails
 705                          * HDCP caps will be querried again later by the upper layer (caller
 706                          * of this function). */
 707                         query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 708 #endif
 709                         /*
 710                          * This call will initiate MST topology discovery. Which
 711                          * will detect MST ports and add new DRM connector DRM
 712                          * framework. Then read EDID via remote i2c over aux. In
 713                          * the end, will notify DRM detect result and save EDID
 714                          * into DRM framework.
 715                          *
 716                          * .detect is called by .fill_modes.
 717                          * .fill_modes is called by user mode ioctl
 718                          * DRM_IOCTL_MODE_GETCONNECTOR.
 719                          *
 720                          * .get_modes is called by .fill_modes.
 721                          *
 722                          * call .get_modes, AMDGPU DM implementation will create
 723                          * new dc_sink and add to dc_link. For long HPD plug
 724                          * in/out, MST has its own handle.
 725                          *
 726                          * Therefore, just after dc_create, link->sink is not
 727                          * created for MST until user mode app calls
 728                          * DRM_IOCTL_MODE_GETCONNECTOR.
 729                          *
 730                          * Need check ->sink usages in case ->sink = NULL
 731                          * TODO: s3 resume check
 732                          */
 733                         if (reason == DETECT_REASON_BOOT)
 734                                 boot = true;
 735
 736                         dm_helpers_dp_update_branch_info(link->ctx, link);
 737
 738                         if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
 739                                                              link, boot)) {
 740                                 /* MST not supported */
 741                                 link->type = dc_connection_single;
 742                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 743                         }
 744                 }
 745
 746                 if (link->type != dc_connection_mst_branch &&
 747                     is_dp_active_dongle(link)) {
 748                         /* DP active dongles */
 749                         link->type = dc_connection_active_dongle;
 750                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 751                                 /*
 752                                  * active dongle unplug processing for short irq
 753                                  */
 754                                 link_disconnect_sink(link);
 755                                 return true;
 756                         }
 757
 758                         if (link->dpcd_caps.dongle_type !=
 759                             DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 760                                 *converter_disable_audio = true;
 761                 }
 762         } else {
 763                 /* DP passive dongles */
 764                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 765                                                                 sink_caps,
 766                                                                 audio_support);
 767         }
 768
 769         return true;
 770 }
 771
 772 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 773 {
 774         if (old_edid->length != new_edid->length)
 775                 return false;
 776
 777         if (new_edid->length == 0)
 778                 return false;
 779
 780         return (memcmp(old_edid->raw_edid,
 781                        new_edid->raw_edid, new_edid->length) == 0);
 782 }
 783
 784 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 785 {
 786         /**
 787          * something is terribly wrong if time out is > 200ms. (5Hz)
 788          * 500 microseconds * 400 tries us 200 ms
 789          **/
 790         unsigned int sleep_time_in_microseconds = 500;
 791         unsigned int tries_allowed = 400;
 792         bool is_in_alt_mode;
 793         unsigned long long enter_timestamp;
 794         unsigned long long finish_timestamp;
 795         unsigned long long time_taken_in_ns;
 796         int tries_taken;
 797
 798         DC_LOGGER_INIT(link->ctx->logger);
 799
 800         if (!link->link_enc->funcs->is_in_alt_mode)
 801                 return true;
 802
 803         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 804         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 805
 806         if (is_in_alt_mode)
 807                 return true;
 808
 809         enter_timestamp = dm_get_timestamp(link->ctx);
 810
 811         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 812                 udelay(sleep_time_in_microseconds);
 813                 /* ask the link if alt mode is enabled, if so return ok */
 814                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 815                         finish_timestamp = dm_get_timestamp(link->ctx);
 816                         time_taken_in_ns =
 817                                 dm_get_elapse_time_in_ns(link->ctx,
 818                                                          finish_timestamp,
 819                                                          enter_timestamp);
 820                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 821                                        div_u64(time_taken_in_ns, 1000000));
 822                         return true;
 823                 }
 824         }
 825         finish_timestamp = dm_get_timestamp(link->ctx);
 826         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 827                                                     enter_timestamp);
 828         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 829                        div_u64(time_taken_in_ns, 1000000));
 830         return false;
 831 }
 832
 833 /**
 834  * dc_link_detect() - Detect if a sink is attached to a given link
 835  *
 836  * link->local_sink is created or destroyed as needed.
 837  *
 838  * This does not create remote sinks but will trigger DM
 839  * to start MST detection if a branch is detected.
 840  */
 841 static bool dc_link_detect_helper(struct dc_link *link,
 842                                   enum dc_detect_reason reason)
 843 {
 844         struct dc_sink_init_data sink_init_data = { 0 };
 845         struct display_sink_capability sink_caps = { 0 };
 846         uint8_t i;
 847         bool converter_disable_audio = false;
 848         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 849         bool same_edid = false;
 850         enum dc_edid_status edid_status;
 851         struct dc_context *dc_ctx = link->ctx;
 852         struct dc_sink *sink = NULL;
 853         struct dc_sink *prev_sink = NULL;
 854         struct dpcd_caps prev_dpcd_caps;
 855         bool same_dpcd = true;
 856         enum dc_connection_type new_connection_type = dc_connection_none;
 857         bool perform_dp_seamless_boot = false;
 858
 859         DC_LOGGER_INIT(link->ctx->logger);
 860
 861         if (dc_is_virtual_signal(link->connector_signal))
 862                 return false;
 863
 864         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 865              link->connector_signal == SIGNAL_TYPE_EDP) &&
 866             link->local_sink) {
 867                 // need to re-write OUI and brightness in resume case
 868                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 869                         dpcd_set_source_specific_data(link);
 870                         dc_link_set_default_brightness_aux(link);
 871                         //TODO: use cached
 872                 }
 873
 874                 return true;
 875         }
 876
 877         if (!dc_link_detect_sink(link, &new_connection_type)) {
 878                 BREAK_TO_DEBUGGER();
 879                 return false;
 880         }
 881
 882         prev_sink = link->local_sink;
 883         if (prev_sink) {
 884                 dc_sink_retain(prev_sink);
 885                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 886         }
 887
 888         link_disconnect_sink(link);
 889         if (new_connection_type != dc_connection_none) {
 890                 link->type = new_connection_type;
 891                 link->link_state_valid = false;
 892
 893                 /* From Disconnected-to-Connected. */
 894                 switch (link->connector_signal) {
 895                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 896                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 897                         if (aud_support->hdmi_audio_native)
 898                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 899                         else
 900                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 901                         break;
 902                 }
 903
 904                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 905                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 906                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 907                         break;
 908                 }
 909
 910                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 911                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 912                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 913                         break;
 914                 }
 915
 916                 case SIGNAL_TYPE_LVDS: {
 917                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 918                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 919                         break;
 920                 }
 921
 922                 case SIGNAL_TYPE_EDP: {
 923                         read_current_link_settings_on_detect(link);
 924
 925                         dpcd_set_source_specific_data(link);
 926
 927                         detect_edp_sink_caps(link);
 928                         read_current_link_settings_on_detect(link);
 929                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 930                         sink_caps.signal = SIGNAL_TYPE_EDP;
 931                         break;
 932                 }
 933
 934                 case SIGNAL_TYPE_DISPLAY_PORT: {
 935                         /* wa HPD high coming too early*/
 936                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 937                                 /* if alt mode times out, return false */
 938                                 if (!wait_for_entering_dp_alt_mode(link))
 939                                         return false;
 940                         }
 941
 942                         if (!detect_dp(link, &sink_caps,
 943                                        &converter_disable_audio,
 944                                        aud_support, reason)) {
 945                                 if (prev_sink)
 946                                         dc_sink_release(prev_sink);
 947                                 return false;
 948                         }
 949
 950                         // Check if dpcp block is the same
 951                         if (prev_sink) {
 952                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
 953                                            sizeof(struct dpcd_caps)))
 954                                         same_dpcd = false;
 955                         }
 956                         /* Active dongle downstream unplug*/
 957                         if (link->type == dc_connection_active_dongle &&
 958                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 959                                 if (prev_sink)
 960                                         /* Downstream unplug */
 961                                         dc_sink_release(prev_sink);
 962                                 return true;
 963                         }
 964
 965                         if (link->type == dc_connection_mst_branch) {
 966                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 967                                           link->link_index);
 968                                 /* Need to setup mst link_cap struct here
 969                                  * otherwise dc_link_detect() will leave mst link_cap
 970                                  * empty which leads to allocate_mst_payload() has "0"
 971                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 972                                  */
 973                                 dp_verify_mst_link_cap(link);
 974
 975                                 if (prev_sink)
 976                                         dc_sink_release(prev_sink);
 977                                 return false;
 978                         }
 979
 980                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 981                         if (reason == DETECT_REASON_BOOT &&
 982                             !dc_ctx->dc->config.power_down_display_on_boot &&
 983                             link->link_status.link_active)
 984                                 perform_dp_seamless_boot = true;
 985
 986                         if (perform_dp_seamless_boot) {
 987                                 read_current_link_settings_on_detect(link);
 988                                 link->verified_link_cap = link->reported_link_cap;
 989                         }
 990
 991                         break;
 992                 }
 993
 994                 default:
 995                         DC_ERROR("Invalid connector type! signal:%d\n",
 996                                  link->connector_signal);
 997                         if (prev_sink)
 998                                 dc_sink_release(prev_sink);
 999                         return false;
1000                 } /* switch() */
1001
1002                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1003                         link->dpcd_sink_count =
1004                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1005                 else
1006                         link->dpcd_sink_count = 1;
1007
1008                 dal_ddc_service_set_transaction_type(link->ddc,
1009                                                      sink_caps.transaction_type);
1010
1011                 link->aux_mode =
1012                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1013
1014                 sink_init_data.link = link;
1015                 sink_init_data.sink_signal = sink_caps.signal;
1016
1017                 sink = dc_sink_create(&sink_init_data);
1018                 if (!sink) {
1019                         DC_ERROR("Failed to create sink!\n");
1020                         if (prev_sink)
1021                                 dc_sink_release(prev_sink);
1022                         return false;
1023                 }
1024
1025                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1026                 sink->converter_disable_audio = converter_disable_audio;
1027
1028                 /* dc_sink_create returns a new reference */
1029                 link->local_sink = sink;
1030
1031                 edid_status = dm_helpers_read_local_edid(link->ctx,
1032                                                          link, sink);
1033
1034                 switch (edid_status) {
1035                 case EDID_BAD_CHECKSUM:
1036                         DC_LOG_ERROR("EDID checksum invalid.\n");
1037                         break;
1038                 case EDID_NO_RESPONSE:
1039                         DC_LOG_ERROR("No EDID read.\n");
1040                         /*
1041                          * Abort detection for non-DP connectors if we have
1042                          * no EDID
1043                          *
1044                          * DP needs to report as connected if HDP is high
1045                          * even if we have no EDID in order to go to
1046                          * fail-safe mode
1047                          */
1048                         if (dc_is_hdmi_signal(link->connector_signal) ||
1049                             dc_is_dvi_signal(link->connector_signal)) {
1050                                 if (prev_sink)
1051                                         dc_sink_release(prev_sink);
1052
1053                                 return false;
1054                         }
1055                 default:
1056                         break;
1057                 }
1058
1059                 if (link->local_sink->edid_caps.panel_patch.disable_fec)
1060                         link->ctx->dc->debug.disable_fec = true;
1061
1062                 // Check if edid is the same
1063                 if ((prev_sink) &&
1064                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1065                         same_edid = is_same_edid(&prev_sink->dc_edid,
1066                                                  &sink->dc_edid);
1067
1068                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1069                         link->ctx->dc->debug.hdmi20_disable = true;
1070
1071                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1072                     sink_caps.transaction_type ==
1073                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1074                         /*
1075                          * TODO debug why Dell 2413 doesn't like
1076                          *  two link trainings
1077                          */
1078 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1079                         query_hdcp_capability(sink->sink_signal, link);
1080 #endif
1081
1082                         // verify link cap for SST non-seamless boot
1083                         if (!perform_dp_seamless_boot)
1084                                 dp_verify_link_cap_with_retries(link,
1085                                                                 &link->reported_link_cap,
1086                                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
1087                 } else {
1088                         // If edid is the same, then discard new sink and revert back to original sink
1089                         if (same_edid) {
1090                                 link_disconnect_remap(prev_sink, link);
1091                                 sink = prev_sink;
1092                                 prev_sink = NULL;
1093                         }
1094 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1095                         query_hdcp_capability(sink->sink_signal, link);
1096 #endif
1097                 }
1098
1099                 /* HDMI-DVI Dongle */
1100                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1101                     !sink->edid_caps.edid_hdmi)
1102                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1103
1104                 /* Connectivity log: detection */
1105                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1106                         CONN_DATA_DETECT(link,
1107                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1108                                          DC_EDID_BLOCK_SIZE,
1109                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1110                 }
1111
1112                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1113                         "manufacturer_id = %X, "
1114                         "product_id = %X, "
1115                         "serial_number = %X, "
1116                         "manufacture_week = %d, "
1117                         "manufacture_year = %d, "
1118                         "display_name = %s, "
1119                         "speaker_flag = %d, "
1120                         "audio_mode_count = %d\n",
1121                         __func__,
1122                         sink->edid_caps.manufacturer_id,
1123                         sink->edid_caps.product_id,
1124                         sink->edid_caps.serial_number,
1125                         sink->edid_caps.manufacture_week,
1126                         sink->edid_caps.manufacture_year,
1127                         sink->edid_caps.display_name,
1128                         sink->edid_caps.speaker_flags,
1129                         sink->edid_caps.audio_mode_count);
1130
1131                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1132                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1133                                 "format_code = %d, "
1134                                 "channel_count = %d, "
1135                                 "sample_rate = %d, "
1136                                 "sample_size = %d\n",
1137                                 __func__,
1138                                 i,
1139                                 sink->edid_caps.audio_modes[i].format_code,
1140                                 sink->edid_caps.audio_modes[i].channel_count,
1141                                 sink->edid_caps.audio_modes[i].sample_rate,
1142                                 sink->edid_caps.audio_modes[i].sample_size);
1143                 }
1144         } else {
1145                 /* From Connected-to-Disconnected. */
1146                 if (link->type == dc_connection_mst_branch) {
1147                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1148                                   link->link_index);
1149
1150                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1151
1152                         link->mst_stream_alloc_table.stream_count = 0;
1153                         memset(link->mst_stream_alloc_table.stream_allocations,
1154                                0,
1155                                sizeof(link->mst_stream_alloc_table.stream_allocations));
1156                 }
1157
1158                 link->type = dc_connection_none;
1159                 sink_caps.signal = SIGNAL_TYPE_NONE;
1160                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1161                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1162                  *  the dongle is still there and limits the number of modes we can emulate.
1163                  *  Clear dongle_max_pix_clk on disconnect to fix this
1164                  */
1165                 link->dongle_max_pix_clk = 0;
1166         }
1167
1168         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1169                   link->link_index, sink,
1170                   (sink_caps.signal ==
1171                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1172                   prev_sink, same_dpcd, same_edid);
1173
1174         if (prev_sink)
1175                 dc_sink_release(prev_sink);
1176
1177         return true;
1178 }
1179
1180 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1181 {
1182         const struct dc *dc = link->dc;
1183         bool ret;
1184
1185         /* get out of low power state */
1186         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1187
1188         ret = dc_link_detect_helper(link, reason);
1189
1190         /* Go back to power optimized state */
1191         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1192
1193         return ret;
1194 }
1195
1196 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1197 {
1198         uint32_t state;
1199
1200         dal_gpio_lock_pin(dc_link->hpd_gpio);
1201         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1202         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1203
1204         return state;
1205 }
1206
1207 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1208 {
1209         struct gpio *hpd;
1210         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1211
1212         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1213                            link->ctx->gpio_service);
1214
1215         if (hpd) {
1216                 switch (dal_irq_get_source(hpd)) {
1217                 case DC_IRQ_SOURCE_HPD1:
1218                         hpd_id = HPD_SOURCEID1;
1219                 break;
1220                 case DC_IRQ_SOURCE_HPD2:
1221                         hpd_id = HPD_SOURCEID2;
1222                 break;
1223                 case DC_IRQ_SOURCE_HPD3:
1224                         hpd_id = HPD_SOURCEID3;
1225                 break;
1226                 case DC_IRQ_SOURCE_HPD4:
1227                         hpd_id = HPD_SOURCEID4;
1228                 break;
1229                 case DC_IRQ_SOURCE_HPD5:
1230                         hpd_id = HPD_SOURCEID5;
1231                 break;
1232                 case DC_IRQ_SOURCE_HPD6:
1233                         hpd_id = HPD_SOURCEID6;
1234                 break;
1235                 default:
1236                         BREAK_TO_DEBUGGER();
1237                 break;
1238                 }
1239
1240                 dal_gpio_destroy_irq(&hpd);
1241         }
1242
1243         return hpd_id;
1244 }
1245
1246 static enum channel_id get_ddc_line(struct dc_link *link)
1247 {
1248         struct ddc *ddc;
1249         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1250
1251         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1252
1253         if (ddc) {
1254                 switch (dal_ddc_get_line(ddc)) {
1255                 case GPIO_DDC_LINE_DDC1:
1256                         channel = CHANNEL_ID_DDC1;
1257                         break;
1258                 case GPIO_DDC_LINE_DDC2:
1259                         channel = CHANNEL_ID_DDC2;
1260                         break;
1261                 case GPIO_DDC_LINE_DDC3:
1262                         channel = CHANNEL_ID_DDC3;
1263                         break;
1264                 case GPIO_DDC_LINE_DDC4:
1265                         channel = CHANNEL_ID_DDC4;
1266                         break;
1267                 case GPIO_DDC_LINE_DDC5:
1268                         channel = CHANNEL_ID_DDC5;
1269                         break;
1270                 case GPIO_DDC_LINE_DDC6:
1271                         channel = CHANNEL_ID_DDC6;
1272                         break;
1273                 case GPIO_DDC_LINE_DDC_VGA:
1274                         channel = CHANNEL_ID_DDC_VGA;
1275                         break;
1276                 case GPIO_DDC_LINE_I2C_PAD:
1277                         channel = CHANNEL_ID_I2C_PAD;
1278                         break;
1279                 default:
1280                         BREAK_TO_DEBUGGER();
1281                         break;
1282                 }
1283         }
1284
1285         return channel;
1286 }
1287
1288 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1289 {
1290         switch (encoder.id) {
1291         case ENCODER_ID_INTERNAL_UNIPHY:
1292                 switch (encoder.enum_id) {
1293                 case ENUM_ID_1:
1294                         return TRANSMITTER_UNIPHY_A;
1295                 case ENUM_ID_2:
1296                         return TRANSMITTER_UNIPHY_B;
1297                 default:
1298                         return TRANSMITTER_UNKNOWN;
1299                 }
1300         break;
1301         case ENCODER_ID_INTERNAL_UNIPHY1:
1302                 switch (encoder.enum_id) {
1303                 case ENUM_ID_1:
1304                         return TRANSMITTER_UNIPHY_C;
1305                 case ENUM_ID_2:
1306                         return TRANSMITTER_UNIPHY_D;
1307                 default:
1308                         return TRANSMITTER_UNKNOWN;
1309                 }
1310         break;
1311         case ENCODER_ID_INTERNAL_UNIPHY2:
1312                 switch (encoder.enum_id) {
1313                 case ENUM_ID_1:
1314                         return TRANSMITTER_UNIPHY_E;
1315                 case ENUM_ID_2:
1316                         return TRANSMITTER_UNIPHY_F;
1317                 default:
1318                         return TRANSMITTER_UNKNOWN;
1319                 }
1320         break;
1321         case ENCODER_ID_INTERNAL_UNIPHY3:
1322                 switch (encoder.enum_id) {
1323                 case ENUM_ID_1:
1324                         return TRANSMITTER_UNIPHY_G;
1325                 default:
1326                         return TRANSMITTER_UNKNOWN;
1327                 }
1328         break;
1329         case ENCODER_ID_EXTERNAL_NUTMEG:
1330                 switch (encoder.enum_id) {
1331                 case ENUM_ID_1:
1332                         return TRANSMITTER_NUTMEG_CRT;
1333                 default:
1334                         return TRANSMITTER_UNKNOWN;
1335                 }
1336         break;
1337         case ENCODER_ID_EXTERNAL_TRAVIS:
1338                 switch (encoder.enum_id) {
1339                 case ENUM_ID_1:
1340                         return TRANSMITTER_TRAVIS_CRT;
1341                 case ENUM_ID_2:
1342                         return TRANSMITTER_TRAVIS_LCD;
1343                 default:
1344                         return TRANSMITTER_UNKNOWN;
1345                 }
1346         break;
1347         default:
1348                 return TRANSMITTER_UNKNOWN;
1349         }
1350 }
1351
1352 static bool dc_link_construct(struct dc_link *link,
1353                               const struct link_init_data *init_params)
1354 {
1355         uint8_t i;
1356         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1357         struct dc_context *dc_ctx = init_params->ctx;
1358         struct encoder_init_data enc_init_data = { 0 };
1359         struct panel_init_data panel_init_data = { 0 };
1360         struct integrated_info info = {{{ 0 }}};
1361         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1362         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1363
1364         DC_LOGGER_INIT(dc_ctx->logger);
1365
1366         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1367         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1368
1369         link->link_status.dpcd_caps = &link->dpcd_caps;
1370
1371         link->dc = init_params->dc;
1372         link->ctx = dc_ctx;
1373         link->link_index = init_params->link_index;
1374
1375         memset(&link->preferred_training_settings, 0,
1376                sizeof(struct dc_link_training_overrides));
1377         memset(&link->preferred_link_setting, 0,
1378                sizeof(struct dc_link_settings));
1379
1380         link->link_id =
1381                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1382
1383         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1384                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1385                                      __func__, init_params->connector_index,
1386                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1387                 goto create_fail;
1388         }
1389
1390         if (link->dc->res_pool->funcs->link_init)
1391                 link->dc->res_pool->funcs->link_init(link);
1392
1393         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1394                                       link->ctx->gpio_service);
1395         if (link->hpd_gpio) {
1396                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1397                 dal_gpio_unlock_pin(link->hpd_gpio);
1398                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1399         }
1400
1401         switch (link->link_id.id) {
1402         case CONNECTOR_ID_HDMI_TYPE_A:
1403                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1404
1405                 break;
1406         case CONNECTOR_ID_SINGLE_LINK_DVID:
1407         case CONNECTOR_ID_SINGLE_LINK_DVII:
1408                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1409                 break;
1410         case CONNECTOR_ID_DUAL_LINK_DVID:
1411         case CONNECTOR_ID_DUAL_LINK_DVII:
1412                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1413                 break;
1414         case CONNECTOR_ID_DISPLAY_PORT:
1415                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1416
1417                 if (link->hpd_gpio)
1418                         link->irq_source_hpd_rx =
1419                                         dal_irq_get_rx_source(link->hpd_gpio);
1420
1421                 break;
1422         case CONNECTOR_ID_EDP:
1423                 link->connector_signal = SIGNAL_TYPE_EDP;
1424
1425                 if (link->hpd_gpio) {
1426                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1427                         link->irq_source_hpd_rx =
1428                                         dal_irq_get_rx_source(link->hpd_gpio);
1429                 }
1430
1431                 break;
1432         case CONNECTOR_ID_LVDS:
1433                 link->connector_signal = SIGNAL_TYPE_LVDS;
1434                 break;
1435         default:
1436                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1437                                link->link_id.id);
1438                 goto create_fail;
1439         }
1440
1441         /* TODO: #DAL3 Implement id to str function.*/
1442         LINK_INFO("Connector[%d] description:"
1443                   "signal %d\n",
1444                   init_params->connector_index,
1445                   link->connector_signal);
1446
1447         ddc_service_init_data.ctx = link->ctx;
1448         ddc_service_init_data.id = link->link_id;
1449         ddc_service_init_data.link = link;
1450         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1451
1452         if (!link->ddc) {
1453                 DC_ERROR("Failed to create ddc_service!\n");
1454                 goto ddc_create_fail;
1455         }
1456
1457         link->ddc_hw_inst =
1458                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1459
1460
1461         if (link->dc->res_pool->funcs->panel_create &&
1462                 (link->link_id.id == CONNECTOR_ID_EDP ||
1463                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1464                 panel_init_data.ctx = dc_ctx;
1465                 panel_init_data.inst = 0;
1466                 link->panel =
1467                         link->dc->res_pool->funcs->panel_create(
1468                                                                 &panel_init_data);
1469
1470                 if (link->panel == NULL) {
1471                         DC_ERROR("Failed to create link panel!\n");
1472                         goto panel_create_fail;
1473                 }
1474         }
1475
1476         enc_init_data.ctx = dc_ctx;
1477         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1478                               &enc_init_data.encoder);
1479         enc_init_data.connector = link->link_id;
1480         enc_init_data.channel = get_ddc_line(link);
1481         enc_init_data.hpd_source = get_hpd_line(link);
1482
1483         link->hpd_src = enc_init_data.hpd_source;
1484
1485         enc_init_data.transmitter =
1486                 translate_encoder_to_transmitter(enc_init_data.encoder);
1487         link->link_enc =
1488                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1489
1490         if (!link->link_enc) {
1491                 DC_ERROR("Failed to create link encoder!\n");
1492                 goto link_enc_create_fail;
1493         }
1494
1495         link->link_enc_hw_inst = link->link_enc->transmitter;
1496
1497         for (i = 0; i < 4; i++) {
1498                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1499                                              link->link_id, i,
1500                                              &link->device_tag) != BP_RESULT_OK) {
1501                         DC_ERROR("Failed to find device tag!\n");
1502                         goto device_tag_fail;
1503                 }
1504
1505                 /* Look for device tag that matches connector signal,
1506                  * CRT for rgb, LCD for other supported signal tyes
1507                  */
1508                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1509                                                       link->device_tag.dev_id))
1510                         continue;
1511                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1512                     link->connector_signal != SIGNAL_TYPE_RGB)
1513                         continue;
1514                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1515                     link->connector_signal == SIGNAL_TYPE_RGB)
1516                         continue;
1517                 break;
1518         }
1519
1520         if (bios->integrated_info)
1521                 info = *bios->integrated_info;
1522
1523         /* Look for channel mapping corresponding to connector and device tag */
1524         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1525                 struct external_display_path *path =
1526                         &info.ext_disp_conn_info.path[i];
1527
1528                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1529                     path->device_connector_id.id == link->link_id.id &&
1530                     path->device_connector_id.type == link->link_id.type) {
1531                         if (link->device_tag.acpi_device != 0 &&
1532                             path->device_acpi_enum == link->device_tag.acpi_device) {
1533                                 link->ddi_channel_mapping = path->channel_mapping;
1534                                 link->chip_caps = path->caps;
1535                         } else if (path->device_tag ==
1536                                    link->device_tag.dev_id.raw_device_tag) {
1537                                 link->ddi_channel_mapping = path->channel_mapping;
1538                                 link->chip_caps = path->caps;
1539                         }
1540                         break;
1541                 }
1542         }
1543
1544         /*
1545          * TODO check if GPIO programmed correctly
1546          *
1547          * If GPIO isn't programmed correctly HPD might not rise or drain
1548          * fast enough, leading to bounces.
1549          */
1550         program_hpd_filter(link);
1551
1552         link->psr_settings.psr_version = PSR_VERSION_UNSUPPORTED;
1553
1554         return true;
1555 device_tag_fail:
1556         link->link_enc->funcs->destroy(&link->link_enc);
1557 link_enc_create_fail:
1558         if (link->panel != NULL)
1559                 link->panel->funcs->destroy(&link->panel);
1560 panel_create_fail:
1561         dal_ddc_service_destroy(&link->ddc);
1562 ddc_create_fail:
1563 create_fail:
1564
1565         if (link->hpd_gpio) {
1566                 dal_gpio_destroy_irq(&link->hpd_gpio);
1567                 link->hpd_gpio = NULL;
1568         }
1569
1570         return false;
1571 }
1572
1573 /*******************************************************************************
1574  * Public functions
1575  ******************************************************************************/
1576 struct dc_link *link_create(const struct link_init_data *init_params)
1577 {
1578         struct dc_link *link =
1579                         kzalloc(sizeof(*link), GFP_KERNEL);
1580
1581         if (NULL == link)
1582                 goto alloc_fail;
1583
1584         if (false == dc_link_construct(link, init_params))
1585                 goto construct_fail;
1586
1587         return link;
1588
1589 construct_fail:
1590         kfree(link);
1591
1592 alloc_fail:
1593         return NULL;
1594 }
1595
1596 void link_destroy(struct dc_link **link)
1597 {
1598         dc_link_destruct(*link);
1599         kfree(*link);
1600         *link = NULL;
1601 }
1602
1603 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1604 {
1605         struct dc_stream_state *stream = pipe_ctx->stream;
1606         struct dc_link *link = stream->link;
1607         union down_spread_ctrl old_downspread;
1608         union down_spread_ctrl new_downspread;
1609
1610         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1611                         &old_downspread.raw, sizeof(old_downspread));
1612
1613         new_downspread.raw = old_downspread.raw;
1614
1615         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1616                         (stream->ignore_msa_timing_param) ? 1 : 0;
1617
1618         if (new_downspread.raw != old_downspread.raw) {
1619                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1620                         &new_downspread.raw, sizeof(new_downspread));
1621         }
1622 }
1623
1624 static enum dc_status enable_link_dp(struct dc_state *state,
1625                                      struct pipe_ctx *pipe_ctx)
1626 {
1627         struct dc_stream_state *stream = pipe_ctx->stream;
1628         enum dc_status status;
1629         bool skip_video_pattern;
1630         struct dc_link *link = stream->link;
1631         struct dc_link_settings link_settings = {0};
1632         bool fec_enable;
1633         int i;
1634         bool apply_seamless_boot_optimization = false;
1635         uint32_t bl_oled_enable_delay = 50; // in ms
1636
1637         // check for seamless boot
1638         for (i = 0; i < state->stream_count; i++) {
1639                 if (state->streams[i]->apply_seamless_boot_optimization) {
1640                         apply_seamless_boot_optimization = true;
1641                         break;
1642                 }
1643         }
1644
1645         /* get link settings for video mode timing */
1646         decide_link_settings(stream, &link_settings);
1647
1648         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1649                 /*in case it is not on*/
1650                 link->dc->hwss.edp_power_control(link, true);
1651                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1652         }
1653
1654         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1655                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1656         if (state->clk_mgr && !apply_seamless_boot_optimization)
1657                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1658                                                      state, false);
1659
1660         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1661         dpcd_set_source_specific_data(link);
1662
1663         skip_video_pattern = true;
1664
1665         if (link_settings.link_rate == LINK_RATE_LOW)
1666                 skip_video_pattern = false;
1667
1668         if (perform_link_training_with_retries(&link_settings,
1669                                                skip_video_pattern,
1670                                                LINK_TRAINING_ATTEMPTS,
1671                                                pipe_ctx,
1672                                                pipe_ctx->stream->signal)) {
1673                 link->cur_link_settings = link_settings;
1674                 status = DC_OK;
1675         } else {
1676                 status = DC_FAIL_DP_LINK_TRAINING;
1677         }
1678
1679         if (link->preferred_training_settings.fec_enable)
1680                 fec_enable = *link->preferred_training_settings.fec_enable;
1681         else
1682                 fec_enable = true;
1683
1684         dp_set_fec_enable(link, fec_enable);
1685
1686         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1687         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1688                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1689                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1690                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1691                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1692                         msleep(bl_oled_enable_delay);
1693                 dc_link_backlight_enable_aux(link, true);
1694         }
1695
1696         return status;
1697 }
1698
1699 static enum dc_status enable_link_edp(
1700                 struct dc_state *state,
1701                 struct pipe_ctx *pipe_ctx)
1702 {
1703         enum dc_status status;
1704
1705         status = enable_link_dp(state, pipe_ctx);
1706
1707         return status;
1708 }
1709
1710 static enum dc_status enable_link_dp_mst(
1711                 struct dc_state *state,
1712                 struct pipe_ctx *pipe_ctx)
1713 {
1714         struct dc_link *link = pipe_ctx->stream->link;
1715
1716         /* sink signal type after MST branch is MST. Multiple MST sinks
1717          * share one link. Link DP PHY is enable or training only once.
1718          */
1719         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1720                 return DC_OK;
1721
1722         /* clear payload table */
1723         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1724
1725         /* to make sure the pending down rep can be processed
1726          * before enabling the link
1727          */
1728         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1729
1730         /* set the sink to MST mode before enabling the link */
1731         dp_enable_mst_on_sink(link, true);
1732
1733         return enable_link_dp(state, pipe_ctx);
1734 }
1735
1736 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1737                 enum engine_id eng_id,
1738                 struct ext_hdmi_settings *settings)
1739 {
1740         bool result = false;
1741         int i = 0;
1742         struct integrated_info *integrated_info =
1743                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1744
1745         if (integrated_info == NULL)
1746                 return false;
1747
1748         /*
1749          * Get retimer settings from sbios for passing SI eye test for DCE11
1750          * The setting values are varied based on board revision and port id
1751          * Therefore the setting values of each ports is passed by sbios.
1752          */
1753
1754         // Check if current bios contains ext Hdmi settings
1755         if (integrated_info->gpu_cap_info & 0x20) {
1756                 switch (eng_id) {
1757                 case ENGINE_ID_DIGA:
1758                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1759                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1760                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1761                         memmove(settings->reg_settings,
1762                                         integrated_info->dp0_ext_hdmi_reg_settings,
1763                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1764                         memmove(settings->reg_settings_6g,
1765                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1766                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1767                         result = true;
1768                         break;
1769                 case ENGINE_ID_DIGB:
1770                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1771                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1772                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1773                         memmove(settings->reg_settings,
1774                                         integrated_info->dp1_ext_hdmi_reg_settings,
1775                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1776                         memmove(settings->reg_settings_6g,
1777                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1778                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1779                         result = true;
1780                         break;
1781                 case ENGINE_ID_DIGC:
1782                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1783                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1784                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1785                         memmove(settings->reg_settings,
1786                                         integrated_info->dp2_ext_hdmi_reg_settings,
1787                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1788                         memmove(settings->reg_settings_6g,
1789                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1790                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1791                         result = true;
1792                         break;
1793                 case ENGINE_ID_DIGD:
1794                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1795                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1796                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1797                         memmove(settings->reg_settings,
1798                                         integrated_info->dp3_ext_hdmi_reg_settings,
1799                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1800                         memmove(settings->reg_settings_6g,
1801                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1802                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1803                         result = true;
1804                         break;
1805                 default:
1806                         break;
1807                 }
1808
1809                 if (result == true) {
1810                         // Validate settings from bios integrated info table
1811                         if (settings->slv_addr == 0)
1812                                 return false;
1813                         if (settings->reg_num > 9)
1814                                 return false;
1815                         if (settings->reg_num_6g > 3)
1816                                 return false;
1817
1818                         for (i = 0; i < settings->reg_num; i++) {
1819                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1820                                         return false;
1821                         }
1822
1823                         for (i = 0; i < settings->reg_num_6g; i++) {
1824                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1825                                         return false;
1826                         }
1827                 }
1828         }
1829
1830         return result;
1831 }
1832
1833 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1834                 uint8_t address, uint8_t *buffer, uint32_t length)
1835 {
1836         struct i2c_command cmd = {0};
1837         struct i2c_payload payload = {0};
1838
1839         memset(&payload, 0, sizeof(payload));
1840         memset(&cmd, 0, sizeof(cmd));
1841
1842         cmd.number_of_payloads = 1;
1843         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1844         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1845
1846         payload.address = address;
1847         payload.data = buffer;
1848         payload.length = length;
1849         payload.write = true;
1850         cmd.payloads = &payload;
1851
1852         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1853                         pipe_ctx->stream->link, &cmd))
1854                 return true;
1855
1856         return false;
1857 }
1858
1859 static void write_i2c_retimer_setting(
1860                 struct pipe_ctx *pipe_ctx,
1861                 bool is_vga_mode,
1862                 bool is_over_340mhz,
1863                 struct ext_hdmi_settings *settings)
1864 {
1865         uint8_t slave_address = (settings->slv_addr >> 1);
1866         uint8_t buffer[2];
1867         const uint8_t apply_rx_tx_change = 0x4;
1868         uint8_t offset = 0xA;
1869         uint8_t value = 0;
1870         int i = 0;
1871         bool i2c_success = false;
1872         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1873
1874         memset(&buffer, 0, sizeof(buffer));
1875
1876         /* Start Ext-Hdmi programming*/
1877
1878         for (i = 0; i < settings->reg_num; i++) {
1879                 /* Apply 3G settings */
1880                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1881
1882                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1883                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1884                         i2c_success = i2c_write(pipe_ctx, slave_address,
1885                                                 buffer, sizeof(buffer));
1886                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1887                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1888                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1889
1890                         if (!i2c_success)
1891                                 goto i2c_write_fail;
1892
1893                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1894                          * needs to be set to 1 on every 0xA-0xC write.
1895                          */
1896                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1897                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1898                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1899
1900                                 /* Query current value from offset 0xA */
1901                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1902                                         value = settings->reg_settings[i].i2c_reg_val;
1903                                 else {
1904                                         i2c_success =
1905                                                 dal_ddc_service_query_ddc_data(
1906                                                 pipe_ctx->stream->link->ddc,
1907                                                 slave_address, &offset, 1, &value, 1);
1908                                         if (!i2c_success)
1909                                                 goto i2c_write_fail;
1910                                 }
1911
1912                                 buffer[0] = offset;
1913                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1914                                 buffer[1] = value | apply_rx_tx_change;
1915                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1916                                                 buffer, sizeof(buffer));
1917                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1918                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1919                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1920                                 if (!i2c_success)
1921                                         goto i2c_write_fail;
1922                         }
1923                 }
1924         }
1925
1926         /* Apply 3G settings */
1927         if (is_over_340mhz) {
1928                 for (i = 0; i < settings->reg_num_6g; i++) {
1929                         /* Apply 3G settings */
1930                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1931
1932                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1933                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1934                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1935                                                         buffer, sizeof(buffer));
1936                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1937                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1938                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1939
1940                                 if (!i2c_success)
1941                                         goto i2c_write_fail;
1942
1943                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1944                                  * needs to be set to 1 on every 0xA-0xC write.
1945                                  */
1946                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1947                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1948                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1949
1950                                         /* Query current value from offset 0xA */
1951                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1952                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1953                                         else {
1954                                                 i2c_success =
1955                                                                 dal_ddc_service_query_ddc_data(
1956                                                                 pipe_ctx->stream->link->ddc,
1957                                                                 slave_address, &offset, 1, &value, 1);
1958                                                 if (!i2c_success)
1959                                                         goto i2c_write_fail;
1960                                         }
1961
1962                                         buffer[0] = offset;
1963                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1964                                         buffer[1] = value | apply_rx_tx_change;
1965                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1966                                                         buffer, sizeof(buffer));
1967                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1968                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1969                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1970                                         if (!i2c_success)
1971                                                 goto i2c_write_fail;
1972                                 }
1973                         }
1974                 }
1975         }
1976
1977         if (is_vga_mode) {
1978                 /* Program additional settings if using 640x480 resolution */
1979
1980                 /* Write offset 0xFF to 0x01 */
1981                 buffer[0] = 0xff;
1982                 buffer[1] = 0x01;
1983                 i2c_success = i2c_write(pipe_ctx, slave_address,
1984                                 buffer, sizeof(buffer));
1985                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1986                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1987                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1988                 if (!i2c_success)
1989                         goto i2c_write_fail;
1990
1991                 /* Write offset 0x00 to 0x23 */
1992                 buffer[0] = 0x00;
1993                 buffer[1] = 0x23;
1994                 i2c_success = i2c_write(pipe_ctx, slave_address,
1995                                 buffer, sizeof(buffer));
1996                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1997                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1998                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1999                 if (!i2c_success)
2000                         goto i2c_write_fail;
2001
2002                 /* Write offset 0xff to 0x00 */
2003                 buffer[0] = 0xff;
2004                 buffer[1] = 0x00;
2005                 i2c_success = i2c_write(pipe_ctx, slave_address,
2006                                 buffer, sizeof(buffer));
2007                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2008                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2009                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2010                 if (!i2c_success)
2011                         goto i2c_write_fail;
2012
2013         }
2014
2015         return;
2016
2017 i2c_write_fail:
2018         DC_LOG_DEBUG("Set retimer failed");
2019 }
2020
2021 static void write_i2c_default_retimer_setting(
2022                 struct pipe_ctx *pipe_ctx,
2023                 bool is_vga_mode,
2024                 bool is_over_340mhz)
2025 {
2026         uint8_t slave_address = (0xBA >> 1);
2027         uint8_t buffer[2];
2028         bool i2c_success = false;
2029         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2030
2031         memset(&buffer, 0, sizeof(buffer));
2032
2033         /* Program Slave Address for tuning single integrity */
2034         /* Write offset 0x0A to 0x13 */
2035         buffer[0] = 0x0A;
2036         buffer[1] = 0x13;
2037         i2c_success = i2c_write(pipe_ctx, slave_address,
2038                         buffer, sizeof(buffer));
2039         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2040                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2041                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2042         if (!i2c_success)
2043                 goto i2c_write_fail;
2044
2045         /* Write offset 0x0A to 0x17 */
2046         buffer[0] = 0x0A;
2047         buffer[1] = 0x17;
2048         i2c_success = i2c_write(pipe_ctx, slave_address,
2049                         buffer, sizeof(buffer));
2050         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2051                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2052                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2053         if (!i2c_success)
2054                 goto i2c_write_fail;
2055
2056         /* Write offset 0x0B to 0xDA or 0xD8 */
2057         buffer[0] = 0x0B;
2058         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2059         i2c_success = i2c_write(pipe_ctx, slave_address,
2060                         buffer, sizeof(buffer));
2061         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2062                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2063                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2064         if (!i2c_success)
2065                 goto i2c_write_fail;
2066
2067         /* Write offset 0x0A to 0x17 */
2068         buffer[0] = 0x0A;
2069         buffer[1] = 0x17;
2070         i2c_success = i2c_write(pipe_ctx, slave_address,
2071                         buffer, sizeof(buffer));
2072         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2073                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2074                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2075         if (!i2c_success)
2076                 goto i2c_write_fail;
2077
2078         /* Write offset 0x0C to 0x1D or 0x91 */
2079         buffer[0] = 0x0C;
2080         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2081         i2c_success = i2c_write(pipe_ctx, slave_address,
2082                         buffer, sizeof(buffer));
2083         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2084                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2085                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2086         if (!i2c_success)
2087                 goto i2c_write_fail;
2088
2089         /* Write offset 0x0A to 0x17 */
2090         buffer[0] = 0x0A;
2091         buffer[1] = 0x17;
2092         i2c_success = i2c_write(pipe_ctx, slave_address,
2093                         buffer, sizeof(buffer));
2094         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2095                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2096                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2097         if (!i2c_success)
2098                 goto i2c_write_fail;
2099
2100
2101         if (is_vga_mode) {
2102                 /* Program additional settings if using 640x480 resolution */
2103
2104                 /* Write offset 0xFF to 0x01 */
2105                 buffer[0] = 0xff;
2106                 buffer[1] = 0x01;
2107                 i2c_success = i2c_write(pipe_ctx, slave_address,
2108                                 buffer, sizeof(buffer));
2109                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2110                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2111                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2112                 if (!i2c_success)
2113                         goto i2c_write_fail;
2114
2115                 /* Write offset 0x00 to 0x23 */
2116                 buffer[0] = 0x00;
2117                 buffer[1] = 0x23;
2118                 i2c_success = i2c_write(pipe_ctx, slave_address,
2119                                 buffer, sizeof(buffer));
2120                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2121                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2122                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2123                 if (!i2c_success)
2124                         goto i2c_write_fail;
2125
2126                 /* Write offset 0xff to 0x00 */
2127                 buffer[0] = 0xff;
2128                 buffer[1] = 0x00;
2129                 i2c_success = i2c_write(pipe_ctx, slave_address,
2130                                 buffer, sizeof(buffer));
2131                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2132                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2133                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2134                 if (!i2c_success)
2135                         goto i2c_write_fail;
2136         }
2137
2138         return;
2139
2140 i2c_write_fail:
2141         DC_LOG_DEBUG("Set default retimer failed");
2142 }
2143
2144 static void write_i2c_redriver_setting(
2145                 struct pipe_ctx *pipe_ctx,
2146                 bool is_over_340mhz)
2147 {
2148         uint8_t slave_address = (0xF0 >> 1);
2149         uint8_t buffer[16];
2150         bool i2c_success = false;
2151         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2152
2153         memset(&buffer, 0, sizeof(buffer));
2154
2155         // Program Slave Address for tuning single integrity
2156         buffer[3] = 0x4E;
2157         buffer[4] = 0x4E;
2158         buffer[5] = 0x4E;
2159         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2160
2161         i2c_success = i2c_write(pipe_ctx, slave_address,
2162                                         buffer, sizeof(buffer));
2163         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2164                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2165                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2166                 i2c_success = %d\n",
2167                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2168
2169         if (!i2c_success)
2170                 DC_LOG_DEBUG("Set redriver failed");
2171 }
2172
2173 static void disable_link(struct dc_link *link, enum signal_type signal)
2174 {
2175         /*
2176          * TODO: implement call for dp_set_hw_test_pattern
2177          * it is needed for compliance testing
2178          */
2179
2180         /* Here we need to specify that encoder output settings
2181          * need to be calculated as for the set mode,
2182          * it will lead to querying dynamic link capabilities
2183          * which should be done before enable output
2184          */
2185
2186         if (dc_is_dp_signal(signal)) {
2187                 /* SST DP, eDP */
2188                 if (dc_is_dp_sst_signal(signal))
2189                         dp_disable_link_phy(link, signal);
2190                 else
2191                         dp_disable_link_phy_mst(link, signal);
2192
2193                 if (dc_is_dp_sst_signal(signal) ||
2194                                 link->mst_stream_alloc_table.stream_count == 0) {
2195                         dp_set_fec_enable(link, false);
2196                         dp_set_fec_ready(link, false);
2197                 }
2198         } else {
2199                 if (signal != SIGNAL_TYPE_VIRTUAL)
2200                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2201         }
2202
2203         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2204                 /* MST disable link only when no stream use the link */
2205                 if (link->mst_stream_alloc_table.stream_count <= 0)
2206                         link->link_status.link_active = false;
2207         } else {
2208                 link->link_status.link_active = false;
2209         }
2210 }
2211
2212 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2213 {
2214         struct dc_stream_state *stream = pipe_ctx->stream;
2215         struct dc_link *link = stream->link;
2216         enum dc_color_depth display_color_depth;
2217         enum engine_id eng_id;
2218         struct ext_hdmi_settings settings = {0};
2219         bool is_over_340mhz = false;
2220         bool is_vga_mode = (stream->timing.h_addressable == 640)
2221                         && (stream->timing.v_addressable == 480);
2222
2223         if (stream->phy_pix_clk == 0)
2224                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2225         if (stream->phy_pix_clk > 340000)
2226                 is_over_340mhz = true;
2227
2228         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2229                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2230                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2231                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2232                         /* DP159, Retimer settings */
2233                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2234
2235                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2236                                 write_i2c_retimer_setting(pipe_ctx,
2237                                                 is_vga_mode, is_over_340mhz, &settings);
2238                         } else {
2239                                 write_i2c_default_retimer_setting(pipe_ctx,
2240                                                 is_vga_mode, is_over_340mhz);
2241                         }
2242                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2243                         /* PI3EQX1204, Redriver settings */
2244                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2245                 }
2246         }
2247
2248         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2249                 dal_ddc_service_write_scdc_data(
2250                         stream->link->ddc,
2251                         stream->phy_pix_clk,
2252                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2253
2254         memset(&stream->link->cur_link_settings, 0,
2255                         sizeof(struct dc_link_settings));
2256
2257         display_color_depth = stream->timing.display_color_depth;
2258         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2259                 display_color_depth = COLOR_DEPTH_888;
2260
2261         link->link_enc->funcs->enable_tmds_output(
2262                         link->link_enc,
2263                         pipe_ctx->clock_source->id,
2264                         display_color_depth,
2265                         pipe_ctx->stream->signal,
2266                         stream->phy_pix_clk);
2267
2268         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2269                 dal_ddc_service_read_scdc_data(link->ddc);
2270 }
2271
2272 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2273 {
2274         struct dc_stream_state *stream = pipe_ctx->stream;
2275         struct dc_link *link = stream->link;
2276
2277         if (stream->phy_pix_clk == 0)
2278                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2279
2280         memset(&stream->link->cur_link_settings, 0,
2281                         sizeof(struct dc_link_settings));
2282
2283         link->link_enc->funcs->enable_lvds_output(
2284                         link->link_enc,
2285                         pipe_ctx->clock_source->id,
2286                         stream->phy_pix_clk);
2287
2288 }
2289
2290 /****************************enable_link***********************************/
2291 static enum dc_status enable_link(
2292                 struct dc_state *state,
2293                 struct pipe_ctx *pipe_ctx)
2294 {
2295         enum dc_status status = DC_ERROR_UNEXPECTED;
2296         struct dc_stream_state *stream = pipe_ctx->stream;
2297         struct dc_link *link = stream->link;
2298
2299         /* There's some scenarios where driver is unloaded with display
2300          * still enabled. When driver is reloaded, it may cause a display
2301          * to not light up if there is a mismatch between old and new
2302          * link settings. Need to call disable first before enabling at
2303          * new link settings.
2304          */
2305         if (link->link_status.link_active) {
2306                 disable_link(link, pipe_ctx->stream->signal);
2307         }
2308
2309         switch (pipe_ctx->stream->signal) {
2310         case SIGNAL_TYPE_DISPLAY_PORT:
2311                 status = enable_link_dp(state, pipe_ctx);
2312                 break;
2313         case SIGNAL_TYPE_EDP:
2314                 status = enable_link_edp(state, pipe_ctx);
2315                 break;
2316         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2317                 status = enable_link_dp_mst(state, pipe_ctx);
2318                 msleep(200);
2319                 break;
2320         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2321         case SIGNAL_TYPE_DVI_DUAL_LINK:
2322         case SIGNAL_TYPE_HDMI_TYPE_A:
2323                 enable_link_hdmi(pipe_ctx);
2324                 status = DC_OK;
2325                 break;
2326         case SIGNAL_TYPE_LVDS:
2327                 enable_link_lvds(pipe_ctx);
2328                 status = DC_OK;
2329                 break;
2330         case SIGNAL_TYPE_VIRTUAL:
2331                 status = DC_OK;
2332                 break;
2333         default:
2334                 break;
2335         }
2336
2337         if (status == DC_OK)
2338                 pipe_ctx->stream->link->link_status.link_active = true;
2339
2340         return status;
2341 }
2342
2343 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2344 {
2345
2346         uint32_t pxl_clk = timing->pix_clk_100hz;
2347
2348         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2349                 pxl_clk /= 2;
2350         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2351                 pxl_clk = pxl_clk * 2 / 3;
2352
2353         if (timing->display_color_depth == COLOR_DEPTH_101010)
2354                 pxl_clk = pxl_clk * 10 / 8;
2355         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2356                 pxl_clk = pxl_clk * 12 / 8;
2357
2358         return pxl_clk;
2359 }
2360
2361 static bool dp_active_dongle_validate_timing(
2362                 const struct dc_crtc_timing *timing,
2363                 const struct dpcd_caps *dpcd_caps)
2364 {
2365         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2366
2367         switch (dpcd_caps->dongle_type) {
2368         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2369         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2370         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2371                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2372                         return true;
2373                 else
2374                         return false;
2375         default:
2376                 break;
2377         }
2378
2379         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2380                 dongle_caps->extendedCapValid == false)
2381                 return true;
2382
2383         /* Check Pixel Encoding */
2384         switch (timing->pixel_encoding) {
2385         case PIXEL_ENCODING_RGB:
2386         case PIXEL_ENCODING_YCBCR444:
2387                 break;
2388         case PIXEL_ENCODING_YCBCR422:
2389                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2390                         return false;
2391                 break;
2392         case PIXEL_ENCODING_YCBCR420:
2393                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2394                         return false;
2395                 break;
2396         default:
2397                 /* Invalid Pixel Encoding*/
2398                 return false;
2399         }
2400
2401         switch (timing->display_color_depth) {
2402         case COLOR_DEPTH_666:
2403         case COLOR_DEPTH_888:
2404                 /*888 and 666 should always be supported*/
2405                 break;
2406         case COLOR_DEPTH_101010:
2407                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2408                         return false;
2409                 break;
2410         case COLOR_DEPTH_121212:
2411                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2412                         return false;
2413                 break;
2414         case COLOR_DEPTH_141414:
2415         case COLOR_DEPTH_161616:
2416         default:
2417                 /* These color depths are currently not supported */
2418                 return false;
2419         }
2420
2421         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2422                 return false;
2423
2424         return true;
2425 }
2426
2427 enum dc_status dc_link_validate_mode_timing(
2428                 const struct dc_stream_state *stream,
2429                 struct dc_link *link,
2430                 const struct dc_crtc_timing *timing)
2431 {
2432         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2433         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2434
2435         /* A hack to avoid failing any modes for EDID override feature on
2436          * topology change such as lower quality cable for DP or different dongle
2437          */
2438         if (link->remote_sinks[0])
2439                 return DC_OK;
2440
2441         /* Passive Dongle */
2442         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2443                 return DC_EXCEED_DONGLE_CAP;
2444
2445         /* Active Dongle*/
2446         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2447                 return DC_EXCEED_DONGLE_CAP;
2448
2449         switch (stream->signal) {
2450         case SIGNAL_TYPE_EDP:
2451         case SIGNAL_TYPE_DISPLAY_PORT:
2452                 if (!dp_validate_mode_timing(
2453                                 link,
2454                                 timing))
2455                         return DC_NO_DP_LINK_BANDWIDTH;
2456                 break;
2457
2458         default:
2459                 break;
2460         }
2461
2462         return DC_OK;
2463 }
2464
2465 int dc_link_get_backlight_level(const struct dc_link *link)
2466 {
2467         struct abm *abm = link->ctx->dc->res_pool->abm;
2468
2469         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2470                 return DC_ERROR_UNEXPECTED;
2471
2472         return (int) abm->funcs->get_current_backlight(abm);
2473 }
2474
2475 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2476 {
2477         struct abm *abm = link->ctx->dc->res_pool->abm;
2478
2479         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2480                 return DC_ERROR_UNEXPECTED;
2481
2482         return (int) abm->funcs->get_target_backlight(abm);
2483 }
2484
2485 bool dc_link_set_backlight_level(const struct dc_link *link,
2486                 uint32_t backlight_pwm_u16_16,
2487                 uint32_t frame_ramp)
2488 {
2489         struct dc  *dc = link->ctx->dc;
2490         struct abm *abm = dc->res_pool->abm;
2491         struct dmcu *dmcu = dc->res_pool->dmcu;
2492         unsigned int controller_id = 0;
2493         bool fw_set_brightness = true;
2494         int i;
2495         DC_LOGGER_INIT(link->ctx->logger);
2496
2497         if (abm == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2498                 return false;
2499
2500         if (dmcu)
2501                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2502
2503         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2504                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2505
2506         if (dc_is_embedded_signal(link->connector_signal)) {
2507                 for (i = 0; i < MAX_PIPES; i++) {
2508                         if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2509                                 if (dc->current_state->res_ctx.
2510                                                 pipe_ctx[i].stream->link
2511                                                 == link) {
2512                                         /* DMCU -1 for all controller id values,
2513                                          * therefore +1 here
2514                                          */
2515                                         controller_id =
2516                                                 dc->current_state->
2517                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2518                                                 1;
2519
2520                                         /* Disable brightness ramping when the display is blanked
2521                                          * as it can hang the DMCU
2522                                          */
2523                                         if (dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
2524                                                 frame_ramp = 0;
2525                                 }
2526                         }
2527                 }
2528                 abm->funcs->set_backlight_level_pwm(
2529                                 abm,
2530                                 backlight_pwm_u16_16,
2531                                 frame_ramp,
2532                                 controller_id,
2533                                 fw_set_brightness);
2534         }
2535
2536         return true;
2537 }
2538
2539 bool dc_link_set_abm_disable(const struct dc_link *link)
2540 {
2541         struct dc  *dc = link->ctx->dc;
2542         struct abm *abm = NULL;
2543         bool success = false;
2544         int i;
2545
2546         for (i = 0; i < MAX_PIPES; i++) {
2547                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2548                 struct dc_stream_state *stream = pipe_ctx.stream;
2549
2550                 if (stream && stream->link == link) {
2551                         abm = pipe_ctx.stream_res.abm;
2552                         break;
2553                 }
2554         }
2555
2556         if (abm)
2557                 success = abm->funcs->set_abm_immediate_disable(abm);
2558
2559         return success;
2560 }
2561
2562 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
2563 {
2564         struct dc  *dc = link->ctx->dc;
2565         struct dmcu *dmcu = dc->res_pool->dmcu;
2566         struct dmub_psr *psr = dc->res_pool->psr;
2567
2568         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2569                 psr->funcs->psr_enable(psr, allow_active);
2570         else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2571                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2572
2573         link->psr_settings.psr_allow_active = allow_active;
2574
2575         return true;
2576 }
2577
2578 bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
2579 {
2580         struct dc  *dc = link->ctx->dc;
2581         struct dmcu *dmcu = dc->res_pool->dmcu;
2582         struct dmub_psr *psr = dc->res_pool->psr;
2583
2584         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2585                 psr->funcs->psr_get_state(psr, psr_state);
2586         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2587                 dmcu->funcs->get_psr_state(dmcu, psr_state);
2588
2589         return true;
2590 }
2591
2592 static inline enum physical_phy_id
2593 transmitter_to_phy_id(enum transmitter transmitter_value)
2594 {
2595         switch (transmitter_value) {
2596         case TRANSMITTER_UNIPHY_A:
2597                 return PHYLD_0;
2598         case TRANSMITTER_UNIPHY_B:
2599                 return PHYLD_1;
2600         case TRANSMITTER_UNIPHY_C:
2601                 return PHYLD_2;
2602         case TRANSMITTER_UNIPHY_D:
2603                 return PHYLD_3;
2604         case TRANSMITTER_UNIPHY_E:
2605                 return PHYLD_4;
2606         case TRANSMITTER_UNIPHY_F:
2607                 return PHYLD_5;
2608         case TRANSMITTER_NUTMEG_CRT:
2609                 return PHYLD_6;
2610         case TRANSMITTER_TRAVIS_CRT:
2611                 return PHYLD_7;
2612         case TRANSMITTER_TRAVIS_LCD:
2613                 return PHYLD_8;
2614         case TRANSMITTER_UNIPHY_G:
2615                 return PHYLD_9;
2616         case TRANSMITTER_COUNT:
2617                 return PHYLD_COUNT;
2618         case TRANSMITTER_UNKNOWN:
2619                 return PHYLD_UNKNOWN;
2620         default:
2621                 WARN_ONCE(1, "Unknown transmitter value %d\n",
2622                           transmitter_value);
2623                 return PHYLD_UNKNOWN;
2624         }
2625 }
2626
2627 bool dc_link_setup_psr(struct dc_link *link,
2628                 const struct dc_stream_state *stream, struct psr_config *psr_config,
2629                 struct psr_context *psr_context)
2630 {
2631         struct dc *dc;
2632         struct dmcu *dmcu;
2633         struct dmub_psr *psr;
2634         int i;
2635         /* updateSinkPsrDpcdConfig*/
2636         union dpcd_psr_configuration psr_configuration;
2637
2638         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2639
2640         if (!link)
2641                 return false;
2642
2643         dc = link->ctx->dc;
2644         dmcu = dc->res_pool->dmcu;
2645         psr = dc->res_pool->psr;
2646
2647         if (!dmcu && !psr)
2648                 return false;
2649
2650
2651         memset(&psr_configuration, 0, sizeof(psr_configuration));
2652
2653         psr_configuration.bits.ENABLE                    = 1;
2654         psr_configuration.bits.CRC_VERIFICATION          = 1;
2655         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
2656                         psr_config->psr_frame_capture_indication_req;
2657
2658         /* Check for PSR v2*/
2659         if (psr_config->psr_version == 0x2) {
2660                 /* For PSR v2 selective update.
2661                  * Indicates whether sink should start capturing
2662                  * immediately following active scan line,
2663                  * or starting with the 2nd active scan line.
2664                  */
2665                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2666                 /*For PSR v2, determines whether Sink should generate
2667                  * IRQ_HPD when CRC mismatch is detected.
2668                  */
2669                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
2670         }
2671
2672         dm_helpers_dp_write_dpcd(
2673                 link->ctx,
2674                 link,
2675                 368,
2676                 &psr_configuration.raw,
2677                 sizeof(psr_configuration.raw));
2678
2679         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2680         psr_context->transmitterId = link->link_enc->transmitter;
2681         psr_context->engineId = link->link_enc->preferred_engine;
2682
2683         for (i = 0; i < MAX_PIPES; i++) {
2684                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2685                                 == stream) {
2686                         /* dmcu -1 for all controller id values,
2687                          * therefore +1 here
2688                          */
2689                         psr_context->controllerId =
2690                                 dc->current_state->res_ctx.
2691                                 pipe_ctx[i].stream_res.tg->inst + 1;
2692                         break;
2693                 }
2694         }
2695
2696         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
2697         psr_context->phyType = PHY_TYPE_UNIPHY;
2698         /*PhyId is associated with the transmitter id*/
2699         psr_context->smuPhyId =
2700                 transmitter_to_phy_id(link->link_enc->transmitter);
2701
2702         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2703         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2704                                         timing.pix_clk_100hz * 100),
2705                                         stream->timing.v_total),
2706                                         stream->timing.h_total);
2707
2708         psr_context->psrSupportedDisplayConfig = true;
2709         psr_context->psrExitLinkTrainingRequired =
2710                 psr_config->psr_exit_link_training_required;
2711         psr_context->sdpTransmitLineNumDeadline =
2712                 psr_config->psr_sdp_transmit_line_num_deadline;
2713         psr_context->psrFrameCaptureIndicationReq =
2714                 psr_config->psr_frame_capture_indication_req;
2715
2716         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2717
2718         psr_context->numberOfControllers =
2719                         link->dc->res_pool->timing_generator_count;
2720
2721         psr_context->rfb_update_auto_en = true;
2722
2723         /* 2 frames before enter PSR. */
2724         psr_context->timehyst_frames = 2;
2725         /* half a frame
2726          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2727          */
2728         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2729         psr_context->aux_repeats = 10;
2730
2731         psr_context->psr_level.u32all = 0;
2732
2733 #if defined(CONFIG_DRM_AMD_DC_DCN)
2734         /*skip power down the single pipe since it blocks the cstate*/
2735         if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
2736                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2737 #endif
2738
2739         /* SMU will perform additional powerdown sequence.
2740          * For unsupported ASICs, set psr_level flag to skip PSR
2741          *  static screen notification to SMU.
2742          *  (Always set for DAL2, did not check ASIC)
2743          */
2744         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2745
2746         /* Complete PSR entry before aborting to prevent intermittent
2747          * freezes on certain eDPs
2748          */
2749         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2750
2751         /* Controls additional delay after remote frame capture before
2752          * continuing power down, default = 0
2753          */
2754         psr_context->frame_delay = 0;
2755
2756         if (psr)
2757                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
2758         else
2759                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2760
2761         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2762          * should not happen since firmware should be running at this point
2763          */
2764         if (link->psr_settings.psr_feature_enabled == 0)
2765                 ASSERT(0);
2766
2767         return true;
2768
2769 }
2770
2771 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2772 {
2773         return &link->link_status;
2774 }
2775
2776 void core_link_resume(struct dc_link *link)
2777 {
2778         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2779                 program_hpd_filter(link);
2780 }
2781
2782 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2783 {
2784         struct fixed31_32 mbytes_per_sec;
2785         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2786                         &stream->link->cur_link_settings);
2787         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2788
2789         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2790
2791         return dc_fixpt_div_int(mbytes_per_sec, 54);
2792 }
2793
2794 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2795 {
2796         uint64_t kbps;
2797         struct fixed31_32 peak_kbps;
2798         uint32_t numerator;
2799         uint32_t denominator;
2800
2801         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2802
2803         /*
2804          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2805          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2806          * common multiplier to render an integer PBN for all link rate/lane
2807          * counts combinations
2808          * calculate
2809          * peak_kbps *= (1006/1000)
2810          * peak_kbps *= (64/54)
2811          * peak_kbps *= 8    convert to bytes
2812          */
2813
2814         numerator = 64 * PEAK_FACTOR_X1000;
2815         denominator = 54 * 8 * 1000 * 1000;
2816         kbps *= numerator;
2817         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2818
2819         return peak_kbps;
2820 }
2821
2822 static void update_mst_stream_alloc_table(
2823         struct dc_link *link,
2824         struct stream_encoder *stream_enc,
2825         const struct dp_mst_stream_allocation_table *proposed_table)
2826 {
2827         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2828                         { 0 } };
2829         struct link_mst_stream_allocation *dc_alloc;
2830
2831         int i;
2832         int j;
2833
2834         /* if DRM proposed_table has more than one new payload */
2835         ASSERT(proposed_table->stream_count -
2836                         link->mst_stream_alloc_table.stream_count < 2);
2837
2838         /* copy proposed_table to link, add stream encoder */
2839         for (i = 0; i < proposed_table->stream_count; i++) {
2840
2841                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2842                         dc_alloc =
2843                         &link->mst_stream_alloc_table.stream_allocations[j];
2844
2845                         if (dc_alloc->vcp_id ==
2846                                 proposed_table->stream_allocations[i].vcp_id) {
2847
2848                                 work_table[i] = *dc_alloc;
2849                                 break; /* exit j loop */
2850                         }
2851                 }
2852
2853                 /* new vcp_id */
2854                 if (j == link->mst_stream_alloc_table.stream_count) {
2855                         work_table[i].vcp_id =
2856                                 proposed_table->stream_allocations[i].vcp_id;
2857                         work_table[i].slot_count =
2858                                 proposed_table->stream_allocations[i].slot_count;
2859                         work_table[i].stream_enc = stream_enc;
2860                 }
2861         }
2862
2863         /* update link->mst_stream_alloc_table with work_table */
2864         link->mst_stream_alloc_table.stream_count =
2865                         proposed_table->stream_count;
2866         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2867                 link->mst_stream_alloc_table.stream_allocations[i] =
2868                                 work_table[i];
2869 }
2870
2871 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2872  * because stream_encoder is not exposed to dm
2873  */
2874 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2875 {
2876         struct dc_stream_state *stream = pipe_ctx->stream;
2877         struct dc_link *link = stream->link;
2878         struct link_encoder *link_encoder = link->link_enc;
2879         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2880         struct dp_mst_stream_allocation_table proposed_table = {0};
2881         struct fixed31_32 avg_time_slots_per_mtp;
2882         struct fixed31_32 pbn;
2883         struct fixed31_32 pbn_per_slot;
2884         uint8_t i;
2885         enum act_return_status ret;
2886         DC_LOGGER_INIT(link->ctx->logger);
2887
2888         /* enable_link_dp_mst already check link->enabled_stream_count
2889          * and stream is in link->stream[]. This is called during set mode,
2890          * stream_enc is available.
2891          */
2892
2893         /* get calculate VC payload for stream: stream_alloc */
2894         if (dm_helpers_dp_mst_write_payload_allocation_table(
2895                 stream->ctx,
2896                 stream,
2897                 &proposed_table,
2898                 true)) {
2899                 update_mst_stream_alloc_table(
2900                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2901         }
2902         else
2903                 DC_LOG_WARNING("Failed to update"
2904                                 "MST allocation table for"
2905                                 "pipe idx:%d\n",
2906                                 pipe_ctx->pipe_idx);
2907
2908         DC_LOG_MST("%s  "
2909                         "stream_count: %d: \n ",
2910                         __func__,
2911                         link->mst_stream_alloc_table.stream_count);
2912
2913         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2914                 DC_LOG_MST("stream_enc[%d]: %p      "
2915                 "stream[%d].vcp_id: %d      "
2916                 "stream[%d].slot_count: %d\n",
2917                 i,
2918                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2919                 i,
2920                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2921                 i,
2922                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2923         }
2924
2925         ASSERT(proposed_table.stream_count > 0);
2926
2927         /* program DP source TX for payload */
2928         link_encoder->funcs->update_mst_stream_allocation_table(
2929                 link_encoder,
2930                 &link->mst_stream_alloc_table);
2931
2932         /* send down message */
2933         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2934                         stream->ctx,
2935                         stream);
2936
2937         if (ret != ACT_LINK_LOST) {
2938                 dm_helpers_dp_mst_send_payload_allocation(
2939                                 stream->ctx,
2940                                 stream,
2941                                 true);
2942         }
2943
2944         /* slot X.Y for only current stream */
2945         pbn_per_slot = get_pbn_per_slot(stream);
2946         pbn = get_pbn_from_timing(pipe_ctx);
2947         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2948
2949         stream_encoder->funcs->set_mst_bandwidth(
2950                 stream_encoder,
2951                 avg_time_slots_per_mtp);
2952
2953         return DC_OK;
2954
2955 }
2956
2957 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2958 {
2959         struct dc_stream_state *stream = pipe_ctx->stream;
2960         struct dc_link *link = stream->link;
2961         struct link_encoder *link_encoder = link->link_enc;
2962         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2963         struct dp_mst_stream_allocation_table proposed_table = {0};
2964         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2965         uint8_t i;
2966         bool mst_mode = (link->type == dc_connection_mst_branch);
2967         DC_LOGGER_INIT(link->ctx->logger);
2968
2969         /* deallocate_mst_payload is called before disable link. When mode or
2970          * disable/enable monitor, new stream is created which is not in link
2971          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2972          * should not done. For new mode set, map_resources will get engine
2973          * for new stream, so stream_enc->id should be validated until here.
2974          */
2975
2976         /* slot X.Y */
2977         stream_encoder->funcs->set_mst_bandwidth(
2978                 stream_encoder,
2979                 avg_time_slots_per_mtp);
2980
2981         /* TODO: which component is responsible for remove payload table? */
2982         if (mst_mode) {
2983                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2984                                 stream->ctx,
2985                                 stream,
2986                                 &proposed_table,
2987                                 false)) {
2988
2989                         update_mst_stream_alloc_table(
2990                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2991                 }
2992                 else {
2993                                 DC_LOG_WARNING("Failed to update"
2994                                                 "MST allocation table for"
2995                                                 "pipe idx:%d\n",
2996                                                 pipe_ctx->pipe_idx);
2997                 }
2998         }
2999
3000         DC_LOG_MST("%s"
3001                         "stream_count: %d: ",
3002                         __func__,
3003                         link->mst_stream_alloc_table.stream_count);
3004
3005         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3006                 DC_LOG_MST("stream_enc[%d]: %p      "
3007                 "stream[%d].vcp_id: %d      "
3008                 "stream[%d].slot_count: %d\n",
3009                 i,
3010                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3011                 i,
3012                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3013                 i,
3014                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3015         }
3016
3017         link_encoder->funcs->update_mst_stream_allocation_table(
3018                 link_encoder,
3019                 &link->mst_stream_alloc_table);
3020
3021         if (mst_mode) {
3022                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3023                         stream->ctx,
3024                         stream);
3025
3026                 dm_helpers_dp_mst_send_payload_allocation(
3027                         stream->ctx,
3028                         stream,
3029                         false);
3030         }
3031
3032         return DC_OK;
3033 }
3034
3035 enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link)
3036 {
3037         int i;
3038         struct pipe_ctx *pipe_ctx;
3039
3040         // Clear all of MST payload then reallocate
3041         for (i = 0; i < MAX_PIPES; i++) {
3042                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3043
3044                 /* driver enable split pipe for external monitors
3045                  * we have to check pipe_ctx is split pipe or not
3046                  * If it's split pipe, driver using top pipe to
3047                  * reaallocate.
3048                  */
3049                 if (!pipe_ctx || pipe_ctx->top_pipe)
3050                         continue;
3051
3052                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3053                                 pipe_ctx->stream->dpms_off == false &&
3054                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3055                         deallocate_mst_payload(pipe_ctx);
3056                 }
3057         }
3058
3059         for (i = 0; i < MAX_PIPES; i++) {
3060                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3061
3062                 if (!pipe_ctx || pipe_ctx->top_pipe)
3063                         continue;
3064
3065                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
3066                                 pipe_ctx->stream->dpms_off == false &&
3067                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3068                         /* enable/disable PHY will clear connection between BE and FE
3069                          * need to restore it.
3070                          */
3071                         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
3072                                                                         pipe_ctx->stream_res.stream_enc->id, true);
3073                         dc_link_allocate_mst_payload(pipe_ctx);
3074                 }
3075         }
3076
3077         return DC_OK;
3078 }
3079
3080 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3081 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3082 {
3083         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3084         if (cp_psp && cp_psp->funcs.update_stream_config) {
3085                 struct cp_psp_stream_config config;
3086
3087                 memset(&config, 0, sizeof(config));
3088
3089                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3090                 /*stream_enc_inst*/
3091                 config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3092                 config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
3093                 config.dpms_off = dpms_off;
3094                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3095                 config.mst_supported = (pipe_ctx->stream->signal ==
3096                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
3097                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3098         }
3099 }
3100 #endif
3101
3102 void core_link_enable_stream(
3103                 struct dc_state *state,
3104                 struct pipe_ctx *pipe_ctx)
3105 {
3106         struct dc *dc = pipe_ctx->stream->ctx->dc;
3107         struct dc_stream_state *stream = pipe_ctx->stream;
3108         enum dc_status status;
3109         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3110
3111         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3112                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3113                 return;
3114
3115         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3116                 stream->link->link_enc->funcs->setup(
3117                         stream->link->link_enc,
3118                         pipe_ctx->stream->signal);
3119                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3120                         pipe_ctx->stream_res.stream_enc,
3121                         pipe_ctx->stream_res.tg->inst,
3122                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3123         }
3124
3125         if (dc_is_dp_signal(pipe_ctx->stream->signal))
3126                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3127                         pipe_ctx->stream_res.stream_enc,
3128                         &stream->timing,
3129                         stream->output_color_space,
3130                         stream->use_vsc_sdp_for_colorimetry,
3131                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3132
3133         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3134                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3135                         pipe_ctx->stream_res.stream_enc,
3136                         &stream->timing,
3137                         stream->phy_pix_clk,
3138                         pipe_ctx->stream_res.audio != NULL);
3139
3140         pipe_ctx->stream->link->link_state_valid = true;
3141
3142         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3143                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3144                         pipe_ctx->stream_res.stream_enc,
3145                         &stream->timing,
3146                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3147                         true : false);
3148
3149         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3150                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3151                         pipe_ctx->stream_res.stream_enc,
3152                         &stream->timing);
3153
3154         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3155                 bool apply_edp_fast_boot_optimization =
3156                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
3157
3158                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3159
3160                 resource_build_info_frame(pipe_ctx);
3161                 dc->hwss.update_info_frame(pipe_ctx);
3162
3163                 /* Do not touch link on seamless boot optimization. */
3164                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3165                         pipe_ctx->stream->dpms_off = false;
3166 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3167                         update_psp_stream_config(pipe_ctx, false);
3168 #endif
3169                         return;
3170                 }
3171
3172                 /* eDP lit up by bios already, no need to enable again. */
3173                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3174                                         apply_edp_fast_boot_optimization) {
3175                         pipe_ctx->stream->dpms_off = false;
3176 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3177                         update_psp_stream_config(pipe_ctx, false);
3178 #endif
3179                         return;
3180                 }
3181
3182                 if (pipe_ctx->stream->dpms_off)
3183                         return;
3184
3185                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3186                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
3187                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3188                  * will be automatically set at a later time when the video is enabled
3189                  * (DP_VID_STREAM_EN = 1).
3190                  */
3191                 if (pipe_ctx->stream->timing.flags.DSC) {
3192                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3193                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3194                                 dp_set_dsc_enable(pipe_ctx, true);
3195                 }
3196
3197                 status = enable_link(state, pipe_ctx);
3198
3199                 if (status != DC_OK) {
3200                         DC_LOG_WARNING("enabling link %u failed: %d\n",
3201                         pipe_ctx->stream->link->link_index,
3202                         status);
3203
3204                         /* Abort stream enable *unless* the failure was due to
3205                          * DP link training - some DP monitors will recover and
3206                          * show the stream anyway. But MST displays can't proceed
3207                          * without link training.
3208                          */
3209                         if (status != DC_FAIL_DP_LINK_TRAINING ||
3210                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3211                                 BREAK_TO_DEBUGGER();
3212                                 return;
3213                         }
3214                 }
3215
3216                 dc->hwss.enable_audio_stream(pipe_ctx);
3217
3218                 /* turn off otg test pattern if enable */
3219                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3220                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3221                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3222                                         COLOR_DEPTH_UNDEFINED);
3223
3224                 dc->hwss.enable_stream(pipe_ctx);
3225
3226                 /* Set DPS PPS SDP (AKA "info frames") */
3227                 if (pipe_ctx->stream->timing.flags.DSC) {
3228                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3229                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3230                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
3231                 }
3232
3233                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3234                         dc_link_allocate_mst_payload(pipe_ctx);
3235
3236                 dc->hwss.unblank_stream(pipe_ctx,
3237                         &pipe_ctx->stream->link->cur_link_settings);
3238
3239                 if (stream->sink_patches.delay_ignore_msa > 0)
3240                         msleep(stream->sink_patches.delay_ignore_msa);
3241
3242                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3243                         enable_stream_features(pipe_ctx);
3244 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3245                 update_psp_stream_config(pipe_ctx, false);
3246 #endif
3247         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3248                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3249                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
3250                         dp_set_dsc_enable(pipe_ctx, true);
3251
3252         }
3253 }
3254
3255 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3256 {
3257         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3258         struct dc_stream_state *stream = pipe_ctx->stream;
3259         struct dc_link *link = stream->sink->link;
3260
3261         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3262                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3263                 return;
3264
3265 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3266         update_psp_stream_config(pipe_ctx, true);
3267 #endif
3268
3269         dc->hwss.blank_stream(pipe_ctx);
3270
3271         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3272                 deallocate_mst_payload(pipe_ctx);
3273
3274         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3275                 struct ext_hdmi_settings settings = {0};
3276                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3277
3278                 unsigned short masked_chip_caps = link->chip_caps &
3279                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3280                 //Need to inform that sink is going to use legacy HDMI mode.
3281                 dal_ddc_service_write_scdc_data(
3282                         link->ddc,
3283                         165000,//vbios only handles 165Mhz.
3284                         false);
3285                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3286                         /* DP159, Retimer settings */
3287                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3288                                 write_i2c_retimer_setting(pipe_ctx,
3289                                                 false, false, &settings);
3290                         else
3291                                 write_i2c_default_retimer_setting(pipe_ctx,
3292                                                 false, false);
3293                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3294                         /* PI3EQX1204, Redriver settings */
3295                         write_i2c_redriver_setting(pipe_ctx, false);
3296                 }
3297         }
3298         dc->hwss.disable_stream(pipe_ctx);
3299
3300         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3301         if (pipe_ctx->stream->timing.flags.DSC) {
3302                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3303                         dp_set_dsc_enable(pipe_ctx, false);
3304         }
3305 }
3306
3307 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3308 {
3309         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3310
3311         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3312                 return;
3313
3314         dc->hwss.set_avmute(pipe_ctx, enable);
3315 }
3316
3317 /**
3318  *****************************************************************************
3319  *  Function: dc_link_enable_hpd_filter
3320  *
3321  *  @brief
3322  *     If enable is true, programs HPD filter on associated HPD line using
3323  *     delay_on_disconnect/delay_on_connect values dependent on
3324  *     link->connector_signal
3325  *
3326  *     If enable is false, programs HPD filter on associated HPD line with no
3327  *     delays on connect or disconnect
3328  *
3329  *  @param [in] link: pointer to the dc link
3330  *  @param [in] enable: boolean specifying whether to enable hbd
3331  *****************************************************************************
3332  */
3333 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3334 {
3335         struct gpio *hpd;
3336
3337         if (enable) {
3338                 link->is_hpd_filter_disabled = false;
3339                 program_hpd_filter(link);
3340         } else {
3341                 link->is_hpd_filter_disabled = true;
3342                 /* Obtain HPD handle */
3343                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3344
3345                 if (!hpd)
3346                         return;
3347
3348                 /* Setup HPD filtering */
3349                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3350                         struct gpio_hpd_config config;
3351
3352                         config.delay_on_connect = 0;
3353                         config.delay_on_disconnect = 0;
3354
3355                         dal_irq_setup_hpd_filter(hpd, &config);
3356
3357                         dal_gpio_close(hpd);
3358                 } else {
3359                         ASSERT_CRITICAL(false);
3360                 }
3361                 /* Release HPD handle */
3362                 dal_gpio_destroy_irq(&hpd);
3363         }
3364 }
3365
3366 uint32_t dc_bandwidth_in_kbps_from_timing(
3367         const struct dc_crtc_timing *timing)
3368 {
3369         uint32_t bits_per_channel = 0;
3370         uint32_t kbps;
3371
3372         if (timing->flags.DSC) {
3373                 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
3374                 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
3375                 return kbps;
3376         }
3377
3378         switch (timing->display_color_depth) {
3379         case COLOR_DEPTH_666:
3380                 bits_per_channel = 6;
3381                 break;
3382         case COLOR_DEPTH_888:
3383                 bits_per_channel = 8;
3384                 break;
3385         case COLOR_DEPTH_101010:
3386                 bits_per_channel = 10;
3387                 break;
3388         case COLOR_DEPTH_121212:
3389                 bits_per_channel = 12;
3390                 break;
3391         case COLOR_DEPTH_141414:
3392                 bits_per_channel = 14;
3393                 break;
3394         case COLOR_DEPTH_161616:
3395                 bits_per_channel = 16;
3396                 break;
3397         default:
3398                 break;
3399         }
3400
3401         ASSERT(bits_per_channel != 0);
3402
3403         kbps = timing->pix_clk_100hz / 10;
3404         kbps *= bits_per_channel;
3405
3406         if (timing->flags.Y_ONLY != 1) {
3407                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3408                 kbps *= 3;
3409                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3410                         kbps /= 2;
3411                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3412                         kbps = kbps * 2 / 3;
3413         }
3414
3415         return kbps;
3416
3417 }
3418
3419 void dc_link_set_drive_settings(struct dc *dc,
3420                                 struct link_training_settings *lt_settings,
3421                                 const struct dc_link *link)
3422 {
3423
3424         int i;
3425
3426         for (i = 0; i < dc->link_count; i++) {
3427                 if (dc->links[i] == link)
3428                         break;
3429         }
3430
3431         if (i >= dc->link_count)
3432                 ASSERT_CRITICAL(false);
3433
3434         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3435 }
3436
3437 void dc_link_perform_link_training(struct dc *dc,
3438                                    struct dc_link_settings *link_setting,
3439                                    bool skip_video_pattern)
3440 {
3441         int i;
3442
3443         for (i = 0; i < dc->link_count; i++)
3444                 dc_link_dp_perform_link_training(
3445                         dc->links[i],
3446                         link_setting,
3447                         skip_video_pattern);
3448 }
3449
3450 void dc_link_set_preferred_link_settings(struct dc *dc,
3451                                          struct dc_link_settings *link_setting,
3452                                          struct dc_link *link)
3453 {
3454         int i;
3455         struct pipe_ctx *pipe;
3456         struct dc_stream_state *link_stream;
3457         struct dc_link_settings store_settings = *link_setting;
3458
3459         link->preferred_link_setting = store_settings;
3460
3461         /* Retrain with preferred link settings only relevant for
3462          * DP signal type
3463          * Check for non-DP signal or if passive dongle present
3464          */
3465         if (!dc_is_dp_signal(link->connector_signal) ||
3466                 link->dongle_max_pix_clk > 0)
3467                 return;
3468
3469         for (i = 0; i < MAX_PIPES; i++) {
3470                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3471                 if (pipe->stream && pipe->stream->link) {
3472                         if (pipe->stream->link == link) {
3473                                 link_stream = pipe->stream;
3474                                 break;
3475                         }
3476                 }
3477         }
3478
3479         /* Stream not found */
3480         if (i == MAX_PIPES)
3481                 return;
3482
3483         /* Cannot retrain link if backend is off */
3484         if (link_stream->dpms_off)
3485                 return;
3486
3487         decide_link_settings(link_stream, &store_settings);
3488
3489         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3490                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3491                 dp_retrain_link_dp_test(link, &store_settings, false);
3492 }
3493
3494 void dc_link_set_preferred_training_settings(struct dc *dc,
3495                                                  struct dc_link_settings *link_setting,
3496                                                  struct dc_link_training_overrides *lt_overrides,
3497                                                  struct dc_link *link,
3498                                                  bool skip_immediate_retrain)
3499 {
3500         if (lt_overrides != NULL)
3501                 link->preferred_training_settings = *lt_overrides;
3502         else
3503                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3504
3505         if (link_setting != NULL) {
3506                 link->preferred_link_setting = *link_setting;
3507         } else {
3508                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3509                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3510         }
3511
3512         /* Retrain now, or wait until next stream update to apply */
3513         if (skip_immediate_retrain == false)
3514                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3515 }
3516
3517 void dc_link_enable_hpd(const struct dc_link *link)
3518 {
3519         dc_link_dp_enable_hpd(link);
3520 }
3521
3522 void dc_link_disable_hpd(const struct dc_link *link)
3523 {
3524         dc_link_dp_disable_hpd(link);
3525 }
3526
3527 void dc_link_set_test_pattern(struct dc_link *link,
3528                               enum dp_test_pattern test_pattern,
3529                               enum dp_test_pattern_color_space test_pattern_color_space,
3530                               const struct link_training_settings *p_link_settings,
3531                               const unsigned char *p_custom_pattern,
3532                               unsigned int cust_pattern_size)
3533 {
3534         if (link != NULL)
3535                 dc_link_dp_set_test_pattern(
3536                         link,
3537                         test_pattern,
3538                         test_pattern_color_space,
3539                         p_link_settings,
3540                         p_custom_pattern,
3541                         cust_pattern_size);
3542 }
3543
3544 uint32_t dc_link_bandwidth_kbps(
3545         const struct dc_link *link,
3546         const struct dc_link_settings *link_setting)
3547 {
3548         uint32_t link_bw_kbps =
3549                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3550
3551         link_bw_kbps *= 8;   /* 8 bits per byte*/
3552         link_bw_kbps *= link_setting->lane_count;
3553
3554         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
3555                 /* Account for FEC overhead.
3556                  * We have to do it based on caps,
3557                  * and not based on FEC being set ready,
3558                  * because FEC is set ready too late in
3559                  * the process to correctly be picked up
3560                  * by mode enumeration.
3561                  *
3562                  * There's enough zeros at the end of 'kbps'
3563                  * that make the below operation 100% precise
3564                  * for our purposes.
3565                  * 'long long' makes it work even for HDMI 2.1
3566                  * max bandwidth (and much, much bigger bandwidths
3567                  * than that, actually).
3568                  *
3569                  * NOTE: Reducing link BW by 3% may not be precise
3570                  * because it may be a stream BT that increases by 3%, and so
3571                  * 1/1.03 = 0.970873 factor should have been used instead,
3572                  * but the difference is minimal and is in a safe direction,
3573                  * which all works well around potential ambiguity of DP 1.4a spec.
3574                  */
3575                 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
3576                                                link_bw_kbps, 32);
3577         }
3578
3579         return link_bw_kbps;
3580
3581 }
3582
3583 const struct dc_link_settings *dc_link_get_link_cap(
3584                 const struct dc_link *link)
3585 {
3586         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3587                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3588                 return &link->preferred_link_setting;
3589         return &link->verified_link_cap;
3590 }
3591
3592 void dc_link_overwrite_extended_receiver_cap(
3593                 struct dc_link *link)
3594 {
3595         dp_overwrite_extended_receiver_cap(link);
3596 }
3597
3598 bool dc_link_is_fec_supported(const struct dc_link *link)
3599 {
3600         return (dc_is_dp_signal(link->connector_signal) &&
3601                         link->link_enc->features.fec_supported &&
3602                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3603                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3604 }
3605