drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "bios/bios_parser_helper.h"
  45 #include "include/irq_service_interface.h"
  46 #include "transform.h"
  47 #include "dmcu.h"
  48 #include "dpp.h"
  49 #include "timing_generator.h"
  50 #include "abm.h"
  51 #include "virtual/virtual_link_encoder.h"
  52 #include "hubp.h"
  53
  54 #include "link_hwss.h"
  55 #include "link_encoder.h"
  56 #include "link_enc_cfg.h"
  57
  58 #include "dc_link.h"
  59 #include "dc_link_ddc.h"
  60 #include "dm_helpers.h"
  61 #include "mem_input.h"
  62
  63 #include "dc_link_dp.h"
  64 #include "dc_dmub_srv.h"
  65
  66 #include "dsc.h"
  67
  68 #include "vm_helper.h"
  69
  70 #include "dce/dce_i2c.h"
  71
  72 #include "dmub/dmub_srv.h"
  73
  74 #include "i2caux_interface.h"
  75 #include "dce/dmub_hw_lock_mgr.h"
  76
  77 #include "dc_trace.h"
  78
  79 #define CTX \
  80         dc->ctx
  81
  82 #define DC_LOGGER \
  83         dc->ctx->logger
  84
  85 static const char DC_BUILD_ID[] = "production-build";
  86
  87 /**
  88  * DOC: Overview
  89  *
  90  * DC is the OS-agnostic component of the amdgpu DC driver.
  91  *
  92  * DC maintains and validates a set of structs representing the state of the
  93  * driver and writes that state to AMD hardware
  94  *
  95  * Main DC HW structs:
  96  *
  97  * struct dc - The central struct.  One per driver.  Created on driver load,
  98  * destroyed on driver unload.
  99  *
 100  * struct dc_context - One per driver.
 101  * Used as a backpointer by most other structs in dc.
 102  *
 103  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 104  * plugpoints).  Created on driver load, destroyed on driver unload.
 105  *
 106  * struct dc_sink - One per display.  Created on boot or hotplug.
 107  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 108  * (the display directly attached).  It may also have one or more remote
 109  * sinks (in the Multi-Stream Transport case)
 110  *
 111  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 112  * main pipeline.  Not directly accessible by dm.
 113  *
 114  * Main dc state structs:
 115  *
 116  * These structs can be created and destroyed as needed.  There is a full set of
 117  * these structs in dc->current_state representing the currently programmed state.
 118  *
 119  * struct dc_state - The global DC state to track global state information,
 120  * such as bandwidth values.
 121  *
 122  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 123  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 124  *
 125  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 126  * and may have more in the Multi-Plane Overlay case.
 127  *
 128  * struct resource_context - Represents the programmable state of everything in
 129  * the resource_pool.  Not directly accessible by dm.
 130  *
 131  * struct pipe_ctx - A member of struct resource_context.  Represents the
 132  * internal hardware pipeline components.  Each dc_plane_state has either
 133  * one or two (in the pipe-split case).
 134  */
 135
 136 /*******************************************************************************
 137  * Private functions
 138  ******************************************************************************/
 139
 140 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 141 {
 142         if (new > *original)
 143                 *original = new;
 144 }
 145
 146 static void destroy_links(struct dc *dc)
 147 {
 148         uint32_t i;
 149
 150         for (i = 0; i < dc->link_count; i++) {
 151                 if (NULL != dc->links[i])
 152                         link_destroy(&dc->links[i]);
 153         }
 154 }
 155
 156 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 157 {
 158         int i;
 159         uint32_t count = 0;
 160
 161         for (i = 0; i < num_links; i++) {
 162                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 163                                 links[i]->is_internal_display)
 164                         count++;
 165         }
 166
 167         return count;
 168 }
 169
 170 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 171 {
 172         uint8_t i;
 173         uint8_t seamless_boot_stream_count = 0;
 174
 175         for (i = 0; i < ctx->stream_count; i++)
 176                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 177                         seamless_boot_stream_count++;
 178
 179         return seamless_boot_stream_count;
 180 }
 181
 182 static bool create_links(
 183                 struct dc *dc,
 184                 uint32_t num_virtual_links)
 185 {
 186         int i;
 187         int connectors_num;
 188         struct dc_bios *bios = dc->ctx->dc_bios;
 189
 190         dc->link_count = 0;
 191
 192         connectors_num = bios->funcs->get_connectors_number(bios);
 193
 194         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 195
 196         if (connectors_num > ENUM_ID_COUNT) {
 197                 dm_error(
 198                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 199                         connectors_num,
 200                         ENUM_ID_COUNT);
 201                 return false;
 202         }
 203
 204         dm_output_to_console(
 205                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 206                 __func__,
 207                 connectors_num,
 208                 num_virtual_links);
 209
 210         for (i = 0; i < connectors_num; i++) {
 211                 struct link_init_data link_init_params = {0};
 212                 struct dc_link *link;
 213
 214                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 215
 216                 link_init_params.ctx = dc->ctx;
 217                 /* next BIOS object table connector */
 218                 link_init_params.connector_index = i;
 219                 link_init_params.link_index = dc->link_count;
 220                 link_init_params.dc = dc;
 221                 link = link_create(&link_init_params);
 222
 223                 if (link) {
 224                                 dc->links[dc->link_count] = link;
 225                                 link->dc = dc;
 226                                 ++dc->link_count;
 227                 }
 228         }
 229
 230         DC_LOG_DC("BIOS object table - end");
 231
 232         for (i = 0; i < num_virtual_links; i++) {
 233                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 234                 struct encoder_init_data enc_init = {0};
 235
 236                 if (link == NULL) {
 237                         BREAK_TO_DEBUGGER();
 238                         goto failed_alloc;
 239                 }
 240
 241                 link->link_index = dc->link_count;
 242                 dc->links[dc->link_count] = link;
 243                 dc->link_count++;
 244
 245                 link->ctx = dc->ctx;
 246                 link->dc = dc;
 247                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 248                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 249                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 250                 link->link_id.enum_id = ENUM_ID_1;
 251                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 252
 253                 if (!link->link_enc) {
 254                         BREAK_TO_DEBUGGER();
 255                         goto failed_alloc;
 256                 }
 257
 258                 link->link_status.dpcd_caps = &link->dpcd_caps;
 259
 260                 enc_init.ctx = dc->ctx;
 261                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 262                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 263                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 264                 enc_init.connector = link->link_id;
 265                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 266                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 267                 enc_init.encoder.enum_id = ENUM_ID_1;
 268                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 269         }
 270
 271         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 272
 273         return true;
 274
 275 failed_alloc:
 276         return false;
 277 }
 278
 279 static struct dc_perf_trace *dc_perf_trace_create(void)
 280 {
 281         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 282 }
 283
 284 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 285 {
 286         kfree(*perf_trace);
 287         *perf_trace = NULL;
 288 }
 289
 290 /**
 291  *  dc_stream_adjust_vmin_vmax:
 292  *
 293  *  Looks up the pipe context of dc_stream_state and updates the
 294  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 295  *  Rate, which is a power-saving feature that targets reducing panel
 296  *  refresh rate while the screen is static
 297  *
 298  *  @dc:     dc reference
 299  *  @stream: Initial dc stream state
 300  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 301  */
 302 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 303                 struct dc_stream_state *stream,
 304                 struct dc_crtc_timing_adjust *adjust)
 305 {
 306         int i;
 307         bool ret = false;
 308
 309         stream->adjust.v_total_max = adjust->v_total_max;
 310         stream->adjust.v_total_mid = adjust->v_total_mid;
 311         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 312         stream->adjust.v_total_min = adjust->v_total_min;
 313
 314         for (i = 0; i < MAX_PIPES; i++) {
 315                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 316
 317                 if (pipe->stream == stream && pipe->stream_res.tg) {
 318                         dc->hwss.set_drr(&pipe,
 319                                         1,
 320                                         *adjust);
 321
 322                         ret = true;
 323                 }
 324         }
 325         return ret;
 326 }
 327
 328 bool dc_stream_get_crtc_position(struct dc *dc,
 329                 struct dc_stream_state **streams, int num_streams,
 330                 unsigned int *v_pos, unsigned int *nom_v_pos)
 331 {
 332         /* TODO: Support multiple streams */
 333         const struct dc_stream_state *stream = streams[0];
 334         int i;
 335         bool ret = false;
 336         struct crtc_position position;
 337
 338         for (i = 0; i < MAX_PIPES; i++) {
 339                 struct pipe_ctx *pipe =
 340                                 &dc->current_state->res_ctx.pipe_ctx[i];
 341
 342                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 343                         dc->hwss.get_position(&pipe, 1, &position);
 344
 345                         *v_pos = position.vertical_count;
 346                         *nom_v_pos = position.nominal_vcount;
 347                         ret = true;
 348                 }
 349         }
 350         return ret;
 351 }
 352
 353 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 354 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
 355                              struct crc_params *crc_window)
 356 {
 357         int i;
 358         struct dmcu *dmcu = dc->res_pool->dmcu;
 359         struct pipe_ctx *pipe;
 360         struct crc_region tmp_win, *crc_win;
 361         struct otg_phy_mux mapping_tmp, *mux_mapping;
 362
 363         /*crc window can't be null*/
 364         if (!crc_window)
 365                 return false;
 366
 367         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 368                 crc_win = &tmp_win;
 369                 mux_mapping = &mapping_tmp;
 370                 /*set crc window*/
 371                 tmp_win.x_start = crc_window->windowa_x_start;
 372                 tmp_win.y_start = crc_window->windowa_y_start;
 373                 tmp_win.x_end = crc_window->windowa_x_end;
 374                 tmp_win.y_end = crc_window->windowa_y_end;
 375
 376                 for (i = 0; i < MAX_PIPES; i++) {
 377                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 378                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 379                                 break;
 380                 }
 381
 382                 /* Stream not found */
 383                 if (i == MAX_PIPES)
 384                         return false;
 385
 386
 387                 /*set mux routing info*/
 388                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 389                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 390
 391                 dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping);
 392         } else {
 393                 DC_LOG_DC("dmcu is not initialized");
 394                 return false;
 395         }
 396
 397         return true;
 398 }
 399
 400 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream)
 401 {
 402         int i;
 403         struct dmcu *dmcu = dc->res_pool->dmcu;
 404         struct pipe_ctx *pipe;
 405         struct otg_phy_mux mapping_tmp, *mux_mapping;
 406
 407         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 408                 mux_mapping = &mapping_tmp;
 409
 410                 for (i = 0; i < MAX_PIPES; i++) {
 411                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 412                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 413                                 break;
 414                 }
 415
 416                 /* Stream not found */
 417                 if (i == MAX_PIPES)
 418                         return false;
 419
 420
 421                 /*set mux routing info*/
 422                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 423                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 424
 425                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 426         } else {
 427                 DC_LOG_DC("dmcu is not initialized");
 428                 return false;
 429         }
 430
 431         return true;
 432 }
 433 #endif
 434
 435 /**
 436  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 437  * @dc: DC Object
 438  * @stream: The stream to configure CRC on.
 439  * @enable: Enable CRC if true, disable otherwise.
 440  * @crc_window: CRC window (x/y start/end) information
 441  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 442  *              once.
 443  *
 444  * By default, only CRC0 is configured, and the entire frame is used to
 445  * calculate the crc.
 446  */
 447 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 448                              struct crc_params *crc_window, bool enable, bool continuous)
 449 {
 450         int i;
 451         struct pipe_ctx *pipe;
 452         struct crc_params param;
 453         struct timing_generator *tg;
 454
 455         for (i = 0; i < MAX_PIPES; i++) {
 456                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 457                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 458                         break;
 459         }
 460         /* Stream not found */
 461         if (i == MAX_PIPES)
 462                 return false;
 463
 464         /* By default, capture the full frame */
 465         param.windowa_x_start = 0;
 466         param.windowa_y_start = 0;
 467         param.windowa_x_end = pipe->stream->timing.h_addressable;
 468         param.windowa_y_end = pipe->stream->timing.v_addressable;
 469         param.windowb_x_start = 0;
 470         param.windowb_y_start = 0;
 471         param.windowb_x_end = pipe->stream->timing.h_addressable;
 472         param.windowb_y_end = pipe->stream->timing.v_addressable;
 473
 474         if (crc_window) {
 475                 param.windowa_x_start = crc_window->windowa_x_start;
 476                 param.windowa_y_start = crc_window->windowa_y_start;
 477                 param.windowa_x_end = crc_window->windowa_x_end;
 478                 param.windowa_y_end = crc_window->windowa_y_end;
 479                 param.windowb_x_start = crc_window->windowb_x_start;
 480                 param.windowb_y_start = crc_window->windowb_y_start;
 481                 param.windowb_x_end = crc_window->windowb_x_end;
 482                 param.windowb_y_end = crc_window->windowb_y_end;
 483         }
 484
 485         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 486         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 487
 488         /* Default to the union of both windows */
 489         param.selection = UNION_WINDOW_A_B;
 490         param.continuous_mode = continuous;
 491         param.enable = enable;
 492
 493         tg = pipe->stream_res.tg;
 494
 495         /* Only call if supported */
 496         if (tg->funcs->configure_crc)
 497                 return tg->funcs->configure_crc(tg, &param);
 498         DC_LOG_WARNING("CRC capture not supported.");
 499         return false;
 500 }
 501
 502 /**
 503  * dc_stream_get_crc() - Get CRC values for the given stream.
 504  * @dc: DC object
 505  * @stream: The DC stream state of the stream to get CRCs from.
 506  * @r_cr: CRC value for the first of the 3 channels stored here.
 507  * @g_y:  CRC value for the second of the 3 channels stored here.
 508  * @b_cb: CRC value for the third of the 3 channels stored here.
 509  *
 510  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 511  * Return false if stream is not found, or if CRCs are not enabled.
 512  */
 513 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 514                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 515 {
 516         int i;
 517         struct pipe_ctx *pipe;
 518         struct timing_generator *tg;
 519
 520         for (i = 0; i < MAX_PIPES; i++) {
 521                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 522                 if (pipe->stream == stream)
 523                         break;
 524         }
 525         /* Stream not found */
 526         if (i == MAX_PIPES)
 527                 return false;
 528
 529         tg = pipe->stream_res.tg;
 530
 531         if (tg->funcs->get_crc)
 532                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 533         DC_LOG_WARNING("CRC capture not supported.");
 534         return false;
 535 }
 536
 537 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 538                 enum dc_dynamic_expansion option)
 539 {
 540         /* OPP FMT dyn expansion updates*/
 541         int i;
 542         struct pipe_ctx *pipe_ctx;
 543
 544         for (i = 0; i < MAX_PIPES; i++) {
 545                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 546                                 == stream) {
 547                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 548                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 549                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 550                                         pipe_ctx->stream_res.opp,
 551                                         COLOR_SPACE_YCBCR601,
 552                                         stream->timing.display_color_depth,
 553                                         stream->signal);
 554                 }
 555         }
 556 }
 557
 558 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 559                 enum dc_dither_option option)
 560 {
 561         struct bit_depth_reduction_params params;
 562         struct dc_link *link = stream->link;
 563         struct pipe_ctx *pipes = NULL;
 564         int i;
 565
 566         for (i = 0; i < MAX_PIPES; i++) {
 567                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 568                                 stream) {
 569                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 570                         break;
 571                 }
 572         }
 573
 574         if (!pipes)
 575                 return;
 576         if (option > DITHER_OPTION_MAX)
 577                 return;
 578
 579         stream->dither_option = option;
 580
 581         memset(&params, 0, sizeof(params));
 582         resource_build_bit_depth_reduction_params(stream, &params);
 583         stream->bit_depth_params = params;
 584
 585         if (pipes->plane_res.xfm &&
 586             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 587                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 588                         pipes->plane_res.xfm,
 589                         pipes->plane_res.scl_data.lb_params.depth,
 590                         &stream->bit_depth_params);
 591         }
 592
 593         pipes->stream_res.opp->funcs->
 594                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 595 }
 596
 597 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 598 {
 599         int i;
 600         bool ret = false;
 601         struct pipe_ctx *pipes;
 602
 603         for (i = 0; i < MAX_PIPES; i++) {
 604                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 605                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 606                         dc->hwss.program_gamut_remap(pipes);
 607                         ret = true;
 608                 }
 609         }
 610
 611         return ret;
 612 }
 613
 614 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 615 {
 616         int i;
 617         bool ret = false;
 618         struct pipe_ctx *pipes;
 619
 620         for (i = 0; i < MAX_PIPES; i++) {
 621                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 622                                 == stream) {
 623
 624                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 625                         dc->hwss.program_output_csc(dc,
 626                                         pipes,
 627                                         stream->output_color_space,
 628                                         stream->csc_color_matrix.matrix,
 629                                         pipes->stream_res.opp->inst);
 630                         ret = true;
 631                 }
 632         }
 633
 634         return ret;
 635 }
 636
 637 void dc_stream_set_static_screen_params(struct dc *dc,
 638                 struct dc_stream_state **streams,
 639                 int num_streams,
 640                 const struct dc_static_screen_params *params)
 641 {
 642         int i, j;
 643         struct pipe_ctx *pipes_affected[MAX_PIPES];
 644         int num_pipes_affected = 0;
 645
 646         for (i = 0; i < num_streams; i++) {
 647                 struct dc_stream_state *stream = streams[i];
 648
 649                 for (j = 0; j < MAX_PIPES; j++) {
 650                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 651                                         == stream) {
 652                                 pipes_affected[num_pipes_affected++] =
 653                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 654                         }
 655                 }
 656         }
 657
 658         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 659 }
 660
 661 static void dc_destruct(struct dc *dc)
 662 {
 663         if (dc->current_state) {
 664                 dc_release_state(dc->current_state);
 665                 dc->current_state = NULL;
 666         }
 667
 668         destroy_links(dc);
 669
 670         if (dc->clk_mgr) {
 671                 dc_destroy_clk_mgr(dc->clk_mgr);
 672                 dc->clk_mgr = NULL;
 673         }
 674
 675         dc_destroy_resource_pool(dc);
 676
 677         if (dc->ctx->gpio_service)
 678                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 679
 680         if (dc->ctx->created_bios)
 681                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 682
 683         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 684
 685         kfree(dc->ctx);
 686         dc->ctx = NULL;
 687
 688         kfree(dc->bw_vbios);
 689         dc->bw_vbios = NULL;
 690
 691         kfree(dc->bw_dceip);
 692         dc->bw_dceip = NULL;
 693
 694 #ifdef CONFIG_DRM_AMD_DC_DCN
 695         kfree(dc->dcn_soc);
 696         dc->dcn_soc = NULL;
 697
 698         kfree(dc->dcn_ip);
 699         dc->dcn_ip = NULL;
 700
 701 #endif
 702         kfree(dc->vm_helper);
 703         dc->vm_helper = NULL;
 704
 705 }
 706
 707 static bool dc_construct_ctx(struct dc *dc,
 708                 const struct dc_init_data *init_params)
 709 {
 710         struct dc_context *dc_ctx;
 711         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 712
 713         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 714         if (!dc_ctx)
 715                 return false;
 716
 717         dc_ctx->cgs_device = init_params->cgs_device;
 718         dc_ctx->driver_context = init_params->driver;
 719         dc_ctx->dc = dc;
 720         dc_ctx->asic_id = init_params->asic_id;
 721         dc_ctx->dc_sink_id_count = 0;
 722         dc_ctx->dc_stream_id_count = 0;
 723         dc_ctx->dce_environment = init_params->dce_environment;
 724
 725         /* Create logger */
 726
 727         dc_version = resource_parse_asic_id(init_params->asic_id);
 728         dc_ctx->dce_version = dc_version;
 729
 730         dc_ctx->perf_trace = dc_perf_trace_create();
 731         if (!dc_ctx->perf_trace) {
 732                 ASSERT_CRITICAL(false);
 733                 return false;
 734         }
 735
 736         dc->ctx = dc_ctx;
 737
 738         return true;
 739 }
 740
 741 static bool dc_construct(struct dc *dc,
 742                 const struct dc_init_data *init_params)
 743 {
 744         struct dc_context *dc_ctx;
 745         struct bw_calcs_dceip *dc_dceip;
 746         struct bw_calcs_vbios *dc_vbios;
 747 #ifdef CONFIG_DRM_AMD_DC_DCN
 748         struct dcn_soc_bounding_box *dcn_soc;
 749         struct dcn_ip_params *dcn_ip;
 750 #endif
 751
 752         dc->config = init_params->flags;
 753
 754         // Allocate memory for the vm_helper
 755         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 756         if (!dc->vm_helper) {
 757                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 758                 goto fail;
 759         }
 760
 761         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 762
 763         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 764         if (!dc_dceip) {
 765                 dm_error("%s: failed to create dceip\n", __func__);
 766                 goto fail;
 767         }
 768
 769         dc->bw_dceip = dc_dceip;
 770
 771         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 772         if (!dc_vbios) {
 773                 dm_error("%s: failed to create vbios\n", __func__);
 774                 goto fail;
 775         }
 776
 777         dc->bw_vbios = dc_vbios;
 778 #ifdef CONFIG_DRM_AMD_DC_DCN
 779         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 780         if (!dcn_soc) {
 781                 dm_error("%s: failed to create dcn_soc\n", __func__);
 782                 goto fail;
 783         }
 784
 785         dc->dcn_soc = dcn_soc;
 786
 787         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 788         if (!dcn_ip) {
 789                 dm_error("%s: failed to create dcn_ip\n", __func__);
 790                 goto fail;
 791         }
 792
 793         dc->dcn_ip = dcn_ip;
 794 #endif
 795
 796         if (!dc_construct_ctx(dc, init_params)) {
 797                 dm_error("%s: failed to create ctx\n", __func__);
 798                 goto fail;
 799         }
 800
 801         dc_ctx = dc->ctx;
 802
 803         /* Resource should construct all asic specific resources.
 804          * This should be the only place where we need to parse the asic id
 805          */
 806         if (init_params->vbios_override)
 807                 dc_ctx->dc_bios = init_params->vbios_override;
 808         else {
 809                 /* Create BIOS parser */
 810                 struct bp_init_data bp_init_data;
 811
 812                 bp_init_data.ctx = dc_ctx;
 813                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 814
 815                 dc_ctx->dc_bios = dal_bios_parser_create(
 816                                 &bp_init_data, dc_ctx->dce_version);
 817
 818                 if (!dc_ctx->dc_bios) {
 819                         ASSERT_CRITICAL(false);
 820                         goto fail;
 821                 }
 822
 823                 dc_ctx->created_bios = true;
 824         }
 825
 826         dc->vendor_signature = init_params->vendor_signature;
 827
 828         /* Create GPIO service */
 829         dc_ctx->gpio_service = dal_gpio_service_create(
 830                         dc_ctx->dce_version,
 831                         dc_ctx->dce_environment,
 832                         dc_ctx);
 833
 834         if (!dc_ctx->gpio_service) {
 835                 ASSERT_CRITICAL(false);
 836                 goto fail;
 837         }
 838
 839         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 840         if (!dc->res_pool)
 841                 goto fail;
 842
 843         /* set i2c speed if not done by the respective dcnxxx__resource.c */
 844         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
 845                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
 846
 847         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 848         if (!dc->clk_mgr)
 849                 goto fail;
 850 #ifdef CONFIG_DRM_AMD_DC_DCN
 851         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 852 #endif
 853
 854         if (dc->res_pool->funcs->update_bw_bounding_box)
 855                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 856
 857         /* Creation of current_state must occur after dc->dml
 858          * is initialized in dc_create_resource_pool because
 859          * on creation it copies the contents of dc->dml
 860          */
 861
 862         dc->current_state = dc_create_state(dc);
 863
 864         if (!dc->current_state) {
 865                 dm_error("%s: failed to create validate ctx\n", __func__);
 866                 goto fail;
 867         }
 868
 869         dc_resource_state_construct(dc, dc->current_state);
 870
 871         if (!create_links(dc, init_params->num_virtual_links))
 872                 goto fail;
 873
 874         /* Initialise DIG link encoder resource tracking variables. */
 875         link_enc_cfg_init(dc, dc->current_state);
 876
 877         return true;
 878
 879 fail:
 880         return false;
 881 }
 882
 883 static void disable_all_writeback_pipes_for_stream(
 884                 const struct dc *dc,
 885                 struct dc_stream_state *stream,
 886                 struct dc_state *context)
 887 {
 888         int i;
 889
 890         for (i = 0; i < stream->num_wb_info; i++)
 891                 stream->writeback_info[i].wb_enabled = false;
 892 }
 893
 894 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
 895                                           struct dc_stream_state *stream, bool lock)
 896 {
 897         int i;
 898
 899         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 900         if (dc->hwss.interdependent_update_lock)
 901                 dc->hwss.interdependent_update_lock(dc, context, lock);
 902         else {
 903                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 904                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 905                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 906
 907                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 908                         if (stream == pipe_ctx->stream) {
 909                                 if (!pipe_ctx->top_pipe &&
 910                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 911                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 912                         }
 913                 }
 914         }
 915 }
 916
 917 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 918 {
 919         int i, j;
 920         struct dc_state *dangling_context = dc_create_state(dc);
 921         struct dc_state *current_ctx;
 922
 923         if (dangling_context == NULL)
 924                 return;
 925
 926         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 927
 928         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 929                 struct dc_stream_state *old_stream =
 930                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 931                 bool should_disable = true;
 932
 933                 for (j = 0; j < context->stream_count; j++) {
 934                         if (old_stream == context->streams[j]) {
 935                                 should_disable = false;
 936                                 break;
 937                         }
 938                 }
 939                 if (should_disable && old_stream) {
 940                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 941                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 942
 943                         if (dc->hwss.apply_ctx_for_surface) {
 944                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 945                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 946                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 947                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 948                         }
 949                         if (dc->hwss.program_front_end_for_ctx) {
 950                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 951                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 952                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 953                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 954                         }
 955                 }
 956         }
 957
 958         current_ctx = dc->current_state;
 959         dc->current_state = dangling_context;
 960         dc_release_state(current_ctx);
 961 }
 962
 963 static void disable_vbios_mode_if_required(
 964                 struct dc *dc,
 965                 struct dc_state *context)
 966 {
 967         unsigned int i, j;
 968
 969         /* check if timing_changed, disable stream*/
 970         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 971                 struct dc_stream_state *stream = NULL;
 972                 struct dc_link *link = NULL;
 973                 struct pipe_ctx *pipe = NULL;
 974
 975                 pipe = &context->res_ctx.pipe_ctx[i];
 976                 stream = pipe->stream;
 977                 if (stream == NULL)
 978                         continue;
 979
 980                 // only looking for first odm pipe
 981                 if (pipe->prev_odm_pipe)
 982                         continue;
 983
 984                 if (stream->link->local_sink &&
 985                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
 986                         link = stream->link;
 987                 }
 988
 989                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 990                         unsigned int enc_inst, tg_inst = 0;
 991                         unsigned int pix_clk_100hz;
 992
 993                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 994                         if (enc_inst != ENGINE_ID_UNKNOWN) {
 995                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
 996                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
 997                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
 998                                                         dc->res_pool->stream_enc[j]);
 999                                                 break;
1000                                         }
1001                                 }
1002
1003                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1004                                         dc->res_pool->dp_clock_source,
1005                                         tg_inst, &pix_clk_100hz);
1006
1007                                 if (link->link_status.link_active) {
1008                                         uint32_t requested_pix_clk_100hz =
1009                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1010
1011                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1012                                                 core_link_disable_stream(pipe);
1013                                                 pipe->stream->dpms_off = false;
1014                                         }
1015                                 }
1016                         }
1017                 }
1018         }
1019 }
1020
1021 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1022 {
1023         int i;
1024         PERF_TRACE();
1025         for (i = 0; i < MAX_PIPES; i++) {
1026                 int count = 0;
1027                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1028
1029                 if (!pipe->plane_state)
1030                         continue;
1031
1032                 /* Timeout 100 ms */
1033                 while (count < 100000) {
1034                         /* Must set to false to start with, due to OR in update function */
1035                         pipe->plane_state->status.is_flip_pending = false;
1036                         dc->hwss.update_pending_status(pipe);
1037                         if (!pipe->plane_state->status.is_flip_pending)
1038                                 break;
1039                         udelay(1);
1040                         count++;
1041                 }
1042                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1043         }
1044         PERF_TRACE();
1045 }
1046
1047 /*******************************************************************************
1048  * Public functions
1049  ******************************************************************************/
1050
1051 struct dc *dc_create(const struct dc_init_data *init_params)
1052 {
1053         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1054         unsigned int full_pipe_count;
1055
1056         if (!dc)
1057                 return NULL;
1058
1059         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1060                 if (!dc_construct_ctx(dc, init_params))
1061                         goto destruct_dc;
1062         } else {
1063                 if (!dc_construct(dc, init_params))
1064                         goto destruct_dc;
1065
1066                 full_pipe_count = dc->res_pool->pipe_count;
1067                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1068                         full_pipe_count--;
1069                 dc->caps.max_streams = min(
1070                                 full_pipe_count,
1071                                 dc->res_pool->stream_enc_count);
1072
1073                 dc->caps.max_links = dc->link_count;
1074                 dc->caps.max_audios = dc->res_pool->audio_count;
1075                 dc->caps.linear_pitch_alignment = 64;
1076
1077                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1078
1079                 if (dc->res_pool->dmcu != NULL)
1080                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1081         }
1082
1083         /* Populate versioning information */
1084         dc->versions.dc_ver = DC_VER;
1085
1086         dc->build_id = DC_BUILD_ID;
1087
1088         DC_LOG_DC("Display Core initialized\n");
1089
1090
1091
1092         return dc;
1093
1094 destruct_dc:
1095         dc_destruct(dc);
1096         kfree(dc);
1097         return NULL;
1098 }
1099
1100 static void detect_edp_presence(struct dc *dc)
1101 {
1102         struct dc_link *edp_links[MAX_NUM_EDP];
1103         struct dc_link *edp_link = NULL;
1104         enum dc_connection_type type;
1105         int i;
1106         int edp_num;
1107
1108         get_edp_links(dc, edp_links, &edp_num);
1109         if (!edp_num)
1110                 return;
1111
1112         for (i = 0; i < edp_num; i++) {
1113                 edp_link = edp_links[i];
1114                 if (dc->config.edp_not_connected) {
1115                         edp_link->edp_sink_present = false;
1116                 } else {
1117                         dc_link_detect_sink(edp_link, &type);
1118                         edp_link->edp_sink_present = (type != dc_connection_none);
1119                 }
1120         }
1121 }
1122
1123 void dc_hardware_init(struct dc *dc)
1124 {
1125
1126         detect_edp_presence(dc);
1127         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1128                 dc->hwss.init_hw(dc);
1129 }
1130
1131 void dc_init_callbacks(struct dc *dc,
1132                 const struct dc_callback_init *init_params)
1133 {
1134 #ifdef CONFIG_DRM_AMD_DC_HDCP
1135         dc->ctx->cp_psp = init_params->cp_psp;
1136 #endif
1137 }
1138
1139 void dc_deinit_callbacks(struct dc *dc)
1140 {
1141 #ifdef CONFIG_DRM_AMD_DC_HDCP
1142         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1143 #endif
1144 }
1145
1146 void dc_destroy(struct dc **dc)
1147 {
1148         dc_destruct(*dc);
1149         kfree(*dc);
1150         *dc = NULL;
1151 }
1152
1153 static void enable_timing_multisync(
1154                 struct dc *dc,
1155                 struct dc_state *ctx)
1156 {
1157         int i, multisync_count = 0;
1158         int pipe_count = dc->res_pool->pipe_count;
1159         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1160
1161         for (i = 0; i < pipe_count; i++) {
1162                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1163                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1164                         continue;
1165                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1166                         continue;
1167                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1168                 multisync_count++;
1169         }
1170
1171         if (multisync_count > 0) {
1172                 dc->hwss.enable_per_frame_crtc_position_reset(
1173                         dc, multisync_count, multisync_pipes);
1174         }
1175 }
1176
1177 static void program_timing_sync(
1178                 struct dc *dc,
1179                 struct dc_state *ctx)
1180 {
1181         int i, j, k;
1182         int group_index = 0;
1183         int num_group = 0;
1184         int pipe_count = dc->res_pool->pipe_count;
1185         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1186
1187         for (i = 0; i < pipe_count; i++) {
1188                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1189                         continue;
1190
1191                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1192         }
1193
1194         for (i = 0; i < pipe_count; i++) {
1195                 int group_size = 1;
1196                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1197                 struct pipe_ctx *pipe_set[MAX_PIPES];
1198
1199                 if (!unsynced_pipes[i])
1200                         continue;
1201
1202                 pipe_set[0] = unsynced_pipes[i];
1203                 unsynced_pipes[i] = NULL;
1204
1205                 /* Add tg to the set, search rest of the tg's for ones with
1206                  * same timing, add all tgs with same timing to the group
1207                  */
1208                 for (j = i + 1; j < pipe_count; j++) {
1209                         if (!unsynced_pipes[j])
1210                                 continue;
1211                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1212                                 dc->hwss.enable_vblanks_synchronization &&
1213                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1214                                 resource_are_vblanks_synchronizable(
1215                                         unsynced_pipes[j]->stream,
1216                                         pipe_set[0]->stream)) {
1217                                 sync_type = VBLANK_SYNCHRONIZABLE;
1218                                 pipe_set[group_size] = unsynced_pipes[j];
1219                                 unsynced_pipes[j] = NULL;
1220                                 group_size++;
1221                         } else
1222                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1223                                 resource_are_streams_timing_synchronizable(
1224                                         unsynced_pipes[j]->stream,
1225                                         pipe_set[0]->stream)) {
1226                                 sync_type = TIMING_SYNCHRONIZABLE;
1227                                 pipe_set[group_size] = unsynced_pipes[j];
1228                                 unsynced_pipes[j] = NULL;
1229                                 group_size++;
1230                         }
1231                 }
1232
1233                 /* set first unblanked pipe as master */
1234                 for (j = 0; j < group_size; j++) {
1235                         bool is_blanked;
1236
1237                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1238                                 is_blanked =
1239                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1240                         else
1241                                 is_blanked =
1242                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1243                         if (!is_blanked) {
1244                                 if (j == 0)
1245                                         break;
1246
1247                                 swap(pipe_set[0], pipe_set[j]);
1248                                 break;
1249                         }
1250                 }
1251
1252                 for (k = 0; k < group_size; k++) {
1253                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1254
1255                         status->timing_sync_info.group_id = num_group;
1256                         status->timing_sync_info.group_size = group_size;
1257                         if (k == 0)
1258                                 status->timing_sync_info.master = true;
1259                         else
1260                                 status->timing_sync_info.master = false;
1261
1262                 }
1263                 /* remove any other unblanked pipes as they have already been synced */
1264                 for (j = j + 1; j < group_size; j++) {
1265                         bool is_blanked;
1266
1267                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1268                                 is_blanked =
1269                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1270                         else
1271                                 is_blanked =
1272                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1273                         if (!is_blanked) {
1274                                 group_size--;
1275                                 pipe_set[j] = pipe_set[group_size];
1276                                 j--;
1277                         }
1278                 }
1279
1280                 if (group_size > 1) {
1281                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1282                                 dc->hwss.enable_timing_synchronization(
1283                                         dc, group_index, group_size, pipe_set);
1284                         } else
1285                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1286                                 dc->hwss.enable_vblanks_synchronization(
1287                                         dc, group_index, group_size, pipe_set);
1288                                 }
1289                         group_index++;
1290                 }
1291                 num_group++;
1292         }
1293 }
1294
1295 static bool context_changed(
1296                 struct dc *dc,
1297                 struct dc_state *context)
1298 {
1299         uint8_t i;
1300
1301         if (context->stream_count != dc->current_state->stream_count)
1302                 return true;
1303
1304         for (i = 0; i < dc->current_state->stream_count; i++) {
1305                 if (dc->current_state->streams[i] != context->streams[i])
1306                         return true;
1307         }
1308
1309         return false;
1310 }
1311
1312 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1313                                 const struct dc_sink *sink,
1314                                 struct dc_crtc_timing *crtc_timing)
1315 {
1316         struct timing_generator *tg;
1317         struct stream_encoder *se = NULL;
1318
1319         struct dc_crtc_timing hw_crtc_timing = {0};
1320
1321         struct dc_link *link = sink->link;
1322         unsigned int i, enc_inst, tg_inst = 0;
1323
1324         /* Support seamless boot on EDP displays only */
1325         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1326                 return false;
1327         }
1328
1329         /* Check for enabled DIG to identify enabled display */
1330         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1331                 return false;
1332
1333         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1334
1335         if (enc_inst == ENGINE_ID_UNKNOWN)
1336                 return false;
1337
1338         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1339                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1340
1341                         se = dc->res_pool->stream_enc[i];
1342
1343                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1344                                 dc->res_pool->stream_enc[i]);
1345                         break;
1346                 }
1347         }
1348
1349         // tg_inst not found
1350         if (i == dc->res_pool->stream_enc_count)
1351                 return false;
1352
1353         if (tg_inst >= dc->res_pool->timing_generator_count)
1354                 return false;
1355
1356         tg = dc->res_pool->timing_generators[tg_inst];
1357
1358         if (!tg->funcs->get_hw_timing)
1359                 return false;
1360
1361         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1362                 return false;
1363
1364         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1365                 return false;
1366
1367         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1368                 return false;
1369
1370         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1371                 return false;
1372
1373         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1374                 return false;
1375
1376         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1377                 return false;
1378
1379         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1380                 return false;
1381
1382         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1383                 return false;
1384
1385         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1386                 return false;
1387
1388         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1389                 return false;
1390
1391         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1392                 return false;
1393
1394         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1395                 return false;
1396
1397         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1398                 return false;
1399
1400         /* block DSC for now, as VBIOS does not currently support DSC timings */
1401         if (crtc_timing->flags.DSC)
1402                 return false;
1403
1404         if (dc_is_dp_signal(link->connector_signal)) {
1405                 unsigned int pix_clk_100hz;
1406
1407                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1408                         dc->res_pool->dp_clock_source,
1409                         tg_inst, &pix_clk_100hz);
1410
1411                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1412                         return false;
1413
1414                 if (!se->funcs->dp_get_pixel_format)
1415                         return false;
1416
1417                 if (!se->funcs->dp_get_pixel_format(
1418                         se,
1419                         &hw_crtc_timing.pixel_encoding,
1420                         &hw_crtc_timing.display_color_depth))
1421                         return false;
1422
1423                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1424                         return false;
1425
1426                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1427                         return false;
1428         }
1429
1430         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1431                 return false;
1432         }
1433
1434         if (is_edp_ilr_optimization_required(link, crtc_timing)) {
1435                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1436                 return false;
1437         }
1438
1439         return true;
1440 }
1441
1442 void dc_enable_stereo(
1443         struct dc *dc,
1444         struct dc_state *context,
1445         struct dc_stream_state *streams[],
1446         uint8_t stream_count)
1447 {
1448         int i, j;
1449         struct pipe_ctx *pipe;
1450
1451         for (i = 0; i < MAX_PIPES; i++) {
1452                 if (context != NULL)
1453                         pipe = &context->res_ctx.pipe_ctx[i];
1454                 else
1455                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1456                 for (j = 0 ; pipe && j < stream_count; j++)  {
1457                         if (streams[j] && streams[j] == pipe->stream &&
1458                                 dc->hwss.setup_stereo)
1459                                 dc->hwss.setup_stereo(pipe, dc);
1460                 }
1461         }
1462 }
1463
1464 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1465 {
1466         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1467                 enable_timing_multisync(dc, context);
1468                 program_timing_sync(dc, context);
1469         }
1470 }
1471
1472 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1473 {
1474         int i;
1475         unsigned int stream_mask = 0;
1476
1477         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1478                 if (context->res_ctx.pipe_ctx[i].stream)
1479                         stream_mask |= 1 << i;
1480         }
1481
1482         return stream_mask;
1483 }
1484
1485 /*
1486  * Applies given context to HW and copy it into current context.
1487  * It's up to the user to release the src context afterwards.
1488  */
1489 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1490 {
1491         struct dc_bios *dcb = dc->ctx->dc_bios;
1492         enum dc_status result = DC_ERROR_UNEXPECTED;
1493         struct pipe_ctx *pipe;
1494         int i, k, l;
1495         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1496
1497 #if defined(CONFIG_DRM_AMD_DC_DCN)
1498         dc_allow_idle_optimizations(dc, false);
1499 #endif
1500
1501         for (i = 0; i < context->stream_count; i++)
1502                 dc_streams[i] =  context->streams[i];
1503
1504         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1505                 disable_vbios_mode_if_required(dc, context);
1506                 dc->hwss.enable_accelerated_mode(dc, context);
1507         }
1508
1509         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1510                 context->stream_count == 0)
1511                 dc->hwss.prepare_bandwidth(dc, context);
1512
1513         disable_dangling_plane(dc, context);
1514         /* re-program planes for existing stream, in case we need to
1515          * free up plane resource for later use
1516          */
1517         if (dc->hwss.apply_ctx_for_surface) {
1518                 for (i = 0; i < context->stream_count; i++) {
1519                         if (context->streams[i]->mode_changed)
1520                                 continue;
1521                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1522                         dc->hwss.apply_ctx_for_surface(
1523                                 dc, context->streams[i],
1524                                 context->stream_status[i].plane_count,
1525                                 context); /* use new pipe config in new context */
1526                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1527                         dc->hwss.post_unlock_program_front_end(dc, context);
1528                 }
1529         }
1530
1531         /* Program hardware */
1532         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1533                 pipe = &context->res_ctx.pipe_ctx[i];
1534                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1535         }
1536
1537         result = dc->hwss.apply_ctx_to_hw(dc, context);
1538
1539         if (result != DC_OK)
1540                 return result;
1541
1542         dc_trigger_sync(dc, context);
1543
1544         /* Program all planes within new context*/
1545         if (dc->hwss.program_front_end_for_ctx) {
1546                 dc->hwss.interdependent_update_lock(dc, context, true);
1547                 dc->hwss.program_front_end_for_ctx(dc, context);
1548                 dc->hwss.interdependent_update_lock(dc, context, false);
1549                 dc->hwss.post_unlock_program_front_end(dc, context);
1550         }
1551         for (i = 0; i < context->stream_count; i++) {
1552                 const struct dc_link *link = context->streams[i]->link;
1553
1554                 if (!context->streams[i]->mode_changed)
1555                         continue;
1556
1557                 if (dc->hwss.apply_ctx_for_surface) {
1558                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1559                         dc->hwss.apply_ctx_for_surface(
1560                                         dc, context->streams[i],
1561                                         context->stream_status[i].plane_count,
1562                                         context);
1563                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1564                         dc->hwss.post_unlock_program_front_end(dc, context);
1565                 }
1566
1567                 /*
1568                  * enable stereo
1569                  * TODO rework dc_enable_stereo call to work with validation sets?
1570                  */
1571                 for (k = 0; k < MAX_PIPES; k++) {
1572                         pipe = &context->res_ctx.pipe_ctx[k];
1573
1574                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1575                                 if (context->streams[l] &&
1576                                         context->streams[l] == pipe->stream &&
1577                                         dc->hwss.setup_stereo)
1578                                         dc->hwss.setup_stereo(pipe, dc);
1579                         }
1580                 }
1581
1582                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1583                                 context->streams[i]->timing.h_addressable,
1584                                 context->streams[i]->timing.v_addressable,
1585                                 context->streams[i]->timing.h_total,
1586                                 context->streams[i]->timing.v_total,
1587                                 context->streams[i]->timing.pix_clk_100hz / 10);
1588         }
1589
1590         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1591
1592         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1593                 context->stream_count == 0) {
1594                 /* Must wait for no flips to be pending before doing optimize bw */
1595                 wait_for_no_pipes_pending(dc, context);
1596                 /* pplib is notified if disp_num changed */
1597                 dc->hwss.optimize_bandwidth(dc, context);
1598         }
1599
1600         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1601                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1602         else
1603                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1604
1605         context->stream_mask = get_stream_mask(dc, context);
1606
1607         if (context->stream_mask != dc->current_state->stream_mask)
1608                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1609
1610         for (i = 0; i < context->stream_count; i++)
1611                 context->streams[i]->mode_changed = false;
1612
1613         dc_release_state(dc->current_state);
1614
1615         dc->current_state = context;
1616
1617         dc_retain_state(dc->current_state);
1618
1619         return result;
1620 }
1621
1622 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1623 {
1624         enum dc_status result = DC_ERROR_UNEXPECTED;
1625         int i;
1626
1627         if (!context_changed(dc, context))
1628                 return DC_OK;
1629
1630         DC_LOG_DC("%s: %d streams\n",
1631                                 __func__, context->stream_count);
1632
1633         for (i = 0; i < context->stream_count; i++) {
1634                 struct dc_stream_state *stream = context->streams[i];
1635
1636                 dc_stream_log(dc, stream);
1637         }
1638
1639         result = dc_commit_state_no_check(dc, context);
1640
1641         return (result == DC_OK);
1642 }
1643
1644 #if defined(CONFIG_DRM_AMD_DC_DCN)
1645 bool dc_acquire_release_mpc_3dlut(
1646                 struct dc *dc, bool acquire,
1647                 struct dc_stream_state *stream,
1648                 struct dc_3dlut **lut,
1649                 struct dc_transfer_func **shaper)
1650 {
1651         int pipe_idx;
1652         bool ret = false;
1653         bool found_pipe_idx = false;
1654         const struct resource_pool *pool = dc->res_pool;
1655         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1656         int mpcc_id = 0;
1657
1658         if (pool && res_ctx) {
1659                 if (acquire) {
1660                         /*find pipe idx for the given stream*/
1661                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1662                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1663                                         found_pipe_idx = true;
1664                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1665                                         break;
1666                                 }
1667                         }
1668                 } else
1669                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1670
1671                 if (found_pipe_idx) {
1672                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1673                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1674                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
1675                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1676                 }
1677         }
1678         return ret;
1679 }
1680 #endif
1681 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1682 {
1683         int i;
1684         struct pipe_ctx *pipe;
1685
1686         for (i = 0; i < MAX_PIPES; i++) {
1687                 pipe = &context->res_ctx.pipe_ctx[i];
1688
1689                 if (!pipe->plane_state)
1690                         continue;
1691
1692                 /* Must set to false to start with, due to OR in update function */
1693                 pipe->plane_state->status.is_flip_pending = false;
1694                 dc->hwss.update_pending_status(pipe);
1695                 if (pipe->plane_state->status.is_flip_pending)
1696                         return true;
1697         }
1698         return false;
1699 }
1700
1701 void dc_post_update_surfaces_to_stream(struct dc *dc)
1702 {
1703         int i;
1704         struct dc_state *context = dc->current_state;
1705
1706         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
1707                 return;
1708
1709         post_surface_trace(dc);
1710
1711         if (is_flip_pending_in_pipes(dc, context))
1712                 return;
1713
1714         for (i = 0; i < dc->res_pool->pipe_count; i++)
1715                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1716                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1717                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1718                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1719                 }
1720
1721         dc->hwss.optimize_bandwidth(dc, context);
1722
1723         dc->optimized_required = false;
1724         dc->wm_optimized_required = false;
1725 }
1726
1727 static void init_state(struct dc *dc, struct dc_state *context)
1728 {
1729         /* Each context must have their own instance of VBA and in order to
1730          * initialize and obtain IP and SOC the base DML instance from DC is
1731          * initially copied into every context
1732          */
1733 #ifdef CONFIG_DRM_AMD_DC_DCN
1734         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1735 #endif
1736 }
1737
1738 struct dc_state *dc_create_state(struct dc *dc)
1739 {
1740         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1741                                             GFP_KERNEL);
1742
1743         if (!context)
1744                 return NULL;
1745
1746         init_state(dc, context);
1747
1748         kref_init(&context->refcount);
1749
1750         return context;
1751 }
1752
1753 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1754 {
1755         int i, j;
1756         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1757
1758         if (!new_ctx)
1759                 return NULL;
1760         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1761
1762         for (i = 0; i < MAX_PIPES; i++) {
1763                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1764
1765                         if (cur_pipe->top_pipe)
1766                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1767
1768                         if (cur_pipe->bottom_pipe)
1769                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1770
1771                         if (cur_pipe->prev_odm_pipe)
1772                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1773
1774                         if (cur_pipe->next_odm_pipe)
1775                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1776
1777         }
1778
1779         for (i = 0; i < new_ctx->stream_count; i++) {
1780                         dc_stream_retain(new_ctx->streams[i]);
1781                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1782                                 dc_plane_state_retain(
1783                                         new_ctx->stream_status[i].plane_states[j]);
1784         }
1785
1786         kref_init(&new_ctx->refcount);
1787
1788         return new_ctx;
1789 }
1790
1791 void dc_retain_state(struct dc_state *context)
1792 {
1793         kref_get(&context->refcount);
1794 }
1795
1796 static void dc_state_free(struct kref *kref)
1797 {
1798         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1799         dc_resource_state_destruct(context);
1800         kvfree(context);
1801 }
1802
1803 void dc_release_state(struct dc_state *context)
1804 {
1805         kref_put(&context->refcount, dc_state_free);
1806 }
1807
1808 bool dc_set_generic_gpio_for_stereo(bool enable,
1809                 struct gpio_service *gpio_service)
1810 {
1811         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1812         struct gpio_pin_info pin_info;
1813         struct gpio *generic;
1814         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1815                            GFP_KERNEL);
1816
1817         if (!config)
1818                 return false;
1819         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1820
1821         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1822                 kfree(config);
1823                 return false;
1824         } else {
1825                 generic = dal_gpio_service_create_generic_mux(
1826                         gpio_service,
1827                         pin_info.offset,
1828                         pin_info.mask);
1829         }
1830
1831         if (!generic) {
1832                 kfree(config);
1833                 return false;
1834         }
1835
1836         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1837
1838         config->enable_output_from_mux = enable;
1839         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1840
1841         if (gpio_result == GPIO_RESULT_OK)
1842                 gpio_result = dal_mux_setup_config(generic, config);
1843
1844         if (gpio_result == GPIO_RESULT_OK) {
1845                 dal_gpio_close(generic);
1846                 dal_gpio_destroy_generic_mux(&generic);
1847                 kfree(config);
1848                 return true;
1849         } else {
1850                 dal_gpio_close(generic);
1851                 dal_gpio_destroy_generic_mux(&generic);
1852                 kfree(config);
1853                 return false;
1854         }
1855 }
1856
1857 static bool is_surface_in_context(
1858                 const struct dc_state *context,
1859                 const struct dc_plane_state *plane_state)
1860 {
1861         int j;
1862
1863         for (j = 0; j < MAX_PIPES; j++) {
1864                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1865
1866                 if (plane_state == pipe_ctx->plane_state) {
1867                         return true;
1868                 }
1869         }
1870
1871         return false;
1872 }
1873
1874 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1875 {
1876         union surface_update_flags *update_flags = &u->surface->update_flags;
1877         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1878
1879         if (!u->plane_info)
1880                 return UPDATE_TYPE_FAST;
1881
1882         if (u->plane_info->color_space != u->surface->color_space) {
1883                 update_flags->bits.color_space_change = 1;
1884                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1885         }
1886
1887         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1888                 update_flags->bits.horizontal_mirror_change = 1;
1889                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1890         }
1891
1892         if (u->plane_info->rotation != u->surface->rotation) {
1893                 update_flags->bits.rotation_change = 1;
1894                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1895         }
1896
1897         if (u->plane_info->format != u->surface->format) {
1898                 update_flags->bits.pixel_format_change = 1;
1899                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1900         }
1901
1902         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1903                 update_flags->bits.stereo_format_change = 1;
1904                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1905         }
1906
1907         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1908                 update_flags->bits.per_pixel_alpha_change = 1;
1909                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1910         }
1911
1912         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1913                 update_flags->bits.global_alpha_change = 1;
1914                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1915         }
1916
1917         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1918                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1919                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1920                 update_flags->bits.dcc_change = 1;
1921                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1922         }
1923
1924         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1925                         resource_pixel_format_to_bpp(u->surface->format)) {
1926                 /* different bytes per element will require full bandwidth
1927                  * and DML calculation
1928                  */
1929                 update_flags->bits.bpp_change = 1;
1930                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1931         }
1932
1933         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1934                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1935                 update_flags->bits.plane_size_change = 1;
1936                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1937         }
1938
1939
1940         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1941                         sizeof(union dc_tiling_info)) != 0) {
1942                 update_flags->bits.swizzle_change = 1;
1943                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1944
1945                 /* todo: below are HW dependent, we should add a hook to
1946                  * DCE/N resource and validated there.
1947                  */
1948                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1949                         /* swizzled mode requires RQ to be setup properly,
1950                          * thus need to run DML to calculate RQ settings
1951                          */
1952                         update_flags->bits.bandwidth_change = 1;
1953                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1954                 }
1955         }
1956
1957         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1958         return update_type;
1959 }
1960
1961 static enum surface_update_type get_scaling_info_update_type(
1962                 const struct dc_surface_update *u)
1963 {
1964         union surface_update_flags *update_flags = &u->surface->update_flags;
1965
1966         if (!u->scaling_info)
1967                 return UPDATE_TYPE_FAST;
1968
1969         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1970                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1971                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1972                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1973                         || u->scaling_info->scaling_quality.integer_scaling !=
1974                                 u->surface->scaling_quality.integer_scaling
1975                         ) {
1976                 update_flags->bits.scaling_change = 1;
1977
1978                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1979                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1980                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1981                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1982                         /* Making dst rect smaller requires a bandwidth change */
1983                         update_flags->bits.bandwidth_change = 1;
1984         }
1985
1986         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1987                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1988
1989                 update_flags->bits.scaling_change = 1;
1990                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1991                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1992                         /* Making src rect bigger requires a bandwidth change */
1993                         update_flags->bits.clock_change = 1;
1994         }
1995
1996         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1997                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1998                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1999                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2000                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2001                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2002                 update_flags->bits.position_change = 1;
2003
2004         if (update_flags->bits.clock_change
2005                         || update_flags->bits.bandwidth_change
2006                         || update_flags->bits.scaling_change)
2007                 return UPDATE_TYPE_FULL;
2008
2009         if (update_flags->bits.position_change)
2010                 return UPDATE_TYPE_MED;
2011
2012         return UPDATE_TYPE_FAST;
2013 }
2014
2015 static enum surface_update_type det_surface_update(const struct dc *dc,
2016                 const struct dc_surface_update *u)
2017 {
2018         const struct dc_state *context = dc->current_state;
2019         enum surface_update_type type;
2020         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2021         union surface_update_flags *update_flags = &u->surface->update_flags;
2022
2023         if (u->flip_addr)
2024                 update_flags->bits.addr_update = 1;
2025
2026         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2027                 update_flags->raw = 0xFFFFFFFF;
2028                 return UPDATE_TYPE_FULL;
2029         }
2030
2031         update_flags->raw = 0; // Reset all flags
2032
2033         type = get_plane_info_update_type(u);
2034         elevate_update_type(&overall_type, type);
2035
2036         type = get_scaling_info_update_type(u);
2037         elevate_update_type(&overall_type, type);
2038
2039         if (u->flip_addr)
2040                 update_flags->bits.addr_update = 1;
2041
2042         if (u->in_transfer_func)
2043                 update_flags->bits.in_transfer_func_change = 1;
2044
2045         if (u->input_csc_color_matrix)
2046                 update_flags->bits.input_csc_change = 1;
2047
2048         if (u->coeff_reduction_factor)
2049                 update_flags->bits.coeff_reduction_change = 1;
2050
2051         if (u->gamut_remap_matrix)
2052                 update_flags->bits.gamut_remap_change = 1;
2053
2054         if (u->gamma) {
2055                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2056
2057                 if (u->plane_info)
2058                         format = u->plane_info->format;
2059                 else if (u->surface)
2060                         format = u->surface->format;
2061
2062                 if (dce_use_lut(format))
2063                         update_flags->bits.gamma_change = 1;
2064         }
2065
2066         if (u->hdr_mult.value)
2067                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2068                         update_flags->bits.hdr_mult = 1;
2069                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2070                 }
2071
2072         if (update_flags->bits.in_transfer_func_change) {
2073                 type = UPDATE_TYPE_MED;
2074                 elevate_update_type(&overall_type, type);
2075         }
2076
2077         if (update_flags->bits.input_csc_change
2078                         || update_flags->bits.coeff_reduction_change
2079                         || update_flags->bits.gamma_change
2080                         || update_flags->bits.gamut_remap_change) {
2081                 type = UPDATE_TYPE_FULL;
2082                 elevate_update_type(&overall_type, type);
2083         }
2084
2085         return overall_type;
2086 }
2087
2088 static enum surface_update_type check_update_surfaces_for_stream(
2089                 struct dc *dc,
2090                 struct dc_surface_update *updates,
2091                 int surface_count,
2092                 struct dc_stream_update *stream_update,
2093                 const struct dc_stream_status *stream_status)
2094 {
2095         int i;
2096         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2097
2098 #if defined(CONFIG_DRM_AMD_DC_DCN)
2099         if (dc->idle_optimizations_allowed)
2100                 overall_type = UPDATE_TYPE_FULL;
2101
2102 #endif
2103         if (stream_status == NULL || stream_status->plane_count != surface_count)
2104                 overall_type = UPDATE_TYPE_FULL;
2105
2106         if (stream_update && stream_update->pending_test_pattern) {
2107                 overall_type = UPDATE_TYPE_FULL;
2108         }
2109
2110         /* some stream updates require passive update */
2111         if (stream_update) {
2112                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2113
2114                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2115                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2116                         stream_update->integer_scaling_update)
2117                         su_flags->bits.scaling = 1;
2118
2119                 if (stream_update->out_transfer_func)
2120                         su_flags->bits.out_tf = 1;
2121
2122                 if (stream_update->abm_level)
2123                         su_flags->bits.abm_level = 1;
2124
2125                 if (stream_update->dpms_off)
2126                         su_flags->bits.dpms_off = 1;
2127
2128                 if (stream_update->gamut_remap)
2129                         su_flags->bits.gamut_remap = 1;
2130
2131                 if (stream_update->wb_update)
2132                         su_flags->bits.wb_update = 1;
2133
2134                 if (stream_update->dsc_config)
2135                         su_flags->bits.dsc_changed = 1;
2136
2137                 if (su_flags->raw != 0)
2138                         overall_type = UPDATE_TYPE_FULL;
2139
2140                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2141                         su_flags->bits.out_csc = 1;
2142         }
2143
2144         for (i = 0 ; i < surface_count; i++) {
2145                 enum surface_update_type type =
2146                                 det_surface_update(dc, &updates[i]);
2147
2148                 elevate_update_type(&overall_type, type);
2149         }
2150
2151         return overall_type;
2152 }
2153
2154 /*
2155  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2156  *
2157  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2158  */
2159 enum surface_update_type dc_check_update_surfaces_for_stream(
2160                 struct dc *dc,
2161                 struct dc_surface_update *updates,
2162                 int surface_count,
2163                 struct dc_stream_update *stream_update,
2164                 const struct dc_stream_status *stream_status)
2165 {
2166         int i;
2167         enum surface_update_type type;
2168
2169         if (stream_update)
2170                 stream_update->stream->update_flags.raw = 0;
2171         for (i = 0; i < surface_count; i++)
2172                 updates[i].surface->update_flags.raw = 0;
2173
2174         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2175         if (type == UPDATE_TYPE_FULL) {
2176                 if (stream_update) {
2177                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2178                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2179                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2180                 }
2181                 for (i = 0; i < surface_count; i++)
2182                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2183         }
2184
2185         if (type == UPDATE_TYPE_FAST) {
2186                 // If there's an available clock comparator, we use that.
2187                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2188                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2189                                 dc->optimized_required = true;
2190                 // Else we fallback to mem compare.
2191                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2192                         dc->optimized_required = true;
2193                 }
2194
2195                 dc->optimized_required |= dc->wm_optimized_required;
2196         }
2197
2198         return type;
2199 }
2200
2201 static struct dc_stream_status *stream_get_status(
2202         struct dc_state *ctx,
2203         struct dc_stream_state *stream)
2204 {
2205         uint8_t i;
2206
2207         for (i = 0; i < ctx->stream_count; i++) {
2208                 if (stream == ctx->streams[i]) {
2209                         return &ctx->stream_status[i];
2210                 }
2211         }
2212
2213         return NULL;
2214 }
2215
2216 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2217
2218 static void copy_surface_update_to_plane(
2219                 struct dc_plane_state *surface,
2220                 struct dc_surface_update *srf_update)
2221 {
2222         if (srf_update->flip_addr) {
2223                 surface->address = srf_update->flip_addr->address;
2224                 surface->flip_immediate =
2225                         srf_update->flip_addr->flip_immediate;
2226                 surface->time.time_elapsed_in_us[surface->time.index] =
2227                         srf_update->flip_addr->flip_timestamp_in_us -
2228                                 surface->time.prev_update_time_in_us;
2229                 surface->time.prev_update_time_in_us =
2230                         srf_update->flip_addr->flip_timestamp_in_us;
2231                 surface->time.index++;
2232                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2233                         surface->time.index = 0;
2234
2235                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2236         }
2237
2238         if (srf_update->scaling_info) {
2239                 surface->scaling_quality =
2240                                 srf_update->scaling_info->scaling_quality;
2241                 surface->dst_rect =
2242                                 srf_update->scaling_info->dst_rect;
2243                 surface->src_rect =
2244                                 srf_update->scaling_info->src_rect;
2245                 surface->clip_rect =
2246                                 srf_update->scaling_info->clip_rect;
2247         }
2248
2249         if (srf_update->plane_info) {
2250                 surface->color_space =
2251                                 srf_update->plane_info->color_space;
2252                 surface->format =
2253                                 srf_update->plane_info->format;
2254                 surface->plane_size =
2255                                 srf_update->plane_info->plane_size;
2256                 surface->rotation =
2257                                 srf_update->plane_info->rotation;
2258                 surface->horizontal_mirror =
2259                                 srf_update->plane_info->horizontal_mirror;
2260                 surface->stereo_format =
2261                                 srf_update->plane_info->stereo_format;
2262                 surface->tiling_info =
2263                                 srf_update->plane_info->tiling_info;
2264                 surface->visible =
2265                                 srf_update->plane_info->visible;
2266                 surface->per_pixel_alpha =
2267                                 srf_update->plane_info->per_pixel_alpha;
2268                 surface->global_alpha =
2269                                 srf_update->plane_info->global_alpha;
2270                 surface->global_alpha_value =
2271                                 srf_update->plane_info->global_alpha_value;
2272                 surface->dcc =
2273                                 srf_update->plane_info->dcc;
2274                 surface->layer_index =
2275                                 srf_update->plane_info->layer_index;
2276         }
2277
2278         if (srf_update->gamma &&
2279                         (surface->gamma_correction !=
2280                                         srf_update->gamma)) {
2281                 memcpy(&surface->gamma_correction->entries,
2282                         &srf_update->gamma->entries,
2283                         sizeof(struct dc_gamma_entries));
2284                 surface->gamma_correction->is_identity =
2285                         srf_update->gamma->is_identity;
2286                 surface->gamma_correction->num_entries =
2287                         srf_update->gamma->num_entries;
2288                 surface->gamma_correction->type =
2289                         srf_update->gamma->type;
2290         }
2291
2292         if (srf_update->in_transfer_func &&
2293                         (surface->in_transfer_func !=
2294                                 srf_update->in_transfer_func)) {
2295                 surface->in_transfer_func->sdr_ref_white_level =
2296                         srf_update->in_transfer_func->sdr_ref_white_level;
2297                 surface->in_transfer_func->tf =
2298                         srf_update->in_transfer_func->tf;
2299                 surface->in_transfer_func->type =
2300                         srf_update->in_transfer_func->type;
2301                 memcpy(&surface->in_transfer_func->tf_pts,
2302                         &srf_update->in_transfer_func->tf_pts,
2303                         sizeof(struct dc_transfer_func_distributed_points));
2304         }
2305
2306         if (srf_update->func_shaper &&
2307                         (surface->in_shaper_func !=
2308                         srf_update->func_shaper))
2309                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2310                 sizeof(*surface->in_shaper_func));
2311
2312         if (srf_update->lut3d_func &&
2313                         (surface->lut3d_func !=
2314                         srf_update->lut3d_func))
2315                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2316                 sizeof(*surface->lut3d_func));
2317
2318         if (srf_update->hdr_mult.value)
2319                 surface->hdr_mult =
2320                                 srf_update->hdr_mult;
2321
2322         if (srf_update->blend_tf &&
2323                         (surface->blend_tf !=
2324                         srf_update->blend_tf))
2325                 memcpy(surface->blend_tf, srf_update->blend_tf,
2326                 sizeof(*surface->blend_tf));
2327
2328         if (srf_update->input_csc_color_matrix)
2329                 surface->input_csc_color_matrix =
2330                         *srf_update->input_csc_color_matrix;
2331
2332         if (srf_update->coeff_reduction_factor)
2333                 surface->coeff_reduction_factor =
2334                         *srf_update->coeff_reduction_factor;
2335
2336         if (srf_update->gamut_remap_matrix)
2337                 surface->gamut_remap_matrix =
2338                         *srf_update->gamut_remap_matrix;
2339 }
2340
2341 static void copy_stream_update_to_stream(struct dc *dc,
2342                                          struct dc_state *context,
2343                                          struct dc_stream_state *stream,
2344                                          struct dc_stream_update *update)
2345 {
2346         struct dc_context *dc_ctx = dc->ctx;
2347
2348         if (update == NULL || stream == NULL)
2349                 return;
2350
2351         if (update->src.height && update->src.width)
2352                 stream->src = update->src;
2353
2354         if (update->dst.height && update->dst.width)
2355                 stream->dst = update->dst;
2356
2357         if (update->out_transfer_func &&
2358             stream->out_transfer_func != update->out_transfer_func) {
2359                 stream->out_transfer_func->sdr_ref_white_level =
2360                         update->out_transfer_func->sdr_ref_white_level;
2361                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2362                 stream->out_transfer_func->type =
2363                         update->out_transfer_func->type;
2364                 memcpy(&stream->out_transfer_func->tf_pts,
2365                        &update->out_transfer_func->tf_pts,
2366                        sizeof(struct dc_transfer_func_distributed_points));
2367         }
2368
2369         if (update->hdr_static_metadata)
2370                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2371
2372         if (update->abm_level)
2373                 stream->abm_level = *update->abm_level;
2374
2375         if (update->periodic_interrupt0)
2376                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2377
2378         if (update->periodic_interrupt1)
2379                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2380
2381         if (update->gamut_remap)
2382                 stream->gamut_remap_matrix = *update->gamut_remap;
2383
2384         /* Note: this being updated after mode set is currently not a use case
2385          * however if it arises OCSC would need to be reprogrammed at the
2386          * minimum
2387          */
2388         if (update->output_color_space)
2389                 stream->output_color_space = *update->output_color_space;
2390
2391         if (update->output_csc_transform)
2392                 stream->csc_color_matrix = *update->output_csc_transform;
2393
2394         if (update->vrr_infopacket)
2395                 stream->vrr_infopacket = *update->vrr_infopacket;
2396
2397         if (update->dpms_off)
2398                 stream->dpms_off = *update->dpms_off;
2399
2400         if (update->vsc_infopacket)
2401                 stream->vsc_infopacket = *update->vsc_infopacket;
2402
2403         if (update->vsp_infopacket)
2404                 stream->vsp_infopacket = *update->vsp_infopacket;
2405
2406         if (update->dither_option)
2407                 stream->dither_option = *update->dither_option;
2408
2409         if (update->pending_test_pattern)
2410                 stream->test_pattern = *update->pending_test_pattern;
2411         /* update current stream with writeback info */
2412         if (update->wb_update) {
2413                 int i;
2414
2415                 stream->num_wb_info = update->wb_update->num_wb_info;
2416                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2417                 for (i = 0; i < stream->num_wb_info; i++)
2418                         stream->writeback_info[i] =
2419                                 update->wb_update->writeback_info[i];
2420         }
2421         if (update->dsc_config) {
2422                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2423                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2424                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2425                                        update->dsc_config->num_slices_v != 0);
2426
2427                 /* Use temporarry context for validating new DSC config */
2428                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2429
2430                 if (dsc_validate_context) {
2431                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2432
2433                         stream->timing.dsc_cfg = *update->dsc_config;
2434                         stream->timing.flags.DSC = enable_dsc;
2435                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2436                                 stream->timing.dsc_cfg = old_dsc_cfg;
2437                                 stream->timing.flags.DSC = old_dsc_enabled;
2438                                 update->dsc_config = NULL;
2439                         }
2440
2441                         dc_release_state(dsc_validate_context);
2442                 } else {
2443                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2444                         update->dsc_config = NULL;
2445                 }
2446         }
2447 }
2448
2449 static void commit_planes_do_stream_update(struct dc *dc,
2450                 struct dc_stream_state *stream,
2451                 struct dc_stream_update *stream_update,
2452                 enum surface_update_type update_type,
2453                 struct dc_state *context)
2454 {
2455         int j;
2456
2457         // Stream updates
2458         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2459                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2460
2461                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2462
2463                         if (stream_update->periodic_interrupt0 &&
2464                                         dc->hwss.setup_periodic_interrupt)
2465                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2466
2467                         if (stream_update->periodic_interrupt1 &&
2468                                         dc->hwss.setup_periodic_interrupt)
2469                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2470
2471                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2472                                         stream_update->vrr_infopacket ||
2473                                         stream_update->vsc_infopacket ||
2474                                         stream_update->vsp_infopacket) {
2475                                 resource_build_info_frame(pipe_ctx);
2476                                 dc->hwss.update_info_frame(pipe_ctx);
2477                         }
2478
2479                         if (stream_update->hdr_static_metadata &&
2480                                         stream->use_dynamic_meta &&
2481                                         dc->hwss.set_dmdata_attributes &&
2482                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2483                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2484
2485                         if (stream_update->gamut_remap)
2486                                 dc_stream_set_gamut_remap(dc, stream);
2487
2488                         if (stream_update->output_csc_transform)
2489                                 dc_stream_program_csc_matrix(dc, stream);
2490
2491                         if (stream_update->dither_option) {
2492                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2493                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2494                                                                         &pipe_ctx->stream->bit_depth_params);
2495                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2496                                                 &stream->bit_depth_params,
2497                                                 &stream->clamping);
2498                                 while (odm_pipe) {
2499                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2500                                                         &stream->bit_depth_params,
2501                                                         &stream->clamping);
2502                                         odm_pipe = odm_pipe->next_odm_pipe;
2503                                 }
2504                         }
2505
2506
2507                         /* Full fe update*/
2508                         if (update_type == UPDATE_TYPE_FAST)
2509                                 continue;
2510
2511                         if (stream_update->dsc_config)
2512                                 dp_update_dsc_config(pipe_ctx);
2513
2514                         if (stream_update->pending_test_pattern) {
2515                                 dc_link_dp_set_test_pattern(stream->link,
2516                                         stream->test_pattern.type,
2517                                         stream->test_pattern.color_space,
2518                                         stream->test_pattern.p_link_settings,
2519                                         stream->test_pattern.p_custom_pattern,
2520                                         stream->test_pattern.cust_pattern_size);
2521                         }
2522
2523                         if (stream_update->dpms_off) {
2524                                 if (*stream_update->dpms_off) {
2525                                         core_link_disable_stream(pipe_ctx);
2526                                         /* for dpms, keep acquired resources*/
2527                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2528                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2529
2530                                         dc->optimized_required = true;
2531
2532                                 } else {
2533                                         if (get_seamless_boot_stream_count(context) == 0)
2534                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2535
2536                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2537                                 }
2538                         }
2539
2540                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2541                                 bool should_program_abm = true;
2542
2543                                 // if otg funcs defined check if blanked before programming
2544                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2545                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2546                                                 should_program_abm = false;
2547
2548                                 if (should_program_abm) {
2549                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2550                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2551                                         } else {
2552                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2553                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2554                                         }
2555                                 }
2556                         }
2557                 }
2558         }
2559 }
2560
2561 static void commit_planes_for_stream(struct dc *dc,
2562                 struct dc_surface_update *srf_updates,
2563                 int surface_count,
2564                 struct dc_stream_state *stream,
2565                 struct dc_stream_update *stream_update,
2566                 enum surface_update_type update_type,
2567                 struct dc_state *context)
2568 {
2569         int i, j;
2570         struct pipe_ctx *top_pipe_to_program = NULL;
2571
2572         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
2573                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2574                  * first flip. After first flip, optimization is required to lower
2575                  * bandwidth. Important to note that it is expected UEFI will
2576                  * only light up a single display on POST, therefore we only expect
2577                  * one stream with seamless boot flag set.
2578                  */
2579                 if (stream->apply_seamless_boot_optimization) {
2580                         stream->apply_seamless_boot_optimization = false;
2581
2582                         if (get_seamless_boot_stream_count(context) == 0)
2583                                 dc->optimized_required = true;
2584                 }
2585         }
2586
2587         if (update_type == UPDATE_TYPE_FULL) {
2588 #if defined(CONFIG_DRM_AMD_DC_DCN)
2589                 dc_allow_idle_optimizations(dc, false);
2590
2591 #endif
2592                 if (get_seamless_boot_stream_count(context) == 0)
2593                         dc->hwss.prepare_bandwidth(dc, context);
2594
2595                 context_clock_trace(dc, context);
2596         }
2597
2598         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2599                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2600
2601                 if (!pipe_ctx->top_pipe &&
2602                         !pipe_ctx->prev_odm_pipe &&
2603                         pipe_ctx->stream &&
2604                         pipe_ctx->stream == stream) {
2605                         top_pipe_to_program = pipe_ctx;
2606                 }
2607         }
2608
2609 #ifdef CONFIG_DRM_AMD_DC_DCN
2610         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
2611                 struct pipe_ctx *mpcc_pipe;
2612                 struct pipe_ctx *odm_pipe;
2613
2614                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
2615                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2616                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
2617         }
2618 #endif
2619
2620         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2621                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2622                         if (should_use_dmub_lock(stream->link)) {
2623                                 union dmub_hw_lock_flags hw_locks = { 0 };
2624                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2625
2626                                 hw_locks.bits.lock_dig = 1;
2627                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2628
2629                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2630                                                         true,
2631                                                         &hw_locks,
2632                                                         &inst_flags);
2633                         } else
2634                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2635                                                 top_pipe_to_program->stream_res.tg);
2636                 }
2637
2638         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2639                 dc->hwss.interdependent_update_lock(dc, context, true);
2640         else
2641                 /* Lock the top pipe while updating plane addrs, since freesync requires
2642                  *  plane addr update event triggers to be synchronized.
2643                  *  top_pipe_to_program is expected to never be NULL
2644                  */
2645                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2646
2647         // Stream updates
2648         if (stream_update)
2649                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2650
2651         if (surface_count == 0) {
2652                 /*
2653                  * In case of turning off screen, no need to program front end a second time.
2654                  * just return after program blank.
2655                  */
2656                 if (dc->hwss.apply_ctx_for_surface)
2657                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2658                 if (dc->hwss.program_front_end_for_ctx)
2659                         dc->hwss.program_front_end_for_ctx(dc, context);
2660
2661                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2662                         dc->hwss.interdependent_update_lock(dc, context, false);
2663                 else
2664                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2665                 dc->hwss.post_unlock_program_front_end(dc, context);
2666                 return;
2667         }
2668
2669         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2670                 for (i = 0; i < surface_count; i++) {
2671                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2672                         /*set logical flag for lock/unlock use*/
2673                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2674                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2675                                 if (!pipe_ctx->plane_state)
2676                                         continue;
2677                                 if (pipe_ctx->plane_state != plane_state)
2678                                         continue;
2679                                 plane_state->triplebuffer_flips = false;
2680                                 if (update_type == UPDATE_TYPE_FAST &&
2681                                         dc->hwss.program_triplebuffer != NULL &&
2682                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2683                                                 /*triple buffer for VUpdate  only*/
2684                                                 plane_state->triplebuffer_flips = true;
2685                                 }
2686                         }
2687                         if (update_type == UPDATE_TYPE_FULL) {
2688                                 /* force vsync flip when reconfiguring pipes to prevent underflow */
2689                                 plane_state->flip_immediate = false;
2690                         }
2691                 }
2692         }
2693
2694         // Update Type FULL, Surface updates
2695         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2696                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2697
2698                 if (!pipe_ctx->top_pipe &&
2699                         !pipe_ctx->prev_odm_pipe &&
2700                         pipe_ctx->stream &&
2701                         pipe_ctx->stream == stream) {
2702                         struct dc_stream_status *stream_status = NULL;
2703
2704                         if (!pipe_ctx->plane_state)
2705                                 continue;
2706
2707                         /* Full fe update*/
2708                         if (update_type == UPDATE_TYPE_FAST)
2709                                 continue;
2710
2711                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2712
2713                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2714                                 /*turn off triple buffer for full update*/
2715                                 dc->hwss.program_triplebuffer(
2716                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2717                         }
2718                         stream_status =
2719                                 stream_get_status(context, pipe_ctx->stream);
2720
2721                         if (dc->hwss.apply_ctx_for_surface)
2722                                 dc->hwss.apply_ctx_for_surface(
2723                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2724                 }
2725         }
2726         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2727                 dc->hwss.program_front_end_for_ctx(dc, context);
2728 #ifdef CONFIG_DRM_AMD_DC_DCN
2729                 if (dc->debug.validate_dml_output) {
2730                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2731                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2732                                 if (cur_pipe.stream == NULL)
2733                                         continue;
2734
2735                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2736                                                 cur_pipe.plane_res.hubp, dc->ctx,
2737                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2738                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2739                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2740                         }
2741                 }
2742 #endif
2743         }
2744
2745         // Update Type FAST, Surface updates
2746         if (update_type == UPDATE_TYPE_FAST) {
2747                 if (dc->hwss.set_flip_control_gsl)
2748                         for (i = 0; i < surface_count; i++) {
2749                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2750
2751                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2752                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2753
2754                                         if (pipe_ctx->stream != stream)
2755                                                 continue;
2756
2757                                         if (pipe_ctx->plane_state != plane_state)
2758                                                 continue;
2759
2760                                         // GSL has to be used for flip immediate
2761                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2762                                                         plane_state->flip_immediate);
2763                                 }
2764                         }
2765
2766                 /* Perform requested Updates */
2767                 for (i = 0; i < surface_count; i++) {
2768                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2769
2770                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2771                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2772
2773                                 if (pipe_ctx->stream != stream)
2774                                         continue;
2775
2776                                 if (pipe_ctx->plane_state != plane_state)
2777                                         continue;
2778                                 /*program triple buffer after lock based on flip type*/
2779                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2780                                         /*only enable triplebuffer for  fast_update*/
2781                                         dc->hwss.program_triplebuffer(
2782                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2783                                 }
2784                                 if (srf_updates[i].flip_addr)
2785                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2786                         }
2787                 }
2788
2789         }
2790
2791         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2792                 dc->hwss.interdependent_update_lock(dc, context, false);
2793         else
2794                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2795
2796         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2797                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2798                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2799                                         top_pipe_to_program->stream_res.tg,
2800                                         CRTC_STATE_VACTIVE);
2801                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2802                                         top_pipe_to_program->stream_res.tg,
2803                                         CRTC_STATE_VBLANK);
2804                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2805                                         top_pipe_to_program->stream_res.tg,
2806                                         CRTC_STATE_VACTIVE);
2807
2808                         if (stream && should_use_dmub_lock(stream->link)) {
2809                                 union dmub_hw_lock_flags hw_locks = { 0 };
2810                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2811
2812                                 hw_locks.bits.lock_dig = 1;
2813                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2814
2815                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2816                                                         false,
2817                                                         &hw_locks,
2818                                                         &inst_flags);
2819                         } else
2820                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2821                                         top_pipe_to_program->stream_res.tg);
2822                 }
2823
2824         if (update_type != UPDATE_TYPE_FAST)
2825                 dc->hwss.post_unlock_program_front_end(dc, context);
2826
2827         // Fire manual trigger only when bottom plane is flipped
2828         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2829                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2830
2831                 if (!pipe_ctx->plane_state)
2832                         continue;
2833
2834                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2835                                 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2836                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
2837                                 pipe_ctx->plane_state->skip_manual_trigger)
2838                         continue;
2839
2840                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2841                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2842         }
2843 }
2844
2845 void dc_commit_updates_for_stream(struct dc *dc,
2846                 struct dc_surface_update *srf_updates,
2847                 int surface_count,
2848                 struct dc_stream_state *stream,
2849                 struct dc_stream_update *stream_update,
2850                 struct dc_state *state)
2851 {
2852         const struct dc_stream_status *stream_status;
2853         enum surface_update_type update_type;
2854         struct dc_state *context;
2855         struct dc_context *dc_ctx = dc->ctx;
2856         int i, j;
2857
2858         stream_status = dc_stream_get_status(stream);
2859         context = dc->current_state;
2860
2861         update_type = dc_check_update_surfaces_for_stream(
2862                                 dc, srf_updates, surface_count, stream_update, stream_status);
2863
2864         if (update_type >= update_surface_trace_level)
2865                 update_surface_trace(dc, srf_updates, surface_count);
2866
2867
2868         if (update_type >= UPDATE_TYPE_FULL) {
2869
2870                 /* initialize scratch memory for building context */
2871                 context = dc_create_state(dc);
2872                 if (context == NULL) {
2873                         DC_ERROR("Failed to allocate new validate context!\n");
2874                         return;
2875                 }
2876
2877                 dc_resource_state_copy_construct(state, context);
2878
2879                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2880                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2881                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2882
2883                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2884                                 new_pipe->plane_state->force_full_update = true;
2885                 }
2886         }
2887
2888
2889         for (i = 0; i < surface_count; i++) {
2890                 struct dc_plane_state *surface = srf_updates[i].surface;
2891
2892                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2893
2894                 if (update_type >= UPDATE_TYPE_MED) {
2895                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2896                                 struct pipe_ctx *pipe_ctx =
2897                                         &context->res_ctx.pipe_ctx[j];
2898
2899                                 if (pipe_ctx->plane_state != surface)
2900                                         continue;
2901
2902                                 resource_build_scaling_params(pipe_ctx);
2903                         }
2904                 }
2905         }
2906
2907         copy_stream_update_to_stream(dc, context, stream, stream_update);
2908
2909         if (update_type >= UPDATE_TYPE_FULL) {
2910                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2911                         DC_ERROR("Mode validation failed for stream update!\n");
2912                         dc_release_state(context);
2913                         return;
2914                 }
2915         }
2916
2917         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
2918
2919         commit_planes_for_stream(
2920                                 dc,
2921                                 srf_updates,
2922                                 surface_count,
2923                                 stream,
2924                                 stream_update,
2925                                 update_type,
2926                                 context);
2927         /*update current_State*/
2928         if (dc->current_state != context) {
2929
2930                 struct dc_state *old = dc->current_state;
2931
2932                 dc->current_state = context;
2933                 dc_release_state(old);
2934
2935                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2936                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2937
2938                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2939                                 pipe_ctx->plane_state->force_full_update = false;
2940                 }
2941         }
2942         /*let's use current_state to update watermark etc*/
2943         if (update_type >= UPDATE_TYPE_FULL) {
2944                 dc_post_update_surfaces_to_stream(dc);
2945
2946                 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
2947                         TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2948                 else
2949                         TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2950         }
2951
2952         return;
2953
2954 }
2955
2956 uint8_t dc_get_current_stream_count(struct dc *dc)
2957 {
2958         return dc->current_state->stream_count;
2959 }
2960
2961 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2962 {
2963         if (i < dc->current_state->stream_count)
2964                 return dc->current_state->streams[i];
2965         return NULL;
2966 }
2967
2968 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
2969 {
2970         uint8_t i;
2971         struct dc_context *ctx = link->ctx;
2972
2973         for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
2974                 if (ctx->dc->current_state->streams[i]->link == link)
2975                         return ctx->dc->current_state->streams[i];
2976         }
2977
2978         return NULL;
2979 }
2980
2981 enum dc_irq_source dc_interrupt_to_irq_source(
2982                 struct dc *dc,
2983                 uint32_t src_id,
2984                 uint32_t ext_id)
2985 {
2986         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2987 }
2988
2989 /*
2990  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2991  */
2992 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2993 {
2994
2995         if (dc == NULL)
2996                 return false;
2997
2998         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2999 }
3000
3001 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
3002 {
3003         dal_irq_service_ack(dc->res_pool->irqs, src);
3004 }
3005
3006 void dc_power_down_on_boot(struct dc *dc)
3007 {
3008         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
3009                         dc->hwss.power_down_on_boot)
3010                 dc->hwss.power_down_on_boot(dc);
3011 }
3012
3013 void dc_set_power_state(
3014         struct dc *dc,
3015         enum dc_acpi_cm_power_state power_state)
3016 {
3017         struct kref refcount;
3018         struct display_mode_lib *dml;
3019
3020         if (!dc->current_state)
3021                 return;
3022
3023         switch (power_state) {
3024         case DC_ACPI_CM_POWER_STATE_D0:
3025                 dc_resource_state_construct(dc, dc->current_state);
3026
3027                 if (dc->ctx->dmub_srv)
3028                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
3029
3030                 dc->hwss.init_hw(dc);
3031
3032                 if (dc->hwss.init_sys_ctx != NULL &&
3033                         dc->vm_pa_config.valid) {
3034                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
3035                 }
3036
3037                 break;
3038         default:
3039                 ASSERT(dc->current_state->stream_count == 0);
3040                 /* Zero out the current context so that on resume we start with
3041                  * clean state, and dc hw programming optimizations will not
3042                  * cause any trouble.
3043                  */
3044                 dml = kzalloc(sizeof(struct display_mode_lib),
3045                                 GFP_KERNEL);
3046
3047                 ASSERT(dml);
3048                 if (!dml)
3049                         return;
3050
3051                 /* Preserve refcount */
3052                 refcount = dc->current_state->refcount;
3053                 /* Preserve display mode lib */
3054                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
3055
3056                 dc_resource_state_destruct(dc->current_state);
3057                 memset(dc->current_state, 0,
3058                                 sizeof(*dc->current_state));
3059
3060                 dc->current_state->refcount = refcount;
3061                 dc->current_state->bw_ctx.dml = *dml;
3062
3063                 kfree(dml);
3064
3065                 break;
3066         }
3067 }
3068
3069 void dc_resume(struct dc *dc)
3070 {
3071         uint32_t i;
3072
3073         for (i = 0; i < dc->link_count; i++)
3074                 core_link_resume(dc->links[i]);
3075 }
3076
3077 bool dc_is_dmcu_initialized(struct dc *dc)
3078 {
3079         struct dmcu *dmcu = dc->res_pool->dmcu;
3080
3081         if (dmcu)
3082                 return dmcu->funcs->is_dmcu_initialized(dmcu);
3083         return false;
3084 }
3085
3086 bool dc_submit_i2c(
3087                 struct dc *dc,
3088                 uint32_t link_index,
3089                 struct i2c_command *cmd)
3090 {
3091
3092         struct dc_link *link = dc->links[link_index];
3093         struct ddc_service *ddc = link->ddc;
3094         return dce_i2c_submit_command(
3095                 dc->res_pool,
3096                 ddc->ddc_pin,
3097                 cmd);
3098 }
3099
3100 bool dc_submit_i2c_oem(
3101                 struct dc *dc,
3102                 struct i2c_command *cmd)
3103 {
3104         struct ddc_service *ddc = dc->res_pool->oem_device;
3105         return dce_i2c_submit_command(
3106                 dc->res_pool,
3107                 ddc->ddc_pin,
3108                 cmd);
3109 }
3110
3111 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
3112 {
3113         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
3114                 BREAK_TO_DEBUGGER();
3115                 return false;
3116         }
3117
3118         dc_sink_retain(sink);
3119
3120         dc_link->remote_sinks[dc_link->sink_count] = sink;
3121         dc_link->sink_count++;
3122
3123         return true;
3124 }
3125
3126 /*
3127  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
3128  *
3129  * EDID length is in bytes
3130  */
3131 struct dc_sink *dc_link_add_remote_sink(
3132                 struct dc_link *link,
3133                 const uint8_t *edid,
3134                 int len,
3135                 struct dc_sink_init_data *init_data)
3136 {
3137         struct dc_sink *dc_sink;
3138         enum dc_edid_status edid_status;
3139
3140         if (len > DC_MAX_EDID_BUFFER_SIZE) {
3141                 dm_error("Max EDID buffer size breached!\n");
3142                 return NULL;
3143         }
3144
3145         if (!init_data) {
3146                 BREAK_TO_DEBUGGER();
3147                 return NULL;
3148         }
3149
3150         if (!init_data->link) {
3151                 BREAK_TO_DEBUGGER();
3152                 return NULL;
3153         }
3154
3155         dc_sink = dc_sink_create(init_data);
3156
3157         if (!dc_sink)
3158                 return NULL;
3159
3160         memmove(dc_sink->dc_edid.raw_edid, edid, len);
3161         dc_sink->dc_edid.length = len;
3162
3163         if (!link_add_remote_sink_helper(
3164                         link,
3165                         dc_sink))
3166                 goto fail_add_sink;
3167
3168         edid_status = dm_helpers_parse_edid_caps(
3169                         link->ctx,
3170                         &dc_sink->dc_edid,
3171                         &dc_sink->edid_caps);
3172
3173         /*
3174          * Treat device as no EDID device if EDID
3175          * parsing fails
3176          */
3177         if (edid_status != EDID_OK) {
3178                 dc_sink->dc_edid.length = 0;
3179                 dm_error("Bad EDID, status%d!\n", edid_status);
3180         }
3181
3182         return dc_sink;
3183
3184 fail_add_sink:
3185         dc_sink_release(dc_sink);
3186         return NULL;
3187 }
3188
3189 /*
3190  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
3191  *
3192  * Note that this just removes the struct dc_sink - it doesn't
3193  * program hardware or alter other members of dc_link
3194  */
3195 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
3196 {
3197         int i;
3198
3199         if (!link->sink_count) {
3200                 BREAK_TO_DEBUGGER();
3201                 return;
3202         }
3203
3204         for (i = 0; i < link->sink_count; i++) {
3205                 if (link->remote_sinks[i] == sink) {
3206                         dc_sink_release(sink);
3207                         link->remote_sinks[i] = NULL;
3208
3209                         /* shrink array to remove empty place */
3210                         while (i < link->sink_count - 1) {
3211                                 link->remote_sinks[i] = link->remote_sinks[i+1];
3212                                 i++;
3213                         }
3214                         link->remote_sinks[i] = NULL;
3215                         link->sink_count--;
3216                         return;
3217                 }
3218         }
3219 }
3220
3221 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3222 {
3223         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3224         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3225         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3226         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3227         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3228         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3229         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3230         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3231         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3232 }
3233 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3234 {
3235         if (dc->hwss.set_clock)
3236                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3237         return DC_ERROR_UNEXPECTED;
3238 }
3239 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3240 {
3241         if (dc->hwss.get_clock)
3242                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3243 }
3244
3245 /* enable/disable eDP PSR without specify stream for eDP */
3246 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3247 {
3248         int i;
3249
3250         for (i = 0; i < dc->current_state->stream_count ; i++) {
3251                 struct dc_link *link;
3252                 struct dc_stream_state *stream = dc->current_state->streams[i];
3253
3254                 link = stream->link;
3255                 if (!link)
3256                         continue;
3257
3258                 if (link->psr_settings.psr_feature_enabled) {
3259                         if (enable && !link->psr_settings.psr_allow_active)
3260                                 return dc_link_set_psr_allow_active(link, true, false, false);
3261                         else if (!enable && link->psr_settings.psr_allow_active)
3262                                 return dc_link_set_psr_allow_active(link, false, true, false);
3263                 }
3264         }
3265
3266         return true;
3267 }
3268
3269 #if defined(CONFIG_DRM_AMD_DC_DCN)
3270
3271 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3272 {
3273         if (dc->debug.disable_idle_power_optimizations)
3274                 return;
3275
3276         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
3277                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
3278                         return;
3279
3280         if (allow == dc->idle_optimizations_allowed)
3281                 return;
3282
3283         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3284                 dc->idle_optimizations_allowed = allow;
3285 }
3286
3287 /*
3288  * blank all streams, and set min and max memory clock to
3289  * lowest and highest DPM level, respectively
3290  */
3291 void dc_unlock_memory_clock_frequency(struct dc *dc)
3292 {
3293         unsigned int i;
3294
3295         for (i = 0; i < MAX_PIPES; i++)
3296                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3297                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3298
3299         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3300         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3301 }
3302
3303 /*
3304  * set min memory clock to the min required for current mode,
3305  * max to maxDPM, and unblank streams
3306  */
3307 void dc_lock_memory_clock_frequency(struct dc *dc)
3308 {
3309         unsigned int i;
3310
3311         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3312         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3313         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3314
3315         for (i = 0; i < MAX_PIPES; i++)
3316                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3317                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3318 }
3319
3320 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
3321                 struct dc_cursor_attributes *cursor_attr)
3322 {
3323         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
3324                 return true;
3325         return false;
3326 }
3327
3328 /* cleanup on driver unload */
3329 void dc_hardware_release(struct dc *dc)
3330 {
3331         if (dc->hwss.hardware_release)
3332                 dc->hwss.hardware_release(dc);
3333 }
3334 #endif
3335
3336 /**
3337  * dc_enable_dmub_notifications - Returns whether dmub notification can be enabled
3338  * @dc: dc structure
3339  *
3340  * Returns: True to enable dmub notifications, False otherwise
3341  */
3342 bool dc_enable_dmub_notifications(struct dc *dc)
3343 {
3344         /* dmub aux needs dmub notifications to be enabled */
3345         return dc->debug.enable_dmub_aux_for_legacy_ddc;
3346 }
3347
3348 /**
3349  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
3350  *                                      Sets port index appropriately for legacy DDC
3351  * @dc: dc structure
3352  * @link_index: link index
3353  * @payload: aux payload
3354  *
3355  * Returns: True if successful, False if failure
3356  */
3357 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
3358                                 uint32_t link_index,
3359                                 struct aux_payload *payload)
3360 {
3361         uint8_t action;
3362         union dmub_rb_cmd cmd = {0};
3363         struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv;
3364
3365         ASSERT(payload->length <= 16);
3366
3367         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
3368         cmd.dp_aux_access.header.payload_bytes = 0;
3369         cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
3370         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
3371         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
3372         cmd.dp_aux_access.aux_control.timeout = 0;
3373         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
3374         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
3375         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
3376
3377         /* set aux action */
3378         if (payload->i2c_over_aux) {
3379                 if (payload->write) {
3380                         if (payload->mot)
3381                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
3382                         else
3383                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
3384                 } else {
3385                         if (payload->mot)
3386                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
3387                         else
3388                                 action = DP_AUX_REQ_ACTION_I2C_READ;
3389                         }
3390         } else {
3391                 if (payload->write)
3392                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
3393                 else
3394                         action = DP_AUX_REQ_ACTION_DPCD_READ;
3395         }
3396
3397         cmd.dp_aux_access.aux_control.dpaux.action = action;
3398
3399         if (payload->length && payload->write) {
3400                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
3401                         payload->data,
3402                         payload->length
3403                         );
3404         }
3405
3406         dc_dmub_srv_cmd_queue(dmub_srv, &cmd);
3407         dc_dmub_srv_cmd_execute(dmub_srv);
3408         dc_dmub_srv_wait_idle(dmub_srv);
3409
3410         return true;
3411 }
3412
3413 /**
3414  * dc_disable_accelerated_mode - disable accelerated mode
3415  * @dc: dc structure
3416  */
3417 void dc_disable_accelerated_mode(struct dc *dc)
3418 {
3419         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
3420 }