drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28
  29 // For dce12_get_dp_ref_freq_khz
  30 #include "dce100/dce_clk_mgr.h"
  31
  32 // For dcn20_update_clocks_update_dpp_dto
  33 #include "dcn20/dcn20_clk_mgr.h"
  34
  35
  36
  37 #include "vg_clk_mgr.h"
  38 #include "reg_helper.h"
  39 #include "core_types.h"
  40 #include "dm_helpers.h"
  41
  42 #include "atomfirmware.h"
  43 #include "vangogh_ip_offset.h"
  44 #include "clk/clk_11_5_0_offset.h"
  45 #include "clk/clk_11_5_0_sh_mask.h"
  46
  47 /* Constants */
  48
  49 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
  50
  51 /* Macros */
  52
  53 #define REG(reg_name) \
  54         (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  55
  56 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
  57 int vg_get_active_display_cnt_wa(
  58                 struct dc *dc,
  59                 struct dc_state *context)
  60 {
  61         int i, display_count;
  62         bool tmds_present = false;
  63
  64         display_count = 0;
  65         for (i = 0; i < context->stream_count; i++) {
  66                 const struct dc_stream_state *stream = context->streams[i];
  67
  68                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  69                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  70                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  71                         tmds_present = true;
  72         }
  73
  74         for (i = 0; i < dc->link_count; i++) {
  75                 const struct dc_link *link = dc->links[i];
  76
  77                 /*
  78                  * Only notify active stream or virtual stream.
  79                  * Need to notify virtual stream to work around
  80                  * headless case. HPD does not fire when system is in
  81                  * S0i2.
  82                  */
  83                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  84                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
  85                                 link->link_enc->funcs->is_dig_enabled(link->link_enc))
  86                         display_count++;
  87         }
  88
  89         /* WA for hang on HDMI after display off back back on*/
  90         if (display_count == 0 && tmds_present)
  91                 display_count = 1;
  92
  93         return display_count;
  94 }
  95
  96 void vg_update_clocks(struct clk_mgr *clk_mgr_base,
  97                         struct dc_state *context,
  98                         bool safe_to_lower)
  99 {
 100         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 101         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 102         struct dc *dc = clk_mgr_base->ctx->dc;
 103         int display_count;
 104         bool update_dppclk = false;
 105         bool update_dispclk = false;
 106         bool dpp_clock_lowered = false;
 107
 108         if (dc->work_arounds.skip_clock_update)
 109                 return;
 110
 111         /*
 112          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 113          * also if safe to lower is false, we just go in the higher state
 114          */
 115         if (safe_to_lower) {
 116                 /* check that we're not already in lower */
 117                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 118
 119                         display_count = vg_get_active_display_cnt_wa(dc, context);
 120                         /* if we can go lower, go lower */
 121                         if (display_count == 0) {
 122                                 union display_idle_optimization_u idle_info = { 0 };
 123
 124                                 idle_info.idle_info.df_request_disabled = 1;
 125                                 idle_info.idle_info.phy_ref_clk_off = 1;
 126
 127                                 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 128                                 /* update power state */
 129                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 130                         }
 131                 }
 132         } else {
 133                 /* check that we're not already in D0 */
 134                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 135                         union display_idle_optimization_u idle_info = { 0 };
 136
 137                         dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 138                         /* update power state */
 139                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 140                 }
 141         }
 142
 143         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 144                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 145                 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 146         }
 147
 148         if (should_set_clock(safe_to_lower,
 149                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 150                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 151                 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 152         }
 153
 154         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 155         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 156                 if (new_clocks->dppclk_khz < 100000)
 157                         new_clocks->dppclk_khz = 100000;
 158         }
 159
 160         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
 161                 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
 162                         dpp_clock_lowered = true;
 163                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 164                 update_dppclk = true;
 165         }
 166
 167         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 168                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 169                 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 170
 171                 update_dispclk = true;
 172         }
 173
 174         if (dpp_clock_lowered) {
 175                 // increase per DPP DTO before lowering global dppclk
 176                 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 177                 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 178         } else {
 179                 // increase global DPPCLK before lowering per DPP DTO
 180                 if (update_dppclk || update_dispclk)
 181                         dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 182                 // always update dtos unless clock is lowered and not safe to lower
 183                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 184                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 185         }
 186 }
 187
 188
 189 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 190 {
 191         /* get FbMult value */
 192         struct fixed31_32 pll_req;
 193         unsigned int fbmult_frac_val = 0;
 194         unsigned int fbmult_int_val = 0;
 195
 196
 197         /*
 198          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 199          * to leverage the fix point operations available in driver
 200          */
 201
 202         REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 203         REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 204
 205         pll_req = dc_fixpt_from_int(fbmult_int_val);
 206
 207         /*
 208          * since fractional part is only 16 bit in register definition but is 32 bit
 209          * in our fix point definiton, need to shift left by 16 to obtain correct value
 210          */
 211         pll_req.value |= fbmult_frac_val << 16;
 212
 213         /* multiply by REFCLK period */
 214         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 215
 216         /* integer part is now VCO frequency in kHz */
 217         return dc_fixpt_floor(pll_req);
 218 }
 219
 220 static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
 221 {
 222         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 223
 224         internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
 225         internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
 226
 227         internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL);       //dcf deep sleep divider
 228         internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
 229
 230         internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
 231         internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
 232
 233         internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
 234         internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
 235
 236         internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
 237         internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
 238 }
 239
 240 /* This function collect raw clk register values */
 241 static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 242                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 243 {
 244         struct dcn301_clk_internal internal = {0};
 245         char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
 246         unsigned int chars_printed = 0;
 247         unsigned int remaining_buffer = log_info->bufSize;
 248
 249         vg_dump_clk_registers_internal(&internal, clk_mgr_base);
 250
 251         regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
 252         regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
 253         regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
 254         regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
 255         regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
 256         regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 257
 258         regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
 259         if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
 260                 regs_and_bypass->dppclk_bypass = 0;
 261         regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
 262         if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
 263                 regs_and_bypass->dcfclk_bypass = 0;
 264         regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
 265         if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
 266                 regs_and_bypass->dispclk_bypass = 0;
 267         regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
 268         if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
 269                 regs_and_bypass->dprefclk_bypass = 0;
 270
 271         if (log_info->enabled) {
 272                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
 273                 remaining_buffer -= chars_printed;
 274                 *log_info->sum_chars_printed += chars_printed;
 275                 log_info->pBuf += chars_printed;
 276
 277                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
 278                         regs_and_bypass->dcfclk,
 279                         regs_and_bypass->dcf_deep_sleep_divider,
 280                         regs_and_bypass->dcf_deep_sleep_allow,
 281                         bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
 282                 remaining_buffer -= chars_printed;
 283                 *log_info->sum_chars_printed += chars_printed;
 284                 log_info->pBuf += chars_printed;
 285
 286                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
 287                         regs_and_bypass->dprefclk,
 288                         bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
 289                 remaining_buffer -= chars_printed;
 290                 *log_info->sum_chars_printed += chars_printed;
 291                 log_info->pBuf += chars_printed;
 292
 293                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
 294                         regs_and_bypass->dispclk,
 295                         bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
 296                 remaining_buffer -= chars_printed;
 297                 *log_info->sum_chars_printed += chars_printed;
 298                 log_info->pBuf += chars_printed;
 299
 300                 //split
 301                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
 302                 remaining_buffer -= chars_printed;
 303                 *log_info->sum_chars_printed += chars_printed;
 304                 log_info->pBuf += chars_printed;
 305
 306                 // REGISTER VALUES
 307                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
 308                 remaining_buffer -= chars_printed;
 309                 *log_info->sum_chars_printed += chars_printed;
 310                 log_info->pBuf += chars_printed;
 311
 312                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
 313                                 internal.CLK1_CLK3_CURRENT_CNT);
 314                 remaining_buffer -= chars_printed;
 315                 *log_info->sum_chars_printed += chars_printed;
 316                 log_info->pBuf += chars_printed;
 317
 318                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
 319                                         internal.CLK1_CLK3_DS_CNTL);
 320                 remaining_buffer -= chars_printed;
 321                 *log_info->sum_chars_printed += chars_printed;
 322                 log_info->pBuf += chars_printed;
 323
 324                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
 325                                         internal.CLK1_CLK3_ALLOW_DS);
 326                 remaining_buffer -= chars_printed;
 327                 *log_info->sum_chars_printed += chars_printed;
 328                 log_info->pBuf += chars_printed;
 329
 330                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
 331                                         internal.CLK1_CLK2_CURRENT_CNT);
 332                 remaining_buffer -= chars_printed;
 333                 *log_info->sum_chars_printed += chars_printed;
 334                 log_info->pBuf += chars_printed;
 335
 336                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
 337                                         internal.CLK1_CLK0_CURRENT_CNT);
 338                 remaining_buffer -= chars_printed;
 339                 *log_info->sum_chars_printed += chars_printed;
 340                 log_info->pBuf += chars_printed;
 341
 342                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
 343                                         internal.CLK1_CLK1_CURRENT_CNT);
 344                 remaining_buffer -= chars_printed;
 345                 *log_info->sum_chars_printed += chars_printed;
 346                 log_info->pBuf += chars_printed;
 347
 348                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
 349                                         internal.CLK1_CLK3_BYPASS_CNTL);
 350                 remaining_buffer -= chars_printed;
 351                 *log_info->sum_chars_printed += chars_printed;
 352                 log_info->pBuf += chars_printed;
 353
 354                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
 355                                         internal.CLK1_CLK2_BYPASS_CNTL);
 356                 remaining_buffer -= chars_printed;
 357                 *log_info->sum_chars_printed += chars_printed;
 358                 log_info->pBuf += chars_printed;
 359
 360                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
 361                                         internal.CLK1_CLK0_BYPASS_CNTL);
 362                 remaining_buffer -= chars_printed;
 363                 *log_info->sum_chars_printed += chars_printed;
 364                 log_info->pBuf += chars_printed;
 365
 366                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
 367                                         internal.CLK1_CLK1_BYPASS_CNTL);
 368                 remaining_buffer -= chars_printed;
 369                 *log_info->sum_chars_printed += chars_printed;
 370                 log_info->pBuf += chars_printed;
 371         }
 372 }
 373
 374 /* This function produce translated logical clk state values*/
 375 void vg_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
 376 {
 377
 378         struct clk_state_registers_and_bypass sb = { 0 };
 379         struct clk_log_info log_info = { 0 };
 380
 381         vg_dump_clk_registers(&sb, clk_mgr_base, &log_info);
 382
 383         s->dprefclk_khz = sb.dprefclk * 1000;
 384 }
 385
 386 void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 387 {
 388         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 389
 390         dcn301_smu_enable_pme_wa(clk_mgr);
 391 }
 392
 393 void vg_init_clocks(struct clk_mgr *clk_mgr)
 394 {
 395         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 396         // Assumption is that boot state always supports pstate
 397         clk_mgr->clks.p_state_change_support = true;
 398         clk_mgr->clks.prev_p_state_change_support = true;
 399         clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 400 }
 401
 402 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
 403 {
 404         int i, num_valid_sets;
 405
 406         num_valid_sets = 0;
 407
 408         for (i = 0; i < WM_SET_COUNT; i++) {
 409                 /* skip empty entries, the smu array has no holes*/
 410                 if (!bw_params->wm_table.entries[i].valid)
 411                         continue;
 412
 413                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
 414                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
 415                 /* We will not select WM based on fclk, so leave it as unconstrained */
 416                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 417                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 418
 419                 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
 420                         if (i == 0)
 421                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
 422                         else {
 423                                 /* add 1 to make it non-overlapping with next lvl */
 424                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
 425                                                 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 426                         }
 427                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
 428                                         bw_params->clk_table.entries[i].dcfclk_mhz;
 429
 430                 } else {
 431                         /* unconstrained for memory retraining */
 432                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 433                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 434
 435                         /* Modify previous watermark range to cover up to max */
 436                         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 437                 }
 438                 num_valid_sets++;
 439         }
 440
 441         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 442
 443         /* modify the min and max to make sure we cover the whole range*/
 444         table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
 445         table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
 446         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
 447         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 448
 449         /* This is for writeback only, does not matter currently as no writeback support*/
 450         table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
 451         table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
 452         table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
 453         table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
 454         table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
 455 }
 456
 457
 458 void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 459 {
 460         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 461         struct watermarks *table = clk_mgr_base->smu_wm_set.wm_set;
 462
 463         if (!clk_mgr->smu_ver)
 464                 return;
 465
 466         if (!table || clk_mgr_base->smu_wm_set.mc_address.quad_part == 0)
 467                 return;
 468
 469         memset(table, 0, sizeof(*table));
 470
 471         vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
 472
 473         dcn301_smu_set_dram_addr_high(clk_mgr,
 474                         clk_mgr_base->smu_wm_set.mc_address.high_part);
 475         dcn301_smu_set_dram_addr_low(clk_mgr,
 476                         clk_mgr_base->smu_wm_set.mc_address.low_part);
 477         dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 478 }
 479
 480 static bool vg_are_clock_states_equal(struct dc_clocks *a,
 481                 struct dc_clocks *b)
 482 {
 483         if (a->dispclk_khz != b->dispclk_khz)
 484                 return false;
 485         else if (a->dppclk_khz != b->dppclk_khz)
 486                 return false;
 487         else if (a->dcfclk_khz != b->dcfclk_khz)
 488                 return false;
 489         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 490                 return false;
 491
 492         return true;
 493 }
 494
 495
 496 static struct clk_mgr_funcs vg_funcs = {
 497         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 498         .update_clocks = vg_update_clocks,
 499         .init_clocks = vg_init_clocks,
 500         .enable_pme_wa = vg_enable_pme_wa,
 501         .are_clock_states_equal = vg_are_clock_states_equal,
 502         .notify_wm_ranges = vg_notify_wm_ranges
 503 };
 504
 505 static struct clk_bw_params vg_bw_params = {
 506         .vram_type = Ddr4MemType,
 507         .num_channels = 1,
 508         .clk_table = {
 509                 .entries = {
 510                         {
 511                                 .voltage = 0,
 512                                 .dcfclk_mhz = 400,
 513                                 .fclk_mhz = 400,
 514                                 .memclk_mhz = 800,
 515                                 .socclk_mhz = 0,
 516                         },
 517                         {
 518                                 .voltage = 0,
 519                                 .dcfclk_mhz = 483,
 520                                 .fclk_mhz = 800,
 521                                 .memclk_mhz = 1600,
 522                                 .socclk_mhz = 0,
 523                         },
 524                         {
 525                                 .voltage = 0,
 526                                 .dcfclk_mhz = 602,
 527                                 .fclk_mhz = 1067,
 528                                 .memclk_mhz = 1067,
 529                                 .socclk_mhz = 0,
 530                         },
 531                         {
 532                                 .voltage = 0,
 533                                 .dcfclk_mhz = 738,
 534                                 .fclk_mhz = 1333,
 535                                 .memclk_mhz = 1600,
 536                                 .socclk_mhz = 0,
 537                         },
 538                 },
 539
 540                 .num_entries = 4,
 541         },
 542
 543 };
 544
 545 static struct wm_table ddr4_wm_table = {
 546         .entries = {
 547                 {
 548                         .wm_inst = WM_A,
 549                         .wm_type = WM_TYPE_PSTATE_CHG,
 550                         .pstate_latency_us = 11.72,
 551                         .sr_exit_time_us = 6.09,
 552                         .sr_enter_plus_exit_time_us = 7.14,
 553                         .valid = true,
 554                 },
 555                 {
 556                         .wm_inst = WM_B,
 557                         .wm_type = WM_TYPE_PSTATE_CHG,
 558                         .pstate_latency_us = 11.72,
 559                         .sr_exit_time_us = 10.12,
 560                         .sr_enter_plus_exit_time_us = 11.48,
 561                         .valid = true,
 562                 },
 563                 {
 564                         .wm_inst = WM_C,
 565                         .wm_type = WM_TYPE_PSTATE_CHG,
 566                         .pstate_latency_us = 11.72,
 567                         .sr_exit_time_us = 10.12,
 568                         .sr_enter_plus_exit_time_us = 11.48,
 569                         .valid = true,
 570                 },
 571                 {
 572                         .wm_inst = WM_D,
 573                         .wm_type = WM_TYPE_PSTATE_CHG,
 574                         .pstate_latency_us = 11.72,
 575                         .sr_exit_time_us = 10.12,
 576                         .sr_enter_plus_exit_time_us = 11.48,
 577                         .valid = true,
 578                 },
 579         }
 580 };
 581
 582 static struct wm_table lpddr5_wm_table = {
 583         .entries = {
 584                 {
 585                         .wm_inst = WM_A,
 586                         .wm_type = WM_TYPE_PSTATE_CHG,
 587                         .pstate_latency_us = 11.65333,
 588                         .sr_exit_time_us = 5.32,
 589                         .sr_enter_plus_exit_time_us = 6.38,
 590                         .valid = true,
 591                 },
 592                 {
 593                         .wm_inst = WM_B,
 594                         .wm_type = WM_TYPE_PSTATE_CHG,
 595                         .pstate_latency_us = 11.65333,
 596                         .sr_exit_time_us = 9.82,
 597                         .sr_enter_plus_exit_time_us = 11.196,
 598                         .valid = true,
 599                 },
 600                 {
 601                         .wm_inst = WM_C,
 602                         .wm_type = WM_TYPE_PSTATE_CHG,
 603                         .pstate_latency_us = 11.65333,
 604                         .sr_exit_time_us = 9.89,
 605                         .sr_enter_plus_exit_time_us = 11.24,
 606                         .valid = true,
 607                 },
 608                 {
 609                         .wm_inst = WM_D,
 610                         .wm_type = WM_TYPE_PSTATE_CHG,
 611                         .pstate_latency_us = 11.65333,
 612                         .sr_exit_time_us = 9.748,
 613                         .sr_enter_plus_exit_time_us = 11.102,
 614                         .valid = true,
 615                 },
 616         }
 617 };
 618
 619
 620 static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
 621                 unsigned int voltage)
 622 {
 623         int i;
 624
 625         for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
 626                 if (clock_table->SocVoltage[i] == voltage)
 627                         return clock_table->DcfClocks[i];
 628         }
 629
 630         ASSERT(0);
 631         return 0;
 632 }
 633
 634 void vg_clk_mgr_helper_populate_bw_params(
 635                 struct clk_mgr_internal *clk_mgr,
 636                 struct integrated_info *bios_info,
 637                 const struct vg_dpm_clocks *clock_table)
 638 {
 639         int i, j;
 640         struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
 641
 642         j = -1;
 643
 644         ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
 645
 646         /* Find lowest DPM, FCLK is filled in reverse order*/
 647
 648         for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
 649                 if (clock_table->DfPstateTable[i].fclk != 0) {
 650                         j = i;
 651                         break;
 652                 }
 653         }
 654
 655         if (j == -1) {
 656                 /* clock table is all 0s, just use our own hardcode */
 657                 ASSERT(0);
 658                 return;
 659         }
 660
 661         bw_params->clk_table.num_entries = j + 1;
 662
 663         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 664                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
 665                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
 666                 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
 667                 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
 668         }
 669
 670         bw_params->vram_type = bios_info->memory_type;
 671         bw_params->num_channels = bios_info->ma_channel_number;
 672
 673         for (i = 0; i < WM_SET_COUNT; i++) {
 674                 bw_params->wm_table.entries[i].wm_inst = i;
 675
 676                 if (i >= bw_params->clk_table.num_entries) {
 677                         bw_params->wm_table.entries[i].valid = false;
 678                         continue;
 679                 }
 680
 681                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 682                 bw_params->wm_table.entries[i].valid = true;
 683         }
 684
 685         if (bw_params->vram_type == LpDdr4MemType) {
 686                 /*
 687                  * WM set D will be re-purposed for memory retraining
 688                  */
 689                 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
 690                 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
 691                 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
 692                 bw_params->wm_table.entries[WM_D].valid = true;
 693         }
 694
 695 }
 696
 697 /* Temporary Place holder until we can get them from fuse */
 698 static struct vg_dpm_clocks dummy_clocks = {
 699                 .DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
 700                 .SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
 701                 .SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
 702                 .DfPstateTable = {
 703                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 },
 704                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 },
 705                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 },
 706                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 }
 707                 }
 708 };
 709
 710 static struct watermarks dummy_wms = { 0 };
 711
 712 void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
 713                 struct smu_dpm_clks *smu_dpm_clks)
 714 {
 715         struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
 716
 717         if (!clk_mgr->smu_ver)
 718                 return;
 719
 720         if (!table || smu_dpm_clks->mc_address.quad_part == 0)
 721                 return;
 722
 723         memset(table, 0, sizeof(*table));
 724
 725         dcn301_smu_set_dram_addr_high(clk_mgr,
 726                         smu_dpm_clks->mc_address.high_part);
 727         dcn301_smu_set_dram_addr_low(clk_mgr,
 728                         smu_dpm_clks->mc_address.low_part);
 729         dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
 730 }
 731
 732 void vg_clk_mgr_construct(
 733                 struct dc_context *ctx,
 734                 struct clk_mgr_internal *clk_mgr,
 735                 struct pp_smu_funcs *pp_smu,
 736                 struct dccg *dccg)
 737 {
 738         struct smu_dpm_clks smu_dpm_clks = { 0 };
 739
 740         clk_mgr->base.ctx = ctx;
 741         clk_mgr->base.funcs = &vg_funcs;
 742
 743         clk_mgr->pp_smu = pp_smu;
 744
 745         clk_mgr->dccg = dccg;
 746         clk_mgr->dfs_bypass_disp_clk = 0;
 747
 748         clk_mgr->dprefclk_ss_percentage = 0;
 749         clk_mgr->dprefclk_ss_divider = 1000;
 750         clk_mgr->ss_on_dprefclk = false;
 751         clk_mgr->dfs_ref_freq_khz = 48000;
 752
 753         clk_mgr->base.smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
 754                                 clk_mgr->base.ctx,
 755                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 756                                 sizeof(struct watermarks),
 757                                 &clk_mgr->base.smu_wm_set.mc_address.quad_part);
 758
 759         if (clk_mgr->base.smu_wm_set.wm_set == 0) {
 760                 clk_mgr->base.smu_wm_set.wm_set = &dummy_wms;
 761                 clk_mgr->base.smu_wm_set.mc_address.quad_part = 0;
 762         }
 763         ASSERT(clk_mgr->base.smu_wm_set.wm_set);
 764
 765         smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
 766                                 clk_mgr->base.ctx,
 767                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 768                                 sizeof(struct vg_dpm_clocks),
 769                                 &smu_dpm_clks.mc_address.quad_part);
 770
 771         if (smu_dpm_clks.dpm_clks == NULL) {
 772                 smu_dpm_clks.dpm_clks = &dummy_clocks;
 773                 smu_dpm_clks.mc_address.quad_part = 0;
 774         }
 775
 776         ASSERT(smu_dpm_clks.dpm_clks);
 777
 778         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 779                 vg_funcs.update_clocks = dcn2_update_clocks_fpga;
 780                 clk_mgr->base.dentist_vco_freq_khz = 3600000;
 781         } else {
 782                 struct clk_log_info log_info = {0};
 783
 784                 clk_mgr->smu_ver = dcn301_smu_get_smu_version(clk_mgr);
 785
 786                 if (clk_mgr->smu_ver)
 787                         clk_mgr->smu_present = true;
 788
 789                 /* TODO: Check we get what we expect during bringup */
 790                 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 791
 792                 /* in case we don't get a value from the register, use default */
 793                 if (clk_mgr->base.dentist_vco_freq_khz == 0)
 794                         clk_mgr->base.dentist_vco_freq_khz = 3600000;
 795
 796                 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
 797                         vg_bw_params.wm_table = lpddr5_wm_table;
 798                 } else {
 799                         vg_bw_params.wm_table = ddr4_wm_table;
 800                 }
 801                 /* Saved clocks configured at boot for debug purposes */
 802                 vg_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
 803         }
 804
 805         clk_mgr->base.dprefclk_khz = 600000;
 806         dce_clock_read_ss_info(clk_mgr);
 807
 808         clk_mgr->base.bw_params = &vg_bw_params;
 809
 810         vg_get_dpm_table_from_smu(clk_mgr, &smu_dpm_clks);
 811         if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
 812                 vg_clk_mgr_helper_populate_bw_params(
 813                                 clk_mgr,
 814                                 ctx->dc_bios->integrated_info,
 815                                 smu_dpm_clks.dpm_clks);
 816         }
 817
 818         if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
 819                 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 820                                 smu_dpm_clks.dpm_clks);
 821 /*
 822         if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver) {
 823                  enable powerfeatures when displaycount goes to 0
 824                 dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
 825         }
 826 */
 827 }
 828
 829 void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
 830 {
 831         if (clk_mgr->base.smu_wm_set.wm_set && clk_mgr->base.smu_wm_set.mc_address.quad_part != 0)
 832                 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 833                                 clk_mgr->base.smu_wm_set.wm_set);
 834 }