drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28
  29 // For dce12_get_dp_ref_freq_khz
  30 #include "dce100/dce_clk_mgr.h"
  31
  32 // For dcn20_update_clocks_update_dpp_dto
  33 #include "dcn20/dcn20_clk_mgr.h"
  34
  35
  36
  37 #include "vg_clk_mgr.h"
  38 #include "reg_helper.h"
  39 #include "core_types.h"
  40 #include "dm_helpers.h"
  41
  42 #include "atomfirmware.h"
  43 #include "vangogh_ip_offset.h"
  44 #include "clk/clk_11_5_0_offset.h"
  45 #include "clk/clk_11_5_0_sh_mask.h"
  46
  47 /* Constants */
  48
  49 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
  50
  51 /* Macros */
  52
  53 #define REG(reg_name) \
  54         (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  55
  56 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
  57 int vg_get_active_display_cnt_wa(
  58                 struct dc *dc,
  59                 struct dc_state *context)
  60 {
  61         int i, display_count;
  62         bool tmds_present = false;
  63
  64         display_count = 0;
  65         for (i = 0; i < context->stream_count; i++) {
  66                 const struct dc_stream_state *stream = context->streams[i];
  67
  68                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  69                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  70                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  71                         tmds_present = true;
  72         }
  73
  74         for (i = 0; i < dc->link_count; i++) {
  75                 const struct dc_link *link = dc->links[i];
  76
  77                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  78                 if (link->link_enc->funcs->is_dig_enabled(link->link_enc))
  79                         display_count++;
  80         }
  81
  82         /* WA for hang on HDMI after display off back back on*/
  83         if (display_count == 0 && tmds_present)
  84                 display_count = 1;
  85
  86         return display_count;
  87 }
  88
  89 void vg_update_clocks(struct clk_mgr *clk_mgr_base,
  90                         struct dc_state *context,
  91                         bool safe_to_lower)
  92 {
  93         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
  94         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
  95         struct dc *dc = clk_mgr_base->ctx->dc;
  96         int display_count;
  97         bool update_dppclk = false;
  98         bool update_dispclk = false;
  99         bool dpp_clock_lowered = false;
 100
 101         if (dc->work_arounds.skip_clock_update)
 102                 return;
 103
 104         /*
 105          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 106          * also if safe to lower is false, we just go in the higher state
 107          */
 108         if (safe_to_lower) {
 109                 /* check that we're not already in lower */
 110                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 111
 112                         display_count = vg_get_active_display_cnt_wa(dc, context);
 113                         /* if we can go lower, go lower */
 114                         if (display_count == 0) {
 115                                 union display_idle_optimization_u idle_info = { 0 };
 116
 117                                 idle_info.idle_info.df_request_disabled = 1;
 118                                 idle_info.idle_info.phy_ref_clk_off = 1;
 119
 120                                 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 121                                 /* update power state */
 122                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 123                         }
 124                 }
 125         } else {
 126                 /* check that we're not already in D0 */
 127                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 128                         union display_idle_optimization_u idle_info = { 0 };
 129
 130                         dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 131                         /* update power state */
 132                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 133                 }
 134         }
 135
 136         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 137                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 138                 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 139         }
 140
 141         if (should_set_clock(safe_to_lower,
 142                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 143                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 144                 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 145         }
 146
 147         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 148         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
 149                 if (new_clocks->dppclk_khz < 100000)
 150                         new_clocks->dppclk_khz = 100000;
 151         }
 152
 153         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
 154                 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
 155                         dpp_clock_lowered = true;
 156                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 157                 update_dppclk = true;
 158         }
 159
 160         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 161                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 162                 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 163
 164                 update_dispclk = true;
 165         }
 166
 167         if (dpp_clock_lowered) {
 168                 // increase per DPP DTO before lowering global dppclk
 169                 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 170                 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 171         } else {
 172                 // increase global DPPCLK before lowering per DPP DTO
 173                 if (update_dppclk || update_dispclk)
 174                         dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 175                 // always update dtos unless clock is lowered and not safe to lower
 176                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 177                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 178         }
 179 }
 180
 181
 182 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 183 {
 184         /* get FbMult value */
 185         struct fixed31_32 pll_req;
 186         unsigned int fbmult_frac_val = 0;
 187         unsigned int fbmult_int_val = 0;
 188
 189
 190         /*
 191          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 192          * to leverage the fix point operations available in driver
 193          */
 194
 195         REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 196         REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 197
 198         pll_req = dc_fixpt_from_int(fbmult_int_val);
 199
 200         /*
 201          * since fractional part is only 16 bit in register definition but is 32 bit
 202          * in our fix point definiton, need to shift left by 16 to obtain correct value
 203          */
 204         pll_req.value |= fbmult_frac_val << 16;
 205
 206         /* multiply by REFCLK period */
 207         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 208
 209         /* integer part is now VCO frequency in kHz */
 210         return dc_fixpt_floor(pll_req);
 211 }
 212
 213 static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
 214 {
 215         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 216
 217         internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
 218         internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
 219
 220         internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL);       //dcf deep sleep divider
 221         internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
 222
 223         internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
 224         internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
 225
 226         internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
 227         internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
 228
 229         internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
 230         internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
 231 }
 232
 233 /* This function collect raw clk register values */
 234 static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 235                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 236 {
 237         struct dcn301_clk_internal internal = {0};
 238         char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
 239         unsigned int chars_printed = 0;
 240         unsigned int remaining_buffer = log_info->bufSize;
 241
 242         vg_dump_clk_registers_internal(&internal, clk_mgr_base);
 243
 244         regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
 245         regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
 246         regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
 247         regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
 248         regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
 249         regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 250
 251         regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
 252         if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
 253                 regs_and_bypass->dppclk_bypass = 0;
 254         regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
 255         if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
 256                 regs_and_bypass->dcfclk_bypass = 0;
 257         regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
 258         if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
 259                 regs_and_bypass->dispclk_bypass = 0;
 260         regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
 261         if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
 262                 regs_and_bypass->dprefclk_bypass = 0;
 263
 264         if (log_info->enabled) {
 265                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
 266                 remaining_buffer -= chars_printed;
 267                 *log_info->sum_chars_printed += chars_printed;
 268                 log_info->pBuf += chars_printed;
 269
 270                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
 271                         regs_and_bypass->dcfclk,
 272                         regs_and_bypass->dcf_deep_sleep_divider,
 273                         regs_and_bypass->dcf_deep_sleep_allow,
 274                         bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
 275                 remaining_buffer -= chars_printed;
 276                 *log_info->sum_chars_printed += chars_printed;
 277                 log_info->pBuf += chars_printed;
 278
 279                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
 280                         regs_and_bypass->dprefclk,
 281                         bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
 282                 remaining_buffer -= chars_printed;
 283                 *log_info->sum_chars_printed += chars_printed;
 284                 log_info->pBuf += chars_printed;
 285
 286                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
 287                         regs_and_bypass->dispclk,
 288                         bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
 289                 remaining_buffer -= chars_printed;
 290                 *log_info->sum_chars_printed += chars_printed;
 291                 log_info->pBuf += chars_printed;
 292
 293                 //split
 294                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
 295                 remaining_buffer -= chars_printed;
 296                 *log_info->sum_chars_printed += chars_printed;
 297                 log_info->pBuf += chars_printed;
 298
 299                 // REGISTER VALUES
 300                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
 301                 remaining_buffer -= chars_printed;
 302                 *log_info->sum_chars_printed += chars_printed;
 303                 log_info->pBuf += chars_printed;
 304
 305                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
 306                                 internal.CLK1_CLK3_CURRENT_CNT);
 307                 remaining_buffer -= chars_printed;
 308                 *log_info->sum_chars_printed += chars_printed;
 309                 log_info->pBuf += chars_printed;
 310
 311                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
 312                                         internal.CLK1_CLK3_DS_CNTL);
 313                 remaining_buffer -= chars_printed;
 314                 *log_info->sum_chars_printed += chars_printed;
 315                 log_info->pBuf += chars_printed;
 316
 317                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
 318                                         internal.CLK1_CLK3_ALLOW_DS);
 319                 remaining_buffer -= chars_printed;
 320                 *log_info->sum_chars_printed += chars_printed;
 321                 log_info->pBuf += chars_printed;
 322
 323                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
 324                                         internal.CLK1_CLK2_CURRENT_CNT);
 325                 remaining_buffer -= chars_printed;
 326                 *log_info->sum_chars_printed += chars_printed;
 327                 log_info->pBuf += chars_printed;
 328
 329                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
 330                                         internal.CLK1_CLK0_CURRENT_CNT);
 331                 remaining_buffer -= chars_printed;
 332                 *log_info->sum_chars_printed += chars_printed;
 333                 log_info->pBuf += chars_printed;
 334
 335                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
 336                                         internal.CLK1_CLK1_CURRENT_CNT);
 337                 remaining_buffer -= chars_printed;
 338                 *log_info->sum_chars_printed += chars_printed;
 339                 log_info->pBuf += chars_printed;
 340
 341                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
 342                                         internal.CLK1_CLK3_BYPASS_CNTL);
 343                 remaining_buffer -= chars_printed;
 344                 *log_info->sum_chars_printed += chars_printed;
 345                 log_info->pBuf += chars_printed;
 346
 347                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
 348                                         internal.CLK1_CLK2_BYPASS_CNTL);
 349                 remaining_buffer -= chars_printed;
 350                 *log_info->sum_chars_printed += chars_printed;
 351                 log_info->pBuf += chars_printed;
 352
 353                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
 354                                         internal.CLK1_CLK0_BYPASS_CNTL);
 355                 remaining_buffer -= chars_printed;
 356                 *log_info->sum_chars_printed += chars_printed;
 357                 log_info->pBuf += chars_printed;
 358
 359                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
 360                                         internal.CLK1_CLK1_BYPASS_CNTL);
 361                 remaining_buffer -= chars_printed;
 362                 *log_info->sum_chars_printed += chars_printed;
 363                 log_info->pBuf += chars_printed;
 364         }
 365 }
 366
 367 /* This function produce translated logical clk state values*/
 368 void vg_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
 369 {
 370
 371         struct clk_state_registers_and_bypass sb = { 0 };
 372         struct clk_log_info log_info = { 0 };
 373
 374         vg_dump_clk_registers(&sb, clk_mgr_base, &log_info);
 375
 376         s->dprefclk_khz = sb.dprefclk * 1000;
 377 }
 378
 379 void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 380 {
 381         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 382
 383         dcn301_smu_enable_pme_wa(clk_mgr);
 384 }
 385
 386 void vg_init_clocks(struct clk_mgr *clk_mgr)
 387 {
 388         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 389         // Assumption is that boot state always supports pstate
 390         clk_mgr->clks.p_state_change_support = true;
 391         clk_mgr->clks.prev_p_state_change_support = true;
 392         clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 393 }
 394
 395 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
 396 {
 397         int i, num_valid_sets;
 398
 399         num_valid_sets = 0;
 400
 401         for (i = 0; i < WM_SET_COUNT; i++) {
 402                 /* skip empty entries, the smu array has no holes*/
 403                 if (!bw_params->wm_table.entries[i].valid)
 404                         continue;
 405
 406                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
 407                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
 408                 /* We will not select WM based on fclk, so leave it as unconstrained */
 409                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 410                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 411
 412                 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
 413                         if (i == 0)
 414                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
 415                         else {
 416                                 /* add 1 to make it non-overlapping with next lvl */
 417                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
 418                                                 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 419                         }
 420                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
 421                                         bw_params->clk_table.entries[i].dcfclk_mhz;
 422
 423                 } else {
 424                         /* unconstrained for memory retraining */
 425                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 426                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 427
 428                         /* Modify previous watermark range to cover up to max */
 429                         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 430                 }
 431                 num_valid_sets++;
 432         }
 433
 434         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 435
 436         /* modify the min and max to make sure we cover the whole range*/
 437         table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
 438         table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
 439         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
 440         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 441
 442         /* This is for writeback only, does not matter currently as no writeback support*/
 443         table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
 444         table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
 445         table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
 446         table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
 447         table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
 448 }
 449
 450
 451 void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 452 {
 453         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 454         struct watermarks *table = clk_mgr_base->smu_wm_set.wm_set;
 455
 456         if (!clk_mgr->smu_ver)
 457                 return;
 458
 459         if (!table || clk_mgr_base->smu_wm_set.mc_address.quad_part == 0)
 460                 return;
 461
 462         memset(table, 0, sizeof(*table));
 463
 464         vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
 465
 466         dcn301_smu_set_dram_addr_high(clk_mgr,
 467                         clk_mgr_base->smu_wm_set.mc_address.high_part);
 468         dcn301_smu_set_dram_addr_low(clk_mgr,
 469                         clk_mgr_base->smu_wm_set.mc_address.low_part);
 470         dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 471 }
 472
 473 static bool vg_are_clock_states_equal(struct dc_clocks *a,
 474                 struct dc_clocks *b)
 475 {
 476         if (a->dispclk_khz != b->dispclk_khz)
 477                 return false;
 478         else if (a->dppclk_khz != b->dppclk_khz)
 479                 return false;
 480         else if (a->dcfclk_khz != b->dcfclk_khz)
 481                 return false;
 482         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 483                 return false;
 484
 485         return true;
 486 }
 487
 488
 489 static struct clk_mgr_funcs vg_funcs = {
 490         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 491         .update_clocks = vg_update_clocks,
 492         .init_clocks = vg_init_clocks,
 493         .enable_pme_wa = vg_enable_pme_wa,
 494         .are_clock_states_equal = vg_are_clock_states_equal,
 495         .notify_wm_ranges = vg_notify_wm_ranges
 496 };
 497
 498 static struct clk_bw_params vg_bw_params = {
 499         .vram_type = Ddr4MemType,
 500         .num_channels = 1,
 501         .clk_table = {
 502                 .entries = {
 503                         {
 504                                 .voltage = 0,
 505                                 .dcfclk_mhz = 400,
 506                                 .fclk_mhz = 400,
 507                                 .memclk_mhz = 800,
 508                                 .socclk_mhz = 0,
 509                         },
 510                         {
 511                                 .voltage = 0,
 512                                 .dcfclk_mhz = 483,
 513                                 .fclk_mhz = 800,
 514                                 .memclk_mhz = 1600,
 515                                 .socclk_mhz = 0,
 516                         },
 517                         {
 518                                 .voltage = 0,
 519                                 .dcfclk_mhz = 602,
 520                                 .fclk_mhz = 1067,
 521                                 .memclk_mhz = 1067,
 522                                 .socclk_mhz = 0,
 523                         },
 524                         {
 525                                 .voltage = 0,
 526                                 .dcfclk_mhz = 738,
 527                                 .fclk_mhz = 1333,
 528                                 .memclk_mhz = 1600,
 529                                 .socclk_mhz = 0,
 530                         },
 531                 },
 532
 533                 .num_entries = 4,
 534         },
 535
 536 };
 537
 538 static struct wm_table ddr4_wm_table = {
 539         .entries = {
 540                 {
 541                         .wm_inst = WM_A,
 542                         .wm_type = WM_TYPE_PSTATE_CHG,
 543                         .pstate_latency_us = 11.72,
 544                         .sr_exit_time_us = 6.09,
 545                         .sr_enter_plus_exit_time_us = 7.14,
 546                         .valid = true,
 547                 },
 548                 {
 549                         .wm_inst = WM_B,
 550                         .wm_type = WM_TYPE_PSTATE_CHG,
 551                         .pstate_latency_us = 11.72,
 552                         .sr_exit_time_us = 10.12,
 553                         .sr_enter_plus_exit_time_us = 11.48,
 554                         .valid = true,
 555                 },
 556                 {
 557                         .wm_inst = WM_C,
 558                         .wm_type = WM_TYPE_PSTATE_CHG,
 559                         .pstate_latency_us = 11.72,
 560                         .sr_exit_time_us = 10.12,
 561                         .sr_enter_plus_exit_time_us = 11.48,
 562                         .valid = true,
 563                 },
 564                 {
 565                         .wm_inst = WM_D,
 566                         .wm_type = WM_TYPE_PSTATE_CHG,
 567                         .pstate_latency_us = 11.72,
 568                         .sr_exit_time_us = 10.12,
 569                         .sr_enter_plus_exit_time_us = 11.48,
 570                         .valid = true,
 571                 },
 572         }
 573 };
 574
 575 static struct wm_table lpddr5_wm_table = {
 576         .entries = {
 577                 {
 578                         .wm_inst = WM_A,
 579                         .wm_type = WM_TYPE_PSTATE_CHG,
 580                         .pstate_latency_us = 11.65333,
 581                         .sr_exit_time_us = 5.32,
 582                         .sr_enter_plus_exit_time_us = 6.38,
 583                         .valid = true,
 584                 },
 585                 {
 586                         .wm_inst = WM_B,
 587                         .wm_type = WM_TYPE_PSTATE_CHG,
 588                         .pstate_latency_us = 11.65333,
 589                         .sr_exit_time_us = 9.82,
 590                         .sr_enter_plus_exit_time_us = 11.196,
 591                         .valid = true,
 592                 },
 593                 {
 594                         .wm_inst = WM_C,
 595                         .wm_type = WM_TYPE_PSTATE_CHG,
 596                         .pstate_latency_us = 11.65333,
 597                         .sr_exit_time_us = 9.89,
 598                         .sr_enter_plus_exit_time_us = 11.24,
 599                         .valid = true,
 600                 },
 601                 {
 602                         .wm_inst = WM_D,
 603                         .wm_type = WM_TYPE_PSTATE_CHG,
 604                         .pstate_latency_us = 11.65333,
 605                         .sr_exit_time_us = 9.748,
 606                         .sr_enter_plus_exit_time_us = 11.102,
 607                         .valid = true,
 608                 },
 609         }
 610 };
 611
 612
 613 static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
 614                 unsigned int voltage)
 615 {
 616         int i;
 617
 618         for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
 619                 if (clock_table->SocVoltage[i] == voltage)
 620                         return clock_table->DcfClocks[i];
 621         }
 622
 623         ASSERT(0);
 624         return 0;
 625 }
 626
 627 void vg_clk_mgr_helper_populate_bw_params(
 628                 struct clk_mgr_internal *clk_mgr,
 629                 struct integrated_info *bios_info,
 630                 const struct vg_dpm_clocks *clock_table)
 631 {
 632         int i, j;
 633         struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
 634
 635         j = -1;
 636
 637         ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
 638
 639         /* Find lowest DPM, FCLK is filled in reverse order*/
 640
 641         for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
 642                 if (clock_table->DfPstateTable[i].fclk != 0) {
 643                         j = i;
 644                         break;
 645                 }
 646         }
 647
 648         if (j == -1) {
 649                 /* clock table is all 0s, just use our own hardcode */
 650                 ASSERT(0);
 651                 return;
 652         }
 653
 654         bw_params->clk_table.num_entries = j + 1;
 655
 656         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 657                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
 658                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
 659                 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
 660                 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
 661         }
 662
 663         bw_params->vram_type = bios_info->memory_type;
 664         bw_params->num_channels = bios_info->ma_channel_number;
 665
 666         for (i = 0; i < WM_SET_COUNT; i++) {
 667                 bw_params->wm_table.entries[i].wm_inst = i;
 668
 669                 if (i >= bw_params->clk_table.num_entries) {
 670                         bw_params->wm_table.entries[i].valid = false;
 671                         continue;
 672                 }
 673
 674                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 675                 bw_params->wm_table.entries[i].valid = true;
 676         }
 677
 678         if (bw_params->vram_type == LpDdr4MemType) {
 679                 /*
 680                  * WM set D will be re-purposed for memory retraining
 681                  */
 682                 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
 683                 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
 684                 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
 685                 bw_params->wm_table.entries[WM_D].valid = true;
 686         }
 687
 688 }
 689
 690 /* Temporary Place holder until we can get them from fuse */
 691 static struct vg_dpm_clocks dummy_clocks = {
 692                 .DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
 693                 .SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
 694                 .SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
 695                 .DfPstateTable = {
 696                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 },
 697                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 },
 698                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 },
 699                                 { .fclk = 400,  .memclk = 400, .voltage = 2800 }
 700                 }
 701 };
 702
 703 static struct watermarks dummy_wms = { 0 };
 704
 705 void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
 706                 struct smu_dpm_clks *smu_dpm_clks)
 707 {
 708         struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
 709
 710         if (!clk_mgr->smu_ver)
 711                 return;
 712
 713         if (!table || smu_dpm_clks->mc_address.quad_part == 0)
 714                 return;
 715
 716         memset(table, 0, sizeof(*table));
 717
 718         dcn301_smu_set_dram_addr_high(clk_mgr,
 719                         smu_dpm_clks->mc_address.high_part);
 720         dcn301_smu_set_dram_addr_low(clk_mgr,
 721                         smu_dpm_clks->mc_address.low_part);
 722         dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
 723 }
 724
 725 void vg_clk_mgr_construct(
 726                 struct dc_context *ctx,
 727                 struct clk_mgr_internal *clk_mgr,
 728                 struct pp_smu_funcs *pp_smu,
 729                 struct dccg *dccg)
 730 {
 731         struct smu_dpm_clks smu_dpm_clks = { 0 };
 732
 733         clk_mgr->base.ctx = ctx;
 734         clk_mgr->base.funcs = &vg_funcs;
 735
 736         clk_mgr->pp_smu = pp_smu;
 737
 738         clk_mgr->dccg = dccg;
 739         clk_mgr->dfs_bypass_disp_clk = 0;
 740
 741         clk_mgr->dprefclk_ss_percentage = 0;
 742         clk_mgr->dprefclk_ss_divider = 1000;
 743         clk_mgr->ss_on_dprefclk = false;
 744         clk_mgr->dfs_ref_freq_khz = 48000;
 745
 746         clk_mgr->base.smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
 747                                 clk_mgr->base.ctx,
 748                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 749                                 sizeof(struct watermarks),
 750                                 &clk_mgr->base.smu_wm_set.mc_address.quad_part);
 751
 752         if (clk_mgr->base.smu_wm_set.wm_set == 0) {
 753                 clk_mgr->base.smu_wm_set.wm_set = &dummy_wms;
 754                 clk_mgr->base.smu_wm_set.mc_address.quad_part = 0;
 755         }
 756         ASSERT(clk_mgr->base.smu_wm_set.wm_set);
 757
 758         smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
 759                                 clk_mgr->base.ctx,
 760                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 761                                 sizeof(struct vg_dpm_clocks),
 762                                 &smu_dpm_clks.mc_address.quad_part);
 763
 764         if (smu_dpm_clks.dpm_clks == NULL) {
 765                 smu_dpm_clks.dpm_clks = &dummy_clocks;
 766                 smu_dpm_clks.mc_address.quad_part = 0;
 767         }
 768
 769         ASSERT(smu_dpm_clks.dpm_clks);
 770
 771         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 772                 vg_funcs.update_clocks = dcn2_update_clocks_fpga;
 773                 clk_mgr->base.dentist_vco_freq_khz = 3600000;
 774         } else {
 775                 struct clk_log_info log_info = {0};
 776
 777                 clk_mgr->smu_ver = dcn301_smu_get_smu_version(clk_mgr);
 778
 779                 if (clk_mgr->smu_ver)
 780                         clk_mgr->smu_present = true;
 781
 782                 /* TODO: Check we get what we expect during bringup */
 783                 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 784
 785                 /* in case we don't get a value from the register, use default */
 786                 if (clk_mgr->base.dentist_vco_freq_khz == 0)
 787                         clk_mgr->base.dentist_vco_freq_khz = 3600000;
 788
 789                 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
 790                         vg_bw_params.wm_table = lpddr5_wm_table;
 791                 } else {
 792                         vg_bw_params.wm_table = ddr4_wm_table;
 793                 }
 794                 /* Saved clocks configured at boot for debug purposes */
 795                 vg_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
 796         }
 797
 798         clk_mgr->base.dprefclk_khz = 600000;
 799         dce_clock_read_ss_info(clk_mgr);
 800
 801         clk_mgr->base.bw_params = &vg_bw_params;
 802
 803         vg_get_dpm_table_from_smu(clk_mgr, &smu_dpm_clks);
 804         if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
 805                 vg_clk_mgr_helper_populate_bw_params(
 806                                 clk_mgr,
 807                                 ctx->dc_bios->integrated_info,
 808                                 smu_dpm_clks.dpm_clks);
 809         }
 810
 811         if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
 812                 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 813                                 smu_dpm_clks.dpm_clks);
 814 /*
 815         if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver) {
 816                  enable powerfeatures when displaycount goes to 0
 817                 dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
 818         }
 819 */
 820 }
 821
 822 void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
 823 {
 824         if (clk_mgr->base.smu_wm_set.wm_set && clk_mgr->base.smu_wm_set.mc_address.quad_part != 0)
 825                 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 826                                 clk_mgr->base.smu_wm_set.wm_set);
 827 }