drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dcn_calcs.h"
  28 #include "dcn_calc_auto.h"
  29 #include "dc.h"
  30 #include "dal_asic_id.h"
  31
  32 #include "resource.h"
  33 #include "dcn10/dcn10_resource.h"
  34 #include "dcn10/dcn10_hubbub.h"
  35
  36 #include "dcn_calc_math.h"
  37
  38 #define DC_LOGGER \
  39         dc->ctx->logger
  40
  41 #define WM_SET_COUNT 4
  42 #define WM_A 0
  43 #define WM_B 1
  44 #define WM_C 2
  45 #define WM_D 3
  46
  47 /*
  48  * NOTE:
  49  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
  50  *
  51  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
  52  * ways. Unless there is something clearly wrong with it the code should
  53  * remain as-is as it provides us with a guarantee from HW that it is correct.
  54  */
  55
  56 /* Defaults from spreadsheet rev#247 */
  57 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
  58                 /* latencies */
  59                 .sr_exit_time = 17, /*us*/
  60                 .sr_enter_plus_exit_time = 19, /*us*/
  61                 .urgent_latency = 4, /*us*/
  62                 .dram_clock_change_latency = 17, /*us*/
  63                 .write_back_latency = 12, /*us*/
  64                 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
  65
  66                 /* below default clocks derived from STA target base on
  67                  * slow-slow corner + 10% margin with voltages aligned to FCLK.
  68                  *
  69                  * Use these value if fused value doesn't make sense as earlier
  70                  * part don't have correct value fused */
  71                 /* default DCF CLK DPM on RV*/
  72                 .dcfclkv_max0p9 = 655,  /* MHz, = 3600/5.5 */
  73                 .dcfclkv_nom0p8 = 626,  /* MHz, = 3600/5.75 */
  74                 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
  75                 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
  76
  77                 /* default DISP CLK voltage state on RV */
  78                 .max_dispclk_vmax0p9 = 1108,    /* MHz, = 3600/3.25 */
  79                 .max_dispclk_vnom0p8 = 1029,    /* MHz, = 3600/3.5 */
  80                 .max_dispclk_vmid0p72 = 960,    /* MHz, = 3600/3.75 */
  81                 .max_dispclk_vmin0p65 = 626,    /* MHz, = 3600/5.75 */
  82
  83                 /* default DPP CLK voltage state on RV */
  84                 .max_dppclk_vmax0p9 = 720,      /* MHz, = 3600/5 */
  85                 .max_dppclk_vnom0p8 = 686,      /* MHz, = 3600/5.25 */
  86                 .max_dppclk_vmid0p72 = 626,     /* MHz, = 3600/5.75 */
  87                 .max_dppclk_vmin0p65 = 400,     /* MHz, = 3600/9 */
  88
  89                 /* default PHY CLK voltage state on RV */
  90                 .phyclkv_max0p9 = 900, /*MHz*/
  91                 .phyclkv_nom0p8 = 847, /*MHz*/
  92                 .phyclkv_mid0p72 = 800, /*MHz*/
  93                 .phyclkv_min0p65 = 600, /*MHz*/
  94
  95                 /* BW depend on FCLK, MCLK, # of channels */
  96                 /* dual channel BW */
  97                 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
  98                 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
  99                 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
 100                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
 101                 /* single channel BW
 102                 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
 103                 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
 104                 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
 105                 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
 106                 */
 107
 108                 .number_of_channels = 2,
 109
 110                 .socclk = 208, /*MHz*/
 111                 .downspreading = 0.5f, /*%*/
 112                 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
 113                 .urgent_out_of_order_return_per_channel = 256, /*bytes*/
 114                 .vmm_page_size = 4096, /*bytes*/
 115                 .return_bus_width = 64, /*bytes*/
 116                 .max_request_size = 256, /*bytes*/
 117
 118                 /* Depends on user class (client vs embedded, workstation, etc) */
 119                 .percent_disp_bw_limit = 0.3f /*%*/
 120 };
 121
 122 const struct dcn_ip_params dcn10_ip_defaults = {
 123                 .rob_buffer_size_in_kbyte = 64,
 124                 .det_buffer_size_in_kbyte = 164,
 125                 .dpp_output_buffer_pixels = 2560,
 126                 .opp_output_buffer_lines = 1,
 127                 .pixel_chunk_size_in_kbyte = 8,
 128                 .pte_enable = dcn_bw_yes,
 129                 .pte_chunk_size = 2, /*kbytes*/
 130                 .meta_chunk_size = 2, /*kbytes*/
 131                 .writeback_chunk_size = 2, /*kbytes*/
 132                 .odm_capability = dcn_bw_no,
 133                 .dsc_capability = dcn_bw_no,
 134                 .line_buffer_size = 589824, /*bit*/
 135                 .max_line_buffer_lines = 12,
 136                 .is_line_buffer_bpp_fixed = dcn_bw_no,
 137                 .line_buffer_fixed_bpp = dcn_bw_na,
 138                 .writeback_luma_buffer_size = 12, /*kbytes*/
 139                 .writeback_chroma_buffer_size = 8, /*kbytes*/
 140                 .max_num_dpp = 4,
 141                 .max_num_writeback = 2,
 142                 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
 143                 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
 144                 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
 145                 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
 146                 .max_hscl_ratio = 4,
 147                 .max_vscl_ratio = 4,
 148                 .max_hscl_taps = 8,
 149                 .max_vscl_taps = 8,
 150                 .pte_buffer_size_in_requests = 42,
 151                 .dispclk_ramping_margin = 1, /*%*/
 152                 .under_scan_factor = 1.11f,
 153                 .max_inter_dcn_tile_repeaters = 8,
 154                 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
 155                 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
 156                 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
 157 };
 158
 159 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
 160 {
 161         switch (sw_mode) {
 162         case DC_SW_LINEAR:
 163                 return dcn_bw_sw_linear;
 164         case DC_SW_4KB_S:
 165                 return dcn_bw_sw_4_kb_s;
 166         case DC_SW_4KB_D:
 167                 return dcn_bw_sw_4_kb_d;
 168         case DC_SW_64KB_S:
 169                 return dcn_bw_sw_64_kb_s;
 170         case DC_SW_64KB_D:
 171                 return dcn_bw_sw_64_kb_d;
 172         case DC_SW_VAR_S:
 173                 return dcn_bw_sw_var_s;
 174         case DC_SW_VAR_D:
 175                 return dcn_bw_sw_var_d;
 176         case DC_SW_64KB_S_T:
 177                 return dcn_bw_sw_64_kb_s_t;
 178         case DC_SW_64KB_D_T:
 179                 return dcn_bw_sw_64_kb_d_t;
 180         case DC_SW_4KB_S_X:
 181                 return dcn_bw_sw_4_kb_s_x;
 182         case DC_SW_4KB_D_X:
 183                 return dcn_bw_sw_4_kb_d_x;
 184         case DC_SW_64KB_S_X:
 185                 return dcn_bw_sw_64_kb_s_x;
 186         case DC_SW_64KB_D_X:
 187                 return dcn_bw_sw_64_kb_d_x;
 188         case DC_SW_VAR_S_X:
 189                 return dcn_bw_sw_var_s_x;
 190         case DC_SW_VAR_D_X:
 191                 return dcn_bw_sw_var_d_x;
 192         case DC_SW_256B_S:
 193         case DC_SW_256_D:
 194         case DC_SW_256_R:
 195         case DC_SW_4KB_R:
 196         case DC_SW_64KB_R:
 197         case DC_SW_VAR_R:
 198         case DC_SW_4KB_R_X:
 199         case DC_SW_64KB_R_X:
 200         case DC_SW_VAR_R_X:
 201         default:
 202                 BREAK_TO_DEBUGGER(); /*not in formula*/
 203                 return dcn_bw_sw_4_kb_s;
 204         }
 205 }
 206
 207 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
 208 {
 209         switch (depth) {
 210         case LB_PIXEL_DEPTH_18BPP:
 211                 return 18;
 212         case LB_PIXEL_DEPTH_24BPP:
 213                 return 24;
 214         case LB_PIXEL_DEPTH_30BPP:
 215                 return 30;
 216         case LB_PIXEL_DEPTH_36BPP:
 217                 return 36;
 218         default:
 219                 return 30;
 220         }
 221 }
 222
 223 static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
 224 {
 225         switch (format) {
 226         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 227         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 228                 return dcn_bw_rgb_sub_16;
 229         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 230         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 231         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 232         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 233         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 234                 return dcn_bw_rgb_sub_32;
 235         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 236         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 237         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 238                 return dcn_bw_rgb_sub_64;
 239         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 240         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 241                 return dcn_bw_yuv420_sub_8;
 242         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 243         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 244                 return dcn_bw_yuv420_sub_10;
 245         default:
 246                 return dcn_bw_rgb_sub_32;
 247         }
 248 }
 249
 250 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
 251 {
 252         switch (sw_mode) {
 253         /* for 4/8/16 high tiles */
 254         case DC_SW_LINEAR:
 255                 return dm_4k_tile;
 256         case DC_SW_4KB_S:
 257         case DC_SW_4KB_S_X:
 258                 return dm_4k_tile;
 259         case DC_SW_64KB_S:
 260         case DC_SW_64KB_S_X:
 261         case DC_SW_64KB_S_T:
 262                 return dm_64k_tile;
 263         case DC_SW_VAR_S:
 264         case DC_SW_VAR_S_X:
 265                 return dm_256k_tile;
 266
 267         /* For 64bpp 2 high tiles */
 268         case DC_SW_4KB_D:
 269         case DC_SW_4KB_D_X:
 270                 return dm_4k_tile;
 271         case DC_SW_64KB_D:
 272         case DC_SW_64KB_D_X:
 273         case DC_SW_64KB_D_T:
 274                 return dm_64k_tile;
 275         case DC_SW_VAR_D:
 276         case DC_SW_VAR_D_X:
 277                 return dm_256k_tile;
 278
 279         case DC_SW_4KB_R:
 280         case DC_SW_4KB_R_X:
 281                 return dm_4k_tile;
 282         case DC_SW_64KB_R:
 283         case DC_SW_64KB_R_X:
 284                 return dm_64k_tile;
 285         case DC_SW_VAR_R:
 286         case DC_SW_VAR_R_X:
 287                 return dm_256k_tile;
 288
 289         /* Unsupported swizzle modes for dcn */
 290         case DC_SW_256B_S:
 291         default:
 292                 ASSERT(0); /* Not supported */
 293                 return 0;
 294         }
 295 }
 296
 297 static void pipe_ctx_to_e2e_pipe_params (
 298                 const struct pipe_ctx *pipe,
 299                 struct _vcs_dpi_display_pipe_params_st *input)
 300 {
 301         input->src.is_hsplit = false;
 302         if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
 303                 input->src.is_hsplit = true;
 304         else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
 305                 input->src.is_hsplit = true;
 306
 307         if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
 308                 /*
 309                  * this method requires us to always re-calculate watermark when dcc change
 310                  * between flip.
 311                  */
 312                 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
 313         } else {
 314                 /*
 315                  * allow us to disable dcc on the fly without re-calculating WM
 316                  *
 317                  * extra overhead for DCC is quite small.  for 1080p WM without
 318                  * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
 319                  */
 320                 unsigned int bpe;
 321
 322                 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
 323                         dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
 324         }
 325         input->src.dcc_rate            = 1;
 326         input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
 327         input->src.source_scan         = dm_horz;
 328         input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
 329
 330         input->src.viewport_width      = pipe->plane_res.scl_data.viewport.width;
 331         input->src.viewport_height     = pipe->plane_res.scl_data.viewport.height;
 332         input->src.data_pitch          = pipe->plane_res.scl_data.viewport.width;
 333         input->src.data_pitch_c        = pipe->plane_res.scl_data.viewport.width;
 334         input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
 335         input->src.cur0_bpp            = 32;
 336
 337         input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
 338
 339         switch (pipe->plane_state->rotation) {
 340         case ROTATION_ANGLE_0:
 341         case ROTATION_ANGLE_180:
 342                 input->src.source_scan = dm_horz;
 343                 break;
 344         case ROTATION_ANGLE_90:
 345         case ROTATION_ANGLE_270:
 346                 input->src.source_scan = dm_vert;
 347                 break;
 348         default:
 349                 ASSERT(0); /* Not supported */
 350                 break;
 351         }
 352
 353         /* TODO: Fix pixel format mappings */
 354         switch (pipe->plane_state->format) {
 355         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 356         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 357                 input->src.source_format = dm_420_8;
 358                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 359                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 360                 break;
 361         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 362         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 363                 input->src.source_format = dm_420_10;
 364                 input->src.viewport_width_c    = input->src.viewport_width / 2;
 365                 input->src.viewport_height_c   = input->src.viewport_height / 2;
 366                 break;
 367         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 368         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 369         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 370                 input->src.source_format = dm_444_64;
 371                 input->src.viewport_width_c    = input->src.viewport_width;
 372                 input->src.viewport_height_c   = input->src.viewport_height;
 373                 break;
 374         default:
 375                 input->src.source_format = dm_444_32;
 376                 input->src.viewport_width_c    = input->src.viewport_width;
 377                 input->src.viewport_height_c   = input->src.viewport_height;
 378                 break;
 379         }
 380
 381         input->scale_taps.htaps                = pipe->plane_res.scl_data.taps.h_taps;
 382         input->scale_ratio_depth.hscl_ratio    = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
 383         input->scale_ratio_depth.vscl_ratio    = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
 384         input->scale_ratio_depth.vinit =  pipe->plane_res.scl_data.inits.v.value/4294967296.0;
 385         if (input->scale_ratio_depth.vinit < 1.0)
 386                         input->scale_ratio_depth.vinit = 1;
 387         input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
 388         input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
 389         input->scale_taps.htaps_c              = pipe->plane_res.scl_data.taps.h_taps_c;
 390         input->scale_ratio_depth.hscl_ratio_c  = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
 391         input->scale_ratio_depth.vscl_ratio_c  = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
 392         input->scale_ratio_depth.vinit_c       = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
 393         if (input->scale_ratio_depth.vinit_c < 1.0)
 394                         input->scale_ratio_depth.vinit_c = 1;
 395         switch (pipe->plane_res.scl_data.lb_params.depth) {
 396         case LB_PIXEL_DEPTH_30BPP:
 397                 input->scale_ratio_depth.lb_depth = 30; break;
 398         case LB_PIXEL_DEPTH_36BPP:
 399                 input->scale_ratio_depth.lb_depth = 36; break;
 400         default:
 401                 input->scale_ratio_depth.lb_depth = 24; break;
 402         }
 403
 404
 405         input->dest.vactive        = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
 406                         + pipe->stream->timing.v_border_bottom;
 407
 408         input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;
 409         input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
 410
 411         input->dest.full_recout_width   = pipe->plane_res.scl_data.recout.width;
 412         input->dest.full_recout_height  = pipe->plane_res.scl_data.recout.height;
 413
 414         input->dest.htotal         = pipe->stream->timing.h_total;
 415         input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;
 416         input->dest.hblank_end     = input->dest.hblank_start
 417                         - pipe->stream->timing.h_addressable
 418                         - pipe->stream->timing.h_border_left
 419                         - pipe->stream->timing.h_border_right;
 420
 421         input->dest.vtotal         = pipe->stream->timing.v_total;
 422         input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;
 423         input->dest.vblank_end     = input->dest.vblank_start
 424                         - pipe->stream->timing.v_addressable
 425                         - pipe->stream->timing.v_border_bottom
 426                         - pipe->stream->timing.v_border_top;
 427         input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
 428         input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
 429         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 430         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 431         input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
 432
 433 }
 434
 435 static void dcn_bw_calc_rq_dlg_ttu(
 436                 const struct dc *dc,
 437                 const struct dcn_bw_internal_vars *v,
 438                 struct pipe_ctx *pipe,
 439                 int in_idx)
 440 {
 441         struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
 442         struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
 443         struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
 444         struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
 445         struct _vcs_dpi_display_rq_params_st rq_param = {0};
 446         struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
 447         struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
 448         float total_active_bw = 0;
 449         float total_prefetch_bw = 0;
 450         int total_flip_bytes = 0;
 451         int i;
 452
 453         memset(dlg_regs, 0, sizeof(*dlg_regs));
 454         memset(ttu_regs, 0, sizeof(*ttu_regs));
 455         memset(rq_regs, 0, sizeof(*rq_regs));
 456
 457         for (i = 0; i < number_of_planes; i++) {
 458                 total_active_bw += v->read_bandwidth[i];
 459                 total_prefetch_bw += v->prefetch_bandwidth[i];
 460                 total_flip_bytes += v->total_immediate_flip_bytes[i];
 461         }
 462         dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
 463         if (dlg_sys_param.total_flip_bw < 0.0)
 464                 dlg_sys_param.total_flip_bw = 0;
 465
 466         dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
 467         dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
 468         dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
 469         dlg_sys_param.t_extra_us = v->urgent_extra_latency;
 470         dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
 471         dlg_sys_param.total_flip_bytes = total_flip_bytes;
 472
 473         pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
 474         input.clks_cfg.dcfclk_mhz = v->dcfclk;
 475         input.clks_cfg.dispclk_mhz = v->dispclk;
 476         input.clks_cfg.dppclk_mhz = v->dppclk;
 477         input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
 478         input.clks_cfg.socclk_mhz = v->socclk;
 479         input.clks_cfg.voltage = v->voltage_level;
 480 //      dc->dml.logger = pool->base.logger;
 481         input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
 482         input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
 483         //input[in_idx].dout.output_standard;
 484
 485         /*todo: soc->sr_enter_plus_exit_time??*/
 486         dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
 487
 488         dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
 489         dml1_extract_rq_regs(dml, rq_regs, rq_param);
 490         dml1_rq_dlg_get_dlg_params(
 491                         dml,
 492                         dlg_regs,
 493                         ttu_regs,
 494                         rq_param.dlg,
 495                         dlg_sys_param,
 496                         input,
 497                         true,
 498                         true,
 499                         v->pte_enable == dcn_bw_yes,
 500                         pipe->plane_state->flip_immediate);
 501 }
 502
 503 static void split_stream_across_pipes(
 504                 struct resource_context *res_ctx,
 505                 const struct resource_pool *pool,
 506                 struct pipe_ctx *primary_pipe,
 507                 struct pipe_ctx *secondary_pipe)
 508 {
 509         int pipe_idx = secondary_pipe->pipe_idx;
 510
 511         if (!primary_pipe->plane_state)
 512                 return;
 513
 514         *secondary_pipe = *primary_pipe;
 515
 516         secondary_pipe->pipe_idx = pipe_idx;
 517         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
 518         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
 519         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
 520         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
 521         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
 522         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
 523         if (primary_pipe->bottom_pipe) {
 524                 ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
 525                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
 526                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
 527         }
 528         primary_pipe->bottom_pipe = secondary_pipe;
 529         secondary_pipe->top_pipe = primary_pipe;
 530
 531         resource_build_scaling_params(primary_pipe);
 532         resource_build_scaling_params(secondary_pipe);
 533 }
 534
 535 #if 0
 536 static void calc_wm_sets_and_perf_params(
 537                 struct dc_state *context,
 538                 struct dcn_bw_internal_vars *v)
 539 {
 540         /* Calculate set A last to keep internal var state consistent for required config */
 541         if (v->voltage_level < 2) {
 542                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
 543                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
 544                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
 545                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 546
 547                 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
 548                         v->stutter_exit_watermark * 1000;
 549                 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
 550                                 v->stutter_enter_plus_exit_watermark * 1000;
 551                 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
 552                                 v->dram_clock_change_watermark * 1000;
 553                 context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 554                 context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
 555
 556                 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
 557                 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
 558                 v->dcfclk = v->dcfclkv_nom0p8;
 559                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 560
 561                 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
 562                         v->stutter_exit_watermark * 1000;
 563                 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
 564                                 v->stutter_enter_plus_exit_watermark * 1000;
 565                 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
 566                                 v->dram_clock_change_watermark * 1000;
 567                 context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 568                 context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
 569         }
 570
 571         if (v->voltage_level < 3) {
 572                 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
 573                 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
 574                 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
 575                 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
 576                 v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
 577                 v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
 578                 v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
 579                 v->dcfclk = v->dcfclkv_max0p9;
 580                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 581
 582                 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
 583                         v->stutter_exit_watermark * 1000;
 584                 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
 585                                 v->stutter_enter_plus_exit_watermark * 1000;
 586                 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
 587                                 v->dram_clock_change_watermark * 1000;
 588                 context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 589                 context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
 590         }
 591
 592         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 593         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 594         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 595         v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
 596         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 597         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 598         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 599         v->dcfclk = v->dcfclk_per_state[v->voltage_level];
 600         dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
 601
 602         context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
 603                 v->stutter_exit_watermark * 1000;
 604         context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
 605                         v->stutter_enter_plus_exit_watermark * 1000;
 606         context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
 607                         v->dram_clock_change_watermark * 1000;
 608         context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
 609         context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
 610         if (v->voltage_level >= 2) {
 611                 context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
 612                 context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
 613         }
 614         if (v->voltage_level >= 3)
 615                 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
 616 }
 617 #endif
 618
 619 static bool dcn_bw_apply_registry_override(struct dc *dc)
 620 {
 621         bool updated = false;
 622
 623         kernel_fpu_begin();
 624         if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
 625                         && dc->debug.sr_exit_time_ns) {
 626                 updated = true;
 627                 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
 628         }
 629
 630         if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
 631                                 != dc->debug.sr_enter_plus_exit_time_ns
 632                         && dc->debug.sr_enter_plus_exit_time_ns) {
 633                 updated = true;
 634                 dc->dcn_soc->sr_enter_plus_exit_time =
 635                                 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
 636         }
 637
 638         if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
 639                         && dc->debug.urgent_latency_ns) {
 640                 updated = true;
 641                 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
 642         }
 643
 644         if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
 645                                 != dc->debug.percent_of_ideal_drambw
 646                         && dc->debug.percent_of_ideal_drambw) {
 647                 updated = true;
 648                 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
 649                                 dc->debug.percent_of_ideal_drambw;
 650         }
 651
 652         if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
 653                                 != dc->debug.dram_clock_change_latency_ns
 654                         && dc->debug.dram_clock_change_latency_ns) {
 655                 updated = true;
 656                 dc->dcn_soc->dram_clock_change_latency =
 657                                 dc->debug.dram_clock_change_latency_ns / 1000.0;
 658         }
 659         kernel_fpu_end();
 660
 661         return updated;
 662 }
 663
 664 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
 665 {
 666         /*
 667          * disable optional pipe split by lower dispclk bounding box
 668          * at DPM0
 669          */
 670         v->max_dispclk[0] = v->max_dppclk_vmin0p65;
 671 }
 672
 673 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
 674                 unsigned int pixel_rate_100hz)
 675 {
 676         float pixel_rate_mhz = pixel_rate_100hz / 10000;
 677
 678         /*
 679          * force enabling pipe split by lower dpp clock for DPM0 to just
 680          * below the specify pixel_rate, so bw calc would split pipe.
 681          */
 682         if (pixel_rate_mhz < v->max_dppclk[0])
 683                 v->max_dppclk[0] = pixel_rate_mhz;
 684 }
 685
 686 static void hack_bounding_box(struct dcn_bw_internal_vars *v,
 687                 struct dc_debug_options *dbg,
 688                 struct dc_state *context)
 689 {
 690         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
 691                 hack_disable_optional_pipe_split(v);
 692
 693         if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
 694                 context->stream_count >= 2)
 695                 hack_disable_optional_pipe_split(v);
 696
 697         if (context->stream_count == 1 &&
 698                         dbg->force_single_disp_pipe_split)
 699                 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
 700 }
 701
 702 bool dcn_validate_bandwidth(
 703                 struct dc *dc,
 704                 struct dc_state *context)
 705 {
 706         const struct resource_pool *pool = dc->res_pool;
 707         struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
 708         int i, input_idx;
 709         int vesa_sync_start, asic_blank_end, asic_blank_start;
 710         bool bw_limit_pass;
 711         float bw_limit;
 712
 713         PERFORMANCE_TRACE_START();
 714         if (dcn_bw_apply_registry_override(dc))
 715                 dcn_bw_sync_calcs_and_dml(dc);
 716
 717         memset(v, 0, sizeof(*v));
 718         kernel_fpu_begin();
 719         v->sr_exit_time = dc->dcn_soc->sr_exit_time;
 720         v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
 721         v->urgent_latency = dc->dcn_soc->urgent_latency;
 722         v->write_back_latency = dc->dcn_soc->write_back_latency;
 723         v->percent_of_ideal_drambw_received_after_urg_latency =
 724                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
 725
 726         v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
 727         v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
 728         v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
 729         v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
 730
 731         v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
 732         v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
 733         v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
 734         v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
 735
 736         v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
 737         v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
 738         v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
 739         v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
 740
 741         v->socclk = dc->dcn_soc->socclk;
 742
 743         v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
 744         v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
 745         v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
 746         v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
 747
 748         v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
 749         v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
 750         v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
 751         v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
 752
 753         v->downspreading = dc->dcn_soc->downspreading;
 754         v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
 755         v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
 756         v->number_of_channels = dc->dcn_soc->number_of_channels;
 757         v->vmm_page_size = dc->dcn_soc->vmm_page_size;
 758         v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
 759         v->return_bus_width = dc->dcn_soc->return_bus_width;
 760
 761         v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
 762         v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
 763         v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
 764         v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
 765         v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
 766         v->pte_enable = dc->dcn_ip->pte_enable;
 767         v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
 768         v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
 769         v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
 770         v->odm_capability = dc->dcn_ip->odm_capability;
 771         v->dsc_capability = dc->dcn_ip->dsc_capability;
 772         v->line_buffer_size = dc->dcn_ip->line_buffer_size;
 773         v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
 774         v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
 775         v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
 776         v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
 777         v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
 778         v->max_num_dpp = dc->dcn_ip->max_num_dpp;
 779         v->max_num_writeback = dc->dcn_ip->max_num_writeback;
 780         v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
 781         v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
 782         v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
 783         v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
 784         v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
 785         v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
 786         v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
 787         v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
 788         v->under_scan_factor = dc->dcn_ip->under_scan_factor;
 789         v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
 790         v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
 791         v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
 792         v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
 793                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
 794         v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
 795                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
 796
 797         v->voltage[5] = dcn_bw_no_support;
 798         v->voltage[4] = dcn_bw_v_max0p9;
 799         v->voltage[3] = dcn_bw_v_max0p9;
 800         v->voltage[2] = dcn_bw_v_nom0p8;
 801         v->voltage[1] = dcn_bw_v_mid0p72;
 802         v->voltage[0] = dcn_bw_v_min0p65;
 803         v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
 804         v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
 805         v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
 806         v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
 807         v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
 808         v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
 809         v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
 810         v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
 811         v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
 812         v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
 813         v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
 814         v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
 815         v->max_dispclk[5] = v->max_dispclk_vmax0p9;
 816         v->max_dispclk[4] = v->max_dispclk_vmax0p9;
 817         v->max_dispclk[3] = v->max_dispclk_vmax0p9;
 818         v->max_dispclk[2] = v->max_dispclk_vnom0p8;
 819         v->max_dispclk[1] = v->max_dispclk_vmid0p72;
 820         v->max_dispclk[0] = v->max_dispclk_vmin0p65;
 821         v->max_dppclk[5] = v->max_dppclk_vmax0p9;
 822         v->max_dppclk[4] = v->max_dppclk_vmax0p9;
 823         v->max_dppclk[3] = v->max_dppclk_vmax0p9;
 824         v->max_dppclk[2] = v->max_dppclk_vnom0p8;
 825         v->max_dppclk[1] = v->max_dppclk_vmid0p72;
 826         v->max_dppclk[0] = v->max_dppclk_vmin0p65;
 827         v->phyclk_per_state[5] = v->phyclkv_max0p9;
 828         v->phyclk_per_state[4] = v->phyclkv_max0p9;
 829         v->phyclk_per_state[3] = v->phyclkv_max0p9;
 830         v->phyclk_per_state[2] = v->phyclkv_nom0p8;
 831         v->phyclk_per_state[1] = v->phyclkv_mid0p72;
 832         v->phyclk_per_state[0] = v->phyclkv_min0p65;
 833         v->synchronized_vblank = dcn_bw_no;
 834         v->ta_pscalculation = dcn_bw_override;
 835         v->allow_different_hratio_vratio = dcn_bw_yes;
 836
 837         for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
 838                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 839
 840                 if (!pipe->stream)
 841                         continue;
 842                 /* skip all but first of split pipes */
 843                 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
 844                         continue;
 845
 846                 v->underscan_output[input_idx] = false; /* taken care of in recout already*/
 847                 v->interlace_output[input_idx] = false;
 848
 849                 v->htotal[input_idx] = pipe->stream->timing.h_total;
 850                 v->vtotal[input_idx] = pipe->stream->timing.v_total;
 851                 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
 852                                 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
 853                 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
 854                                 - v->vactive[input_idx]
 855                                 - pipe->stream->timing.v_front_porch;
 856                 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
 857                 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 858                         v->pixel_clock[input_idx] *= 2;
 859                 if (!pipe->plane_state) {
 860                         v->dcc_enable[input_idx] = dcn_bw_yes;
 861                         v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
 862                         v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
 863                         v->lb_bit_per_pixel[input_idx] = 30;
 864                         v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
 865                         v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
 866                         v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;
 867                         v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;
 868                         v->override_hta_ps[input_idx] = 1;
 869                         v->override_vta_ps[input_idx] = 1;
 870                         v->override_hta_pschroma[input_idx] = 1;
 871                         v->override_vta_pschroma[input_idx] = 1;
 872                         v->source_scan[input_idx] = dcn_bw_hor;
 873
 874                 } else {
 875                         v->viewport_height[input_idx] =  pipe->plane_res.scl_data.viewport.height;
 876                         v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
 877                         v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
 878                         v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
 879                         if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
 880                                 if (pipe->plane_state->rotation % 2 == 0) {
 881                                         int viewport_end = pipe->plane_res.scl_data.viewport.width
 882                                                         + pipe->plane_res.scl_data.viewport.x;
 883                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
 884                                                         + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 885
 886                                         if (viewport_end > viewport_b_end)
 887                                                 v->viewport_width[input_idx] = viewport_end
 888                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
 889                                         else
 890                                                 v->viewport_width[input_idx] = viewport_b_end
 891                                                                         - pipe->plane_res.scl_data.viewport.x;
 892                                 } else  {
 893                                         int viewport_end = pipe->plane_res.scl_data.viewport.height
 894                                                 + pipe->plane_res.scl_data.viewport.y;
 895                                         int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
 896                                                 + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 897
 898                                         if (viewport_end > viewport_b_end)
 899                                                 v->viewport_height[input_idx] = viewport_end
 900                                                         - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
 901                                         else
 902                                                 v->viewport_height[input_idx] = viewport_b_end
 903                                                                         - pipe->plane_res.scl_data.viewport.y;
 904                                 }
 905                                 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
 906                                                 + pipe->bottom_pipe->plane_res.scl_data.recout.width;
 907                         }
 908
 909                         if (pipe->plane_state->rotation % 2 == 0) {
 910                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
 911                                         || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
 912                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
 913                                         || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
 914                         } else {
 915                                 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
 916                                         || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
 917                                 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
 918                                         || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
 919                         }
 920
 921                         if (dc->debug.optimized_watermark) {
 922                                 /*
 923                                  * this method requires us to always re-calculate watermark when dcc change
 924                                  * between flip.
 925                                  */
 926                                 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
 927                         } else {
 928                                 /*
 929                                  * allow us to disable dcc on the fly without re-calculating WM
 930                                  *
 931                                  * extra overhead for DCC is quite small.  for 1080p WM without
 932                                  * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
 933                                  */
 934                                 unsigned int bpe;
 935
 936                                 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
 937                                                 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
 938                         }
 939
 940                         v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
 941                                         pipe->plane_state->format);
 942                         v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
 943                                         pipe->plane_state->tiling_info.gfx9.swizzle);
 944                         v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
 945                         v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
 946                         v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
 947                         v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
 948                         v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
 949                         /*
 950                          * Spreadsheet doesn't handle taps_c is one properly,
 951                          * need to force Chroma to always be scaled to pass
 952                          * bandwidth validation.
 953                          */
 954                         if (v->override_hta_pschroma[input_idx] == 1)
 955                                 v->override_hta_pschroma[input_idx] = 2;
 956                         if (v->override_vta_pschroma[input_idx] == 1)
 957                                 v->override_vta_pschroma[input_idx] = 2;
 958                         v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
 959                 }
 960                 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
 961                         v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
 962                 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
 963                 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
 964                                 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
 965                 v->output[input_idx] = pipe->stream->signal ==
 966                                 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
 967                 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
 968                 if (v->output[input_idx] == dcn_bw_hdmi) {
 969                         switch (pipe->stream->timing.display_color_depth) {
 970                         case COLOR_DEPTH_101010:
 971                                 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
 972                                 break;
 973                         case COLOR_DEPTH_121212:
 974                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_12bpc;
 975                                 break;
 976                         case COLOR_DEPTH_161616:
 977                                 v->output_deep_color[input_idx]  = dcn_bw_encoder_16bpc;
 978                                 break;
 979                         default:
 980                                 break;
 981                         }
 982                 }
 983
 984                 input_idx++;
 985         }
 986         v->number_of_active_planes = input_idx;
 987
 988         scaler_settings_calculation(v);
 989
 990         hack_bounding_box(v, &dc->debug, context);
 991
 992         mode_support_and_system_configuration(v);
 993
 994         /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
 995         if (v->voltage_level != 0
 996                         && context->stream_count == 1
 997                         && dc->debug.force_single_disp_pipe_split) {
 998                 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
 999                 mode_support_and_system_configuration(v);
1000         }
1001
1002         if (v->voltage_level == 0 &&
1003                         (dc->debug.sr_exit_time_dpm0_ns
1004                                 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
1005
1006                 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
1007                         v->sr_enter_plus_exit_time =
1008                                 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1009                 if (dc->debug.sr_exit_time_dpm0_ns)
1010                         v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1011                 dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1012                 dc->dml.soc.sr_exit_time_us = v->sr_exit_time;
1013                 mode_support_and_system_configuration(v);
1014         }
1015
1016         if (v->voltage_level != 5) {
1017                 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1018                 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1019                         bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1020                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
1021                         bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
1022                 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
1023                         bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
1024                 else
1025                         bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
1026
1027                 if (bw_consumed < v->fabric_and_dram_bandwidth)
1028                         if (dc->debug.voltage_align_fclk)
1029                                 bw_consumed = v->fabric_and_dram_bandwidth;
1030
1031                 display_pipe_configuration(v);
1032                 /*calc_wm_sets_and_perf_params(context, v);*/
1033                 /* Only 1 set is used by dcn since no noticeable
1034                  * performance improvement was measured and due to hw bug DEGVIDCN10-254
1035                  */
1036                 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1037
1038                 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1039                         v->stutter_exit_watermark * 1000;
1040                 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1041                                 v->stutter_enter_plus_exit_watermark * 1000;
1042                 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1043                                 v->dram_clock_change_watermark * 1000;
1044                 context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1045                 context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1046                 context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
1047                 context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
1048                 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
1049
1050                 context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1051                                 (ddr4_dram_factor_single_Channel * v->number_of_channels));
1052                 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
1053                         context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1054                 }
1055
1056                 context->bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1057                 context->bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1058
1059                 context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1060                 if (dc->debug.max_disp_clk == true)
1061                         context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1062
1063                 if (context->bw.dcn.clk.dispclk_khz <
1064                                 dc->debug.min_disp_clk_khz) {
1065                         context->bw.dcn.clk.dispclk_khz =
1066                                         dc->debug.min_disp_clk_khz;
1067                 }
1068
1069                 context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio;
1070                 context->bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1071                 switch (v->voltage_level) {
1072                 case 0:
1073                         context->bw.dcn.clk.max_supported_dppclk_khz =
1074                                         (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1075                         break;
1076                 case 1:
1077                         context->bw.dcn.clk.max_supported_dppclk_khz =
1078                                         (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1079                         break;
1080                 case 2:
1081                         context->bw.dcn.clk.max_supported_dppclk_khz =
1082                                         (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1083                         break;
1084                 default:
1085                         context->bw.dcn.clk.max_supported_dppclk_khz =
1086                                         (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1087                         break;
1088                 }
1089
1090                 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1091                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1092
1093                         /* skip inactive pipe */
1094                         if (!pipe->stream)
1095                                 continue;
1096                         /* skip all but first of split pipes */
1097                         if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1098                                 continue;
1099
1100                         pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1101                         pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1102                         pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1103                         pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1104
1105                         pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1106                         pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1107                         vesa_sync_start = pipe->stream->timing.v_addressable +
1108                                                 pipe->stream->timing.v_border_bottom +
1109                                                 pipe->stream->timing.v_front_porch;
1110
1111                         asic_blank_end = (pipe->stream->timing.v_total -
1112                                                 vesa_sync_start -
1113                                                 pipe->stream->timing.v_border_top)
1114                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1115
1116                         asic_blank_start = asic_blank_end +
1117                                                 (pipe->stream->timing.v_border_top +
1118                                                 pipe->stream->timing.v_addressable +
1119                                                 pipe->stream->timing.v_border_bottom)
1120                         * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1121
1122                         pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1123                         pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1124
1125                         if (pipe->plane_state) {
1126                                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1127
1128                                 pipe->plane_state->update_flags.bits.full_update = 1;
1129
1130                                 if (v->dpp_per_plane[input_idx] == 2 ||
1131                                         ((pipe->stream->view_format ==
1132                                           VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1133                                           pipe->stream->view_format ==
1134                                           VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1135                                         (pipe->stream->timing.timing_3d_format ==
1136                                          TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1137                                          pipe->stream->timing.timing_3d_format ==
1138                                          TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1139                                         if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1140                                                 /* update previously split pipe */
1141                                                 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1142                                                 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1143                                                 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1144                                                 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1145
1146                                                 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1147                                                 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1148                                                 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1149                                                 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1150                                         } else {
1151                                                 /* pipe not split previously needs split */
1152                                                 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
1153                                                 ASSERT(hsplit_pipe);
1154                                                 split_stream_across_pipes(
1155                                                         &context->res_ctx, pool,
1156                                                         pipe, hsplit_pipe);
1157                                         }
1158
1159                                         dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1160                                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1161                                         /* merge previously split pipe */
1162                                         pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1163                                         if (hsplit_pipe->bottom_pipe)
1164                                                 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1165                                         hsplit_pipe->plane_state = NULL;
1166                                         hsplit_pipe->stream = NULL;
1167                                         hsplit_pipe->top_pipe = NULL;
1168                                         hsplit_pipe->bottom_pipe = NULL;
1169                                         /* Clear plane_res and stream_res */
1170                                         memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1171                                         memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1172                                         resource_build_scaling_params(pipe);
1173                                 }
1174                                 /* for now important to do this after pipe split for building e2e params */
1175                                 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1176                         }
1177
1178                         input_idx++;
1179                 }
1180         }
1181
1182         if (v->voltage_level == 0) {
1183
1184                 dc->dml.soc.sr_enter_plus_exit_time_us =
1185                                 dc->dcn_soc->sr_enter_plus_exit_time;
1186                 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1187         }
1188
1189         /*
1190          * BW limit is set to prevent display from impacting other system functions
1191          */
1192
1193         bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1194         bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1195
1196         kernel_fpu_end();
1197
1198         PERFORMANCE_TRACE_END();
1199
1200         if (bw_limit_pass && v->voltage_level != 5)
1201                 return true;
1202         else
1203                 return false;
1204 }
1205
1206 static unsigned int dcn_find_normalized_clock_vdd_Level(
1207         const struct dc *dc,
1208         enum dm_pp_clock_type clocks_type,
1209         int clocks_in_khz)
1210 {
1211         int vdd_level = dcn_bw_v_min0p65;
1212
1213         if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1214                 return vdd_level;
1215
1216         switch (clocks_type) {
1217         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1218                 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1219                         vdd_level = dcn_bw_v_max0p91;
1220                         BREAK_TO_DEBUGGER();
1221                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1222                         vdd_level = dcn_bw_v_max0p9;
1223                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1224                         vdd_level = dcn_bw_v_nom0p8;
1225                 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1226                         vdd_level = dcn_bw_v_mid0p72;
1227                 } else
1228                         vdd_level = dcn_bw_v_min0p65;
1229                 break;
1230         case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1231                 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1232                         vdd_level = dcn_bw_v_max0p91;
1233                         BREAK_TO_DEBUGGER();
1234                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1235                         vdd_level = dcn_bw_v_max0p9;
1236                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1237                         vdd_level = dcn_bw_v_nom0p8;
1238                 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1239                         vdd_level = dcn_bw_v_mid0p72;
1240                 } else
1241                         vdd_level = dcn_bw_v_min0p65;
1242                 break;
1243
1244         case DM_PP_CLOCK_TYPE_DPPCLK:
1245                 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1246                         vdd_level = dcn_bw_v_max0p91;
1247                         BREAK_TO_DEBUGGER();
1248                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1249                         vdd_level = dcn_bw_v_max0p9;
1250                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1251                         vdd_level = dcn_bw_v_nom0p8;
1252                 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1253                         vdd_level = dcn_bw_v_mid0p72;
1254                 } else
1255                         vdd_level = dcn_bw_v_min0p65;
1256                 break;
1257
1258         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1259                 {
1260                         unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1261
1262                         if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1263                                 vdd_level = dcn_bw_v_max0p91;
1264                                 BREAK_TO_DEBUGGER();
1265                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1266                                 vdd_level = dcn_bw_v_max0p9;
1267                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1268                                 vdd_level = dcn_bw_v_nom0p8;
1269                         } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1270                                 vdd_level = dcn_bw_v_mid0p72;
1271                         } else
1272                                 vdd_level = dcn_bw_v_min0p65;
1273                 }
1274                 break;
1275
1276         case DM_PP_CLOCK_TYPE_DCFCLK:
1277                 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1278                         vdd_level = dcn_bw_v_max0p91;
1279                         BREAK_TO_DEBUGGER();
1280                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1281                         vdd_level = dcn_bw_v_max0p9;
1282                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1283                         vdd_level = dcn_bw_v_nom0p8;
1284                 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1285                         vdd_level = dcn_bw_v_mid0p72;
1286                 } else
1287                         vdd_level = dcn_bw_v_min0p65;
1288                 break;
1289
1290         default:
1291                  break;
1292         }
1293         return vdd_level;
1294 }
1295
1296 unsigned int dcn_find_dcfclk_suits_all(
1297         const struct dc *dc,
1298         struct dc_clocks *clocks)
1299 {
1300         unsigned vdd_level, vdd_level_temp;
1301         unsigned dcf_clk;
1302
1303         /*find a common supported voltage level*/
1304         vdd_level = dcn_find_normalized_clock_vdd_Level(
1305                 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
1306         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1307                 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
1308
1309         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1310         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1311                 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
1312         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1313
1314         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1315                 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
1316         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1317         vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1318                 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
1319
1320         /*find that level conresponding dcfclk*/
1321         vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1322         if (vdd_level == dcn_bw_v_max0p91) {
1323                 BREAK_TO_DEBUGGER();
1324                 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1325         } else if (vdd_level == dcn_bw_v_max0p9)
1326                 dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
1327         else if (vdd_level == dcn_bw_v_nom0p8)
1328                 dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
1329         else if (vdd_level == dcn_bw_v_mid0p72)
1330                 dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
1331         else
1332                 dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
1333
1334         DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1335         return dcf_clk;
1336 }
1337
1338 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1339 {
1340         int i;
1341
1342         if (clks->num_levels == 0)
1343                 return false;
1344
1345         for (i = 0; i < clks->num_levels; i++)
1346                 /* Ensure that the result is sane */
1347                 if (clks->data[i].clocks_in_khz == 0)
1348                         return false;
1349
1350         return true;
1351 }
1352
1353 void dcn_bw_update_from_pplib(struct dc *dc)
1354 {
1355         struct dc_context *ctx = dc->ctx;
1356         struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1357         bool res;
1358
1359         /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1360         res = dm_pp_get_clock_levels_by_type_with_voltage(
1361                         ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1362
1363         kernel_fpu_begin();
1364
1365         if (res)
1366                 res = verify_clock_values(&fclks);
1367
1368         if (res) {
1369                 ASSERT(fclks.num_levels >= 3);
1370                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
1371                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
1372                                 (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
1373                                 * ddr4_dram_factor_single_Channel / 1000.0;
1374                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
1375                                 (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
1376                                 * ddr4_dram_factor_single_Channel / 1000.0;
1377                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
1378                                 (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
1379                                 * ddr4_dram_factor_single_Channel / 1000.0;
1380         } else
1381                 BREAK_TO_DEBUGGER();
1382
1383         kernel_fpu_end();
1384
1385         res = dm_pp_get_clock_levels_by_type_with_voltage(
1386                         ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1387
1388         kernel_fpu_begin();
1389
1390         if (res)
1391                 res = verify_clock_values(&dcfclks);
1392
1393         if (res && dcfclks.num_levels >= 3) {
1394                 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1395                 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1396                 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1397                 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1398         } else
1399                 BREAK_TO_DEBUGGER();
1400
1401         kernel_fpu_end();
1402 }
1403
1404 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1405 {
1406         struct pp_smu_funcs_rv *pp = NULL;
1407         struct pp_smu_wm_range_sets ranges = {0};
1408         int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1409         const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1410
1411         if (dc->res_pool->pp_smu)
1412                 pp = &dc->res_pool->pp_smu->rv_funcs;
1413         if (!pp || !pp->set_wm_ranges)
1414                 return;
1415
1416         kernel_fpu_begin();
1417         min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1418         min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1419         socclk_khz = dc->dcn_soc->socclk * 1000;
1420         kernel_fpu_end();
1421
1422         /* Now notify PPLib/SMU about which Watermarks sets they should select
1423          * depending on DPM state they are in. And update BW MGR GFX Engine and
1424          * Memory clock member variables for Watermarks calculations for each
1425          * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
1426          */
1427         /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1428          * care what the value is, hence min to overdrive level
1429          */
1430         ranges.num_reader_wm_sets = WM_SET_COUNT;
1431         ranges.num_writer_wm_sets = WM_SET_COUNT;
1432         ranges.reader_wm_sets[0].wm_inst = WM_A;
1433         ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1434         ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1435         ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1436         ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1437         ranges.writer_wm_sets[0].wm_inst = WM_A;
1438         ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1439         ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1440         ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1441         ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1442
1443         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1444                 ranges.reader_wm_sets[0].wm_inst = WM_A;
1445                 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1446                 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1447                 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1448                 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1449                 ranges.writer_wm_sets[0].wm_inst = WM_A;
1450                 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1451                 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1452                 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1453                 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1454         }
1455
1456         ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
1457         ranges.reader_wm_sets[1].wm_inst = WM_B;
1458
1459         ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
1460         ranges.reader_wm_sets[2].wm_inst = WM_C;
1461
1462         ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
1463         ranges.reader_wm_sets[3].wm_inst = WM_D;
1464
1465         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1466         pp->set_wm_ranges(&pp->pp_smu, &ranges);
1467 }
1468
1469 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1470 {
1471         kernel_fpu_begin();
1472         DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1473                         "sr_enter_plus_exit_time: %f ns\n"
1474                         "urgent_latency: %f ns\n"
1475                         "write_back_latency: %f ns\n"
1476                         "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1477                         "max_request_size: %d bytes\n"
1478                         "dcfclkv_max0p9: %f kHz\n"
1479                         "dcfclkv_nom0p8: %f kHz\n"
1480                         "dcfclkv_mid0p72: %f kHz\n"
1481                         "dcfclkv_min0p65: %f kHz\n"
1482                         "max_dispclk_vmax0p9: %f kHz\n"
1483                         "max_dispclk_vnom0p8: %f kHz\n"
1484                         "max_dispclk_vmid0p72: %f kHz\n"
1485                         "max_dispclk_vmin0p65: %f kHz\n"
1486                         "max_dppclk_vmax0p9: %f kHz\n"
1487                         "max_dppclk_vnom0p8: %f kHz\n"
1488                         "max_dppclk_vmid0p72: %f kHz\n"
1489                         "max_dppclk_vmin0p65: %f kHz\n"
1490                         "socclk: %f kHz\n"
1491                         "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1492                         "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1493                         "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1494                         "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1495                         "phyclkv_max0p9: %f kHz\n"
1496                         "phyclkv_nom0p8: %f kHz\n"
1497                         "phyclkv_mid0p72: %f kHz\n"
1498                         "phyclkv_min0p65: %f kHz\n"
1499                         "downspreading: %f %%\n"
1500                         "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1501                         "urgent_out_of_order_return_per_channel: %d Bytes\n"
1502                         "number_of_channels: %d\n"
1503                         "vmm_page_size: %d Bytes\n"
1504                         "dram_clock_change_latency: %f ns\n"
1505                         "return_bus_width: %d Bytes\n",
1506                         dc->dcn_soc->sr_exit_time * 1000,
1507                         dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1508                         dc->dcn_soc->urgent_latency * 1000,
1509                         dc->dcn_soc->write_back_latency * 1000,
1510                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1511                         dc->dcn_soc->max_request_size,
1512                         dc->dcn_soc->dcfclkv_max0p9 * 1000,
1513                         dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1514                         dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1515                         dc->dcn_soc->dcfclkv_min0p65 * 1000,
1516                         dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1517                         dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1518                         dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1519                         dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1520                         dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1521                         dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1522                         dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1523                         dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1524                         dc->dcn_soc->socclk * 1000,
1525                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1526                         dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1527                         dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1528                         dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1529                         dc->dcn_soc->phyclkv_max0p9 * 1000,
1530                         dc->dcn_soc->phyclkv_nom0p8 * 1000,
1531                         dc->dcn_soc->phyclkv_mid0p72 * 1000,
1532                         dc->dcn_soc->phyclkv_min0p65 * 1000,
1533                         dc->dcn_soc->downspreading * 100,
1534                         dc->dcn_soc->round_trip_ping_latency_cycles,
1535                         dc->dcn_soc->urgent_out_of_order_return_per_channel,
1536                         dc->dcn_soc->number_of_channels,
1537                         dc->dcn_soc->vmm_page_size,
1538                         dc->dcn_soc->dram_clock_change_latency * 1000,
1539                         dc->dcn_soc->return_bus_width);
1540         DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1541                         "det_buffer_size_in_kbyte: %f\n"
1542                         "dpp_output_buffer_pixels: %f\n"
1543                         "opp_output_buffer_lines: %f\n"
1544                         "pixel_chunk_size_in_kbyte: %f\n"
1545                         "pte_enable: %d\n"
1546                         "pte_chunk_size: %d kbytes\n"
1547                         "meta_chunk_size: %d kbytes\n"
1548                         "writeback_chunk_size: %d kbytes\n"
1549                         "odm_capability: %d\n"
1550                         "dsc_capability: %d\n"
1551                         "line_buffer_size: %d bits\n"
1552                         "max_line_buffer_lines: %d\n"
1553                         "is_line_buffer_bpp_fixed: %d\n"
1554                         "line_buffer_fixed_bpp: %d\n"
1555                         "writeback_luma_buffer_size: %d kbytes\n"
1556                         "writeback_chroma_buffer_size: %d kbytes\n"
1557                         "max_num_dpp: %d\n"
1558                         "max_num_writeback: %d\n"
1559                         "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1560                         "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1561                         "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1562                         "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1563                         "max_hscl_ratio: %f\n"
1564                         "max_vscl_ratio: %f\n"
1565                         "max_hscl_taps: %d\n"
1566                         "max_vscl_taps: %d\n"
1567                         "pte_buffer_size_in_requests: %d\n"
1568                         "dispclk_ramping_margin: %f %%\n"
1569                         "under_scan_factor: %f %%\n"
1570                         "max_inter_dcn_tile_repeaters: %d\n"
1571                         "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1572                         "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1573                         "dcfclk_cstate_latency: %d\n",
1574                         dc->dcn_ip->rob_buffer_size_in_kbyte,
1575                         dc->dcn_ip->det_buffer_size_in_kbyte,
1576                         dc->dcn_ip->dpp_output_buffer_pixels,
1577                         dc->dcn_ip->opp_output_buffer_lines,
1578                         dc->dcn_ip->pixel_chunk_size_in_kbyte,
1579                         dc->dcn_ip->pte_enable,
1580                         dc->dcn_ip->pte_chunk_size,
1581                         dc->dcn_ip->meta_chunk_size,
1582                         dc->dcn_ip->writeback_chunk_size,
1583                         dc->dcn_ip->odm_capability,
1584                         dc->dcn_ip->dsc_capability,
1585                         dc->dcn_ip->line_buffer_size,
1586                         dc->dcn_ip->max_line_buffer_lines,
1587                         dc->dcn_ip->is_line_buffer_bpp_fixed,
1588                         dc->dcn_ip->line_buffer_fixed_bpp,
1589                         dc->dcn_ip->writeback_luma_buffer_size,
1590                         dc->dcn_ip->writeback_chroma_buffer_size,
1591                         dc->dcn_ip->max_num_dpp,
1592                         dc->dcn_ip->max_num_writeback,
1593                         dc->dcn_ip->max_dchub_topscl_throughput,
1594                         dc->dcn_ip->max_pscl_tolb_throughput,
1595                         dc->dcn_ip->max_lb_tovscl_throughput,
1596                         dc->dcn_ip->max_vscl_tohscl_throughput,
1597                         dc->dcn_ip->max_hscl_ratio,
1598                         dc->dcn_ip->max_vscl_ratio,
1599                         dc->dcn_ip->max_hscl_taps,
1600                         dc->dcn_ip->max_vscl_taps,
1601                         dc->dcn_ip->pte_buffer_size_in_requests,
1602                         dc->dcn_ip->dispclk_ramping_margin,
1603                         dc->dcn_ip->under_scan_factor * 100,
1604                         dc->dcn_ip->max_inter_dcn_tile_repeaters,
1605                         dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1606                         dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1607                         dc->dcn_ip->dcfclk_cstate_latency);
1608
1609         dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1610         dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1611         dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1612         dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1613         dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1614                         dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1615         dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1616         dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1617         dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1618                         dc->dcn_soc->round_trip_ping_latency_cycles;
1619         dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1620                         dc->dcn_soc->urgent_out_of_order_return_per_channel;
1621         dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1622         dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1623         dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1624         dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1625
1626         dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1627         dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1628         dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1629         dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1630         dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1631         dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1632         dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1633         dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1634         dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1635         dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1636         dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1637         dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1638         dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1639         dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1640         dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1641         dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1642         dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1643         dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1644         dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1645         dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1646         dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1647         dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1648         dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1649         dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1650         dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1651         /*pte_buffer_size_in_requests missing in dml*/
1652         dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1653         dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1654         dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1655         dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1656                 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1657         dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1658                 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1659         dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1660         kernel_fpu_end();
1661 }