drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "amdgpu_dm_hdcp.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_dm.h"
  29 #include "dm_helpers.h"
  30 #include <drm/drm_hdcp.h>
  31
  32 bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
  33 {
  34
  35         struct dc_link *link = handle;
  36         struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
  37         struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
  38
  39         return dm_helpers_submit_i2c(link->ctx, link, &cmd);
  40 }
  41
  42 bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)
  43 {
  44         struct dc_link *link = handle;
  45
  46         struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, {false, address, size, data} };
  47         struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
  48
  49         return dm_helpers_submit_i2c(link->ctx, link, &cmd);
  50 }
  51
  52 bool lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
  53 {
  54         struct dc_link *link = handle;
  55
  56         return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
  57 }
  58
  59 bool lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
  60 {
  61         struct dc_link *link = handle;
  62
  63         return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size);
  64 }
  65
  66 static void process_output(struct hdcp_workqueue *hdcp_work)
  67 {
  68         struct mod_hdcp_output output = hdcp_work->output;
  69
  70         if (output.callback_stop)
  71                 cancel_delayed_work(&hdcp_work->callback_dwork);
  72
  73         if (output.callback_needed)
  74                 schedule_delayed_work(&hdcp_work->callback_dwork,
  75                                       msecs_to_jiffies(output.callback_delay));
  76
  77         if (output.watchdog_timer_stop)
  78                 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
  79
  80         if (output.watchdog_timer_needed)
  81                 schedule_delayed_work(&hdcp_work->watchdog_timer_dwork,
  82                                       msecs_to_jiffies(output.watchdog_timer_delay));
  83
  84 }
  85
  86 void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector)
  87 {
  88         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
  89         struct mod_hdcp_display *display = &hdcp_work[link_index].display;
  90         struct mod_hdcp_link *link = &hdcp_work[link_index].link;
  91
  92         mutex_lock(&hdcp_w->mutex);
  93         hdcp_w->aconnector = aconnector;
  94
  95         mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
  96
  97         schedule_delayed_work(&hdcp_w->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
  98
  99         process_output(hdcp_w);
 100
 101         mutex_unlock(&hdcp_w->mutex);
 102
 103 }
 104
 105 void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,  unsigned int display_index)
 106 {
 107         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
 108
 109         mutex_lock(&hdcp_w->mutex);
 110
 111         mod_hdcp_remove_display(&hdcp_w->hdcp, display_index, &hdcp_w->output);
 112
 113         cancel_delayed_work(&hdcp_w->property_validate_dwork);
 114         hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 115
 116         process_output(hdcp_w);
 117
 118         mutex_unlock(&hdcp_w->mutex);
 119
 120 }
 121
 122 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
 123 {
 124         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
 125
 126         mutex_lock(&hdcp_w->mutex);
 127
 128         mod_hdcp_reset_connection(&hdcp_w->hdcp,  &hdcp_w->output);
 129
 130         cancel_delayed_work(&hdcp_w->property_validate_dwork);
 131         hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 132
 133         process_output(hdcp_w);
 134
 135         mutex_unlock(&hdcp_w->mutex);
 136 }
 137
 138 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
 139 {
 140         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
 141
 142         schedule_work(&hdcp_w->cpirq_work);
 143 }
 144
 145
 146
 147
 148 static void event_callback(struct work_struct *work)
 149 {
 150         struct hdcp_workqueue *hdcp_work;
 151
 152         hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue,
 153                                       callback_dwork);
 154
 155         mutex_lock(&hdcp_work->mutex);
 156
 157         cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
 158
 159         mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK,
 160                                &hdcp_work->output);
 161
 162         process_output(hdcp_work);
 163
 164         mutex_unlock(&hdcp_work->mutex);
 165
 166
 167 }
 168 static void event_property_update(struct work_struct *work)
 169 {
 170
 171         struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, property_update_work);
 172         struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
 173         struct drm_device *dev = hdcp_work->aconnector->base.dev;
 174         long ret;
 175
 176         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 177         mutex_lock(&hdcp_work->mutex);
 178
 179
 180         if (aconnector->base.state->commit) {
 181                 ret = wait_for_completion_interruptible_timeout(&aconnector->base.state->commit->hw_done, 10 * HZ);
 182
 183                 if (ret == 0) {
 184                         DRM_ERROR("HDCP state unknown! Setting it to DESIRED");
 185                         hdcp_work->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 186                 }
 187         }
 188
 189         if (hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON)
 190                 drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
 191         else
 192                 drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED);
 193
 194
 195         mutex_unlock(&hdcp_work->mutex);
 196         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 197 }
 198
 199 static void event_property_validate(struct work_struct *work)
 200 {
 201         struct hdcp_workqueue *hdcp_work =
 202                 container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork);
 203         struct mod_hdcp_display_query query;
 204         struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
 205
 206         mutex_lock(&hdcp_work->mutex);
 207
 208         query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 209         mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, &query);
 210
 211         if (query.encryption_status != hdcp_work->encryption_status) {
 212                 hdcp_work->encryption_status = query.encryption_status;
 213                 schedule_work(&hdcp_work->property_update_work);
 214         }
 215
 216         schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
 217
 218         mutex_unlock(&hdcp_work->mutex);
 219 }
 220
 221 static void event_watchdog_timer(struct work_struct *work)
 222 {
 223         struct hdcp_workqueue *hdcp_work;
 224
 225         hdcp_work = container_of(to_delayed_work(work),
 226                                       struct hdcp_workqueue,
 227                                       watchdog_timer_dwork);
 228
 229         mutex_lock(&hdcp_work->mutex);
 230
 231         mod_hdcp_process_event(&hdcp_work->hdcp,
 232                                MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
 233                                &hdcp_work->output);
 234
 235         process_output(hdcp_work);
 236
 237         mutex_unlock(&hdcp_work->mutex);
 238
 239 }
 240
 241 static void event_cpirq(struct work_struct *work)
 242 {
 243         struct hdcp_workqueue *hdcp_work;
 244
 245         hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work);
 246
 247         mutex_lock(&hdcp_work->mutex);
 248
 249         mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output);
 250
 251         process_output(hdcp_work);
 252
 253         mutex_unlock(&hdcp_work->mutex);
 254
 255 }
 256
 257
 258 void hdcp_destroy(struct hdcp_workqueue *hdcp_work)
 259 {
 260         int i = 0;
 261
 262         for (i = 0; i < hdcp_work->max_link; i++) {
 263                 cancel_delayed_work_sync(&hdcp_work[i].callback_dwork);
 264                 cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork);
 265         }
 266
 267         kfree(hdcp_work);
 268
 269 }
 270
 271 static void update_config(void *handle, struct cp_psp_stream_config *config)
 272 {
 273         struct hdcp_workqueue *hdcp_work = handle;
 274         struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx;
 275         int link_index = aconnector->dc_link->link_index;
 276         struct mod_hdcp_display *display = &hdcp_work[link_index].display;
 277         struct mod_hdcp_link *link = &hdcp_work[link_index].link;
 278
 279         memset(display, 0, sizeof(*display));
 280         memset(link, 0, sizeof(*link));
 281
 282         display->index = aconnector->base.index;
 283         display->state = MOD_HDCP_DISPLAY_ACTIVE;
 284
 285         if (aconnector->dc_sink != NULL)
 286                 link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal);
 287
 288         display->controller = CONTROLLER_ID_D0 + config->otg_inst;
 289         display->dig_fe = config->stream_enc_inst;
 290         link->dig_be = config->link_enc_inst;
 291         link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
 292         link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 293         link->adjust.hdcp2.disable = 1;
 294
 295 }
 296
 297 struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc)
 298 {
 299
 300         int max_caps = dc->caps.max_links;
 301         struct hdcp_workqueue *hdcp_work = kzalloc(max_caps*sizeof(*hdcp_work), GFP_KERNEL);
 302         int i = 0;
 303
 304         if (hdcp_work == NULL)
 305                 goto fail_alloc_context;
 306
 307         hdcp_work->max_link = max_caps;
 308
 309         for (i = 0; i < max_caps; i++) {
 310
 311                 mutex_init(&hdcp_work[i].mutex);
 312
 313                 INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq);
 314                 INIT_WORK(&hdcp_work[i].property_update_work, event_property_update);
 315                 INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback);
 316                 INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer);
 317                 INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
 318
 319                 hdcp_work[i].hdcp.config.psp.handle =  psp_context;
 320                 hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
 321                 hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
 322                 hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
 323                 hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd;
 324                 hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd;
 325         }
 326
 327         cp_psp->funcs.update_stream_config = update_config;
 328         cp_psp->handle = hdcp_work;
 329
 330         return hdcp_work;
 331
 332 fail_alloc_context:
 333         kfree(hdcp_work);
 334
 335         return NULL;
 336
 337
 338
 339 }
 340
 341
 342