2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_connector.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_dp_mst_helper.h>
33 #include <drm/drm_plane.h>
36 * This file contains the definition for amdgpu_display_manager
37 * and its API for amdgpu driver's use.
38 * This component provides all the display related functionality
39 * and this is the only component that calls DAL API.
40 * The API contained here intended for amdgpu driver use.
41 * The API that is called directly from KMS framework is located
42 * in amdgpu_dm_kms.h file
45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
47 #define AMDGPU_DM_MAX_CRTC 6
50 #include "include/amdgpu_dal_power_if.h"
51 #include "amdgpu_dm_irq.h"
54 #include "irq_types.h"
55 #include "signal_types.h"
56 #include "amdgpu_dm_crc.h"
58 /* Forward declarations */
61 struct amdgpu_dm_irq_handler_data;
66 struct common_irq_params {
67 struct amdgpu_device *adev;
68 enum dc_irq_source irq_src;
72 * struct irq_list_head - Linked-list for low context IRQ handlers.
74 * @head: The list_head within &struct handler_data
75 * @work: A work_struct containing the deferred handler work
77 struct irq_list_head {
78 struct list_head head;
79 /* In case this interrupt needs post-processing, 'work' will be queued*/
80 struct work_struct work;
84 * struct dm_compressor_info - Buffer info used by frame buffer compression
85 * @cpu_addr: MMIO cpu addr
86 * @bo_ptr: Pointer to the buffer object
87 * @gpu_addr: MMIO gpu addr
89 struct dm_compressor_info {
91 struct amdgpu_bo *bo_ptr;
96 * struct amdgpu_dm_backlight_caps - Information about backlight
98 * Describe the backlight support for ACPI or eDP AUX.
100 struct amdgpu_dm_backlight_caps {
102 * @ext_caps: Keep the data struct with all the information about the
103 * display support for HDR.
105 union dpcd_sink_ext_caps *ext_caps;
107 * @aux_min_input_signal: Min brightness value supported by the display
109 u32 aux_min_input_signal;
111 * @aux_max_input_signal: Max brightness value supported by the display
114 u32 aux_max_input_signal;
116 * @min_input_signal: minimum possible input in range 0-255.
118 int min_input_signal;
120 * @max_input_signal: maximum possible input in range 0-255.
122 int max_input_signal;
124 * @caps_valid: true if these values are from the ACPI interface.
128 * @aux_support: Describes if the display supports AUX backlight.
134 * struct amdgpu_display_manager - Central amdgpu display manager device
136 * @dc: Display Core control structure
137 * @adev: AMDGPU base driver structure
138 * @ddev: DRM base driver structure
139 * @display_indexes_num: Max number of display streams supported
140 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
141 * @backlight_dev: Backlight control device
142 * @backlight_link: Link on which to control backlight
143 * @backlight_caps: Capabilities of the backlight device
144 * @freesync_module: Module handling freesync calculations
145 * @hdcp_workqueue: AMDGPU content protection queue
146 * @fw_dmcu: Reference to DMCU firmware
147 * @dmcu_fw_version: Version of the DMCU firmware
148 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
149 * @cached_state: Caches device atomic state for suspend/resume
150 * @cached_dc_state: Cached state of content streams
151 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
152 * @force_timing_sync: set via debugfs. When set, indicates that all connected
153 * displays will be forced to synchronize.
155 struct amdgpu_display_manager {
162 * DMUB service, used for controlling the DMUB on hardware
163 * that supports it. The pointer to the dmub_srv will be
164 * NULL on hardware that does not support it.
166 struct dmub_srv *dmub_srv;
171 * Framebuffer regions for the DMUB.
173 struct dmub_srv_fb_info *dmub_fb_info;
178 * DMUB firmware, required on hardware that has DMUB support.
180 const struct firmware *dmub_fw;
185 * Buffer object for the DMUB.
187 struct amdgpu_bo *dmub_bo;
192 * GPU virtual address for the DMUB buffer object.
194 u64 dmub_bo_gpu_addr;
199 * CPU address for the DMUB buffer object.
201 void *dmub_bo_cpu_addr;
206 * DMCUB firmware version.
208 uint32_t dmcub_fw_version;
213 * The Common Graphics Services device. It provides an interface for
214 * accessing registers.
216 struct cgs_device *cgs_device;
218 struct amdgpu_device *adev;
219 struct drm_device *ddev;
220 u16 display_indexes_num;
225 * In combination with &dm_atomic_state it helps manage
226 * global atomic state that doesn't map cleanly into existing
227 * drm resources, like &dc_context.
229 struct drm_private_obj atomic_obj;
234 * Guards access to DC functions that can issue register write
237 struct mutex dc_lock;
242 * Guards access to audio instance changes.
244 struct mutex audio_lock;
249 * Used to notify ELD changes to sound driver.
251 struct drm_audio_component *audio_component;
256 * True if the audio component has been registered
257 * successfully, false otherwise.
259 bool audio_registered;
262 * @irq_handler_list_low_tab:
264 * Low priority IRQ handler table.
266 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
267 * source. Low priority IRQ handlers are deferred to a workqueue to be
268 * processed. Hence, they can sleep.
270 * Note that handlers are called in the same order as they were
273 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
276 * @irq_handler_list_high_tab:
278 * High priority IRQ handler table.
280 * It is a n*m table, same as &irq_handler_list_low_tab. However,
281 * handlers in this table are not deferred and are called immediately.
283 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
288 * Page flip IRQ parameters, passed to registered handlers when
291 struct common_irq_params
292 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
297 * Vertical blanking IRQ parameters, passed to registered handlers when
300 struct common_irq_params
301 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
306 * Vertical update IRQ parameters, passed to registered handlers when
309 struct common_irq_params
310 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
312 spinlock_t irq_handler_list_table_lock;
314 struct backlight_device *backlight_dev;
316 const struct dc_link *backlight_link;
317 struct amdgpu_dm_backlight_caps backlight_caps;
319 struct mod_freesync *freesync_module;
320 #ifdef CONFIG_DRM_AMD_DC_HDCP
321 struct hdcp_workqueue *hdcp_workqueue;
324 struct drm_atomic_state *cached_state;
325 struct dc_state *cached_dc_state;
327 struct dm_compressor_info compressor;
329 const struct firmware *fw_dmcu;
330 uint32_t dmcu_fw_version;
334 * gpu_info FW provided soc bounding box struct or 0 if not
337 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
339 #ifdef CONFIG_DEBUG_FS
340 /* set the crc calculation window*/
341 struct drm_property *crc_win_x_start_property;
342 struct drm_property *crc_win_y_start_property;
343 struct drm_property *crc_win_x_end_property;
344 struct drm_property *crc_win_y_end_property;
349 * fake encoders used for DP MST.
351 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
352 bool force_timing_sync;
355 enum dsc_clock_force_state {
356 DSC_CLK_FORCE_DEFAULT = 0,
357 DSC_CLK_FORCE_ENABLE,
358 DSC_CLK_FORCE_DISABLE,
361 struct dsc_preferred_settings {
362 enum dsc_clock_force_state dsc_force_enable;
363 uint32_t dsc_num_slices_v;
364 uint32_t dsc_num_slices_h;
365 uint32_t dsc_bits_per_pixel;
368 struct amdgpu_dm_connector {
370 struct drm_connector base;
371 uint32_t connector_id;
373 /* we need to mind the EDID between detect
374 and get modes due to analog/digital/tvencoder */
377 /* shared with amdgpu */
378 struct amdgpu_hpd hpd;
380 /* number of modes generated from EDID at 'dc_sink' */
383 /* The 'old' sink - before an HPD.
384 * The 'current' sink is in dc_link->sink. */
385 struct dc_sink *dc_sink;
386 struct dc_link *dc_link;
387 struct dc_sink *dc_em_sink;
390 struct drm_dp_mst_topology_mgr mst_mgr;
391 struct amdgpu_dm_dp_aux dm_dp_aux;
392 struct drm_dp_mst_port *port;
393 struct amdgpu_dm_connector *mst_port;
394 struct drm_dp_aux *dsc_aux;
396 /* TODO see if we can merge with ddc_bus or make a dm_connector */
397 struct amdgpu_i2c_adapter *i2c;
399 /* Monitor range limits */
404 /* Audio instance - protected by audio_lock. */
407 struct mutex hpd_lock;
410 #ifdef CONFIG_DEBUG_FS
411 uint32_t debugfs_dpcd_address;
412 uint32_t debugfs_dpcd_size;
414 bool force_yuv420_output;
415 struct dsc_preferred_settings dsc_settings;
418 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
420 extern const struct amdgpu_ip_block_version dm_ip_block;
422 struct amdgpu_framebuffer;
423 struct amdgpu_display_manager;
424 struct dc_validation_set;
425 struct dc_plane_state;
427 struct dm_plane_state {
428 struct drm_plane_state base;
429 struct dc_plane_state *dc_state;
432 #ifdef CONFIG_DEBUG_FS
441 struct dm_crtc_state {
442 struct drm_crtc_state base;
443 struct dc_stream_state *stream;
446 bool cm_is_degamma_srgb;
452 enum amdgpu_dm_pipe_crc_source crc_src;
454 bool freesync_timing_changed;
455 bool freesync_vrr_info_changed;
457 bool dsc_force_changed;
459 struct mod_freesync_config freesync_config;
460 struct dc_info_packet vrr_infopacket;
463 #ifdef CONFIG_DEBUG_FS
464 struct crc_rec crc_window;
468 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
470 struct dm_atomic_state {
471 struct drm_private_state base;
473 struct dc_state *context;
476 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
478 struct dm_connector_state {
479 struct drm_connector_state base;
481 enum amdgpu_rmx_type scaling;
482 uint8_t underscan_vborder;
483 uint8_t underscan_hborder;
484 bool underscan_enable;
485 bool freesync_capable;
486 #ifdef CONFIG_DRM_AMD_DC_HDCP
494 #define to_dm_connector_state(x)\
495 container_of((x), struct dm_connector_state, base)
497 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
498 struct drm_connector_state *
499 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
500 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
501 struct drm_connector_state *state,
502 struct drm_property *property,
505 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
506 const struct drm_connector_state *state,
507 struct drm_property *property,
510 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
512 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
513 struct amdgpu_dm_connector *aconnector,
515 struct dc_link *link,
518 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
519 struct drm_display_mode *mode);
521 void dm_restore_drm_connector_state(struct drm_device *dev,
522 struct drm_connector *connector);
524 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
527 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
529 #define MAX_COLOR_LUT_ENTRIES 4096
530 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
531 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
533 void amdgpu_dm_init_color_mod(void);
534 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
535 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
536 struct dc_plane_state *dc_plane_state);
538 void amdgpu_dm_update_connector_after_detect(
539 struct amdgpu_dm_connector *aconnector);
541 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
543 #endif /* __AMDGPU_DM_H__ */