drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c

   1 /*
   2  * Copyright 2016-2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "kfd_kernel_queue.h"
  25 #include "kfd_device_queue_manager.h"
  26 #include "kfd_pm4_headers_ai.h"
  27 #include "kfd_pm4_opcodes.h"
  28 #include "gc/gc_10_1_0_sh_mask.h"
  29
  30 static int pm_map_process_v9(struct packet_manager *pm,
  31                 uint32_t *buffer, struct qcm_process_device *qpd)
  32 {
  33         struct pm4_mes_map_process *packet;
  34         uint64_t vm_page_table_base_addr = qpd->page_table_base;
  35
  36         packet = (struct pm4_mes_map_process *)buffer;
  37         memset(buffer, 0, sizeof(struct pm4_mes_map_process));
  38
  39         packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
  40                                         sizeof(struct pm4_mes_map_process));
  41         packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
  42         packet->bitfields2.process_quantum = 1;
  43         packet->bitfields2.pasid = qpd->pqm->process->pasid;
  44         packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
  45         packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
  46         packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
  47         packet->bitfields14.num_oac = qpd->num_oac;
  48         packet->bitfields14.sdma_enable = 1;
  49         packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
  50
  51         packet->sh_mem_config = qpd->sh_mem_config;
  52         packet->sh_mem_bases = qpd->sh_mem_bases;
  53         if (qpd->tba_addr) {
  54                 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
  55                 /* On GFX9, unlike GFX10, bit TRAP_EN of SQ_SHADER_TBA_HI is
  56                  * not defined, so setting it won't do any harm.
  57                  */
  58                 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)
  59                                 | 1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT;
  60
  61                 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
  62                 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
  63         }
  64
  65         packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
  66         packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
  67
  68         packet->vm_context_page_table_base_addr_lo32 =
  69                         lower_32_bits(vm_page_table_base_addr);
  70         packet->vm_context_page_table_base_addr_hi32 =
  71                         upper_32_bits(vm_page_table_base_addr);
  72
  73         return 0;
  74 }
  75
  76 static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,
  77                         uint64_t ib, size_t ib_size_in_dwords, bool chain)
  78 {
  79         struct pm4_mes_runlist *packet;
  80
  81         int concurrent_proc_cnt = 0;
  82         struct kfd_dev *kfd = pm->dqm->dev;
  83
  84         /* Determine the number of processes to map together to HW:
  85          * it can not exceed the number of VMIDs available to the
  86          * scheduler, and it is determined by the smaller of the number
  87          * of processes in the runlist and kfd module parameter
  88          * hws_max_conc_proc.
  89          * Note: the arbitration between the number of VMIDs and
  90          * hws_max_conc_proc has been done in
  91          * kgd2kfd_device_init().
  92          */
  93         concurrent_proc_cnt = min(pm->dqm->processes_count,
  94                         kfd->max_proc_per_quantum);
  95
  96         packet = (struct pm4_mes_runlist *)buffer;
  97
  98         memset(buffer, 0, sizeof(struct pm4_mes_runlist));
  99         packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
 100                                                 sizeof(struct pm4_mes_runlist));
 101
 102         packet->bitfields4.ib_size = ib_size_in_dwords;
 103         packet->bitfields4.chain = chain ? 1 : 0;
 104         packet->bitfields4.offload_polling = 0;
 105         packet->bitfields4.chained_runlist_idle_disable = chain ? 1 : 0;
 106         packet->bitfields4.valid = 1;
 107         packet->bitfields4.process_cnt = concurrent_proc_cnt;
 108         packet->ordinal2 = lower_32_bits(ib);
 109         packet->ib_base_hi = upper_32_bits(ib);
 110
 111         return 0;
 112 }
 113
 114 static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer,
 115                                 struct scheduling_resources *res)
 116 {
 117         struct pm4_mes_set_resources *packet;
 118
 119         packet = (struct pm4_mes_set_resources *)buffer;
 120         memset(buffer, 0, sizeof(struct pm4_mes_set_resources));
 121
 122         packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
 123                                         sizeof(struct pm4_mes_set_resources));
 124
 125         packet->bitfields2.queue_type =
 126                         queue_type__mes_set_resources__hsa_interface_queue_hiq;
 127         packet->bitfields2.vmid_mask = res->vmid_mask;
 128         packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
 129         packet->bitfields7.oac_mask = res->oac_mask;
 130         packet->bitfields8.gds_heap_base = res->gds_heap_base;
 131         packet->bitfields8.gds_heap_size = res->gds_heap_size;
 132
 133         packet->gws_mask_lo = lower_32_bits(res->gws_mask);
 134         packet->gws_mask_hi = upper_32_bits(res->gws_mask);
 135
 136         packet->queue_mask_lo = lower_32_bits(res->queue_mask);
 137         packet->queue_mask_hi = upper_32_bits(res->queue_mask);
 138
 139         return 0;
 140 }
 141
 142 static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
 143                 struct queue *q, bool is_static)
 144 {
 145         struct pm4_mes_map_queues *packet;
 146         bool use_static = is_static;
 147
 148         packet = (struct pm4_mes_map_queues *)buffer;
 149         memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
 150
 151         packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
 152                                         sizeof(struct pm4_mes_map_queues));
 153         packet->bitfields2.num_queues = 1;
 154         packet->bitfields2.queue_sel =
 155                 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
 156
 157         packet->bitfields2.engine_sel =
 158                 engine_sel__mes_map_queues__compute_vi;
 159         packet->bitfields2.gws_control_queue = q->gws ? 1 : 0;
 160         packet->bitfields2.extended_engine_sel =
 161                 extended_engine_sel__mes_map_queues__legacy_engine_sel;
 162         packet->bitfields2.queue_type =
 163                 queue_type__mes_map_queues__normal_compute_vi;
 164
 165         switch (q->properties.type) {
 166         case KFD_QUEUE_TYPE_COMPUTE:
 167                 if (use_static)
 168                         packet->bitfields2.queue_type =
 169                 queue_type__mes_map_queues__normal_latency_static_queue_vi;
 170                 break;
 171         case KFD_QUEUE_TYPE_DIQ:
 172                 packet->bitfields2.queue_type =
 173                         queue_type__mes_map_queues__debug_interface_queue_vi;
 174                 break;
 175         case KFD_QUEUE_TYPE_SDMA:
 176         case KFD_QUEUE_TYPE_SDMA_XGMI:
 177                 use_static = false; /* no static queues under SDMA */
 178                 if (q->properties.sdma_engine_id < 2)
 179                         packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
 180                                 engine_sel__mes_map_queues__sdma0_vi;
 181                 else {
 182                         packet->bitfields2.extended_engine_sel =
 183                                 extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
 184                         packet->bitfields2.engine_sel = q->properties.sdma_engine_id;
 185                 }
 186                 break;
 187         default:
 188                 WARN(1, "queue type %d", q->properties.type);
 189                 return -EINVAL;
 190         }
 191         packet->bitfields3.doorbell_offset =
 192                         q->properties.doorbell_off;
 193
 194         packet->mqd_addr_lo =
 195                         lower_32_bits(q->gart_mqd_addr);
 196
 197         packet->mqd_addr_hi =
 198                         upper_32_bits(q->gart_mqd_addr);
 199
 200         packet->wptr_addr_lo =
 201                         lower_32_bits((uint64_t)q->properties.write_ptr);
 202
 203         packet->wptr_addr_hi =
 204                         upper_32_bits((uint64_t)q->properties.write_ptr);
 205
 206         return 0;
 207 }
 208
 209 static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer,
 210                         enum kfd_queue_type type,
 211                         enum kfd_unmap_queues_filter filter,
 212                         uint32_t filter_param, bool reset,
 213                         unsigned int sdma_engine)
 214 {
 215         struct pm4_mes_unmap_queues *packet;
 216
 217         packet = (struct pm4_mes_unmap_queues *)buffer;
 218         memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
 219
 220         packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
 221                                         sizeof(struct pm4_mes_unmap_queues));
 222         switch (type) {
 223         case KFD_QUEUE_TYPE_COMPUTE:
 224         case KFD_QUEUE_TYPE_DIQ:
 225                 packet->bitfields2.extended_engine_sel =
 226                         extended_engine_sel__mes_unmap_queues__legacy_engine_sel;
 227                 packet->bitfields2.engine_sel =
 228                         engine_sel__mes_unmap_queues__compute;
 229                 break;
 230         case KFD_QUEUE_TYPE_SDMA:
 231         case KFD_QUEUE_TYPE_SDMA_XGMI:
 232                 if (sdma_engine < 2) {
 233                         packet->bitfields2.extended_engine_sel =
 234                                 extended_engine_sel__mes_unmap_queues__legacy_engine_sel;
 235                         packet->bitfields2.engine_sel =
 236                                 engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
 237                 } else {
 238                         packet->bitfields2.extended_engine_sel =
 239                                 extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel;
 240                         packet->bitfields2.engine_sel = sdma_engine;
 241                 }
 242                 break;
 243         default:
 244                 WARN(1, "queue type %d", type);
 245                 return -EINVAL;
 246         }
 247
 248         if (reset)
 249                 packet->bitfields2.action =
 250                         action__mes_unmap_queues__reset_queues;
 251         else
 252                 packet->bitfields2.action =
 253                         action__mes_unmap_queues__preempt_queues;
 254
 255         switch (filter) {
 256         case KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE:
 257                 packet->bitfields2.queue_sel =
 258                         queue_sel__mes_unmap_queues__perform_request_on_specified_queues;
 259                 packet->bitfields2.num_queues = 1;
 260                 packet->bitfields3b.doorbell_offset0 = filter_param;
 261                 break;
 262         case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
 263                 packet->bitfields2.queue_sel =
 264                         queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
 265                 packet->bitfields3a.pasid = filter_param;
 266                 break;
 267         case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
 268                 packet->bitfields2.queue_sel =
 269                         queue_sel__mes_unmap_queues__unmap_all_queues;
 270                 break;
 271         case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
 272                 /* in this case, we do not preempt static queues */
 273                 packet->bitfields2.queue_sel =
 274                         queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
 275                 break;
 276         default:
 277                 WARN(1, "filter %d", filter);
 278                 return -EINVAL;
 279         }
 280
 281         return 0;
 282
 283 }
 284
 285 static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,
 286                         uint64_t fence_address, uint32_t fence_value)
 287 {
 288         struct pm4_mes_query_status *packet;
 289
 290         packet = (struct pm4_mes_query_status *)buffer;
 291         memset(buffer, 0, sizeof(struct pm4_mes_query_status));
 292
 293
 294         packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
 295                                         sizeof(struct pm4_mes_query_status));
 296
 297         packet->bitfields2.context_id = 0;
 298         packet->bitfields2.interrupt_sel =
 299                         interrupt_sel__mes_query_status__completion_status;
 300         packet->bitfields2.command =
 301                         command__mes_query_status__fence_only_after_write_ack;
 302
 303         packet->addr_hi = upper_32_bits((uint64_t)fence_address);
 304         packet->addr_lo = lower_32_bits((uint64_t)fence_address);
 305         packet->data_hi = upper_32_bits((uint64_t)fence_value);
 306         packet->data_lo = lower_32_bits((uint64_t)fence_value);
 307
 308         return 0;
 309 }
 310
 311 const struct packet_manager_funcs kfd_v9_pm_funcs = {
 312         .map_process            = pm_map_process_v9,
 313         .runlist                = pm_runlist_v9,
 314         .set_resources          = pm_set_resources_v9,
 315         .map_queues             = pm_map_queues_v9,
 316         .unmap_queues           = pm_unmap_queues_v9,
 317         .query_status           = pm_query_status_v9,
 318         .release_mem            = NULL,
 319         .map_process_size       = sizeof(struct pm4_mes_map_process),
 320         .runlist_size           = sizeof(struct pm4_mes_runlist),
 321         .set_resources_size     = sizeof(struct pm4_mes_set_resources),
 322         .map_queues_size        = sizeof(struct pm4_mes_map_queues),
 323         .unmap_queues_size      = sizeof(struct pm4_mes_unmap_queues),
 324         .query_status_size      = sizeof(struct pm4_mes_query_status),
 325         .release_mem_size       = 0,
 326 };