2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/device.h>
24 #include <linux/export.h>
25 #include <linux/err.h>
27 #include <linux/file.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 #include <linux/compat.h>
32 #include <uapi/linux/kfd_ioctl.h>
33 #include <linux/time.h>
35 #include <linux/mman.h>
36 #include <linux/dma-buf.h>
37 #include <asm/processor.h>
39 #include "kfd_device_queue_manager.h"
40 #include "kfd_dbgmgr.h"
41 #include "amdgpu_amdkfd.h"
43 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
44 static int kfd_open(struct inode *, struct file *);
45 static int kfd_release(struct inode *, struct file *);
46 static int kfd_mmap(struct file *, struct vm_area_struct *);
48 static const char kfd_dev_name[] = "kfd";
50 static const struct file_operations kfd_fops = {
52 .unlocked_ioctl = kfd_ioctl,
53 .compat_ioctl = compat_ptr_ioctl,
55 .release = kfd_release,
59 static int kfd_char_dev_major = -1;
60 static struct class *kfd_class;
61 struct device *kfd_device;
63 int kfd_chardev_init(void)
67 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
68 err = kfd_char_dev_major;
70 goto err_register_chrdev;
72 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
73 err = PTR_ERR(kfd_class);
74 if (IS_ERR(kfd_class))
75 goto err_class_create;
77 kfd_device = device_create(kfd_class, NULL,
78 MKDEV(kfd_char_dev_major, 0),
80 err = PTR_ERR(kfd_device);
81 if (IS_ERR(kfd_device))
82 goto err_device_create;
87 class_destroy(kfd_class);
89 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
94 void kfd_chardev_exit(void)
96 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
97 class_destroy(kfd_class);
98 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
101 struct device *kfd_chardev(void)
107 static int kfd_open(struct inode *inode, struct file *filep)
109 struct kfd_process *process;
110 bool is_32bit_user_mode;
112 if (iminor(inode) != 0)
115 is_32bit_user_mode = in_compat_syscall();
117 if (is_32bit_user_mode) {
119 "Process %d (32-bit) failed to open /dev/kfd\n"
120 "32-bit processes are not supported by amdkfd\n",
125 process = kfd_create_process(filep);
127 return PTR_ERR(process);
129 if (kfd_is_locked()) {
130 dev_dbg(kfd_device, "kfd is locked!\n"
131 "process %d unreferenced", process->pasid);
132 kfd_unref_process(process);
136 /* filep now owns the reference returned by kfd_create_process */
137 filep->private_data = process;
139 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
140 process->pasid, process->is_32bit_user_mode);
145 static int kfd_release(struct inode *inode, struct file *filep)
147 struct kfd_process *process = filep->private_data;
150 kfd_unref_process(process);
155 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
158 struct kfd_ioctl_get_version_args *args = data;
160 args->major_version = KFD_IOCTL_MAJOR_VERSION;
161 args->minor_version = KFD_IOCTL_MINOR_VERSION;
166 static int set_queue_properties_from_user(struct queue_properties *q_properties,
167 struct kfd_ioctl_create_queue_args *args)
169 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
170 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
174 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
175 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
179 if ((args->ring_base_address) &&
180 (!access_ok((const void __user *) args->ring_base_address,
181 sizeof(uint64_t)))) {
182 pr_err("Can't access ring base address\n");
186 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
187 pr_err("Ring size must be a power of 2 or 0\n");
191 if (!access_ok((const void __user *) args->read_pointer_address,
193 pr_err("Can't access read pointer\n");
197 if (!access_ok((const void __user *) args->write_pointer_address,
199 pr_err("Can't access write pointer\n");
203 if (args->eop_buffer_address &&
204 !access_ok((const void __user *) args->eop_buffer_address,
206 pr_debug("Can't access eop buffer");
210 if (args->ctx_save_restore_address &&
211 !access_ok((const void __user *) args->ctx_save_restore_address,
213 pr_debug("Can't access ctx save restore buffer");
217 q_properties->is_interop = false;
218 q_properties->is_gws = false;
219 q_properties->queue_percent = args->queue_percentage;
220 q_properties->priority = args->queue_priority;
221 q_properties->queue_address = args->ring_base_address;
222 q_properties->queue_size = args->ring_size;
223 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
224 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
225 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
226 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
227 q_properties->ctx_save_restore_area_address =
228 args->ctx_save_restore_address;
229 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
230 q_properties->ctl_stack_size = args->ctl_stack_size;
231 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
232 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
233 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
234 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
235 q_properties->type = KFD_QUEUE_TYPE_SDMA;
236 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
237 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
241 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
242 q_properties->format = KFD_QUEUE_FORMAT_AQL;
244 q_properties->format = KFD_QUEUE_FORMAT_PM4;
246 pr_debug("Queue Percentage: %d, %d\n",
247 q_properties->queue_percent, args->queue_percentage);
249 pr_debug("Queue Priority: %d, %d\n",
250 q_properties->priority, args->queue_priority);
252 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
253 q_properties->queue_address, args->ring_base_address);
255 pr_debug("Queue Size: 0x%llX, %u\n",
256 q_properties->queue_size, args->ring_size);
258 pr_debug("Queue r/w Pointers: %px, %px\n",
259 q_properties->read_ptr,
260 q_properties->write_ptr);
262 pr_debug("Queue Format: %d\n", q_properties->format);
264 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
266 pr_debug("Queue CTX save area: 0x%llX\n",
267 q_properties->ctx_save_restore_area_address);
272 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
275 struct kfd_ioctl_create_queue_args *args = data;
278 unsigned int queue_id;
279 struct kfd_process_device *pdd;
280 struct queue_properties q_properties;
281 uint32_t doorbell_offset_in_process = 0;
283 memset(&q_properties, 0, sizeof(struct queue_properties));
285 pr_debug("Creating queue ioctl\n");
287 err = set_queue_properties_from_user(&q_properties, args);
291 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
292 dev = kfd_device_by_id(args->gpu_id);
294 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
298 mutex_lock(&p->mutex);
300 pdd = kfd_bind_process_to_device(dev, p);
303 goto err_bind_process;
306 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
310 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id,
311 &doorbell_offset_in_process);
313 goto err_create_queue;
315 args->queue_id = queue_id;
318 /* Return gpu_id as doorbell offset for mmap usage */
319 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
320 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
321 if (KFD_IS_SOC15(dev->device_info->asic_family))
322 /* On SOC15 ASICs, include the doorbell offset within the
323 * process doorbell frame, which is 2 pages.
325 args->doorbell_offset |= doorbell_offset_in_process;
327 mutex_unlock(&p->mutex);
329 pr_debug("Queue id %d was created successfully\n", args->queue_id);
331 pr_debug("Ring buffer address == 0x%016llX\n",
332 args->ring_base_address);
334 pr_debug("Read ptr address == 0x%016llX\n",
335 args->read_pointer_address);
337 pr_debug("Write ptr address == 0x%016llX\n",
338 args->write_pointer_address);
344 mutex_unlock(&p->mutex);
348 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
352 struct kfd_ioctl_destroy_queue_args *args = data;
354 pr_debug("Destroying queue id %d for pasid 0x%x\n",
358 mutex_lock(&p->mutex);
360 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
362 mutex_unlock(&p->mutex);
366 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
370 struct kfd_ioctl_update_queue_args *args = data;
371 struct queue_properties properties;
373 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
374 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
378 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
379 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
383 if ((args->ring_base_address) &&
384 (!access_ok((const void __user *) args->ring_base_address,
385 sizeof(uint64_t)))) {
386 pr_err("Can't access ring base address\n");
390 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
391 pr_err("Ring size must be a power of 2 or 0\n");
395 properties.queue_address = args->ring_base_address;
396 properties.queue_size = args->ring_size;
397 properties.queue_percent = args->queue_percentage;
398 properties.priority = args->queue_priority;
400 pr_debug("Updating queue id %d for pasid 0x%x\n",
401 args->queue_id, p->pasid);
403 mutex_lock(&p->mutex);
405 retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);
407 mutex_unlock(&p->mutex);
412 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
416 const int max_num_cus = 1024;
417 struct kfd_ioctl_set_cu_mask_args *args = data;
418 struct queue_properties properties;
419 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
420 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
422 if ((args->num_cu_mask % 32) != 0) {
423 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
428 properties.cu_mask_count = args->num_cu_mask;
429 if (properties.cu_mask_count == 0) {
430 pr_debug("CU mask cannot be 0");
434 /* To prevent an unreasonably large CU mask size, set an arbitrary
435 * limit of max_num_cus bits. We can then just drop any CU mask bits
436 * past max_num_cus bits and just use the first max_num_cus bits.
438 if (properties.cu_mask_count > max_num_cus) {
439 pr_debug("CU mask cannot be greater than 1024 bits");
440 properties.cu_mask_count = max_num_cus;
441 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
444 properties.cu_mask = kzalloc(cu_mask_size, GFP_KERNEL);
445 if (!properties.cu_mask)
448 retval = copy_from_user(properties.cu_mask, cu_mask_ptr, cu_mask_size);
450 pr_debug("Could not copy CU mask from userspace");
451 kfree(properties.cu_mask);
455 mutex_lock(&p->mutex);
457 retval = pqm_set_cu_mask(&p->pqm, args->queue_id, &properties);
459 mutex_unlock(&p->mutex);
462 kfree(properties.cu_mask);
467 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
468 struct kfd_process *p, void *data)
470 struct kfd_ioctl_get_queue_wave_state_args *args = data;
473 mutex_lock(&p->mutex);
475 r = pqm_get_wave_state(&p->pqm, args->queue_id,
476 (void __user *)args->ctl_stack_address,
477 &args->ctl_stack_used_size,
478 &args->save_area_used_size);
480 mutex_unlock(&p->mutex);
485 static int kfd_ioctl_set_memory_policy(struct file *filep,
486 struct kfd_process *p, void *data)
488 struct kfd_ioctl_set_memory_policy_args *args = data;
491 struct kfd_process_device *pdd;
492 enum cache_policy default_policy, alternate_policy;
494 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
495 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
499 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
500 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
504 dev = kfd_device_by_id(args->gpu_id);
508 mutex_lock(&p->mutex);
510 pdd = kfd_bind_process_to_device(dev, p);
516 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
517 ? cache_policy_coherent : cache_policy_noncoherent;
520 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
521 ? cache_policy_coherent : cache_policy_noncoherent;
523 if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm,
527 (void __user *)args->alternate_aperture_base,
528 args->alternate_aperture_size))
532 mutex_unlock(&p->mutex);
537 static int kfd_ioctl_set_trap_handler(struct file *filep,
538 struct kfd_process *p, void *data)
540 struct kfd_ioctl_set_trap_handler_args *args = data;
543 struct kfd_process_device *pdd;
545 dev = kfd_device_by_id(args->gpu_id);
549 mutex_lock(&p->mutex);
551 pdd = kfd_bind_process_to_device(dev, p);
557 if (dev->dqm->ops.set_trap_handler(dev->dqm,
564 mutex_unlock(&p->mutex);
569 static int kfd_ioctl_dbg_register(struct file *filep,
570 struct kfd_process *p, void *data)
572 struct kfd_ioctl_dbg_register_args *args = data;
574 struct kfd_dbgmgr *dbgmgr_ptr;
575 struct kfd_process_device *pdd;
579 dev = kfd_device_by_id(args->gpu_id);
583 if (dev->device_info->asic_family == CHIP_CARRIZO) {
584 pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");
588 mutex_lock(&p->mutex);
589 mutex_lock(kfd_get_dbgmgr_mutex());
592 * make sure that we have pdd, if this the first queue created for
595 pdd = kfd_bind_process_to_device(dev, p);
597 status = PTR_ERR(pdd);
602 /* In case of a legal call, we have no dbgmgr yet */
603 create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);
605 status = kfd_dbgmgr_register(dbgmgr_ptr, p);
607 kfd_dbgmgr_destroy(dbgmgr_ptr);
609 dev->dbgmgr = dbgmgr_ptr;
612 pr_debug("debugger already registered\n");
617 mutex_unlock(kfd_get_dbgmgr_mutex());
618 mutex_unlock(&p->mutex);
623 static int kfd_ioctl_dbg_unregister(struct file *filep,
624 struct kfd_process *p, void *data)
626 struct kfd_ioctl_dbg_unregister_args *args = data;
630 dev = kfd_device_by_id(args->gpu_id);
631 if (!dev || !dev->dbgmgr)
634 if (dev->device_info->asic_family == CHIP_CARRIZO) {
635 pr_debug("kfd_ioctl_dbg_unregister not supported on CZ\n");
639 mutex_lock(kfd_get_dbgmgr_mutex());
641 status = kfd_dbgmgr_unregister(dev->dbgmgr, p);
643 kfd_dbgmgr_destroy(dev->dbgmgr);
647 mutex_unlock(kfd_get_dbgmgr_mutex());
653 * Parse and generate variable size data structure for address watch.
654 * Total size of the buffer and # watch points is limited in order
655 * to prevent kernel abuse. (no bearing to the much smaller HW limitation
656 * which is enforced by dbgdev module)
657 * please also note that the watch address itself are not "copied from user",
658 * since it be set into the HW in user mode values.
661 static int kfd_ioctl_dbg_address_watch(struct file *filep,
662 struct kfd_process *p, void *data)
664 struct kfd_ioctl_dbg_address_watch_args *args = data;
666 struct dbg_address_watch_info aw_info;
667 unsigned char *args_buff;
669 void __user *cmd_from_user;
670 uint64_t watch_mask_value = 0;
671 unsigned int args_idx = 0;
673 memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));
675 dev = kfd_device_by_id(args->gpu_id);
679 if (dev->device_info->asic_family == CHIP_CARRIZO) {
680 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
684 cmd_from_user = (void __user *) args->content_ptr;
686 /* Validate arguments */
688 if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
689 (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
690 (cmd_from_user == NULL))
693 /* this is the actual buffer to work with */
694 args_buff = memdup_user(cmd_from_user,
695 args->buf_size_in_bytes - sizeof(*args));
696 if (IS_ERR(args_buff))
697 return PTR_ERR(args_buff);
701 aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));
702 args_idx += sizeof(aw_info.num_watch_points);
704 aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];
705 args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;
708 * set watch address base pointer to point on the array base
711 aw_info.watch_address = (uint64_t *) &args_buff[args_idx];
713 /* skip over the addresses buffer */
714 args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
716 if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
721 watch_mask_value = (uint64_t) args_buff[args_idx];
723 if (watch_mask_value > 0) {
725 * There is an array of masks.
726 * set watch mask base pointer to point on the array base
729 aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];
731 /* skip over the masks buffer */
732 args_idx += sizeof(aw_info.watch_mask) *
733 aw_info.num_watch_points;
735 /* just the NULL mask, set to NULL and skip over it */
736 aw_info.watch_mask = NULL;
737 args_idx += sizeof(aw_info.watch_mask);
740 if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
745 /* Currently HSA Event is not supported for DBG */
746 aw_info.watch_event = NULL;
748 mutex_lock(kfd_get_dbgmgr_mutex());
750 status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);
752 mutex_unlock(kfd_get_dbgmgr_mutex());
760 /* Parse and generate fixed size data structure for wave control */
761 static int kfd_ioctl_dbg_wave_control(struct file *filep,
762 struct kfd_process *p, void *data)
764 struct kfd_ioctl_dbg_wave_control_args *args = data;
766 struct dbg_wave_control_info wac_info;
767 unsigned char *args_buff;
768 uint32_t computed_buff_size;
770 void __user *cmd_from_user;
771 unsigned int args_idx = 0;
773 memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));
775 /* we use compact form, independent of the packing attribute value */
776 computed_buff_size = sizeof(*args) +
777 sizeof(wac_info.mode) +
778 sizeof(wac_info.operand) +
779 sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +
780 sizeof(wac_info.dbgWave_msg.MemoryVA) +
781 sizeof(wac_info.trapId);
783 dev = kfd_device_by_id(args->gpu_id);
787 if (dev->device_info->asic_family == CHIP_CARRIZO) {
788 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
792 /* input size must match the computed "compact" size */
793 if (args->buf_size_in_bytes != computed_buff_size) {
794 pr_debug("size mismatch, computed : actual %u : %u\n",
795 args->buf_size_in_bytes, computed_buff_size);
799 cmd_from_user = (void __user *) args->content_ptr;
801 if (cmd_from_user == NULL)
804 /* copy the entire buffer from user */
806 args_buff = memdup_user(cmd_from_user,
807 args->buf_size_in_bytes - sizeof(*args));
808 if (IS_ERR(args_buff))
809 return PTR_ERR(args_buff);
811 /* move ptr to the start of the "pay-load" area */
812 wac_info.process = p;
814 wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));
815 args_idx += sizeof(wac_info.operand);
817 wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));
818 args_idx += sizeof(wac_info.mode);
820 wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));
821 args_idx += sizeof(wac_info.trapId);
823 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =
824 *((uint32_t *)(&args_buff[args_idx]));
825 wac_info.dbgWave_msg.MemoryVA = NULL;
827 mutex_lock(kfd_get_dbgmgr_mutex());
829 pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",
830 wac_info.process, wac_info.operand,
831 wac_info.mode, wac_info.trapId,
832 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
834 status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);
836 pr_debug("Returned status of dbg manager is %ld\n", status);
838 mutex_unlock(kfd_get_dbgmgr_mutex());
845 static int kfd_ioctl_get_clock_counters(struct file *filep,
846 struct kfd_process *p, void *data)
848 struct kfd_ioctl_get_clock_counters_args *args = data;
851 dev = kfd_device_by_id(args->gpu_id);
853 /* Reading GPU clock counter from KGD */
854 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(dev->kgd);
856 /* Node without GPU resource */
857 args->gpu_clock_counter = 0;
859 /* No access to rdtsc. Using raw monotonic time */
860 args->cpu_clock_counter = ktime_get_raw_ns();
861 args->system_clock_counter = ktime_get_boottime_ns();
863 /* Since the counter is in nano-seconds we use 1GHz frequency */
864 args->system_clock_freq = 1000000000;
870 static int kfd_ioctl_get_process_apertures(struct file *filp,
871 struct kfd_process *p, void *data)
873 struct kfd_ioctl_get_process_apertures_args *args = data;
874 struct kfd_process_device_apertures *pAperture;
875 struct kfd_process_device *pdd;
877 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
879 args->num_of_nodes = 0;
881 mutex_lock(&p->mutex);
883 /*if the process-device list isn't empty*/
884 if (kfd_has_process_device_data(p)) {
885 /* Run over all pdd of the process */
886 pdd = kfd_get_first_process_device_data(p);
889 &args->process_apertures[args->num_of_nodes];
890 pAperture->gpu_id = pdd->dev->id;
891 pAperture->lds_base = pdd->lds_base;
892 pAperture->lds_limit = pdd->lds_limit;
893 pAperture->gpuvm_base = pdd->gpuvm_base;
894 pAperture->gpuvm_limit = pdd->gpuvm_limit;
895 pAperture->scratch_base = pdd->scratch_base;
896 pAperture->scratch_limit = pdd->scratch_limit;
899 "node id %u\n", args->num_of_nodes);
901 "gpu id %u\n", pdd->dev->id);
903 "lds_base %llX\n", pdd->lds_base);
905 "lds_limit %llX\n", pdd->lds_limit);
907 "gpuvm_base %llX\n", pdd->gpuvm_base);
909 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
911 "scratch_base %llX\n", pdd->scratch_base);
913 "scratch_limit %llX\n", pdd->scratch_limit);
915 args->num_of_nodes++;
917 pdd = kfd_get_next_process_device_data(p, pdd);
918 } while (pdd && (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS));
921 mutex_unlock(&p->mutex);
926 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
927 struct kfd_process *p, void *data)
929 struct kfd_ioctl_get_process_apertures_new_args *args = data;
930 struct kfd_process_device_apertures *pa;
931 struct kfd_process_device *pdd;
935 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
937 if (args->num_of_nodes == 0) {
938 /* Return number of nodes, so that user space can alloacate
941 mutex_lock(&p->mutex);
943 if (!kfd_has_process_device_data(p))
946 /* Run over all pdd of the process */
947 pdd = kfd_get_first_process_device_data(p);
949 args->num_of_nodes++;
950 pdd = kfd_get_next_process_device_data(p, pdd);
956 /* Fill in process-aperture information for all available
957 * nodes, but not more than args->num_of_nodes as that is
958 * the amount of memory allocated by user
960 pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
961 args->num_of_nodes), GFP_KERNEL);
965 mutex_lock(&p->mutex);
967 if (!kfd_has_process_device_data(p)) {
968 args->num_of_nodes = 0;
973 /* Run over all pdd of the process */
974 pdd = kfd_get_first_process_device_data(p);
976 pa[nodes].gpu_id = pdd->dev->id;
977 pa[nodes].lds_base = pdd->lds_base;
978 pa[nodes].lds_limit = pdd->lds_limit;
979 pa[nodes].gpuvm_base = pdd->gpuvm_base;
980 pa[nodes].gpuvm_limit = pdd->gpuvm_limit;
981 pa[nodes].scratch_base = pdd->scratch_base;
982 pa[nodes].scratch_limit = pdd->scratch_limit;
985 "gpu id %u\n", pdd->dev->id);
987 "lds_base %llX\n", pdd->lds_base);
989 "lds_limit %llX\n", pdd->lds_limit);
991 "gpuvm_base %llX\n", pdd->gpuvm_base);
993 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
995 "scratch_base %llX\n", pdd->scratch_base);
997 "scratch_limit %llX\n", pdd->scratch_limit);
1000 pdd = kfd_get_next_process_device_data(p, pdd);
1001 } while (pdd && (nodes < args->num_of_nodes));
1002 mutex_unlock(&p->mutex);
1004 args->num_of_nodes = nodes;
1006 (void __user *)args->kfd_process_device_apertures_ptr,
1008 (nodes * sizeof(struct kfd_process_device_apertures)));
1010 return ret ? -EFAULT : 0;
1013 mutex_unlock(&p->mutex);
1017 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
1020 struct kfd_ioctl_create_event_args *args = data;
1023 /* For dGPUs the event page is allocated in user mode. The
1024 * handle is passed to KFD with the first call to this IOCTL
1025 * through the event_page_offset field.
1027 if (args->event_page_offset) {
1028 struct kfd_dev *kfd;
1029 struct kfd_process_device *pdd;
1030 void *mem, *kern_addr;
1033 if (p->signal_page) {
1034 pr_err("Event page is already set\n");
1038 kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset));
1040 pr_err("Getting device by id failed in %s\n", __func__);
1044 mutex_lock(&p->mutex);
1045 pdd = kfd_bind_process_to_device(kfd, p);
1051 mem = kfd_process_device_translate_handle(pdd,
1052 GET_IDR_HANDLE(args->event_page_offset));
1054 pr_err("Can't find BO, offset is 0x%llx\n",
1055 args->event_page_offset);
1059 mutex_unlock(&p->mutex);
1061 err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->kgd,
1062 mem, &kern_addr, &size);
1064 pr_err("Failed to map event page to kernel\n");
1068 err = kfd_event_page_set(p, kern_addr, size);
1070 pr_err("Failed to set event page\n");
1075 err = kfd_event_create(filp, p, args->event_type,
1076 args->auto_reset != 0, args->node_id,
1077 &args->event_id, &args->event_trigger_data,
1078 &args->event_page_offset,
1079 &args->event_slot_index);
1084 mutex_unlock(&p->mutex);
1088 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
1091 struct kfd_ioctl_destroy_event_args *args = data;
1093 return kfd_event_destroy(p, args->event_id);
1096 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
1099 struct kfd_ioctl_set_event_args *args = data;
1101 return kfd_set_event(p, args->event_id);
1104 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
1107 struct kfd_ioctl_reset_event_args *args = data;
1109 return kfd_reset_event(p, args->event_id);
1112 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
1115 struct kfd_ioctl_wait_events_args *args = data;
1118 err = kfd_wait_on_events(p, args->num_events,
1119 (void __user *)args->events_ptr,
1120 (args->wait_for_all != 0),
1121 args->timeout, &args->wait_result);
1125 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
1126 struct kfd_process *p, void *data)
1128 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
1129 struct kfd_process_device *pdd;
1130 struct kfd_dev *dev;
1133 dev = kfd_device_by_id(args->gpu_id);
1137 mutex_lock(&p->mutex);
1139 pdd = kfd_bind_process_to_device(dev, p);
1142 goto bind_process_to_device_fail;
1145 pdd->qpd.sh_hidden_private_base = args->va_addr;
1147 mutex_unlock(&p->mutex);
1149 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
1150 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
1151 dev->kfd2kgd->set_scratch_backing_va(
1152 dev->kgd, args->va_addr, pdd->qpd.vmid);
1156 bind_process_to_device_fail:
1157 mutex_unlock(&p->mutex);
1161 static int kfd_ioctl_get_tile_config(struct file *filep,
1162 struct kfd_process *p, void *data)
1164 struct kfd_ioctl_get_tile_config_args *args = data;
1165 struct kfd_dev *dev;
1166 struct tile_config config;
1169 dev = kfd_device_by_id(args->gpu_id);
1173 amdgpu_amdkfd_get_tile_config(dev->kgd, &config);
1175 args->gb_addr_config = config.gb_addr_config;
1176 args->num_banks = config.num_banks;
1177 args->num_ranks = config.num_ranks;
1179 if (args->num_tile_configs > config.num_tile_configs)
1180 args->num_tile_configs = config.num_tile_configs;
1181 err = copy_to_user((void __user *)args->tile_config_ptr,
1182 config.tile_config_ptr,
1183 args->num_tile_configs * sizeof(uint32_t));
1185 args->num_tile_configs = 0;
1189 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
1190 args->num_macro_tile_configs =
1191 config.num_macro_tile_configs;
1192 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
1193 config.macro_tile_config_ptr,
1194 args->num_macro_tile_configs * sizeof(uint32_t));
1196 args->num_macro_tile_configs = 0;
1203 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
1206 struct kfd_ioctl_acquire_vm_args *args = data;
1207 struct kfd_process_device *pdd;
1208 struct kfd_dev *dev;
1209 struct file *drm_file;
1212 dev = kfd_device_by_id(args->gpu_id);
1216 drm_file = fget(args->drm_fd);
1220 mutex_lock(&p->mutex);
1222 pdd = kfd_get_process_device_data(dev, p);
1228 if (pdd->drm_file) {
1229 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1233 ret = kfd_process_device_init_vm(pdd, drm_file);
1236 /* On success, the PDD keeps the drm_file reference */
1237 mutex_unlock(&p->mutex);
1242 mutex_unlock(&p->mutex);
1247 bool kfd_dev_is_large_bar(struct kfd_dev *dev)
1249 struct kfd_local_mem_info mem_info;
1251 if (debug_largebar) {
1252 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1256 if (dev->device_info->needs_iommu_device)
1259 amdgpu_amdkfd_get_local_mem_info(dev->kgd, &mem_info);
1260 if (mem_info.local_mem_size_private == 0 &&
1261 mem_info.local_mem_size_public > 0)
1266 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1267 struct kfd_process *p, void *data)
1269 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1270 struct kfd_process_device *pdd;
1272 struct kfd_dev *dev;
1275 uint64_t offset = args->mmap_offset;
1276 uint32_t flags = args->flags;
1278 if (args->size == 0)
1281 dev = kfd_device_by_id(args->gpu_id);
1285 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1286 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1287 !kfd_dev_is_large_bar(dev)) {
1288 pr_err("Alloc host visible vram on small bar is not allowed\n");
1292 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1293 if (args->size != kfd_doorbell_process_slice(dev))
1295 offset = kfd_get_process_doorbells(dev, p);
1296 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1297 if (args->size != PAGE_SIZE)
1299 offset = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
1304 mutex_lock(&p->mutex);
1306 pdd = kfd_bind_process_to_device(dev, p);
1312 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1313 dev->kgd, args->va_addr, args->size,
1314 pdd->vm, (struct kgd_mem **) &mem, &offset,
1320 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1321 if (idr_handle < 0) {
1326 mutex_unlock(&p->mutex);
1328 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1329 args->mmap_offset = offset;
1331 /* MMIO is mapped through kfd device
1332 * Generate a kfd mmap offset
1334 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1335 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1336 | KFD_MMAP_GPU_ID(args->gpu_id);
1341 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem);
1343 mutex_unlock(&p->mutex);
1347 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1348 struct kfd_process *p, void *data)
1350 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1351 struct kfd_process_device *pdd;
1353 struct kfd_dev *dev;
1356 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1360 mutex_lock(&p->mutex);
1362 pdd = kfd_get_process_device_data(dev, p);
1364 pr_err("Process device data doesn't exist\n");
1369 mem = kfd_process_device_translate_handle(
1370 pdd, GET_IDR_HANDLE(args->handle));
1376 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd,
1377 (struct kgd_mem *)mem);
1379 /* If freeing the buffer failed, leave the handle in place for
1380 * clean-up during process tear-down.
1383 kfd_process_device_remove_obj_handle(
1384 pdd, GET_IDR_HANDLE(args->handle));
1387 mutex_unlock(&p->mutex);
1391 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1392 struct kfd_process *p, void *data)
1394 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1395 struct kfd_process_device *pdd, *peer_pdd;
1397 struct kfd_dev *dev, *peer;
1400 uint32_t *devices_arr = NULL;
1402 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1406 if (!args->n_devices) {
1407 pr_debug("Device IDs array empty\n");
1410 if (args->n_success > args->n_devices) {
1411 pr_debug("n_success exceeds n_devices\n");
1415 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1420 err = copy_from_user(devices_arr,
1421 (void __user *)args->device_ids_array_ptr,
1422 args->n_devices * sizeof(*devices_arr));
1425 goto copy_from_user_failed;
1428 mutex_lock(&p->mutex);
1430 pdd = kfd_bind_process_to_device(dev, p);
1433 goto bind_process_to_device_failed;
1436 mem = kfd_process_device_translate_handle(pdd,
1437 GET_IDR_HANDLE(args->handle));
1440 goto get_mem_obj_from_handle_failed;
1443 for (i = args->n_success; i < args->n_devices; i++) {
1444 peer = kfd_device_by_id(devices_arr[i]);
1446 pr_debug("Getting device by id failed for 0x%x\n",
1449 goto get_mem_obj_from_handle_failed;
1452 peer_pdd = kfd_bind_process_to_device(peer, p);
1453 if (IS_ERR(peer_pdd)) {
1454 err = PTR_ERR(peer_pdd);
1455 goto get_mem_obj_from_handle_failed;
1457 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1458 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1460 pr_err("Failed to map to gpu %d/%d\n",
1461 i, args->n_devices);
1462 goto map_memory_to_gpu_failed;
1464 args->n_success = i+1;
1467 mutex_unlock(&p->mutex);
1469 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
1471 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1472 goto sync_memory_failed;
1475 /* Flush TLBs after waiting for the page table updates to complete */
1476 for (i = 0; i < args->n_devices; i++) {
1477 peer = kfd_device_by_id(devices_arr[i]);
1478 if (WARN_ON_ONCE(!peer))
1480 peer_pdd = kfd_get_process_device_data(peer, p);
1481 if (WARN_ON_ONCE(!peer_pdd))
1483 kfd_flush_tlb(peer_pdd);
1490 bind_process_to_device_failed:
1491 get_mem_obj_from_handle_failed:
1492 map_memory_to_gpu_failed:
1493 mutex_unlock(&p->mutex);
1494 copy_from_user_failed:
1501 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1502 struct kfd_process *p, void *data)
1504 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1505 struct kfd_process_device *pdd, *peer_pdd;
1507 struct kfd_dev *dev, *peer;
1509 uint32_t *devices_arr = NULL, i;
1511 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1515 if (!args->n_devices) {
1516 pr_debug("Device IDs array empty\n");
1519 if (args->n_success > args->n_devices) {
1520 pr_debug("n_success exceeds n_devices\n");
1524 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1529 err = copy_from_user(devices_arr,
1530 (void __user *)args->device_ids_array_ptr,
1531 args->n_devices * sizeof(*devices_arr));
1534 goto copy_from_user_failed;
1537 mutex_lock(&p->mutex);
1539 pdd = kfd_get_process_device_data(dev, p);
1542 goto bind_process_to_device_failed;
1545 mem = kfd_process_device_translate_handle(pdd,
1546 GET_IDR_HANDLE(args->handle));
1549 goto get_mem_obj_from_handle_failed;
1552 for (i = args->n_success; i < args->n_devices; i++) {
1553 peer = kfd_device_by_id(devices_arr[i]);
1556 goto get_mem_obj_from_handle_failed;
1559 peer_pdd = kfd_get_process_device_data(peer, p);
1562 goto get_mem_obj_from_handle_failed;
1564 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1565 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1567 pr_err("Failed to unmap from gpu %d/%d\n",
1568 i, args->n_devices);
1569 goto unmap_memory_from_gpu_failed;
1571 args->n_success = i+1;
1575 mutex_unlock(&p->mutex);
1579 bind_process_to_device_failed:
1580 get_mem_obj_from_handle_failed:
1581 unmap_memory_from_gpu_failed:
1582 mutex_unlock(&p->mutex);
1583 copy_from_user_failed:
1588 static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1589 struct kfd_process *p, void *data)
1592 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1594 struct kfd_dev *dev;
1596 mutex_lock(&p->mutex);
1597 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1611 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1616 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1617 mutex_unlock(&p->mutex);
1619 args->first_gws = 0;
1623 mutex_unlock(&p->mutex);
1627 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1628 struct kfd_process *p, void *data)
1630 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1631 struct kfd_dev *dev = NULL;
1632 struct kgd_dev *dma_buf_kgd;
1633 void *metadata_buffer = NULL;
1638 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1639 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1645 if (args->metadata_ptr) {
1646 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1647 if (!metadata_buffer)
1651 /* Get dmabuf info from KGD */
1652 r = amdgpu_amdkfd_get_dmabuf_info(dev->kgd, args->dmabuf_fd,
1653 &dma_buf_kgd, &args->size,
1654 metadata_buffer, args->metadata_size,
1655 &args->metadata_size, &flags);
1659 /* Reverse-lookup gpu_id from kgd pointer */
1660 dev = kfd_device_by_kgd(dma_buf_kgd);
1665 args->gpu_id = dev->id;
1666 args->flags = flags;
1668 /* Copy metadata buffer to user mode */
1669 if (metadata_buffer) {
1670 r = copy_to_user((void __user *)args->metadata_ptr,
1671 metadata_buffer, args->metadata_size);
1677 kfree(metadata_buffer);
1682 static int kfd_ioctl_import_dmabuf(struct file *filep,
1683 struct kfd_process *p, void *data)
1685 struct kfd_ioctl_import_dmabuf_args *args = data;
1686 struct kfd_process_device *pdd;
1687 struct dma_buf *dmabuf;
1688 struct kfd_dev *dev;
1694 dev = kfd_device_by_id(args->gpu_id);
1698 dmabuf = dma_buf_get(args->dmabuf_fd);
1700 return PTR_ERR(dmabuf);
1702 mutex_lock(&p->mutex);
1704 pdd = kfd_bind_process_to_device(dev, p);
1710 r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf,
1711 args->va_addr, pdd->vm,
1712 (struct kgd_mem **)&mem, &size,
1717 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1718 if (idr_handle < 0) {
1723 mutex_unlock(&p->mutex);
1725 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1730 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem);
1732 mutex_unlock(&p->mutex);
1736 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
1737 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
1738 .cmd_drv = 0, .name = #ioctl}
1741 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
1742 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
1743 kfd_ioctl_get_version, 0),
1745 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
1746 kfd_ioctl_create_queue, 0),
1748 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
1749 kfd_ioctl_destroy_queue, 0),
1751 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
1752 kfd_ioctl_set_memory_policy, 0),
1754 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
1755 kfd_ioctl_get_clock_counters, 0),
1757 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
1758 kfd_ioctl_get_process_apertures, 0),
1760 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
1761 kfd_ioctl_update_queue, 0),
1763 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
1764 kfd_ioctl_create_event, 0),
1766 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
1767 kfd_ioctl_destroy_event, 0),
1769 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
1770 kfd_ioctl_set_event, 0),
1772 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
1773 kfd_ioctl_reset_event, 0),
1775 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
1776 kfd_ioctl_wait_events, 0),
1778 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,
1779 kfd_ioctl_dbg_register, 0),
1781 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,
1782 kfd_ioctl_dbg_unregister, 0),
1784 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,
1785 kfd_ioctl_dbg_address_watch, 0),
1787 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,
1788 kfd_ioctl_dbg_wave_control, 0),
1790 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
1791 kfd_ioctl_set_scratch_backing_va, 0),
1793 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
1794 kfd_ioctl_get_tile_config, 0),
1796 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
1797 kfd_ioctl_set_trap_handler, 0),
1799 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
1800 kfd_ioctl_get_process_apertures_new, 0),
1802 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
1803 kfd_ioctl_acquire_vm, 0),
1805 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
1806 kfd_ioctl_alloc_memory_of_gpu, 0),
1808 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
1809 kfd_ioctl_free_memory_of_gpu, 0),
1811 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
1812 kfd_ioctl_map_memory_to_gpu, 0),
1814 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
1815 kfd_ioctl_unmap_memory_from_gpu, 0),
1817 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
1818 kfd_ioctl_set_cu_mask, 0),
1820 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
1821 kfd_ioctl_get_queue_wave_state, 0),
1823 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
1824 kfd_ioctl_get_dmabuf_info, 0),
1826 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
1827 kfd_ioctl_import_dmabuf, 0),
1829 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
1830 kfd_ioctl_alloc_queue_gws, 0),
1833 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
1835 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
1837 struct kfd_process *process;
1838 amdkfd_ioctl_t *func;
1839 const struct amdkfd_ioctl_desc *ioctl = NULL;
1840 unsigned int nr = _IOC_NR(cmd);
1841 char stack_kdata[128];
1843 unsigned int usize, asize;
1844 int retcode = -EINVAL;
1846 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
1849 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
1852 ioctl = &amdkfd_ioctls[nr];
1854 amdkfd_size = _IOC_SIZE(ioctl->cmd);
1855 usize = asize = _IOC_SIZE(cmd);
1856 if (amdkfd_size > asize)
1857 asize = amdkfd_size;
1863 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
1865 /* Get the process struct from the filep. Only the process
1866 * that opened /dev/kfd can use the file descriptor. Child
1867 * processes need to create their own KFD device context.
1869 process = filep->private_data;
1870 if (process->lead_thread != current->group_leader) {
1871 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
1876 /* Do not trust userspace, use our own definition */
1879 if (unlikely(!func)) {
1880 dev_dbg(kfd_device, "no function\n");
1885 if (cmd & (IOC_IN | IOC_OUT)) {
1886 if (asize <= sizeof(stack_kdata)) {
1887 kdata = stack_kdata;
1889 kdata = kmalloc(asize, GFP_KERNEL);
1896 memset(kdata + usize, 0, asize - usize);
1900 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
1904 } else if (cmd & IOC_OUT) {
1905 memset(kdata, 0, usize);
1908 retcode = func(filep, process, kdata);
1911 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
1916 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
1917 task_pid_nr(current), cmd, nr);
1919 if (kdata != stack_kdata)
1923 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
1929 static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process,
1930 struct vm_area_struct *vma)
1932 phys_addr_t address;
1935 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1938 address = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
1940 vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
1941 VM_DONTDUMP | VM_PFNMAP;
1943 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1945 pr_debug("pasid 0x%x mapping mmio page\n"
1946 " target user address == 0x%08llX\n"
1947 " physical address == 0x%08llX\n"
1948 " vm_flags == 0x%04lX\n"
1949 " size == 0x%04lX\n",
1950 process->pasid, (unsigned long long) vma->vm_start,
1951 address, vma->vm_flags, PAGE_SIZE);
1953 ret = io_remap_pfn_range(vma,
1955 address >> PAGE_SHIFT,
1962 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
1964 struct kfd_process *process;
1965 struct kfd_dev *dev = NULL;
1966 unsigned long mmap_offset;
1967 unsigned int gpu_id;
1969 process = kfd_get_process(current);
1970 if (IS_ERR(process))
1971 return PTR_ERR(process);
1973 mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
1974 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
1976 dev = kfd_device_by_id(gpu_id);
1978 switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
1979 case KFD_MMAP_TYPE_DOORBELL:
1982 return kfd_doorbell_mmap(dev, process, vma);
1984 case KFD_MMAP_TYPE_EVENTS:
1985 return kfd_event_mmap(process, vma);
1987 case KFD_MMAP_TYPE_RESERVED_MEM:
1990 return kfd_reserved_mem_mmap(dev, process, vma);
1991 case KFD_MMAP_TYPE_MMIO:
1994 return kfd_mmio_mmap(dev, process, vma);