drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
  51
  52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  53
  54 #define SDMA1_REG_OFFSET 0x600
  55 #define SDMA3_REG_OFFSET 0x400
  56 #define SDMA0_HYP_DEC_REG_START 0x5880
  57 #define SDMA0_HYP_DEC_REG_END 0x5893
  58 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  59
  60 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  64
  65 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  66 {
  67         u32 base;
  68
  69         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  70             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  71                 base = adev->reg_offset[GC_HWIP][0][1];
  72                 if (instance != 0)
  73                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  74         } else {
  75                 if (instance < 2) {
  76                         base = adev->reg_offset[GC_HWIP][0][0];
  77                         if (instance == 1)
  78                                 internal_offset += SDMA1_REG_OFFSET;
  79                 } else {
  80                         base = adev->reg_offset[GC_HWIP][0][2];
  81                         if (instance == 3)
  82                                 internal_offset += SDMA3_REG_OFFSET;
  83                 }
  84         }
  85
  86         return base + internal_offset;
  87 }
  88
  89 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  90 {
  91         switch (adev->asic_type) {
  92         case CHIP_SIENNA_CICHLID:
  93         case CHIP_NAVY_FLOUNDER:
  94         case CHIP_VANGOGH:
  95         case CHIP_DIMGREY_CAVEFISH:
  96         case CHIP_BEIGE_GOBY:
  97                 break;
  98         default:
  99                 break;
 100         }
 101 }
 102
 103 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 104 {
 105         int err = 0;
 106         const struct sdma_firmware_header_v1_0 *hdr;
 107
 108         err = amdgpu_ucode_validate(sdma_inst->fw);
 109         if (err)
 110                 return err;
 111
 112         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 113         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 114         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 115
 116         if (sdma_inst->feature_version >= 20)
 117                 sdma_inst->burst_nop = true;
 118
 119         return 0;
 120 }
 121
 122 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 123 {
 124         release_firmware(adev->sdma.instance[0].fw);
 125
 126         memset((void *)adev->sdma.instance, 0,
 127                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 128 }
 129
 130 /**
 131  * sdma_v5_2_init_microcode - load ucode images from disk
 132  *
 133  * @adev: amdgpu_device pointer
 134  *
 135  * Use the firmware interface to load the ucode images into
 136  * the driver (not loaded into hw).
 137  * Returns 0 on success, error on failure.
 138  */
 139
 140 // emulation only, won't work on real chip
 141 // navi10 real chip need to use PSP to load firmware
 142 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 143 {
 144         const char *chip_name;
 145         char fw_name[40];
 146         int err = 0, i;
 147         struct amdgpu_firmware_info *info = NULL;
 148         const struct common_firmware_header *header = NULL;
 149
 150         DRM_DEBUG("\n");
 151
 152         switch (adev->asic_type) {
 153         case CHIP_SIENNA_CICHLID:
 154                 chip_name = "sienna_cichlid";
 155                 break;
 156         case CHIP_NAVY_FLOUNDER:
 157                 chip_name = "navy_flounder";
 158                 break;
 159         case CHIP_VANGOGH:
 160                 chip_name = "vangogh";
 161                 break;
 162         case CHIP_DIMGREY_CAVEFISH:
 163                 chip_name = "dimgrey_cavefish";
 164                 break;
 165         case CHIP_BEIGE_GOBY:
 166                 chip_name = "beige_goby";
 167                 break;
 168         default:
 169                 BUG();
 170         }
 171
 172         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 173
 174         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 175         if (err)
 176                 goto out;
 177
 178         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 179         if (err)
 180                 goto out;
 181
 182         for (i = 1; i < adev->sdma.num_instances; i++)
 183                 memcpy((void *)&adev->sdma.instance[i],
 184                        (void *)&adev->sdma.instance[0],
 185                        sizeof(struct amdgpu_sdma_instance));
 186
 187         if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
 188                 return 0;
 189
 190         DRM_DEBUG("psp_load == '%s'\n",
 191                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 192
 193         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 194                 for (i = 0; i < adev->sdma.num_instances; i++) {
 195                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 196                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 197                         info->fw = adev->sdma.instance[i].fw;
 198                         header = (const struct common_firmware_header *)info->fw->data;
 199                         adev->firmware.fw_size +=
 200                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 201                 }
 202         }
 203
 204 out:
 205         if (err) {
 206                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 207                 sdma_v5_2_destroy_inst_ctx(adev);
 208         }
 209         return err;
 210 }
 211
 212 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 213 {
 214         unsigned ret;
 215
 216         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 217         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 218         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 219         amdgpu_ring_write(ring, 1);
 220         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 221         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 222
 223         return ret;
 224 }
 225
 226 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 227                                            unsigned offset)
 228 {
 229         unsigned cur;
 230
 231         BUG_ON(offset > ring->buf_mask);
 232         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 233
 234         cur = (ring->wptr - 1) & ring->buf_mask;
 235         if (cur > offset)
 236                 ring->ring[offset] = cur - offset;
 237         else
 238                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 239 }
 240
 241 /**
 242  * sdma_v5_2_ring_get_rptr - get the current read pointer
 243  *
 244  * @ring: amdgpu ring pointer
 245  *
 246  * Get the current rptr from the hardware (NAVI10+).
 247  */
 248 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 249 {
 250         u64 *rptr;
 251
 252         /* XXX check if swapping is necessary on BE */
 253         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 254
 255         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 256         return ((*rptr) >> 2);
 257 }
 258
 259 /**
 260  * sdma_v5_2_ring_get_wptr - get the current write pointer
 261  *
 262  * @ring: amdgpu ring pointer
 263  *
 264  * Get the current wptr from the hardware (NAVI10+).
 265  */
 266 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 267 {
 268         struct amdgpu_device *adev = ring->adev;
 269         u64 wptr;
 270
 271         if (ring->use_doorbell) {
 272                 /* XXX check if swapping is necessary on BE */
 273                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 274                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 275         } else {
 276                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 277                 wptr = wptr << 32;
 278                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 279                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 280         }
 281
 282         return wptr >> 2;
 283 }
 284
 285 /**
 286  * sdma_v5_2_ring_set_wptr - commit the write pointer
 287  *
 288  * @ring: amdgpu ring pointer
 289  *
 290  * Write the wptr back to the hardware (NAVI10+).
 291  */
 292 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 293 {
 294         struct amdgpu_device *adev = ring->adev;
 295
 296         DRM_DEBUG("Setting write pointer\n");
 297         if (ring->use_doorbell) {
 298                 DRM_DEBUG("Using doorbell -- "
 299                                 "wptr_offs == 0x%08x "
 300                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 301                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 302                                 ring->wptr_offs,
 303                                 lower_32_bits(ring->wptr << 2),
 304                                 upper_32_bits(ring->wptr << 2));
 305                 /* XXX check if swapping is necessary on BE */
 306                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 307                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 308                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 309                                 ring->doorbell_index, ring->wptr << 2);
 310                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 311         } else {
 312                 DRM_DEBUG("Not using doorbell -- "
 313                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 314                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 315                                 ring->me,
 316                                 lower_32_bits(ring->wptr << 2),
 317                                 ring->me,
 318                                 upper_32_bits(ring->wptr << 2));
 319                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 320                         lower_32_bits(ring->wptr << 2));
 321                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 322                         upper_32_bits(ring->wptr << 2));
 323         }
 324 }
 325
 326 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 327 {
 328         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 329         int i;
 330
 331         for (i = 0; i < count; i++)
 332                 if (sdma && sdma->burst_nop && (i == 0))
 333                         amdgpu_ring_write(ring, ring->funcs->nop |
 334                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 335                 else
 336                         amdgpu_ring_write(ring, ring->funcs->nop);
 337 }
 338
 339 /**
 340  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 341  *
 342  * @ring: amdgpu ring pointer
 343  * @job: job to retrieve vmid from
 344  * @ib: IB object to schedule
 345  * @flags: unused
 346  *
 347  * Schedule an IB in the DMA ring.
 348  */
 349 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 350                                    struct amdgpu_job *job,
 351                                    struct amdgpu_ib *ib,
 352                                    uint32_t flags)
 353 {
 354         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 355         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 356
 357         /* An IB packet must end on a 8 DW boundary--the next dword
 358          * must be on a 8-dword boundary. Our IB packet below is 6
 359          * dwords long, thus add x number of NOPs, such that, in
 360          * modular arithmetic,
 361          * wptr + 6 + x = 8k, k >= 0, which in C is,
 362          * (wptr + 6 + x) % 8 = 0.
 363          * The expression below, is a solution of x.
 364          */
 365         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 366
 367         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 368                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 369         /* base must be 32 byte aligned */
 370         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 371         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 372         amdgpu_ring_write(ring, ib->length_dw);
 373         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 374         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 375 }
 376
 377 /**
 378  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
 379  *
 380  * @ring: amdgpu ring pointer
 381  * @job: job to retrieve vmid from
 382  * @ib: IB object to schedule
 383  *
 384  * flush the IB by graphics cache rinse.
 385  */
 386 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
 387 {
 388     uint32_t gcr_cntl =
 389                     SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 390                         SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 391                         SDMA_GCR_GLI_INV(1);
 392
 393         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 394         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 395         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 396         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 397                         SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 398         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 399                         SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 400         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 401                         SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 402 }
 403
 404 /**
 405  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 406  *
 407  * @ring: amdgpu ring pointer
 408  *
 409  * Emit an hdp flush packet on the requested DMA ring.
 410  */
 411 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 412 {
 413         struct amdgpu_device *adev = ring->adev;
 414         u32 ref_and_mask = 0;
 415         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 416
 417         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 418
 419         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 420                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 421                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 422         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 423         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 424         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 425         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 426         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 427                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 428 }
 429
 430 /**
 431  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 432  *
 433  * @ring: amdgpu ring pointer
 434  * @addr: address
 435  * @seq: sequence number
 436  * @flags: fence related flags
 437  *
 438  * Add a DMA fence packet to the ring to write
 439  * the fence seq number and DMA trap packet to generate
 440  * an interrupt if needed.
 441  */
 442 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 443                                       unsigned flags)
 444 {
 445         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 446         /* write the fence */
 447         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 448                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 449         /* zero in first two bits */
 450         BUG_ON(addr & 0x3);
 451         amdgpu_ring_write(ring, lower_32_bits(addr));
 452         amdgpu_ring_write(ring, upper_32_bits(addr));
 453         amdgpu_ring_write(ring, lower_32_bits(seq));
 454
 455         /* optionally write high bits as well */
 456         if (write64bit) {
 457                 addr += 4;
 458                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 459                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 460                 /* zero in first two bits */
 461                 BUG_ON(addr & 0x3);
 462                 amdgpu_ring_write(ring, lower_32_bits(addr));
 463                 amdgpu_ring_write(ring, upper_32_bits(addr));
 464                 amdgpu_ring_write(ring, upper_32_bits(seq));
 465         }
 466
 467         if (flags & AMDGPU_FENCE_FLAG_INT) {
 468                 /* generate an interrupt */
 469                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 470                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 471         }
 472 }
 473
 474
 475 /**
 476  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 477  *
 478  * @adev: amdgpu_device pointer
 479  *
 480  * Stop the gfx async dma ring buffers.
 481  */
 482 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 483 {
 484         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 485         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 486         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 487         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 488         u32 rb_cntl, ib_cntl;
 489         int i;
 490
 491         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 492             (adev->mman.buffer_funcs_ring == sdma1) ||
 493             (adev->mman.buffer_funcs_ring == sdma2) ||
 494             (adev->mman.buffer_funcs_ring == sdma3))
 495                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 496
 497         for (i = 0; i < adev->sdma.num_instances; i++) {
 498                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 499                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 500                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 501                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 502                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 503                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 504         }
 505 }
 506
 507 /**
 508  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 509  *
 510  * @adev: amdgpu_device pointer
 511  *
 512  * Stop the compute async dma queues.
 513  */
 514 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 515 {
 516         /* XXX todo */
 517 }
 518
 519 /**
 520  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
 521  *
 522  * @adev: amdgpu_device pointer
 523  * @enable: enable/disable the DMA MEs context switch.
 524  *
 525  * Halt or unhalt the async dma engines context switch.
 526  */
 527 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 528 {
 529         u32 f32_cntl, phase_quantum = 0;
 530         int i;
 531
 532         if (amdgpu_sdma_phase_quantum) {
 533                 unsigned value = amdgpu_sdma_phase_quantum;
 534                 unsigned unit = 0;
 535
 536                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 537                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 538                         value = (value + 1) >> 1;
 539                         unit++;
 540                 }
 541                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 542                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 543                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 544                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 545                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 546                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 547                         WARN_ONCE(1,
 548                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 549                                   value << unit);
 550                 }
 551                 phase_quantum =
 552                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 553                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 554         }
 555
 556         for (i = 0; i < adev->sdma.num_instances; i++) {
 557                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 558                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 559                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 560                 if (enable && amdgpu_sdma_phase_quantum) {
 561                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 562                                phase_quantum);
 563                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 564                                phase_quantum);
 565                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 566                                phase_quantum);
 567                 }
 568                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 569         }
 570
 571 }
 572
 573 /**
 574  * sdma_v5_2_enable - stop the async dma engines
 575  *
 576  * @adev: amdgpu_device pointer
 577  * @enable: enable/disable the DMA MEs.
 578  *
 579  * Halt or unhalt the async dma engines.
 580  */
 581 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 582 {
 583         u32 f32_cntl;
 584         int i;
 585
 586         if (!enable) {
 587                 sdma_v5_2_gfx_stop(adev);
 588                 sdma_v5_2_rlc_stop(adev);
 589         }
 590
 591         for (i = 0; i < adev->sdma.num_instances; i++) {
 592                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 593                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 594                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 595         }
 596 }
 597
 598 /**
 599  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 600  *
 601  * @adev: amdgpu_device pointer
 602  *
 603  * Set up the gfx DMA ring buffers and enable them.
 604  * Returns 0 for success, error for failure.
 605  */
 606 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 607 {
 608         struct amdgpu_ring *ring;
 609         u32 rb_cntl, ib_cntl;
 610         u32 rb_bufsz;
 611         u32 wb_offset;
 612         u32 doorbell;
 613         u32 doorbell_offset;
 614         u32 temp;
 615         u32 wptr_poll_cntl;
 616         u64 wptr_gpu_addr;
 617         int i, r;
 618
 619         for (i = 0; i < adev->sdma.num_instances; i++) {
 620                 ring = &adev->sdma.instance[i].ring;
 621                 wb_offset = (ring->rptr_offs * 4);
 622
 623                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 624
 625                 /* Set ring buffer size in dwords */
 626                 rb_bufsz = order_base_2(ring->ring_size / 4);
 627                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 628                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 629 #ifdef __BIG_ENDIAN
 630                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 631                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 632                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 633 #endif
 634                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 635
 636                 /* Initialize the ring buffer's read and write pointers */
 637                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 638                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 639                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 640                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 641
 642                 /* setup the wptr shadow polling */
 643                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 644                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 645                        lower_32_bits(wptr_gpu_addr));
 646                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 647                        upper_32_bits(wptr_gpu_addr));
 648                 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 649                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 650                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 651                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 652                                                F32_POLL_ENABLE, 1);
 653                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 654                        wptr_poll_cntl);
 655
 656                 /* set the wb address whether it's enabled or not */
 657                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 658                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 659                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 660                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 661
 662                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 663
 664                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 665                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 666
 667                 ring->wptr = 0;
 668
 669                 /* before programing wptr to a less value, need set minor_ptr_update first */
 670                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 671
 672                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 673                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 674                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 675                 }
 676
 677                 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 678                 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 679
 680                 if (ring->use_doorbell) {
 681                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 682                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 683                                         OFFSET, ring->doorbell_index);
 684                 } else {
 685                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 686                 }
 687                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 688                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 689
 690                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 691                                                       ring->doorbell_index,
 692                                                       adev->doorbell_index.sdma_doorbell_range);
 693
 694                 if (amdgpu_sriov_vf(adev))
 695                         sdma_v5_2_ring_set_wptr(ring);
 696
 697                 /* set minor_ptr_update to 0 after wptr programed */
 698                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 699
 700                 /* set utc l1 enable flag always to 1 */
 701                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 702                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 703
 704                 /* enable MCBP */
 705                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 706                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 707
 708                 /* Set up RESP_MODE to non-copy addresses */
 709                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 710                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 711                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 712                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 713
 714                 /* program default cache read and write policy */
 715                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 716                 /* clean read policy and write policy bits */
 717                 temp &= 0xFF0FFF;
 718                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 719                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 720                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 721                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 722
 723                 if (!amdgpu_sriov_vf(adev)) {
 724                         /* unhalt engine */
 725                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 726                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 727                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 728                 }
 729
 730                 /* enable DMA RB */
 731                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 732                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 733
 734                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 735                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 736 #ifdef __BIG_ENDIAN
 737                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 738 #endif
 739                 /* enable DMA IBs */
 740                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 741
 742                 ring->sched.ready = true;
 743
 744                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 745                         sdma_v5_2_ctx_switch_enable(adev, true);
 746                         sdma_v5_2_enable(adev, true);
 747                 }
 748
 749                 r = amdgpu_ring_test_ring(ring);
 750                 if (r) {
 751                         ring->sched.ready = false;
 752                         return r;
 753                 }
 754
 755                 if (adev->mman.buffer_funcs_ring == ring)
 756                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 757         }
 758
 759         return 0;
 760 }
 761
 762 /**
 763  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 764  *
 765  * @adev: amdgpu_device pointer
 766  *
 767  * Set up the compute DMA queues and enable them.
 768  * Returns 0 for success, error for failure.
 769  */
 770 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 771 {
 772         return 0;
 773 }
 774
 775 /**
 776  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 777  *
 778  * @adev: amdgpu_device pointer
 779  *
 780  * Loads the sDMA0/1/2/3 ucode.
 781  * Returns 0 for success, -EINVAL if the ucode is not available.
 782  */
 783 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 784 {
 785         const struct sdma_firmware_header_v1_0 *hdr;
 786         const __le32 *fw_data;
 787         u32 fw_size;
 788         int i, j;
 789
 790         /* halt the MEs */
 791         sdma_v5_2_enable(adev, false);
 792
 793         for (i = 0; i < adev->sdma.num_instances; i++) {
 794                 if (!adev->sdma.instance[i].fw)
 795                         return -EINVAL;
 796
 797                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 798                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 799                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 800
 801                 fw_data = (const __le32 *)
 802                         (adev->sdma.instance[i].fw->data +
 803                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 804
 805                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 806
 807                 for (j = 0; j < fw_size; j++) {
 808                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 809                                 msleep(1);
 810                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 811                 }
 812
 813                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 814         }
 815
 816         return 0;
 817 }
 818
 819 static int sdma_v5_2_soft_reset(void *handle)
 820 {
 821         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 822         u32 grbm_soft_reset;
 823         u32 tmp;
 824         int i;
 825
 826         for (i = 0; i < adev->sdma.num_instances; i++) {
 827                 grbm_soft_reset = REG_SET_FIELD(0,
 828                                                 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 829                                                 1);
 830                 grbm_soft_reset <<= i;
 831
 832                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 833                 tmp |= grbm_soft_reset;
 834                 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 835                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 836                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 837
 838                 udelay(50);
 839
 840                 tmp &= ~grbm_soft_reset;
 841                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 842                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 843
 844                 udelay(50);
 845         }
 846
 847         return 0;
 848 }
 849
 850 /**
 851  * sdma_v5_2_start - setup and start the async dma engines
 852  *
 853  * @adev: amdgpu_device pointer
 854  *
 855  * Set up the DMA engines and enable them.
 856  * Returns 0 for success, error for failure.
 857  */
 858 static int sdma_v5_2_start(struct amdgpu_device *adev)
 859 {
 860         int r = 0;
 861
 862         if (amdgpu_sriov_vf(adev)) {
 863                 sdma_v5_2_ctx_switch_enable(adev, false);
 864                 sdma_v5_2_enable(adev, false);
 865
 866                 /* set RB registers */
 867                 r = sdma_v5_2_gfx_resume(adev);
 868                 return r;
 869         }
 870
 871         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 872                 r = sdma_v5_2_load_microcode(adev);
 873                 if (r)
 874                         return r;
 875
 876                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 877                 if (amdgpu_emu_mode == 1)
 878                         msleep(1000);
 879         }
 880
 881         sdma_v5_2_soft_reset(adev);
 882         /* unhalt the MEs */
 883         sdma_v5_2_enable(adev, true);
 884         /* enable sdma ring preemption */
 885         sdma_v5_2_ctx_switch_enable(adev, true);
 886
 887         /* start the gfx rings and rlc compute queues */
 888         r = sdma_v5_2_gfx_resume(adev);
 889         if (r)
 890                 return r;
 891         r = sdma_v5_2_rlc_resume(adev);
 892
 893         return r;
 894 }
 895
 896 /**
 897  * sdma_v5_2_ring_test_ring - simple async dma engine test
 898  *
 899  * @ring: amdgpu_ring structure holding ring information
 900  *
 901  * Test the DMA engine by writing using it to write an
 902  * value to memory.
 903  * Returns 0 for success, error for failure.
 904  */
 905 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 906 {
 907         struct amdgpu_device *adev = ring->adev;
 908         unsigned i;
 909         unsigned index;
 910         int r;
 911         u32 tmp;
 912         u64 gpu_addr;
 913
 914         r = amdgpu_device_wb_get(adev, &index);
 915         if (r) {
 916                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 917                 return r;
 918         }
 919
 920         gpu_addr = adev->wb.gpu_addr + (index * 4);
 921         tmp = 0xCAFEDEAD;
 922         adev->wb.wb[index] = cpu_to_le32(tmp);
 923
 924         r = amdgpu_ring_alloc(ring, 5);
 925         if (r) {
 926                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 927                 amdgpu_device_wb_free(adev, index);
 928                 return r;
 929         }
 930
 931         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 932                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 933         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 934         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 935         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 936         amdgpu_ring_write(ring, 0xDEADBEEF);
 937         amdgpu_ring_commit(ring);
 938
 939         for (i = 0; i < adev->usec_timeout; i++) {
 940                 tmp = le32_to_cpu(adev->wb.wb[index]);
 941                 if (tmp == 0xDEADBEEF)
 942                         break;
 943                 if (amdgpu_emu_mode == 1)
 944                         msleep(1);
 945                 else
 946                         udelay(1);
 947         }
 948
 949         if (i >= adev->usec_timeout)
 950                 r = -ETIMEDOUT;
 951
 952         amdgpu_device_wb_free(adev, index);
 953
 954         return r;
 955 }
 956
 957 /**
 958  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 959  *
 960  * @ring: amdgpu_ring structure holding ring information
 961  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 962  *
 963  * Test a simple IB in the DMA ring.
 964  * Returns 0 on success, error on failure.
 965  */
 966 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 967 {
 968         struct amdgpu_device *adev = ring->adev;
 969         struct amdgpu_ib ib;
 970         struct dma_fence *f = NULL;
 971         unsigned index;
 972         long r;
 973         u32 tmp = 0;
 974         u64 gpu_addr;
 975
 976         r = amdgpu_device_wb_get(adev, &index);
 977         if (r) {
 978                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 979                 return r;
 980         }
 981
 982         gpu_addr = adev->wb.gpu_addr + (index * 4);
 983         tmp = 0xCAFEDEAD;
 984         adev->wb.wb[index] = cpu_to_le32(tmp);
 985         memset(&ib, 0, sizeof(ib));
 986         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 987         if (r) {
 988                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 989                 goto err0;
 990         }
 991
 992         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 993                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 994         ib.ptr[1] = lower_32_bits(gpu_addr);
 995         ib.ptr[2] = upper_32_bits(gpu_addr);
 996         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 997         ib.ptr[4] = 0xDEADBEEF;
 998         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 999         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1000         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1001         ib.length_dw = 8;
1002
1003         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1004         if (r)
1005                 goto err1;
1006
1007         r = dma_fence_wait_timeout(f, false, timeout);
1008         if (r == 0) {
1009                 DRM_ERROR("amdgpu: IB test timed out\n");
1010                 r = -ETIMEDOUT;
1011                 goto err1;
1012         } else if (r < 0) {
1013                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1014                 goto err1;
1015         }
1016         tmp = le32_to_cpu(adev->wb.wb[index]);
1017         if (tmp == 0xDEADBEEF)
1018                 r = 0;
1019         else
1020                 r = -EINVAL;
1021
1022 err1:
1023         amdgpu_ib_free(adev, &ib, NULL);
1024         dma_fence_put(f);
1025 err0:
1026         amdgpu_device_wb_free(adev, index);
1027         return r;
1028 }
1029
1030
1031 /**
1032  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1033  *
1034  * @ib: indirect buffer to fill with commands
1035  * @pe: addr of the page entry
1036  * @src: src addr to copy from
1037  * @count: number of page entries to update
1038  *
1039  * Update PTEs by copying them from the GART using sDMA.
1040  */
1041 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1042                                   uint64_t pe, uint64_t src,
1043                                   unsigned count)
1044 {
1045         unsigned bytes = count * 8;
1046
1047         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1048                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1049         ib->ptr[ib->length_dw++] = bytes - 1;
1050         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1051         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1052         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1053         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1054         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1055
1056 }
1057
1058 /**
1059  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1060  *
1061  * @ib: indirect buffer to fill with commands
1062  * @pe: addr of the page entry
1063  * @value: dst addr to write into pe
1064  * @count: number of page entries to update
1065  * @incr: increase next addr by incr bytes
1066  *
1067  * Update PTEs by writing them manually using sDMA.
1068  */
1069 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1070                                    uint64_t value, unsigned count,
1071                                    uint32_t incr)
1072 {
1073         unsigned ndw = count * 2;
1074
1075         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1076                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1077         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1078         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1079         ib->ptr[ib->length_dw++] = ndw - 1;
1080         for (; ndw > 0; ndw -= 2) {
1081                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1082                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1083                 value += incr;
1084         }
1085 }
1086
1087 /**
1088  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1089  *
1090  * @ib: indirect buffer to fill with commands
1091  * @pe: addr of the page entry
1092  * @addr: dst addr to write into pe
1093  * @count: number of page entries to update
1094  * @incr: increase next addr by incr bytes
1095  * @flags: access flags
1096  *
1097  * Update the page tables using sDMA.
1098  */
1099 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1100                                      uint64_t pe,
1101                                      uint64_t addr, unsigned count,
1102                                      uint32_t incr, uint64_t flags)
1103 {
1104         /* for physically contiguous pages (vram) */
1105         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1106         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1107         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1108         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1109         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1110         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1111         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1112         ib->ptr[ib->length_dw++] = incr; /* increment size */
1113         ib->ptr[ib->length_dw++] = 0;
1114         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1115 }
1116
1117 /**
1118  * sdma_v5_2_ring_pad_ib - pad the IB
1119  *
1120  * @ib: indirect buffer to fill with padding
1121  * @ring: amdgpu_ring structure holding ring information
1122  *
1123  * Pad the IB with NOPs to a boundary multiple of 8.
1124  */
1125 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1126 {
1127         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1128         u32 pad_count;
1129         int i;
1130
1131         pad_count = (-ib->length_dw) & 0x7;
1132         for (i = 0; i < pad_count; i++)
1133                 if (sdma && sdma->burst_nop && (i == 0))
1134                         ib->ptr[ib->length_dw++] =
1135                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1136                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1137                 else
1138                         ib->ptr[ib->length_dw++] =
1139                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1140 }
1141
1142
1143 /**
1144  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1145  *
1146  * @ring: amdgpu_ring pointer
1147  *
1148  * Make sure all previous operations are completed (CIK).
1149  */
1150 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1151 {
1152         uint32_t seq = ring->fence_drv.sync_seq;
1153         uint64_t addr = ring->fence_drv.gpu_addr;
1154
1155         /* wait for idle */
1156         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1157                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1158                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1159                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1160         amdgpu_ring_write(ring, addr & 0xfffffffc);
1161         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1162         amdgpu_ring_write(ring, seq); /* reference */
1163         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1164         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1165                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1166 }
1167
1168
1169 /**
1170  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1171  *
1172  * @ring: amdgpu_ring pointer
1173  * @vmid: vmid number to use
1174  * @pd_addr: address
1175  *
1176  * Update the page table base and flush the VM TLB
1177  * using sDMA.
1178  */
1179 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1180                                          unsigned vmid, uint64_t pd_addr)
1181 {
1182         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1183 }
1184
1185 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1186                                      uint32_t reg, uint32_t val)
1187 {
1188         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1189                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1190         amdgpu_ring_write(ring, reg);
1191         amdgpu_ring_write(ring, val);
1192 }
1193
1194 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1195                                          uint32_t val, uint32_t mask)
1196 {
1197         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1198                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1199                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1200         amdgpu_ring_write(ring, reg << 2);
1201         amdgpu_ring_write(ring, 0);
1202         amdgpu_ring_write(ring, val); /* reference */
1203         amdgpu_ring_write(ring, mask); /* mask */
1204         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1205                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1206 }
1207
1208 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1209                                                    uint32_t reg0, uint32_t reg1,
1210                                                    uint32_t ref, uint32_t mask)
1211 {
1212         amdgpu_ring_emit_wreg(ring, reg0, ref);
1213         /* wait for a cycle to reset vm_inv_eng*_ack */
1214         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1215         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1216 }
1217
1218 static int sdma_v5_2_early_init(void *handle)
1219 {
1220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221
1222         switch (adev->asic_type) {
1223         case CHIP_SIENNA_CICHLID:
1224                 adev->sdma.num_instances = 4;
1225                 break;
1226         case CHIP_NAVY_FLOUNDER:
1227         case CHIP_DIMGREY_CAVEFISH:
1228                 adev->sdma.num_instances = 2;
1229                 break;
1230         case CHIP_VANGOGH:
1231         case CHIP_BEIGE_GOBY:
1232                 adev->sdma.num_instances = 1;
1233                 break;
1234         default:
1235                 break;
1236         }
1237
1238         sdma_v5_2_set_ring_funcs(adev);
1239         sdma_v5_2_set_buffer_funcs(adev);
1240         sdma_v5_2_set_vm_pte_funcs(adev);
1241         sdma_v5_2_set_irq_funcs(adev);
1242
1243         return 0;
1244 }
1245
1246 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1247 {
1248         switch (seq_num) {
1249         case 0:
1250                 return SOC15_IH_CLIENTID_SDMA0;
1251         case 1:
1252                 return SOC15_IH_CLIENTID_SDMA1;
1253         case 2:
1254                 return SOC15_IH_CLIENTID_SDMA2;
1255         case 3:
1256                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1257         default:
1258                 break;
1259         }
1260         return -EINVAL;
1261 }
1262
1263 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1264 {
1265         switch (seq_num) {
1266         case 0:
1267                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1268         case 1:
1269                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1270         case 2:
1271                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1272         case 3:
1273                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1274         default:
1275                 break;
1276         }
1277         return -EINVAL;
1278 }
1279
1280 static int sdma_v5_2_sw_init(void *handle)
1281 {
1282         struct amdgpu_ring *ring;
1283         int r, i;
1284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285
1286         /* SDMA trap event */
1287         for (i = 0; i < adev->sdma.num_instances; i++) {
1288                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1289                                       sdma_v5_2_seq_to_trap_id(i),
1290                                       &adev->sdma.trap_irq);
1291                 if (r)
1292                         return r;
1293         }
1294
1295         r = sdma_v5_2_init_microcode(adev);
1296         if (r) {
1297                 DRM_ERROR("Failed to load sdma firmware!\n");
1298                 return r;
1299         }
1300
1301         for (i = 0; i < adev->sdma.num_instances; i++) {
1302                 ring = &adev->sdma.instance[i].ring;
1303                 ring->ring_obj = NULL;
1304                 ring->use_doorbell = true;
1305                 ring->me = i;
1306
1307                 DRM_INFO("use_doorbell being set to: [%s]\n",
1308                                 ring->use_doorbell?"true":"false");
1309
1310                 ring->doorbell_index =
1311                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1312
1313                 sprintf(ring->name, "sdma%d", i);
1314                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1315                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1316                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1317                 if (r)
1318                         return r;
1319         }
1320
1321         return r;
1322 }
1323
1324 static int sdma_v5_2_sw_fini(void *handle)
1325 {
1326         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1327         int i;
1328
1329         for (i = 0; i < adev->sdma.num_instances; i++)
1330                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1331
1332         sdma_v5_2_destroy_inst_ctx(adev);
1333
1334         return 0;
1335 }
1336
1337 static int sdma_v5_2_hw_init(void *handle)
1338 {
1339         int r;
1340         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341
1342         sdma_v5_2_init_golden_registers(adev);
1343
1344         r = sdma_v5_2_start(adev);
1345
1346         return r;
1347 }
1348
1349 static int sdma_v5_2_hw_fini(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352
1353         if (amdgpu_sriov_vf(adev))
1354                 return 0;
1355
1356         sdma_v5_2_ctx_switch_enable(adev, false);
1357         sdma_v5_2_enable(adev, false);
1358
1359         return 0;
1360 }
1361
1362 static int sdma_v5_2_suspend(void *handle)
1363 {
1364         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1365
1366         return sdma_v5_2_hw_fini(adev);
1367 }
1368
1369 static int sdma_v5_2_resume(void *handle)
1370 {
1371         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372
1373         return sdma_v5_2_hw_init(adev);
1374 }
1375
1376 static bool sdma_v5_2_is_idle(void *handle)
1377 {
1378         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1379         u32 i;
1380
1381         for (i = 0; i < adev->sdma.num_instances; i++) {
1382                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1383
1384                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1385                         return false;
1386         }
1387
1388         return true;
1389 }
1390
1391 static int sdma_v5_2_wait_for_idle(void *handle)
1392 {
1393         unsigned i;
1394         u32 sdma0, sdma1, sdma2, sdma3;
1395         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1396
1397         for (i = 0; i < adev->usec_timeout; i++) {
1398                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1399                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1400                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1401                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1402
1403                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1404                         return 0;
1405                 udelay(1);
1406         }
1407         return -ETIMEDOUT;
1408 }
1409
1410 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1411 {
1412         int i, r = 0;
1413         struct amdgpu_device *adev = ring->adev;
1414         u32 index = 0;
1415         u64 sdma_gfx_preempt;
1416
1417         amdgpu_sdma_get_index_from_ring(ring, &index);
1418         sdma_gfx_preempt =
1419                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1420
1421         /* assert preemption condition */
1422         amdgpu_ring_set_preempt_cond_exec(ring, false);
1423
1424         /* emit the trailing fence */
1425         ring->trail_seq += 1;
1426         amdgpu_ring_alloc(ring, 10);
1427         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1428                                   ring->trail_seq, 0);
1429         amdgpu_ring_commit(ring);
1430
1431         /* assert IB preemption */
1432         WREG32(sdma_gfx_preempt, 1);
1433
1434         /* poll the trailing fence */
1435         for (i = 0; i < adev->usec_timeout; i++) {
1436                 if (ring->trail_seq ==
1437                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1438                         break;
1439                 udelay(1);
1440         }
1441
1442         if (i >= adev->usec_timeout) {
1443                 r = -EINVAL;
1444                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1445         }
1446
1447         /* deassert IB preemption */
1448         WREG32(sdma_gfx_preempt, 0);
1449
1450         /* deassert the preemption condition */
1451         amdgpu_ring_set_preempt_cond_exec(ring, true);
1452         return r;
1453 }
1454
1455 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1456                                         struct amdgpu_irq_src *source,
1457                                         unsigned type,
1458                                         enum amdgpu_interrupt_state state)
1459 {
1460         u32 sdma_cntl;
1461
1462         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1463
1464         sdma_cntl = RREG32(reg_offset);
1465         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1466                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1467         WREG32(reg_offset, sdma_cntl);
1468
1469         return 0;
1470 }
1471
1472 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1473                                       struct amdgpu_irq_src *source,
1474                                       struct amdgpu_iv_entry *entry)
1475 {
1476         DRM_DEBUG("IH: SDMA trap\n");
1477         switch (entry->client_id) {
1478         case SOC15_IH_CLIENTID_SDMA0:
1479                 switch (entry->ring_id) {
1480                 case 0:
1481                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1482                         break;
1483                 case 1:
1484                         /* XXX compute */
1485                         break;
1486                 case 2:
1487                         /* XXX compute */
1488                         break;
1489                 case 3:
1490                         /* XXX page queue*/
1491                         break;
1492                 }
1493                 break;
1494         case SOC15_IH_CLIENTID_SDMA1:
1495                 switch (entry->ring_id) {
1496                 case 0:
1497                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1498                         break;
1499                 case 1:
1500                         /* XXX compute */
1501                         break;
1502                 case 2:
1503                         /* XXX compute */
1504                         break;
1505                 case 3:
1506                         /* XXX page queue*/
1507                         break;
1508                 }
1509                 break;
1510         case SOC15_IH_CLIENTID_SDMA2:
1511                 switch (entry->ring_id) {
1512                 case 0:
1513                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1514                         break;
1515                 case 1:
1516                         /* XXX compute */
1517                         break;
1518                 case 2:
1519                         /* XXX compute */
1520                         break;
1521                 case 3:
1522                         /* XXX page queue*/
1523                         break;
1524                 }
1525                 break;
1526         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1527                 switch (entry->ring_id) {
1528                 case 0:
1529                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1530                         break;
1531                 case 1:
1532                         /* XXX compute */
1533                         break;
1534                 case 2:
1535                         /* XXX compute */
1536                         break;
1537                 case 3:
1538                         /* XXX page queue*/
1539                         break;
1540                 }
1541                 break;
1542         }
1543         return 0;
1544 }
1545
1546 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1547                                               struct amdgpu_irq_src *source,
1548                                               struct amdgpu_iv_entry *entry)
1549 {
1550         return 0;
1551 }
1552
1553 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1554                                                        bool enable)
1555 {
1556         uint32_t data, def;
1557         int i;
1558
1559         for (i = 0; i < adev->sdma.num_instances; i++) {
1560
1561                 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
1562                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1563
1564                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1565                         /* Enable sdma clock gating */
1566                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1567                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1568                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1569                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1570                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1571                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1572                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1573                         if (def != data)
1574                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1575                 } else {
1576                         /* Disable sdma clock gating */
1577                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1578                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1579                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1580                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1581                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1582                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1583                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1584                         if (def != data)
1585                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1586                 }
1587         }
1588 }
1589
1590 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1591                                                       bool enable)
1592 {
1593         uint32_t data, def;
1594         int i;
1595
1596         for (i = 0; i < adev->sdma.num_instances; i++) {
1597
1598                 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH)
1599                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1600
1601                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1602                         /* Enable sdma mem light sleep */
1603                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1604                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1605                         if (def != data)
1606                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1607
1608                 } else {
1609                         /* Disable sdma mem light sleep */
1610                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1611                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1612                         if (def != data)
1613                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1614
1615                 }
1616         }
1617 }
1618
1619 static int sdma_v5_2_set_clockgating_state(void *handle,
1620                                            enum amd_clockgating_state state)
1621 {
1622         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1623
1624         if (amdgpu_sriov_vf(adev))
1625                 return 0;
1626
1627         switch (adev->asic_type) {
1628         case CHIP_SIENNA_CICHLID:
1629         case CHIP_NAVY_FLOUNDER:
1630         case CHIP_VANGOGH:
1631         case CHIP_DIMGREY_CAVEFISH:
1632         case CHIP_BEIGE_GOBY:
1633                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1634                                 state == AMD_CG_STATE_GATE);
1635                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1636                                 state == AMD_CG_STATE_GATE);
1637                 break;
1638         default:
1639                 break;
1640         }
1641
1642         return 0;
1643 }
1644
1645 static int sdma_v5_2_set_powergating_state(void *handle,
1646                                           enum amd_powergating_state state)
1647 {
1648         return 0;
1649 }
1650
1651 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1652 {
1653         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1654         int data;
1655
1656         if (amdgpu_sriov_vf(adev))
1657                 *flags = 0;
1658
1659         /* AMD_CG_SUPPORT_SDMA_LS */
1660         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1661         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1662                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1663 }
1664
1665 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1666         .name = "sdma_v5_2",
1667         .early_init = sdma_v5_2_early_init,
1668         .late_init = NULL,
1669         .sw_init = sdma_v5_2_sw_init,
1670         .sw_fini = sdma_v5_2_sw_fini,
1671         .hw_init = sdma_v5_2_hw_init,
1672         .hw_fini = sdma_v5_2_hw_fini,
1673         .suspend = sdma_v5_2_suspend,
1674         .resume = sdma_v5_2_resume,
1675         .is_idle = sdma_v5_2_is_idle,
1676         .wait_for_idle = sdma_v5_2_wait_for_idle,
1677         .soft_reset = sdma_v5_2_soft_reset,
1678         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1679         .set_powergating_state = sdma_v5_2_set_powergating_state,
1680         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1681 };
1682
1683 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1684         .type = AMDGPU_RING_TYPE_SDMA,
1685         .align_mask = 0xf,
1686         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1687         .support_64bit_ptrs = true,
1688         .vmhub = AMDGPU_GFXHUB_0,
1689         .get_rptr = sdma_v5_2_ring_get_rptr,
1690         .get_wptr = sdma_v5_2_ring_get_wptr,
1691         .set_wptr = sdma_v5_2_ring_set_wptr,
1692         .emit_frame_size =
1693                 5 + /* sdma_v5_2_ring_init_cond_exec */
1694                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1695                 3 + /* hdp_invalidate */
1696                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1697                 /* sdma_v5_2_ring_emit_vm_flush */
1698                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1699                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1700                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1701         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1702         .emit_ib = sdma_v5_2_ring_emit_ib,
1703         .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1704         .emit_fence = sdma_v5_2_ring_emit_fence,
1705         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1706         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1707         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1708         .test_ring = sdma_v5_2_ring_test_ring,
1709         .test_ib = sdma_v5_2_ring_test_ib,
1710         .insert_nop = sdma_v5_2_ring_insert_nop,
1711         .pad_ib = sdma_v5_2_ring_pad_ib,
1712         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1713         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1714         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1715         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1716         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1717         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1718 };
1719
1720 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1721 {
1722         int i;
1723
1724         for (i = 0; i < adev->sdma.num_instances; i++) {
1725                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1726                 adev->sdma.instance[i].ring.me = i;
1727         }
1728 }
1729
1730 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1731         .set = sdma_v5_2_set_trap_irq_state,
1732         .process = sdma_v5_2_process_trap_irq,
1733 };
1734
1735 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1736         .process = sdma_v5_2_process_illegal_inst_irq,
1737 };
1738
1739 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1740 {
1741         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1742                                         adev->sdma.num_instances;
1743         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1744         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1745 }
1746
1747 /**
1748  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1749  *
1750  * @ib: indirect buffer to copy to
1751  * @src_offset: src GPU address
1752  * @dst_offset: dst GPU address
1753  * @byte_count: number of bytes to xfer
1754  * @tmz: if a secure copy should be used
1755  *
1756  * Copy GPU buffers using the DMA engine.
1757  * Used by the amdgpu ttm implementation to move pages if
1758  * registered as the asic copy callback.
1759  */
1760 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1761                                        uint64_t src_offset,
1762                                        uint64_t dst_offset,
1763                                        uint32_t byte_count,
1764                                        bool tmz)
1765 {
1766         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1767                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1768                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1769         ib->ptr[ib->length_dw++] = byte_count - 1;
1770         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1771         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1772         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1773         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1774         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1775 }
1776
1777 /**
1778  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1779  *
1780  * @ib: indirect buffer to fill
1781  * @src_data: value to write to buffer
1782  * @dst_offset: dst GPU address
1783  * @byte_count: number of bytes to xfer
1784  *
1785  * Fill GPU buffers using the DMA engine.
1786  */
1787 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1788                                        uint32_t src_data,
1789                                        uint64_t dst_offset,
1790                                        uint32_t byte_count)
1791 {
1792         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1793         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1794         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1795         ib->ptr[ib->length_dw++] = src_data;
1796         ib->ptr[ib->length_dw++] = byte_count - 1;
1797 }
1798
1799 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1800         .copy_max_bytes = 0x400000,
1801         .copy_num_dw = 7,
1802         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1803
1804         .fill_max_bytes = 0x400000,
1805         .fill_num_dw = 5,
1806         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1807 };
1808
1809 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1810 {
1811         if (adev->mman.buffer_funcs == NULL) {
1812                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1813                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1814         }
1815 }
1816
1817 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1818         .copy_pte_num_dw = 7,
1819         .copy_pte = sdma_v5_2_vm_copy_pte,
1820         .write_pte = sdma_v5_2_vm_write_pte,
1821         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1822 };
1823
1824 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1825 {
1826         unsigned i;
1827
1828         if (adev->vm_manager.vm_pte_funcs == NULL) {
1829                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1830                 for (i = 0; i < adev->sdma.num_instances; i++) {
1831                         adev->vm_manager.vm_pte_scheds[i] =
1832                                 &adev->sdma.instance[i].ring.sched;
1833                 }
1834                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1835         }
1836 }
1837
1838 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1839         .type = AMD_IP_BLOCK_TYPE_SDMA,
1840         .major = 5,
1841         .minor = 2,
1842         .rev = 0,
1843         .funcs = &sdma_v5_2_ip_funcs,
1844 };