drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37
  38 #include "soc15_common.h"
  39 #include "soc15.h"
  40 #include "navi10_sdma_pkt_open.h"
  41 #include "nbio_v2_3.h"
  42 #include "sdma_common.h"
  43 #include "sdma_v5_0.h"
  44
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53
  54 #define SDMA1_REG_OFFSET 0x600
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  65         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  89 };
  90
  91 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112 };
 113
 114 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 117 };
 118
 119 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 122 };
 123
 124 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 131 };
 132
 133 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 134 {
 135         u32 base;
 136
 137         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 138             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 139                 base = adev->reg_offset[GC_HWIP][0][1];
 140                 if (instance == 1)
 141                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 142         } else {
 143                 base = adev->reg_offset[GC_HWIP][0][0];
 144                 if (instance == 1)
 145                         internal_offset += SDMA1_REG_OFFSET;
 146         }
 147
 148         return base + internal_offset;
 149 }
 150
 151 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 152 {
 153         switch (adev->asic_type) {
 154         case CHIP_NAVI10:
 155                 soc15_program_register_sequence(adev,
 156                                                 golden_settings_sdma_5,
 157                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 158                 soc15_program_register_sequence(adev,
 159                                                 golden_settings_sdma_nv10,
 160                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 161                 break;
 162         case CHIP_NAVI14:
 163                 soc15_program_register_sequence(adev,
 164                                                 golden_settings_sdma_5,
 165                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 166                 soc15_program_register_sequence(adev,
 167                                                 golden_settings_sdma_nv14,
 168                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 169                 break;
 170         case CHIP_NAVI12:
 171                 if (amdgpu_sriov_vf(adev))
 172                         soc15_program_register_sequence(adev,
 173                                                         golden_settings_sdma_5_sriov,
 174                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 175                 else
 176                         soc15_program_register_sequence(adev,
 177                                                         golden_settings_sdma_5,
 178                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 179                 soc15_program_register_sequence(adev,
 180                                                 golden_settings_sdma_nv12,
 181                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 182                 break;
 183         default:
 184                 break;
 185         }
 186 }
 187
 188 /**
 189  * sdma_v5_0_init_microcode - load ucode images from disk
 190  *
 191  * @adev: amdgpu_device pointer
 192  *
 193  * Use the firmware interface to load the ucode images into
 194  * the driver (not loaded into hw).
 195  * Returns 0 on success, error on failure.
 196  */
 197
 198 // emulation only, won't work on real chip
 199 // navi10 real chip need to use PSP to load firmware
 200 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 201 {
 202         const char *chip_name;
 203         char fw_name[30];
 204         int err = 0, i;
 205         struct amdgpu_firmware_info *info = NULL;
 206         const struct common_firmware_header *header = NULL;
 207         const struct sdma_firmware_header_v1_0 *hdr;
 208
 209         if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12))
 210                 return 0;
 211
 212         DRM_DEBUG("\n");
 213
 214         switch (adev->asic_type) {
 215         case CHIP_NAVI10:
 216                 chip_name = "navi10";
 217                 break;
 218         case CHIP_NAVI14:
 219                 chip_name = "navi14";
 220                 break;
 221         case CHIP_NAVI12:
 222                 chip_name = "navi12";
 223                 break;
 224         default:
 225                 BUG();
 226         }
 227
 228         for (i = 0; i < adev->sdma.num_instances; i++) {
 229                 if (i == 0)
 230                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 231                 else
 232                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 233                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 234                 if (err)
 235                         goto out;
 236                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 237                 if (err)
 238                         goto out;
 239                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 240                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 241                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 242                 if (adev->sdma.instance[i].feature_version >= 20)
 243                         adev->sdma.instance[i].burst_nop = true;
 244                 DRM_DEBUG("psp_load == '%s'\n",
 245                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 246
 247                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 248                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 249                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 250                         info->fw = adev->sdma.instance[i].fw;
 251                         header = (const struct common_firmware_header *)info->fw->data;
 252                         adev->firmware.fw_size +=
 253                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 254                 }
 255         }
 256 out:
 257         if (err) {
 258                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 259                 for (i = 0; i < adev->sdma.num_instances; i++) {
 260                         release_firmware(adev->sdma.instance[i].fw);
 261                         adev->sdma.instance[i].fw = NULL;
 262                 }
 263         }
 264         return err;
 265 }
 266
 267 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 268 {
 269         unsigned ret;
 270
 271         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 272         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 273         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 274         amdgpu_ring_write(ring, 1);
 275         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 276         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 277
 278         return ret;
 279 }
 280
 281 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 282                                            unsigned offset)
 283 {
 284         unsigned cur;
 285
 286         BUG_ON(offset > ring->buf_mask);
 287         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 288
 289         cur = (ring->wptr - 1) & ring->buf_mask;
 290         if (cur > offset)
 291                 ring->ring[offset] = cur - offset;
 292         else
 293                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 294 }
 295
 296 /**
 297  * sdma_v5_0_ring_get_rptr - get the current read pointer
 298  *
 299  * @ring: amdgpu ring pointer
 300  *
 301  * Get the current rptr from the hardware (NAVI10+).
 302  */
 303 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 304 {
 305         u64 *rptr;
 306
 307         /* XXX check if swapping is necessary on BE */
 308         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 309
 310         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 311         return ((*rptr) >> 2);
 312 }
 313
 314 /**
 315  * sdma_v5_0_ring_get_wptr - get the current write pointer
 316  *
 317  * @ring: amdgpu ring pointer
 318  *
 319  * Get the current wptr from the hardware (NAVI10+).
 320  */
 321 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 322 {
 323         struct amdgpu_device *adev = ring->adev;
 324         u64 wptr;
 325
 326         if (ring->use_doorbell) {
 327                 /* XXX check if swapping is necessary on BE */
 328                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 329                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 330         } else {
 331                 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 332                 wptr = wptr << 32;
 333                 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 334                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 335         }
 336
 337         return wptr >> 2;
 338 }
 339
 340 /**
 341  * sdma_v5_0_ring_set_wptr - commit the write pointer
 342  *
 343  * @ring: amdgpu ring pointer
 344  *
 345  * Write the wptr back to the hardware (NAVI10+).
 346  */
 347 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 348 {
 349         struct amdgpu_device *adev = ring->adev;
 350
 351         DRM_DEBUG("Setting write pointer\n");
 352         if (ring->use_doorbell) {
 353                 DRM_DEBUG("Using doorbell -- "
 354                                 "wptr_offs == 0x%08x "
 355                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 356                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 357                                 ring->wptr_offs,
 358                                 lower_32_bits(ring->wptr << 2),
 359                                 upper_32_bits(ring->wptr << 2));
 360                 /* XXX check if swapping is necessary on BE */
 361                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 362                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 363                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 364                                 ring->doorbell_index, ring->wptr << 2);
 365                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 366         } else {
 367                 DRM_DEBUG("Not using doorbell -- "
 368                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 369                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 370                                 ring->me,
 371                                 lower_32_bits(ring->wptr << 2),
 372                                 ring->me,
 373                                 upper_32_bits(ring->wptr << 2));
 374                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 375                         lower_32_bits(ring->wptr << 2));
 376                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 377                         upper_32_bits(ring->wptr << 2));
 378         }
 379 }
 380
 381 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 382 {
 383         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 384         int i;
 385
 386         for (i = 0; i < count; i++)
 387                 if (sdma && sdma->burst_nop && (i == 0))
 388                         amdgpu_ring_write(ring, ring->funcs->nop |
 389                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 390                 else
 391                         amdgpu_ring_write(ring, ring->funcs->nop);
 392 }
 393
 394 /**
 395  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 396  *
 397  * @ring: amdgpu ring pointer
 398  * @job: job to retrieve vmid from
 399  * @ib: IB object to schedule
 400  * @flags: unused
 401  *
 402  * Schedule an IB in the DMA ring (NAVI10).
 403  */
 404 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 405                                    struct amdgpu_job *job,
 406                                    struct amdgpu_ib *ib,
 407                                    uint32_t flags)
 408 {
 409         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 410         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 411
 412         /* An IB packet must end on a 8 DW boundary--the next dword
 413          * must be on a 8-dword boundary. Our IB packet below is 6
 414          * dwords long, thus add x number of NOPs, such that, in
 415          * modular arithmetic,
 416          * wptr + 6 + x = 8k, k >= 0, which in C is,
 417          * (wptr + 6 + x) % 8 = 0.
 418          * The expression below, is a solution of x.
 419          */
 420         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 421
 422         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 423                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 424         /* base must be 32 byte aligned */
 425         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 426         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 427         amdgpu_ring_write(ring, ib->length_dw);
 428         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 429         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 430 }
 431
 432 /**
 433  * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 434  *
 435  * @ring: amdgpu ring pointer
 436  * @job: job to retrieve vmid from
 437  * @ib: IB object to schedule
 438  *
 439  * flush the IB by graphics cache rinse.
 440  */
 441 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 442 {
 443         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 444                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 445                             SDMA_GCR_GLI_INV(1);
 446
 447         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 448         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 449         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 450         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 451                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 452         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 453                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 454         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 455                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 456 }
 457
 458 /**
 459  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 460  *
 461  * @ring: amdgpu ring pointer
 462  *
 463  * Emit an hdp flush packet on the requested DMA ring.
 464  */
 465 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 466 {
 467         struct amdgpu_device *adev = ring->adev;
 468         u32 ref_and_mask = 0;
 469         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 470
 471         if (ring->me == 0)
 472                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 473         else
 474                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 475
 476         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 477                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 478                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 479         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 480         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 481         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 482         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 483         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 484                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 485 }
 486
 487 /**
 488  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 489  *
 490  * @ring: amdgpu ring pointer
 491  * @addr: address
 492  * @seq: sequence number
 493  * @flags: fence related flags
 494  *
 495  * Add a DMA fence packet to the ring to write
 496  * the fence seq number and DMA trap packet to generate
 497  * an interrupt if needed (NAVI10).
 498  */
 499 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 500                                       unsigned flags)
 501 {
 502         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 503         /* write the fence */
 504         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 505                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 506         /* zero in first two bits */
 507         BUG_ON(addr & 0x3);
 508         amdgpu_ring_write(ring, lower_32_bits(addr));
 509         amdgpu_ring_write(ring, upper_32_bits(addr));
 510         amdgpu_ring_write(ring, lower_32_bits(seq));
 511
 512         /* optionally write high bits as well */
 513         if (write64bit) {
 514                 addr += 4;
 515                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 516                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 517                 /* zero in first two bits */
 518                 BUG_ON(addr & 0x3);
 519                 amdgpu_ring_write(ring, lower_32_bits(addr));
 520                 amdgpu_ring_write(ring, upper_32_bits(addr));
 521                 amdgpu_ring_write(ring, upper_32_bits(seq));
 522         }
 523
 524         if (flags & AMDGPU_FENCE_FLAG_INT) {
 525                 /* generate an interrupt */
 526                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 527                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 528         }
 529 }
 530
 531
 532 /**
 533  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 534  *
 535  * @adev: amdgpu_device pointer
 536  *
 537  * Stop the gfx async dma ring buffers (NAVI10).
 538  */
 539 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 540 {
 541         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 542         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 543         u32 rb_cntl, ib_cntl;
 544         int i;
 545
 546         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 547             (adev->mman.buffer_funcs_ring == sdma1))
 548                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 549
 550         for (i = 0; i < adev->sdma.num_instances; i++) {
 551                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 552                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 553                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 554                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 555                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 556                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 557         }
 558 }
 559
 560 /**
 561  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 562  *
 563  * @adev: amdgpu_device pointer
 564  *
 565  * Stop the compute async dma queues (NAVI10).
 566  */
 567 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 568 {
 569         /* XXX todo */
 570 }
 571
 572 /**
 573  * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
 574  *
 575  * @adev: amdgpu_device pointer
 576  * @enable: enable/disable the DMA MEs context switch.
 577  *
 578  * Halt or unhalt the async dma engines context switch (NAVI10).
 579  */
 580 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 581 {
 582         u32 f32_cntl = 0, phase_quantum = 0;
 583         int i;
 584
 585         if (amdgpu_sdma_phase_quantum) {
 586                 unsigned value = amdgpu_sdma_phase_quantum;
 587                 unsigned unit = 0;
 588
 589                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 590                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 591                         value = (value + 1) >> 1;
 592                         unit++;
 593                 }
 594                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 595                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 596                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 597                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 598                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 599                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 600                         WARN_ONCE(1,
 601                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 602                                   value << unit);
 603                 }
 604                 phase_quantum =
 605                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 606                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 607         }
 608
 609         for (i = 0; i < adev->sdma.num_instances; i++) {
 610                 if (!amdgpu_sriov_vf(adev)) {
 611                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 612                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 613                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 614                 }
 615
 616                 if (enable && amdgpu_sdma_phase_quantum) {
 617                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 618                                phase_quantum);
 619                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 620                                phase_quantum);
 621                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 622                                phase_quantum);
 623                 }
 624                 if (!amdgpu_sriov_vf(adev))
 625                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 626         }
 627
 628 }
 629
 630 /**
 631  * sdma_v5_0_enable - stop the async dma engines
 632  *
 633  * @adev: amdgpu_device pointer
 634  * @enable: enable/disable the DMA MEs.
 635  *
 636  * Halt or unhalt the async dma engines (NAVI10).
 637  */
 638 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 639 {
 640         u32 f32_cntl;
 641         int i;
 642
 643         if (!enable) {
 644                 sdma_v5_0_gfx_stop(adev);
 645                 sdma_v5_0_rlc_stop(adev);
 646         }
 647
 648         if (amdgpu_sriov_vf(adev))
 649                 return;
 650
 651         for (i = 0; i < adev->sdma.num_instances; i++) {
 652                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 653                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 654                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 655         }
 656 }
 657
 658 /**
 659  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 660  *
 661  * @adev: amdgpu_device pointer
 662  *
 663  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 664  * Returns 0 for success, error for failure.
 665  */
 666 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 667 {
 668         struct amdgpu_ring *ring;
 669         u32 rb_cntl, ib_cntl;
 670         u32 rb_bufsz;
 671         u32 wb_offset;
 672         u32 doorbell;
 673         u32 doorbell_offset;
 674         u32 temp;
 675         u32 wptr_poll_cntl;
 676         u64 wptr_gpu_addr;
 677         int i, r;
 678
 679         for (i = 0; i < adev->sdma.num_instances; i++) {
 680                 ring = &adev->sdma.instance[i].ring;
 681                 wb_offset = (ring->rptr_offs * 4);
 682
 683                 if (!amdgpu_sriov_vf(adev))
 684                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 685
 686                 /* Set ring buffer size in dwords */
 687                 rb_bufsz = order_base_2(ring->ring_size / 4);
 688                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 689                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 690 #ifdef __BIG_ENDIAN
 691                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 692                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 693                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 694 #endif
 695                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 696
 697                 /* Initialize the ring buffer's read and write pointers */
 698                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 699                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 700                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 701                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 702
 703                 /* setup the wptr shadow polling */
 704                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 705                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 706                        lower_32_bits(wptr_gpu_addr));
 707                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 708                        upper_32_bits(wptr_gpu_addr));
 709                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 710                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 711                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 712                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 713                                                F32_POLL_ENABLE, 1);
 714                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 715                        wptr_poll_cntl);
 716
 717                 /* set the wb address whether it's enabled or not */
 718                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 719                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 720                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 721                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 722
 723                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 724
 725                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
 726                        ring->gpu_addr >> 8);
 727                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
 728                        ring->gpu_addr >> 40);
 729
 730                 ring->wptr = 0;
 731
 732                 /* before programing wptr to a less value, need set minor_ptr_update first */
 733                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 734
 735                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 736                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
 737                                lower_32_bits(ring->wptr) << 2);
 738                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
 739                                upper_32_bits(ring->wptr) << 2);
 740                 }
 741
 742                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 743                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 744                                                 mmSDMA0_GFX_DOORBELL_OFFSET));
 745
 746                 if (ring->use_doorbell) {
 747                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 748                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 749                                         OFFSET, ring->doorbell_index);
 750                 } else {
 751                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 752                 }
 753                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 754                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
 755                        doorbell_offset);
 756
 757                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 758                                                       ring->doorbell_index, 20);
 759
 760                 if (amdgpu_sriov_vf(adev))
 761                         sdma_v5_0_ring_set_wptr(ring);
 762
 763                 /* set minor_ptr_update to 0 after wptr programed */
 764                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 765
 766                 if (!amdgpu_sriov_vf(adev)) {
 767                         /* set utc l1 enable flag always to 1 */
 768                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 769                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 770
 771                         /* enable MCBP */
 772                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 773                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 774
 775                         /* Set up RESP_MODE to non-copy addresses */
 776                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 777                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 778                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 779                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 780
 781                         /* program default cache read and write policy */
 782                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 783                         /* clean read policy and write policy bits */
 784                         temp &= 0xFF0FFF;
 785                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 786                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 787                 }
 788
 789                 if (!amdgpu_sriov_vf(adev)) {
 790                         /* unhalt engine */
 791                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 792                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 793                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 794                 }
 795
 796                 /* enable DMA RB */
 797                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 798                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 799
 800                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 801                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 802 #ifdef __BIG_ENDIAN
 803                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 804 #endif
 805                 /* enable DMA IBs */
 806                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 807
 808                 ring->sched.ready = true;
 809
 810                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 811                         sdma_v5_0_ctx_switch_enable(adev, true);
 812                         sdma_v5_0_enable(adev, true);
 813                 }
 814
 815                 r = amdgpu_ring_test_helper(ring);
 816                 if (r)
 817                         return r;
 818
 819                 if (adev->mman.buffer_funcs_ring == ring)
 820                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 821         }
 822
 823         return 0;
 824 }
 825
 826 /**
 827  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 828  *
 829  * @adev: amdgpu_device pointer
 830  *
 831  * Set up the compute DMA queues and enable them (NAVI10).
 832  * Returns 0 for success, error for failure.
 833  */
 834 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 835 {
 836         return 0;
 837 }
 838
 839 /**
 840  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 841  *
 842  * @adev: amdgpu_device pointer
 843  *
 844  * Loads the sDMA0/1 ucode.
 845  * Returns 0 for success, -EINVAL if the ucode is not available.
 846  */
 847 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 848 {
 849         const struct sdma_firmware_header_v1_0 *hdr;
 850         const __le32 *fw_data;
 851         u32 fw_size;
 852         int i, j;
 853
 854         /* halt the MEs */
 855         sdma_v5_0_enable(adev, false);
 856
 857         for (i = 0; i < adev->sdma.num_instances; i++) {
 858                 if (!adev->sdma.instance[i].fw)
 859                         return -EINVAL;
 860
 861                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 862                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 863                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 864
 865                 fw_data = (const __le32 *)
 866                         (adev->sdma.instance[i].fw->data +
 867                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 868
 869                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 870
 871                 for (j = 0; j < fw_size; j++) {
 872                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 873                                 msleep(1);
 874                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 875                 }
 876
 877                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 878         }
 879
 880         return 0;
 881 }
 882
 883 /**
 884  * sdma_v5_0_start - setup and start the async dma engines
 885  *
 886  * @adev: amdgpu_device pointer
 887  *
 888  * Set up the DMA engines and enable them (NAVI10).
 889  * Returns 0 for success, error for failure.
 890  */
 891 static int sdma_v5_0_start(struct amdgpu_device *adev)
 892 {
 893         int r = 0;
 894
 895         if (amdgpu_sriov_vf(adev)) {
 896                 sdma_v5_0_ctx_switch_enable(adev, false);
 897                 sdma_v5_0_enable(adev, false);
 898
 899                 /* set RB registers */
 900                 r = sdma_v5_0_gfx_resume(adev);
 901                 return r;
 902         }
 903
 904         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 905                 r = sdma_v5_0_load_microcode(adev);
 906                 if (r)
 907                         return r;
 908         }
 909
 910         /* unhalt the MEs */
 911         sdma_v5_0_enable(adev, true);
 912         /* enable sdma ring preemption */
 913         sdma_v5_0_ctx_switch_enable(adev, true);
 914
 915         /* start the gfx rings and rlc compute queues */
 916         r = sdma_v5_0_gfx_resume(adev);
 917         if (r)
 918                 return r;
 919         r = sdma_v5_0_rlc_resume(adev);
 920
 921         return r;
 922 }
 923
 924 /**
 925  * sdma_v5_0_ring_test_ring - simple async dma engine test
 926  *
 927  * @ring: amdgpu_ring structure holding ring information
 928  *
 929  * Test the DMA engine by writing using it to write an
 930  * value to memory. (NAVI10).
 931  * Returns 0 for success, error for failure.
 932  */
 933 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 934 {
 935         struct amdgpu_device *adev = ring->adev;
 936         unsigned i;
 937         unsigned index;
 938         int r;
 939         u32 tmp;
 940         u64 gpu_addr;
 941
 942         r = amdgpu_device_wb_get(adev, &index);
 943         if (r) {
 944                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 945                 return r;
 946         }
 947
 948         gpu_addr = adev->wb.gpu_addr + (index * 4);
 949         tmp = 0xCAFEDEAD;
 950         adev->wb.wb[index] = cpu_to_le32(tmp);
 951
 952         r = amdgpu_ring_alloc(ring, 5);
 953         if (r) {
 954                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 955                 amdgpu_device_wb_free(adev, index);
 956                 return r;
 957         }
 958
 959         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 960                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 961         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 962         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 963         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 964         amdgpu_ring_write(ring, 0xDEADBEEF);
 965         amdgpu_ring_commit(ring);
 966
 967         for (i = 0; i < adev->usec_timeout; i++) {
 968                 tmp = le32_to_cpu(adev->wb.wb[index]);
 969                 if (tmp == 0xDEADBEEF)
 970                         break;
 971                 if (amdgpu_emu_mode == 1)
 972                         msleep(1);
 973                 else
 974                         udelay(1);
 975         }
 976
 977         if (i >= adev->usec_timeout)
 978                 r = -ETIMEDOUT;
 979
 980         amdgpu_device_wb_free(adev, index);
 981
 982         return r;
 983 }
 984
 985 /**
 986  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 987  *
 988  * @ring: amdgpu_ring structure holding ring information
 989  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 990  *
 991  * Test a simple IB in the DMA ring (NAVI10).
 992  * Returns 0 on success, error on failure.
 993  */
 994 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 995 {
 996         struct amdgpu_device *adev = ring->adev;
 997         struct amdgpu_ib ib;
 998         struct dma_fence *f = NULL;
 999         unsigned index;
1000         long r;
1001         u32 tmp = 0;
1002         u64 gpu_addr;
1003
1004         r = amdgpu_device_wb_get(adev, &index);
1005         if (r) {
1006                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1007                 return r;
1008         }
1009
1010         gpu_addr = adev->wb.gpu_addr + (index * 4);
1011         tmp = 0xCAFEDEAD;
1012         adev->wb.wb[index] = cpu_to_le32(tmp);
1013         memset(&ib, 0, sizeof(ib));
1014         r = amdgpu_ib_get(adev, NULL, 256,
1015                                         AMDGPU_IB_POOL_DIRECT, &ib);
1016         if (r) {
1017                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1018                 goto err0;
1019         }
1020
1021         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1022                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1023         ib.ptr[1] = lower_32_bits(gpu_addr);
1024         ib.ptr[2] = upper_32_bits(gpu_addr);
1025         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1026         ib.ptr[4] = 0xDEADBEEF;
1027         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1028         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1029         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1030         ib.length_dw = 8;
1031
1032         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1033         if (r)
1034                 goto err1;
1035
1036         r = dma_fence_wait_timeout(f, false, timeout);
1037         if (r == 0) {
1038                 DRM_ERROR("amdgpu: IB test timed out\n");
1039                 r = -ETIMEDOUT;
1040                 goto err1;
1041         } else if (r < 0) {
1042                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1043                 goto err1;
1044         }
1045         tmp = le32_to_cpu(adev->wb.wb[index]);
1046         if (tmp == 0xDEADBEEF)
1047                 r = 0;
1048         else
1049                 r = -EINVAL;
1050
1051 err1:
1052         amdgpu_ib_free(adev, &ib, NULL);
1053         dma_fence_put(f);
1054 err0:
1055         amdgpu_device_wb_free(adev, index);
1056         return r;
1057 }
1058
1059
1060 /**
1061  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1062  *
1063  * @ib: indirect buffer to fill with commands
1064  * @pe: addr of the page entry
1065  * @src: src addr to copy from
1066  * @count: number of page entries to update
1067  *
1068  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1069  */
1070 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1071                                   uint64_t pe, uint64_t src,
1072                                   unsigned count)
1073 {
1074         unsigned bytes = count * 8;
1075
1076         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1077                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1078         ib->ptr[ib->length_dw++] = bytes - 1;
1079         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1080         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1081         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1082         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1083         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1084
1085 }
1086
1087 /**
1088  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1089  *
1090  * @ib: indirect buffer to fill with commands
1091  * @pe: addr of the page entry
1092  * @value: dst addr to write into pe
1093  * @count: number of page entries to update
1094  * @incr: increase next addr by incr bytes
1095  *
1096  * Update PTEs by writing them manually using sDMA (NAVI10).
1097  */
1098 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1099                                    uint64_t value, unsigned count,
1100                                    uint32_t incr)
1101 {
1102         unsigned ndw = count * 2;
1103
1104         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1105                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1106         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1107         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1108         ib->ptr[ib->length_dw++] = ndw - 1;
1109         for (; ndw > 0; ndw -= 2) {
1110                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1111                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1112                 value += incr;
1113         }
1114 }
1115
1116 /**
1117  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1118  *
1119  * @ib: indirect buffer to fill with commands
1120  * @pe: addr of the page entry
1121  * @addr: dst addr to write into pe
1122  * @count: number of page entries to update
1123  * @incr: increase next addr by incr bytes
1124  * @flags: access flags
1125  *
1126  * Update the page tables using sDMA (NAVI10).
1127  */
1128 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1129                                      uint64_t pe,
1130                                      uint64_t addr, unsigned count,
1131                                      uint32_t incr, uint64_t flags)
1132 {
1133         /* for physically contiguous pages (vram) */
1134         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1135         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1136         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1137         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1138         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1139         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1140         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1141         ib->ptr[ib->length_dw++] = incr; /* increment size */
1142         ib->ptr[ib->length_dw++] = 0;
1143         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1144 }
1145
1146 /**
1147  * sdma_v5_0_ring_pad_ib - pad the IB
1148  * @ring: amdgpu_ring structure holding ring information
1149  * @ib: indirect buffer to fill with padding
1150  *
1151  * Pad the IB with NOPs to a boundary multiple of 8.
1152  */
1153 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1154 {
1155         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1156         u32 pad_count;
1157         int i;
1158
1159         pad_count = (-ib->length_dw) & 0x7;
1160         for (i = 0; i < pad_count; i++)
1161                 if (sdma && sdma->burst_nop && (i == 0))
1162                         ib->ptr[ib->length_dw++] =
1163                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1164                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1165                 else
1166                         ib->ptr[ib->length_dw++] =
1167                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1168 }
1169
1170
1171 /**
1172  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1173  *
1174  * @ring: amdgpu_ring pointer
1175  *
1176  * Make sure all previous operations are completed (CIK).
1177  */
1178 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1179 {
1180         uint32_t seq = ring->fence_drv.sync_seq;
1181         uint64_t addr = ring->fence_drv.gpu_addr;
1182
1183         /* wait for idle */
1184         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1185                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1186                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1187                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1188         amdgpu_ring_write(ring, addr & 0xfffffffc);
1189         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1190         amdgpu_ring_write(ring, seq); /* reference */
1191         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1192         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1193                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1194 }
1195
1196
1197 /**
1198  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1199  *
1200  * @ring: amdgpu_ring pointer
1201  * @vmid: vmid number to use
1202  * @pd_addr: address
1203  *
1204  * Update the page table base and flush the VM TLB
1205  * using sDMA (NAVI10).
1206  */
1207 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1208                                          unsigned vmid, uint64_t pd_addr)
1209 {
1210         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1211 }
1212
1213 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1214                                      uint32_t reg, uint32_t val)
1215 {
1216         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1217                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1218         amdgpu_ring_write(ring, reg);
1219         amdgpu_ring_write(ring, val);
1220 }
1221
1222 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1223                                          uint32_t val, uint32_t mask)
1224 {
1225         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1226                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1227                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1228         amdgpu_ring_write(ring, reg << 2);
1229         amdgpu_ring_write(ring, 0);
1230         amdgpu_ring_write(ring, val); /* reference */
1231         amdgpu_ring_write(ring, mask); /* mask */
1232         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1233                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1234 }
1235
1236 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1237                                                    uint32_t reg0, uint32_t reg1,
1238                                                    uint32_t ref, uint32_t mask)
1239 {
1240         amdgpu_ring_emit_wreg(ring, reg0, ref);
1241         /* wait for a cycle to reset vm_inv_eng*_ack */
1242         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1243         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1244 }
1245
1246 static int sdma_v5_0_early_init(void *handle)
1247 {
1248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249
1250         adev->sdma.num_instances = 2;
1251
1252         sdma_v5_0_set_ring_funcs(adev);
1253         sdma_v5_0_set_buffer_funcs(adev);
1254         sdma_v5_0_set_vm_pte_funcs(adev);
1255         sdma_v5_0_set_irq_funcs(adev);
1256
1257         return 0;
1258 }
1259
1260
1261 static int sdma_v5_0_sw_init(void *handle)
1262 {
1263         struct amdgpu_ring *ring;
1264         int r, i;
1265         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266
1267         /* SDMA trap event */
1268         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1269                               SDMA0_5_0__SRCID__SDMA_TRAP,
1270                               &adev->sdma.trap_irq);
1271         if (r)
1272                 return r;
1273
1274         /* SDMA trap event */
1275         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1276                               SDMA1_5_0__SRCID__SDMA_TRAP,
1277                               &adev->sdma.trap_irq);
1278         if (r)
1279                 return r;
1280
1281         r = sdma_v5_0_init_microcode(adev);
1282         if (r) {
1283                 DRM_ERROR("Failed to load sdma firmware!\n");
1284                 return r;
1285         }
1286
1287         for (i = 0; i < adev->sdma.num_instances; i++) {
1288                 ring = &adev->sdma.instance[i].ring;
1289                 ring->ring_obj = NULL;
1290                 ring->use_doorbell = true;
1291
1292                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1293                                 ring->use_doorbell?"true":"false");
1294
1295                 ring->doorbell_index = (i == 0) ?
1296                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1297                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1298
1299                 sprintf(ring->name, "sdma%d", i);
1300                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1301                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1302                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1303                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1304                 if (r)
1305                         return r;
1306         }
1307
1308         return r;
1309 }
1310
1311 static int sdma_v5_0_sw_fini(void *handle)
1312 {
1313         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314         int i;
1315
1316         for (i = 0; i < adev->sdma.num_instances; i++) {
1317                 release_firmware(adev->sdma.instance[i].fw);
1318                 adev->sdma.instance[i].fw = NULL;
1319
1320                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1321         }
1322
1323         return 0;
1324 }
1325
1326 static int sdma_v5_0_hw_init(void *handle)
1327 {
1328         int r;
1329         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330
1331         sdma_v5_0_init_golden_registers(adev);
1332
1333         r = sdma_v5_0_start(adev);
1334
1335         return r;
1336 }
1337
1338 static int sdma_v5_0_hw_fini(void *handle)
1339 {
1340         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341
1342         if (amdgpu_sriov_vf(adev))
1343                 return 0;
1344
1345         sdma_v5_0_ctx_switch_enable(adev, false);
1346         sdma_v5_0_enable(adev, false);
1347
1348         return 0;
1349 }
1350
1351 static int sdma_v5_0_suspend(void *handle)
1352 {
1353         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354
1355         return sdma_v5_0_hw_fini(adev);
1356 }
1357
1358 static int sdma_v5_0_resume(void *handle)
1359 {
1360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1361
1362         return sdma_v5_0_hw_init(adev);
1363 }
1364
1365 static bool sdma_v5_0_is_idle(void *handle)
1366 {
1367         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1368         u32 i;
1369
1370         for (i = 0; i < adev->sdma.num_instances; i++) {
1371                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1372
1373                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1374                         return false;
1375         }
1376
1377         return true;
1378 }
1379
1380 static int sdma_v5_0_wait_for_idle(void *handle)
1381 {
1382         unsigned i;
1383         u32 sdma0, sdma1;
1384         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1385
1386         for (i = 0; i < adev->usec_timeout; i++) {
1387                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1388                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1389
1390                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1391                         return 0;
1392                 udelay(1);
1393         }
1394         return -ETIMEDOUT;
1395 }
1396
1397 static int sdma_v5_0_soft_reset(void *handle)
1398 {
1399         /* todo */
1400
1401         return 0;
1402 }
1403
1404 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1405 {
1406         int i, r = 0;
1407         struct amdgpu_device *adev = ring->adev;
1408         u32 index = 0;
1409         u64 sdma_gfx_preempt;
1410
1411         amdgpu_sdma_get_index_from_ring(ring, &index);
1412         if (index == 0)
1413                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1414         else
1415                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1416
1417         /* assert preemption condition */
1418         amdgpu_ring_set_preempt_cond_exec(ring, false);
1419
1420         /* emit the trailing fence */
1421         ring->trail_seq += 1;
1422         amdgpu_ring_alloc(ring, 10);
1423         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1424                                   ring->trail_seq, 0);
1425         amdgpu_ring_commit(ring);
1426
1427         /* assert IB preemption */
1428         WREG32(sdma_gfx_preempt, 1);
1429
1430         /* poll the trailing fence */
1431         for (i = 0; i < adev->usec_timeout; i++) {
1432                 if (ring->trail_seq ==
1433                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1434                         break;
1435                 udelay(1);
1436         }
1437
1438         if (i >= adev->usec_timeout) {
1439                 r = -EINVAL;
1440                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1441         }
1442
1443         /* deassert IB preemption */
1444         WREG32(sdma_gfx_preempt, 0);
1445
1446         /* deassert the preemption condition */
1447         amdgpu_ring_set_preempt_cond_exec(ring, true);
1448         return r;
1449 }
1450
1451 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1452                                         struct amdgpu_irq_src *source,
1453                                         unsigned type,
1454                                         enum amdgpu_interrupt_state state)
1455 {
1456         u32 sdma_cntl;
1457
1458         if (!amdgpu_sriov_vf(adev)) {
1459                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1460                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1461                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1462
1463                 sdma_cntl = RREG32(reg_offset);
1464                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1465                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1466                 WREG32(reg_offset, sdma_cntl);
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1473                                       struct amdgpu_irq_src *source,
1474                                       struct amdgpu_iv_entry *entry)
1475 {
1476         DRM_DEBUG("IH: SDMA trap\n");
1477         switch (entry->client_id) {
1478         case SOC15_IH_CLIENTID_SDMA0:
1479                 switch (entry->ring_id) {
1480                 case 0:
1481                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1482                         break;
1483                 case 1:
1484                         /* XXX compute */
1485                         break;
1486                 case 2:
1487                         /* XXX compute */
1488                         break;
1489                 case 3:
1490                         /* XXX page queue*/
1491                         break;
1492                 }
1493                 break;
1494         case SOC15_IH_CLIENTID_SDMA1:
1495                 switch (entry->ring_id) {
1496                 case 0:
1497                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1498                         break;
1499                 case 1:
1500                         /* XXX compute */
1501                         break;
1502                 case 2:
1503                         /* XXX compute */
1504                         break;
1505                 case 3:
1506                         /* XXX page queue*/
1507                         break;
1508                 }
1509                 break;
1510         }
1511         return 0;
1512 }
1513
1514 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1515                                               struct amdgpu_irq_src *source,
1516                                               struct amdgpu_iv_entry *entry)
1517 {
1518         return 0;
1519 }
1520
1521 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1522                                                        bool enable)
1523 {
1524         uint32_t data, def;
1525         int i;
1526
1527         for (i = 0; i < adev->sdma.num_instances; i++) {
1528                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1529                         /* Enable sdma clock gating */
1530                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1531                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1532                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1533                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1534                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1535                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1536                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1537                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1538                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1539                         if (def != data)
1540                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1541                 } else {
1542                         /* Disable sdma clock gating */
1543                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1544                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1545                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1546                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1547                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1548                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1549                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1550                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1551                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1552                         if (def != data)
1553                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1554                 }
1555         }
1556 }
1557
1558 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1559                                                       bool enable)
1560 {
1561         uint32_t data, def;
1562         int i;
1563
1564         for (i = 0; i < adev->sdma.num_instances; i++) {
1565                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1566                         /* Enable sdma mem light sleep */
1567                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1568                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1569                         if (def != data)
1570                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1571
1572                 } else {
1573                         /* Disable sdma mem light sleep */
1574                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1575                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1576                         if (def != data)
1577                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1578
1579                 }
1580         }
1581 }
1582
1583 static int sdma_v5_0_set_clockgating_state(void *handle,
1584                                            enum amd_clockgating_state state)
1585 {
1586         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1587
1588         if (amdgpu_sriov_vf(adev))
1589                 return 0;
1590
1591         switch (adev->asic_type) {
1592         case CHIP_NAVI10:
1593         case CHIP_NAVI14:
1594         case CHIP_NAVI12:
1595                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1596                                 state == AMD_CG_STATE_GATE);
1597                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1598                                 state == AMD_CG_STATE_GATE);
1599                 break;
1600         default:
1601                 break;
1602         }
1603
1604         return 0;
1605 }
1606
1607 static int sdma_v5_0_set_powergating_state(void *handle,
1608                                           enum amd_powergating_state state)
1609 {
1610         return 0;
1611 }
1612
1613 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1614 {
1615         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1616         int data;
1617
1618         if (amdgpu_sriov_vf(adev))
1619                 *flags = 0;
1620
1621         /* AMD_CG_SUPPORT_SDMA_MGCG */
1622         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1623         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1624                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1625
1626         /* AMD_CG_SUPPORT_SDMA_LS */
1627         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1628         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1629                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1630 }
1631
1632 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1633         .name = "sdma_v5_0",
1634         .early_init = sdma_v5_0_early_init,
1635         .late_init = NULL,
1636         .sw_init = sdma_v5_0_sw_init,
1637         .sw_fini = sdma_v5_0_sw_fini,
1638         .hw_init = sdma_v5_0_hw_init,
1639         .hw_fini = sdma_v5_0_hw_fini,
1640         .suspend = sdma_v5_0_suspend,
1641         .resume = sdma_v5_0_resume,
1642         .is_idle = sdma_v5_0_is_idle,
1643         .wait_for_idle = sdma_v5_0_wait_for_idle,
1644         .soft_reset = sdma_v5_0_soft_reset,
1645         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1646         .set_powergating_state = sdma_v5_0_set_powergating_state,
1647         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1648 };
1649
1650 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1651         .type = AMDGPU_RING_TYPE_SDMA,
1652         .align_mask = 0xf,
1653         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1654         .support_64bit_ptrs = true,
1655         .vmhub = AMDGPU_GFXHUB_0,
1656         .get_rptr = sdma_v5_0_ring_get_rptr,
1657         .get_wptr = sdma_v5_0_ring_get_wptr,
1658         .set_wptr = sdma_v5_0_ring_set_wptr,
1659         .emit_frame_size =
1660                 5 + /* sdma_v5_0_ring_init_cond_exec */
1661                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1662                 3 + /* hdp_invalidate */
1663                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1664                 /* sdma_v5_0_ring_emit_vm_flush */
1665                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1666                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1667                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1668         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1669         .emit_ib = sdma_v5_0_ring_emit_ib,
1670         .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1671         .emit_fence = sdma_v5_0_ring_emit_fence,
1672         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1673         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1674         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1675         .test_ring = sdma_v5_0_ring_test_ring,
1676         .test_ib = sdma_v5_0_ring_test_ib,
1677         .insert_nop = sdma_v5_0_ring_insert_nop,
1678         .pad_ib = sdma_v5_0_ring_pad_ib,
1679         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1680         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1681         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1682         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1683         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1684         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1685 };
1686
1687 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1688 {
1689         int i;
1690
1691         for (i = 0; i < adev->sdma.num_instances; i++) {
1692                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1693                 adev->sdma.instance[i].ring.me = i;
1694         }
1695 }
1696
1697 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1698         .set = sdma_v5_0_set_trap_irq_state,
1699         .process = sdma_v5_0_process_trap_irq,
1700 };
1701
1702 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1703         .process = sdma_v5_0_process_illegal_inst_irq,
1704 };
1705
1706 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1707 {
1708         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1709                                         adev->sdma.num_instances;
1710         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1711         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1712 }
1713
1714 /**
1715  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1716  *
1717  * @ib: indirect buffer to copy to
1718  * @src_offset: src GPU address
1719  * @dst_offset: dst GPU address
1720  * @byte_count: number of bytes to xfer
1721  * @tmz: if a secure copy should be used
1722  *
1723  * Copy GPU buffers using the DMA engine (NAVI10).
1724  * Used by the amdgpu ttm implementation to move pages if
1725  * registered as the asic copy callback.
1726  */
1727 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1728                                        uint64_t src_offset,
1729                                        uint64_t dst_offset,
1730                                        uint32_t byte_count,
1731                                        bool tmz)
1732 {
1733         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1734                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1735                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1736         ib->ptr[ib->length_dw++] = byte_count - 1;
1737         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1738         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1739         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1740         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1741         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1742 }
1743
1744 /**
1745  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1746  *
1747  * @ib: indirect buffer to fill
1748  * @src_data: value to write to buffer
1749  * @dst_offset: dst GPU address
1750  * @byte_count: number of bytes to xfer
1751  *
1752  * Fill GPU buffers using the DMA engine (NAVI10).
1753  */
1754 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1755                                        uint32_t src_data,
1756                                        uint64_t dst_offset,
1757                                        uint32_t byte_count)
1758 {
1759         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1760         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1761         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1762         ib->ptr[ib->length_dw++] = src_data;
1763         ib->ptr[ib->length_dw++] = byte_count - 1;
1764 }
1765
1766 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1767         .copy_max_bytes = 0x400000,
1768         .copy_num_dw = 7,
1769         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1770
1771         .fill_max_bytes = 0x400000,
1772         .fill_num_dw = 5,
1773         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1774 };
1775
1776 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1777 {
1778         if (adev->mman.buffer_funcs == NULL) {
1779                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1780                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1781         }
1782 }
1783
1784 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1785         .copy_pte_num_dw = 7,
1786         .copy_pte = sdma_v5_0_vm_copy_pte,
1787         .write_pte = sdma_v5_0_vm_write_pte,
1788         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1789 };
1790
1791 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1792 {
1793         unsigned i;
1794
1795         if (adev->vm_manager.vm_pte_funcs == NULL) {
1796                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1797                 for (i = 0; i < adev->sdma.num_instances; i++) {
1798                         adev->vm_manager.vm_pte_scheds[i] =
1799                                 &adev->sdma.instance[i].ring.sched;
1800                 }
1801                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1802         }
1803 }
1804
1805 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1806         .type = AMD_IP_BLOCK_TYPE_SDMA,
1807         .major = 5,
1808         .minor = 0,
1809         .rev = 0,
1810         .funcs = &sdma_v5_0_ip_funcs,
1811 };