2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <linux/delay.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
38 #include "gmc/gmc_8_1_d.h"
39 #include "gmc/gmc_8_1_sh_mask.h"
41 #include "gca/gfx_8_0_d.h"
42 #include "gca/gfx_8_0_enum.h"
43 #include "gca/gfx_8_0_sh_mask.h"
45 #include "bif/bif_5_0_d.h"
46 #include "bif/bif_5_0_sh_mask.h"
48 #include "tonga_sdma_pkt_open.h"
50 #include "ivsrcid/ivsrcid_vislands30.h"
52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
76 SDMA0_REGISTER_OFFSET,
80 static const u32 golden_settings_tonga_a11[] =
82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
88 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
89 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
91 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
94 static const u32 tonga_mgcg_cgcg_init[] =
96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
97 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
100 static const u32 golden_settings_fiji_a10[] =
102 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
104 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
107 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
108 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
109 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
112 static const u32 fiji_mgcg_cgcg_init[] =
114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
115 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
118 static const u32 golden_settings_polaris11_a11[] =
120 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
122 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
123 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
124 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
125 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
126 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
127 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
129 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
132 static const u32 golden_settings_polaris10_a11[] =
134 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
136 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
137 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
138 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
139 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
140 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
141 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
142 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
143 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
146 static const u32 cz_golden_settings_a11[] =
148 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
150 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
152 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
153 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
154 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
155 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
156 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
157 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
158 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
159 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
162 static const u32 cz_mgcg_cgcg_init[] =
164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
165 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
168 static const u32 stoney_golden_settings_a11[] =
170 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
172 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
173 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
176 static const u32 stoney_mgcg_cgcg_init[] =
178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
183 * Starting with CIK, the GPU has new asynchronous
184 * DMA engines. These engines are used for compute
185 * and gfx. There are two DMA engines (SDMA0, SDMA1)
186 * and each one supports 1 ring buffer used for gfx
187 * and 2 queues used for compute.
189 * The programming model is very similar to the CP
190 * (ring buffer, IBs, etc.), but sDMA has it's own
191 * packet format that is different from the PM4 format
192 * used by the CP. sDMA supports copying data, writing
193 * embedded data, solid fills, and a number of other
194 * things. It also has support for tiling/detiling of
198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
200 switch (adev->asic_type) {
202 amdgpu_device_program_register_sequence(adev,
204 ARRAY_SIZE(fiji_mgcg_cgcg_init));
205 amdgpu_device_program_register_sequence(adev,
206 golden_settings_fiji_a10,
207 ARRAY_SIZE(golden_settings_fiji_a10));
210 amdgpu_device_program_register_sequence(adev,
211 tonga_mgcg_cgcg_init,
212 ARRAY_SIZE(tonga_mgcg_cgcg_init));
213 amdgpu_device_program_register_sequence(adev,
214 golden_settings_tonga_a11,
215 ARRAY_SIZE(golden_settings_tonga_a11));
220 amdgpu_device_program_register_sequence(adev,
221 golden_settings_polaris11_a11,
222 ARRAY_SIZE(golden_settings_polaris11_a11));
225 amdgpu_device_program_register_sequence(adev,
226 golden_settings_polaris10_a11,
227 ARRAY_SIZE(golden_settings_polaris10_a11));
230 amdgpu_device_program_register_sequence(adev,
232 ARRAY_SIZE(cz_mgcg_cgcg_init));
233 amdgpu_device_program_register_sequence(adev,
234 cz_golden_settings_a11,
235 ARRAY_SIZE(cz_golden_settings_a11));
238 amdgpu_device_program_register_sequence(adev,
239 stoney_mgcg_cgcg_init,
240 ARRAY_SIZE(stoney_mgcg_cgcg_init));
241 amdgpu_device_program_register_sequence(adev,
242 stoney_golden_settings_a11,
243 ARRAY_SIZE(stoney_golden_settings_a11));
250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
253 for (i = 0; i < adev->sdma.num_instances; i++) {
254 release_firmware(adev->sdma.instance[i].fw);
255 adev->sdma.instance[i].fw = NULL;
260 * sdma_v3_0_init_microcode - load ucode images from disk
262 * @adev: amdgpu_device pointer
264 * Use the firmware interface to load the ucode images into
265 * the driver (not loaded into hw).
266 * Returns 0 on success, error on failure.
268 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
270 const char *chip_name;
273 struct amdgpu_firmware_info *info = NULL;
274 const struct common_firmware_header *header = NULL;
275 const struct sdma_firmware_header_v1_0 *hdr;
279 switch (adev->asic_type) {
287 chip_name = "polaris10";
290 chip_name = "polaris11";
293 chip_name = "polaris12";
299 chip_name = "carrizo";
302 chip_name = "stoney";
307 for (i = 0; i < adev->sdma.num_instances; i++) {
309 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
312 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
315 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
318 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
319 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
320 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
321 if (adev->sdma.instance[i].feature_version >= 20)
322 adev->sdma.instance[i].burst_nop = true;
324 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
325 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
326 info->fw = adev->sdma.instance[i].fw;
327 header = (const struct common_firmware_header *)info->fw->data;
328 adev->firmware.fw_size +=
329 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
334 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
335 for (i = 0; i < adev->sdma.num_instances; i++) {
336 release_firmware(adev->sdma.instance[i].fw);
337 adev->sdma.instance[i].fw = NULL;
344 * sdma_v3_0_ring_get_rptr - get the current read pointer
346 * @ring: amdgpu ring pointer
348 * Get the current rptr from the hardware (VI+).
350 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
352 /* XXX check if swapping is necessary on BE */
353 return ring->adev->wb.wb[ring->rptr_offs] >> 2;
357 * sdma_v3_0_ring_get_wptr - get the current write pointer
359 * @ring: amdgpu ring pointer
361 * Get the current wptr from the hardware (VI+).
363 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
365 struct amdgpu_device *adev = ring->adev;
368 if (ring->use_doorbell || ring->use_pollmem) {
369 /* XXX check if swapping is necessary on BE */
370 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
372 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
379 * sdma_v3_0_ring_set_wptr - commit the write pointer
381 * @ring: amdgpu ring pointer
383 * Write the wptr back to the hardware (VI+).
385 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
387 struct amdgpu_device *adev = ring->adev;
389 if (ring->use_doorbell) {
390 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
391 /* XXX check if swapping is necessary on BE */
392 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
393 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
394 } else if (ring->use_pollmem) {
395 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
397 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
403 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
405 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
408 for (i = 0; i < count; i++)
409 if (sdma && sdma->burst_nop && (i == 0))
410 amdgpu_ring_write(ring, ring->funcs->nop |
411 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
413 amdgpu_ring_write(ring, ring->funcs->nop);
417 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
419 * @ring: amdgpu ring pointer
420 * @ib: IB object to schedule
422 * Schedule an IB in the DMA ring (VI).
424 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
425 struct amdgpu_job *job,
426 struct amdgpu_ib *ib,
429 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
431 /* IB packet must end on a 8 DW boundary */
432 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
434 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
435 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
436 /* base must be 32 byte aligned */
437 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
438 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
439 amdgpu_ring_write(ring, ib->length_dw);
440 amdgpu_ring_write(ring, 0);
441 amdgpu_ring_write(ring, 0);
446 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
448 * @ring: amdgpu ring pointer
450 * Emit an hdp flush packet on the requested DMA ring.
452 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
454 u32 ref_and_mask = 0;
457 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
462 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
463 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
464 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
465 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
466 amdgpu_ring_write(ring, ref_and_mask); /* reference */
467 amdgpu_ring_write(ring, ref_and_mask); /* mask */
468 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
469 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
473 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
475 * @ring: amdgpu ring pointer
476 * @fence: amdgpu fence object
478 * Add a DMA fence packet to the ring to write
479 * the fence seq number and DMA trap packet to generate
480 * an interrupt if needed (VI).
482 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
485 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
486 /* write the fence */
487 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
488 amdgpu_ring_write(ring, lower_32_bits(addr));
489 amdgpu_ring_write(ring, upper_32_bits(addr));
490 amdgpu_ring_write(ring, lower_32_bits(seq));
492 /* optionally write high bits as well */
495 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
496 amdgpu_ring_write(ring, lower_32_bits(addr));
497 amdgpu_ring_write(ring, upper_32_bits(addr));
498 amdgpu_ring_write(ring, upper_32_bits(seq));
501 /* generate an interrupt */
502 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
503 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
507 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
509 * @adev: amdgpu_device pointer
511 * Stop the gfx async dma ring buffers (VI).
513 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
515 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
516 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
517 u32 rb_cntl, ib_cntl;
520 if ((adev->mman.buffer_funcs_ring == sdma0) ||
521 (adev->mman.buffer_funcs_ring == sdma1))
522 amdgpu_ttm_set_buffer_funcs_status(adev, false);
524 for (i = 0; i < adev->sdma.num_instances; i++) {
525 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
526 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
527 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
528 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
529 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
530 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
532 sdma0->sched.ready = false;
533 sdma1->sched.ready = false;
537 * sdma_v3_0_rlc_stop - stop the compute async dma engines
539 * @adev: amdgpu_device pointer
541 * Stop the compute async dma queues (VI).
543 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
549 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
551 * @adev: amdgpu_device pointer
552 * @enable: enable/disable the DMA MEs context switch.
554 * Halt or unhalt the async dma engines context switch (VI).
556 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
558 u32 f32_cntl, phase_quantum = 0;
561 if (amdgpu_sdma_phase_quantum) {
562 unsigned value = amdgpu_sdma_phase_quantum;
565 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
566 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
567 value = (value + 1) >> 1;
570 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
571 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
572 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
573 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
574 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
575 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
577 "clamping sdma_phase_quantum to %uK clock cycles\n",
581 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
582 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
585 for (i = 0; i < adev->sdma.num_instances; i++) {
586 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
588 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
589 AUTO_CTXSW_ENABLE, 1);
590 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
592 if (amdgpu_sdma_phase_quantum) {
593 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
595 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
599 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
600 AUTO_CTXSW_ENABLE, 0);
601 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
605 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
610 * sdma_v3_0_enable - stop the async dma engines
612 * @adev: amdgpu_device pointer
613 * @enable: enable/disable the DMA MEs.
615 * Halt or unhalt the async dma engines (VI).
617 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
623 sdma_v3_0_gfx_stop(adev);
624 sdma_v3_0_rlc_stop(adev);
627 for (i = 0; i < adev->sdma.num_instances; i++) {
628 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
630 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
632 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
633 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
638 * sdma_v3_0_gfx_resume - setup and start the async dma engines
640 * @adev: amdgpu_device pointer
642 * Set up the gfx DMA ring buffers and enable them (VI).
643 * Returns 0 for success, error for failure.
645 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
647 struct amdgpu_ring *ring;
648 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
655 for (i = 0; i < adev->sdma.num_instances; i++) {
656 ring = &adev->sdma.instance[i].ring;
657 amdgpu_ring_clear_ring(ring);
658 wb_offset = (ring->rptr_offs * 4);
660 mutex_lock(&adev->srbm_mutex);
661 for (j = 0; j < 16; j++) {
662 vi_srbm_select(adev, 0, 0, 0, j);
664 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
665 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
667 vi_srbm_select(adev, 0, 0, 0, 0);
668 mutex_unlock(&adev->srbm_mutex);
670 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
671 adev->gfx.config.gb_addr_config & 0x70);
673 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
675 /* Set ring buffer size in dwords */
676 rb_bufsz = order_base_2(ring->ring_size / 4);
677 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
681 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
682 RPTR_WRITEBACK_SWAP_ENABLE, 1);
684 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
686 /* Initialize the ring buffer's read and write pointers */
688 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
689 sdma_v3_0_ring_set_wptr(ring);
690 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
691 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
693 /* set the wb address whether it's enabled or not */
694 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
695 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
696 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
697 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
699 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
701 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
702 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
704 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
706 if (ring->use_doorbell) {
707 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
708 OFFSET, ring->doorbell_index);
709 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
711 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
713 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
715 /* setup the wptr shadow polling */
716 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
718 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
719 lower_32_bits(wptr_gpu_addr));
720 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
721 upper_32_bits(wptr_gpu_addr));
722 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
723 if (ring->use_pollmem) {
724 /*wptr polling is not enogh fast, directly clean the wptr register */
725 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
726 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
727 SDMA0_GFX_RB_WPTR_POLL_CNTL,
730 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
731 SDMA0_GFX_RB_WPTR_POLL_CNTL,
734 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
737 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
738 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
740 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
741 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
743 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
746 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
748 ring->sched.ready = true;
752 sdma_v3_0_enable(adev, true);
753 /* enable sdma ring preemption */
754 sdma_v3_0_ctx_switch_enable(adev, true);
756 for (i = 0; i < adev->sdma.num_instances; i++) {
757 ring = &adev->sdma.instance[i].ring;
758 r = amdgpu_ring_test_helper(ring);
762 if (adev->mman.buffer_funcs_ring == ring)
763 amdgpu_ttm_set_buffer_funcs_status(adev, true);
770 * sdma_v3_0_rlc_resume - setup and start the async dma engines
772 * @adev: amdgpu_device pointer
774 * Set up the compute DMA queues and enable them (VI).
775 * Returns 0 for success, error for failure.
777 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
784 * sdma_v3_0_start - setup and start the async dma engines
786 * @adev: amdgpu_device pointer
788 * Set up the DMA engines and enable them (VI).
789 * Returns 0 for success, error for failure.
791 static int sdma_v3_0_start(struct amdgpu_device *adev)
795 /* disable sdma engine before programing it */
796 sdma_v3_0_ctx_switch_enable(adev, false);
797 sdma_v3_0_enable(adev, false);
799 /* start the gfx rings and rlc compute queues */
800 r = sdma_v3_0_gfx_resume(adev);
803 r = sdma_v3_0_rlc_resume(adev);
811 * sdma_v3_0_ring_test_ring - simple async dma engine test
813 * @ring: amdgpu_ring structure holding ring information
815 * Test the DMA engine by writing using it to write an
816 * value to memory. (VI).
817 * Returns 0 for success, error for failure.
819 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
821 struct amdgpu_device *adev = ring->adev;
828 r = amdgpu_device_wb_get(adev, &index);
832 gpu_addr = adev->wb.gpu_addr + (index * 4);
834 adev->wb.wb[index] = cpu_to_le32(tmp);
836 r = amdgpu_ring_alloc(ring, 5);
840 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
841 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
842 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
843 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
844 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
845 amdgpu_ring_write(ring, 0xDEADBEEF);
846 amdgpu_ring_commit(ring);
848 for (i = 0; i < adev->usec_timeout; i++) {
849 tmp = le32_to_cpu(adev->wb.wb[index]);
850 if (tmp == 0xDEADBEEF)
855 if (i >= adev->usec_timeout)
859 amdgpu_device_wb_free(adev, index);
864 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
866 * @ring: amdgpu_ring structure holding ring information
868 * Test a simple IB in the DMA ring (VI).
869 * Returns 0 on success, error on failure.
871 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
873 struct amdgpu_device *adev = ring->adev;
875 struct dma_fence *f = NULL;
881 r = amdgpu_device_wb_get(adev, &index);
885 gpu_addr = adev->wb.gpu_addr + (index * 4);
887 adev->wb.wb[index] = cpu_to_le32(tmp);
888 memset(&ib, 0, sizeof(ib));
889 r = amdgpu_ib_get(adev, NULL, 256,
890 AMDGPU_IB_POOL_DIRECT, &ib);
894 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
895 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
896 ib.ptr[1] = lower_32_bits(gpu_addr);
897 ib.ptr[2] = upper_32_bits(gpu_addr);
898 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
899 ib.ptr[4] = 0xDEADBEEF;
900 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
901 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
902 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
905 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
909 r = dma_fence_wait_timeout(f, false, timeout);
916 tmp = le32_to_cpu(adev->wb.wb[index]);
917 if (tmp == 0xDEADBEEF)
922 amdgpu_ib_free(adev, &ib, NULL);
925 amdgpu_device_wb_free(adev, index);
930 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
932 * @ib: indirect buffer to fill with commands
933 * @pe: addr of the page entry
934 * @src: src addr to copy from
935 * @count: number of page entries to update
937 * Update PTEs by copying them from the GART using sDMA (CIK).
939 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
940 uint64_t pe, uint64_t src,
943 unsigned bytes = count * 8;
945 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
946 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
947 ib->ptr[ib->length_dw++] = bytes;
948 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
949 ib->ptr[ib->length_dw++] = lower_32_bits(src);
950 ib->ptr[ib->length_dw++] = upper_32_bits(src);
951 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
952 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
956 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
958 * @ib: indirect buffer to fill with commands
959 * @pe: addr of the page entry
960 * @value: dst addr to write into pe
961 * @count: number of page entries to update
962 * @incr: increase next addr by incr bytes
964 * Update PTEs by writing them manually using sDMA (CIK).
966 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
967 uint64_t value, unsigned count,
970 unsigned ndw = count * 2;
972 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
973 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
974 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
975 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
976 ib->ptr[ib->length_dw++] = ndw;
977 for (; ndw > 0; ndw -= 2) {
978 ib->ptr[ib->length_dw++] = lower_32_bits(value);
979 ib->ptr[ib->length_dw++] = upper_32_bits(value);
985 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
987 * @ib: indirect buffer to fill with commands
988 * @pe: addr of the page entry
989 * @addr: dst addr to write into pe
990 * @count: number of page entries to update
991 * @incr: increase next addr by incr bytes
992 * @flags: access flags
994 * Update the page tables using sDMA (CIK).
996 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
997 uint64_t addr, unsigned count,
998 uint32_t incr, uint64_t flags)
1000 /* for physically contiguous pages (vram) */
1001 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1002 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1003 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1004 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1005 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1006 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1007 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1008 ib->ptr[ib->length_dw++] = incr; /* increment size */
1009 ib->ptr[ib->length_dw++] = 0;
1010 ib->ptr[ib->length_dw++] = count; /* number of entries */
1014 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1016 * @ib: indirect buffer to fill with padding
1019 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1021 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1025 pad_count = (-ib->length_dw) & 7;
1026 for (i = 0; i < pad_count; i++)
1027 if (sdma && sdma->burst_nop && (i == 0))
1028 ib->ptr[ib->length_dw++] =
1029 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1030 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1032 ib->ptr[ib->length_dw++] =
1033 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1037 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1039 * @ring: amdgpu_ring pointer
1041 * Make sure all previous operations are completed (CIK).
1043 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1045 uint32_t seq = ring->fence_drv.sync_seq;
1046 uint64_t addr = ring->fence_drv.gpu_addr;
1049 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1050 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1051 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1052 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1053 amdgpu_ring_write(ring, addr & 0xfffffffc);
1054 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1055 amdgpu_ring_write(ring, seq); /* reference */
1056 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1057 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1058 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1062 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1064 * @ring: amdgpu_ring pointer
1065 * @vm: amdgpu_vm pointer
1067 * Update the page table base and flush the VM TLB
1070 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1071 unsigned vmid, uint64_t pd_addr)
1073 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1075 /* wait for flush */
1076 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1077 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1078 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1079 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1080 amdgpu_ring_write(ring, 0);
1081 amdgpu_ring_write(ring, 0); /* reference */
1082 amdgpu_ring_write(ring, 0); /* mask */
1083 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1084 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1087 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1088 uint32_t reg, uint32_t val)
1090 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1091 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1092 amdgpu_ring_write(ring, reg);
1093 amdgpu_ring_write(ring, val);
1096 static int sdma_v3_0_early_init(void *handle)
1098 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1100 switch (adev->asic_type) {
1102 adev->sdma.num_instances = 1;
1105 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1109 sdma_v3_0_set_ring_funcs(adev);
1110 sdma_v3_0_set_buffer_funcs(adev);
1111 sdma_v3_0_set_vm_pte_funcs(adev);
1112 sdma_v3_0_set_irq_funcs(adev);
1117 static int sdma_v3_0_sw_init(void *handle)
1119 struct amdgpu_ring *ring;
1121 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1123 /* SDMA trap event */
1124 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1125 &adev->sdma.trap_irq);
1129 /* SDMA Privileged inst */
1130 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1131 &adev->sdma.illegal_inst_irq);
1135 /* SDMA Privileged inst */
1136 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1137 &adev->sdma.illegal_inst_irq);
1141 r = sdma_v3_0_init_microcode(adev);
1143 DRM_ERROR("Failed to load sdma firmware!\n");
1147 for (i = 0; i < adev->sdma.num_instances; i++) {
1148 ring = &adev->sdma.instance[i].ring;
1149 ring->ring_obj = NULL;
1150 if (!amdgpu_sriov_vf(adev)) {
1151 ring->use_doorbell = true;
1152 ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1154 ring->use_pollmem = true;
1157 sprintf(ring->name, "sdma%d", i);
1158 r = amdgpu_ring_init(adev, ring, 1024,
1159 &adev->sdma.trap_irq,
1161 AMDGPU_SDMA_IRQ_INSTANCE0 :
1162 AMDGPU_SDMA_IRQ_INSTANCE1);
1170 static int sdma_v3_0_sw_fini(void *handle)
1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175 for (i = 0; i < adev->sdma.num_instances; i++)
1176 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1178 sdma_v3_0_free_microcode(adev);
1182 static int sdma_v3_0_hw_init(void *handle)
1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187 sdma_v3_0_init_golden_registers(adev);
1189 r = sdma_v3_0_start(adev);
1196 static int sdma_v3_0_hw_fini(void *handle)
1198 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1200 sdma_v3_0_ctx_switch_enable(adev, false);
1201 sdma_v3_0_enable(adev, false);
1206 static int sdma_v3_0_suspend(void *handle)
1208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210 return sdma_v3_0_hw_fini(adev);
1213 static int sdma_v3_0_resume(void *handle)
1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217 return sdma_v3_0_hw_init(adev);
1220 static bool sdma_v3_0_is_idle(void *handle)
1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223 u32 tmp = RREG32(mmSRBM_STATUS2);
1225 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1226 SRBM_STATUS2__SDMA1_BUSY_MASK))
1232 static int sdma_v3_0_wait_for_idle(void *handle)
1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1238 for (i = 0; i < adev->usec_timeout; i++) {
1239 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1240 SRBM_STATUS2__SDMA1_BUSY_MASK);
1249 static bool sdma_v3_0_check_soft_reset(void *handle)
1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1252 u32 srbm_soft_reset = 0;
1253 u32 tmp = RREG32(mmSRBM_STATUS2);
1255 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1256 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1257 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1258 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1261 if (srbm_soft_reset) {
1262 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1265 adev->sdma.srbm_soft_reset = 0;
1270 static int sdma_v3_0_pre_soft_reset(void *handle)
1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1273 u32 srbm_soft_reset = 0;
1275 if (!adev->sdma.srbm_soft_reset)
1278 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1280 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1281 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1282 sdma_v3_0_ctx_switch_enable(adev, false);
1283 sdma_v3_0_enable(adev, false);
1289 static int sdma_v3_0_post_soft_reset(void *handle)
1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292 u32 srbm_soft_reset = 0;
1294 if (!adev->sdma.srbm_soft_reset)
1297 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1299 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1300 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1301 sdma_v3_0_gfx_resume(adev);
1302 sdma_v3_0_rlc_resume(adev);
1308 static int sdma_v3_0_soft_reset(void *handle)
1310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1311 u32 srbm_soft_reset = 0;
1314 if (!adev->sdma.srbm_soft_reset)
1317 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1319 if (srbm_soft_reset) {
1320 tmp = RREG32(mmSRBM_SOFT_RESET);
1321 tmp |= srbm_soft_reset;
1322 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1323 WREG32(mmSRBM_SOFT_RESET, tmp);
1324 tmp = RREG32(mmSRBM_SOFT_RESET);
1328 tmp &= ~srbm_soft_reset;
1329 WREG32(mmSRBM_SOFT_RESET, tmp);
1330 tmp = RREG32(mmSRBM_SOFT_RESET);
1332 /* Wait a little for things to settle down */
1339 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1340 struct amdgpu_irq_src *source,
1342 enum amdgpu_interrupt_state state)
1347 case AMDGPU_SDMA_IRQ_INSTANCE0:
1349 case AMDGPU_IRQ_STATE_DISABLE:
1350 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1351 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1352 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1354 case AMDGPU_IRQ_STATE_ENABLE:
1355 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1356 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1357 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1363 case AMDGPU_SDMA_IRQ_INSTANCE1:
1365 case AMDGPU_IRQ_STATE_DISABLE:
1366 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1367 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1368 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1370 case AMDGPU_IRQ_STATE_ENABLE:
1371 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1372 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1373 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1385 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1386 struct amdgpu_irq_src *source,
1387 struct amdgpu_iv_entry *entry)
1389 u8 instance_id, queue_id;
1391 instance_id = (entry->ring_id & 0x3) >> 0;
1392 queue_id = (entry->ring_id & 0xc) >> 2;
1393 DRM_DEBUG("IH: SDMA trap\n");
1394 switch (instance_id) {
1398 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1411 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1425 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1426 struct amdgpu_irq_src *source,
1427 struct amdgpu_iv_entry *entry)
1429 u8 instance_id, queue_id;
1431 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1432 instance_id = (entry->ring_id & 0x3) >> 0;
1433 queue_id = (entry->ring_id & 0xc) >> 2;
1435 if (instance_id <= 1 && queue_id == 0)
1436 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1440 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1441 struct amdgpu_device *adev,
1444 uint32_t temp, data;
1447 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1448 for (i = 0; i < adev->sdma.num_instances; i++) {
1449 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1450 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1452 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1453 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1454 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1455 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1456 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1459 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1462 for (i = 0; i < adev->sdma.num_instances; i++) {
1463 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1464 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1465 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1466 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1467 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1468 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1469 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1474 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1479 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1480 struct amdgpu_device *adev,
1483 uint32_t temp, data;
1486 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1487 for (i = 0; i < adev->sdma.num_instances; i++) {
1488 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1489 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1492 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1495 for (i = 0; i < adev->sdma.num_instances; i++) {
1496 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1497 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1500 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1505 static int sdma_v3_0_set_clockgating_state(void *handle,
1506 enum amd_clockgating_state state)
1508 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1510 if (amdgpu_sriov_vf(adev))
1513 switch (adev->asic_type) {
1517 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1518 state == AMD_CG_STATE_GATE);
1519 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1520 state == AMD_CG_STATE_GATE);
1528 static int sdma_v3_0_set_powergating_state(void *handle,
1529 enum amd_powergating_state state)
1534 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1536 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1539 if (amdgpu_sriov_vf(adev))
1542 /* AMD_CG_SUPPORT_SDMA_MGCG */
1543 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1544 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1545 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1547 /* AMD_CG_SUPPORT_SDMA_LS */
1548 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1549 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1550 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1553 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1554 .name = "sdma_v3_0",
1555 .early_init = sdma_v3_0_early_init,
1557 .sw_init = sdma_v3_0_sw_init,
1558 .sw_fini = sdma_v3_0_sw_fini,
1559 .hw_init = sdma_v3_0_hw_init,
1560 .hw_fini = sdma_v3_0_hw_fini,
1561 .suspend = sdma_v3_0_suspend,
1562 .resume = sdma_v3_0_resume,
1563 .is_idle = sdma_v3_0_is_idle,
1564 .wait_for_idle = sdma_v3_0_wait_for_idle,
1565 .check_soft_reset = sdma_v3_0_check_soft_reset,
1566 .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1567 .post_soft_reset = sdma_v3_0_post_soft_reset,
1568 .soft_reset = sdma_v3_0_soft_reset,
1569 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1570 .set_powergating_state = sdma_v3_0_set_powergating_state,
1571 .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1574 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1575 .type = AMDGPU_RING_TYPE_SDMA,
1577 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1578 .support_64bit_ptrs = false,
1579 .get_rptr = sdma_v3_0_ring_get_rptr,
1580 .get_wptr = sdma_v3_0_ring_get_wptr,
1581 .set_wptr = sdma_v3_0_ring_set_wptr,
1583 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1584 3 + /* hdp invalidate */
1585 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1586 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1587 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1588 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1589 .emit_ib = sdma_v3_0_ring_emit_ib,
1590 .emit_fence = sdma_v3_0_ring_emit_fence,
1591 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1592 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1593 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1594 .test_ring = sdma_v3_0_ring_test_ring,
1595 .test_ib = sdma_v3_0_ring_test_ib,
1596 .insert_nop = sdma_v3_0_ring_insert_nop,
1597 .pad_ib = sdma_v3_0_ring_pad_ib,
1598 .emit_wreg = sdma_v3_0_ring_emit_wreg,
1601 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1605 for (i = 0; i < adev->sdma.num_instances; i++) {
1606 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1607 adev->sdma.instance[i].ring.me = i;
1611 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1612 .set = sdma_v3_0_set_trap_irq_state,
1613 .process = sdma_v3_0_process_trap_irq,
1616 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1617 .process = sdma_v3_0_process_illegal_inst_irq,
1620 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1622 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1623 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1624 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1628 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1630 * @ring: amdgpu_ring structure holding ring information
1631 * @src_offset: src GPU address
1632 * @dst_offset: dst GPU address
1633 * @byte_count: number of bytes to xfer
1635 * Copy GPU buffers using the DMA engine (VI).
1636 * Used by the amdgpu ttm implementation to move pages if
1637 * registered as the asic copy callback.
1639 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1640 uint64_t src_offset,
1641 uint64_t dst_offset,
1642 uint32_t byte_count)
1644 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1645 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1646 ib->ptr[ib->length_dw++] = byte_count;
1647 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1648 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1649 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1650 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1651 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1655 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1657 * @ring: amdgpu_ring structure holding ring information
1658 * @src_data: value to write to buffer
1659 * @dst_offset: dst GPU address
1660 * @byte_count: number of bytes to xfer
1662 * Fill GPU buffers using the DMA engine (VI).
1664 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1666 uint64_t dst_offset,
1667 uint32_t byte_count)
1669 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1670 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1671 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1672 ib->ptr[ib->length_dw++] = src_data;
1673 ib->ptr[ib->length_dw++] = byte_count;
1676 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1677 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1679 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1681 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1683 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1686 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1688 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1689 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1692 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1693 .copy_pte_num_dw = 7,
1694 .copy_pte = sdma_v3_0_vm_copy_pte,
1696 .write_pte = sdma_v3_0_vm_write_pte,
1697 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1700 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1704 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1705 for (i = 0; i < adev->sdma.num_instances; i++) {
1706 adev->vm_manager.vm_pte_scheds[i] =
1707 &adev->sdma.instance[i].ring.sched;
1709 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1712 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1714 .type = AMD_IP_BLOCK_TYPE_SDMA,
1718 .funcs = &sdma_v3_0_ip_funcs,
1721 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1723 .type = AMD_IP_BLOCK_TYPE_SDMA,
1727 .funcs = &sdma_v3_0_ip_funcs,