drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __MMSCH_V2_0_H__
  25 #define __MMSCH_V2_0_H__
  26
  27 // addressBlock: uvd0_mmsch_dec
  28 // base address: 0x1e000
  29 #define mmMMSCH_UCODE_ADDR                                                                             0x0000
  30 #define mmMMSCH_UCODE_ADDR_BASE_IDX                                                                    0
  31 #define mmMMSCH_UCODE_DATA                                                                             0x0001
  32 #define mmMMSCH_UCODE_DATA_BASE_IDX                                                                    0
  33 #define mmMMSCH_SRAM_ADDR                                                                              0x0002
  34 #define mmMMSCH_SRAM_ADDR_BASE_IDX                                                                     0
  35 #define mmMMSCH_SRAM_DATA                                                                              0x0003
  36 #define mmMMSCH_SRAM_DATA_BASE_IDX                                                                     0
  37 #define mmMMSCH_VF_SRAM_OFFSET                                                                         0x0004
  38 #define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX                                                                0
  39 #define mmMMSCH_DB_SRAM_OFFSET                                                                         0x0005
  40 #define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX                                                                0
  41 #define mmMMSCH_CTX_SRAM_OFFSET                                                                        0x0006
  42 #define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX                                                               0
  43 #define mmMMSCH_CTL                                                                                    0x0007
  44 #define mmMMSCH_CTL_BASE_IDX                                                                           0
  45 #define mmMMSCH_INTR                                                                                   0x0008
  46 #define mmMMSCH_INTR_BASE_IDX                                                                          0
  47 #define mmMMSCH_INTR_ACK                                                                               0x0009
  48 #define mmMMSCH_INTR_ACK_BASE_IDX                                                                      0
  49 #define mmMMSCH_INTR_STATUS                                                                            0x000a
  50 #define mmMMSCH_INTR_STATUS_BASE_IDX                                                                   0
  51 #define mmMMSCH_VF_VMID                                                                                0x000b
  52 #define mmMMSCH_VF_VMID_BASE_IDX                                                                       0
  53 #define mmMMSCH_VF_CTX_ADDR_LO                                                                         0x000c
  54 #define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX                                                                0
  55 #define mmMMSCH_VF_CTX_ADDR_HI                                                                         0x000d
  56 #define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX                                                                0
  57 #define mmMMSCH_VF_CTX_SIZE                                                                            0x000e
  58 #define mmMMSCH_VF_CTX_SIZE_BASE_IDX                                                                   0
  59 #define mmMMSCH_VF_GPCOM_ADDR_LO                                                                       0x000f
  60 #define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX                                                              0
  61 #define mmMMSCH_VF_GPCOM_ADDR_HI                                                                       0x0010
  62 #define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX                                                              0
  63 #define mmMMSCH_VF_GPCOM_SIZE                                                                          0x0011
  64 #define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX                                                                 0
  65 #define mmMMSCH_VF_MAILBOX_HOST                                                                        0x0012
  66 #define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX                                                               0
  67 #define mmMMSCH_VF_MAILBOX_RESP                                                                        0x0013
  68 #define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX                                                               0
  69 #define mmMMSCH_VF_MAILBOX_0                                                                           0x0014
  70 #define mmMMSCH_VF_MAILBOX_0_BASE_IDX                                                                  0
  71 #define mmMMSCH_VF_MAILBOX_0_RESP                                                                      0x0015
  72 #define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX                                                             0
  73 #define mmMMSCH_VF_MAILBOX_1                                                                           0x0016
  74 #define mmMMSCH_VF_MAILBOX_1_BASE_IDX                                                                  0
  75 #define mmMMSCH_VF_MAILBOX_1_RESP                                                                      0x0017
  76 #define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX                                                             0
  77 #define mmMMSCH_CNTL                                                                                   0x001c
  78 #define mmMMSCH_CNTL_BASE_IDX                                                                          0
  79 #define mmMMSCH_NONCACHE_OFFSET0                                                                       0x001d
  80 #define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX                                                              0
  81 #define mmMMSCH_NONCACHE_SIZE0                                                                         0x001e
  82 #define mmMMSCH_NONCACHE_SIZE0_BASE_IDX                                                                0
  83 #define mmMMSCH_NONCACHE_OFFSET1                                                                       0x001f
  84 #define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX                                                              0
  85 #define mmMMSCH_NONCACHE_SIZE1                                                                         0x0020
  86 #define mmMMSCH_NONCACHE_SIZE1_BASE_IDX                                                                0
  87 #define mmMMSCH_PDEBUG_STATUS                                                                          0x0021
  88 #define mmMMSCH_PDEBUG_STATUS_BASE_IDX                                                                 0
  89 #define mmMMSCH_PDEBUG_DATA_32UPPERBITS                                                                0x0022
  90 #define mmMMSCH_PDEBUG_DATA_32UPPERBITS_BASE_IDX                                                       0
  91 #define mmMMSCH_PDEBUG_DATA_32LOWERBITS                                                                0x0023
  92 #define mmMMSCH_PDEBUG_DATA_32LOWERBITS_BASE_IDX                                                       0
  93 #define mmMMSCH_PDEBUG_EPC                                                                             0x0024
  94 #define mmMMSCH_PDEBUG_EPC_BASE_IDX                                                                    0
  95 #define mmMMSCH_PDEBUG_EXCCAUSE                                                                        0x0025
  96 #define mmMMSCH_PDEBUG_EXCCAUSE_BASE_IDX                                                               0
  97 #define mmMMSCH_PROC_STATE1                                                                            0x0026
  98 #define mmMMSCH_PROC_STATE1_BASE_IDX                                                                   0
  99 #define mmMMSCH_LAST_MC_ADDR                                                                           0x0027
 100 #define mmMMSCH_LAST_MC_ADDR_BASE_IDX                                                                  0
 101 #define mmMMSCH_LAST_MEM_ACCESS_HI                                                                     0x0028
 102 #define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX                                                            0
 103 #define mmMMSCH_LAST_MEM_ACCESS_LO                                                                     0x0029
 104 #define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX                                                            0
 105 #define mmMMSCH_IOV_ACTIVE_FCN_ID                                                                      0x002a
 106 #define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX                                                             0
 107 #define mmMMSCH_SCRATCH_0                                                                              0x002b
 108 #define mmMMSCH_SCRATCH_0_BASE_IDX                                                                     0
 109 #define mmMMSCH_SCRATCH_1                                                                              0x002c
 110 #define mmMMSCH_SCRATCH_1_BASE_IDX                                                                     0
 111 #define mmMMSCH_GPUIOV_SCH_BLOCK_0                                                                     0x002d
 112 #define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX                                                            0
 113 #define mmMMSCH_GPUIOV_CMD_CONTROL_0                                                                   0x002e
 114 #define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX                                                          0
 115 #define mmMMSCH_GPUIOV_CMD_STATUS_0                                                                    0x002f
 116 #define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX                                                           0
 117 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0                                                                0x0030
 118 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX                                                       0
 119 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_0                                                                   0x0031
 120 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX                                                          0
 121 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0                                                                 0x0032
 122 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX                                                        0
 123 #define mmMMSCH_GPUIOV_DW6_0                                                                           0x0033
 124 #define mmMMSCH_GPUIOV_DW6_0_BASE_IDX                                                                  0
 125 #define mmMMSCH_GPUIOV_DW7_0                                                                           0x0034
 126 #define mmMMSCH_GPUIOV_DW7_0_BASE_IDX                                                                  0
 127 #define mmMMSCH_GPUIOV_DW8_0                                                                           0x0035
 128 #define mmMMSCH_GPUIOV_DW8_0_BASE_IDX                                                                  0
 129 #define mmMMSCH_GPUIOV_SCH_BLOCK_1                                                                     0x0036
 130 #define mmMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX                                                            0
 131 #define mmMMSCH_GPUIOV_CMD_CONTROL_1                                                                   0x0037
 132 #define mmMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX                                                          0
 133 #define mmMMSCH_GPUIOV_CMD_STATUS_1                                                                    0x0038
 134 #define mmMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX                                                           0
 135 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1                                                                0x0039
 136 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX                                                       0
 137 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_1                                                                   0x003a
 138 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX                                                          0
 139 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1                                                                 0x003b
 140 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX                                                        0
 141 #define mmMMSCH_GPUIOV_DW6_1                                                                           0x003c
 142 #define mmMMSCH_GPUIOV_DW6_1_BASE_IDX                                                                  0
 143 #define mmMMSCH_GPUIOV_DW7_1                                                                           0x003d
 144 #define mmMMSCH_GPUIOV_DW7_1_BASE_IDX                                                                  0
 145 #define mmMMSCH_GPUIOV_DW8_1                                                                           0x003e
 146 #define mmMMSCH_GPUIOV_DW8_1_BASE_IDX                                                                  0
 147 #define mmMMSCH_GPUIOV_CNTXT                                                                           0x003f
 148 #define mmMMSCH_GPUIOV_CNTXT_BASE_IDX                                                                  0
 149 #define mmMMSCH_SCRATCH_2                                                                              0x0040
 150 #define mmMMSCH_SCRATCH_2_BASE_IDX                                                                     0
 151 #define mmMMSCH_SCRATCH_3                                                                              0x0041
 152 #define mmMMSCH_SCRATCH_3_BASE_IDX                                                                     0
 153 #define mmMMSCH_SCRATCH_4                                                                              0x0042
 154 #define mmMMSCH_SCRATCH_4_BASE_IDX                                                                     0
 155 #define mmMMSCH_SCRATCH_5                                                                              0x0043
 156 #define mmMMSCH_SCRATCH_5_BASE_IDX                                                                     0
 157 #define mmMMSCH_SCRATCH_6                                                                              0x0044
 158 #define mmMMSCH_SCRATCH_6_BASE_IDX                                                                     0
 159 #define mmMMSCH_SCRATCH_7                                                                              0x0045
 160 #define mmMMSCH_SCRATCH_7_BASE_IDX                                                                     0
 161 #define mmMMSCH_VFID_FIFO_HEAD_0                                                                       0x0046
 162 #define mmMMSCH_VFID_FIFO_HEAD_0_BASE_IDX                                                              0
 163 #define mmMMSCH_VFID_FIFO_TAIL_0                                                                       0x0047
 164 #define mmMMSCH_VFID_FIFO_TAIL_0_BASE_IDX                                                              0
 165 #define mmMMSCH_VFID_FIFO_HEAD_1                                                                       0x0048
 166 #define mmMMSCH_VFID_FIFO_HEAD_1_BASE_IDX                                                              0
 167 #define mmMMSCH_VFID_FIFO_TAIL_1                                                                       0x0049
 168 #define mmMMSCH_VFID_FIFO_TAIL_1_BASE_IDX                                                              0
 169 #define mmMMSCH_NACK_STATUS                                                                            0x004a
 170 #define mmMMSCH_NACK_STATUS_BASE_IDX                                                                   0
 171 #define mmMMSCH_VF_MAILBOX0_DATA                                                                       0x004b
 172 #define mmMMSCH_VF_MAILBOX0_DATA_BASE_IDX                                                              0
 173 #define mmMMSCH_VF_MAILBOX1_DATA                                                                       0x004c
 174 #define mmMMSCH_VF_MAILBOX1_DATA_BASE_IDX                                                              0
 175 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0                                                                  0x004d
 176 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX                                                         0
 177 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_0                                                                 0x004e
 178 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX                                                        0
 179 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0                                                              0x004f
 180 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX                                                     0
 181 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1                                                                  0x0050
 182 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX                                                         0
 183 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_1                                                                 0x0051
 184 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX                                                        0
 185 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1                                                              0x0052
 186 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX                                                     0
 187 #define mmMMSCH_GPUIOV_CNTXT_IP                                                                        0x0053
 188 #define mmMMSCH_GPUIOV_CNTXT_IP_BASE_IDX                                                               0
 189 #define mmMMSCH_GPUIOV_SCH_BLOCK_2                                                                     0x0054
 190 #define mmMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX                                                            0
 191 #define mmMMSCH_GPUIOV_CMD_CONTROL_2                                                                   0x0055
 192 #define mmMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX                                                          0
 193 #define mmMMSCH_GPUIOV_CMD_STATUS_2                                                                    0x0056
 194 #define mmMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX                                                           0
 195 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2                                                                0x0057
 196 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX                                                       0
 197 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_2                                                                   0x0058
 198 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX                                                          0
 199 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2                                                                 0x0059
 200 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX                                                        0
 201 #define mmMMSCH_GPUIOV_DW6_2                                                                           0x005a
 202 #define mmMMSCH_GPUIOV_DW6_2_BASE_IDX                                                                  0
 203 #define mmMMSCH_GPUIOV_DW7_2                                                                           0x005b
 204 #define mmMMSCH_GPUIOV_DW7_2_BASE_IDX                                                                  0
 205 #define mmMMSCH_GPUIOV_DW8_2                                                                           0x005c
 206 #define mmMMSCH_GPUIOV_DW8_2_BASE_IDX                                                                  0
 207 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2                                                                  0x005d
 208 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX                                                         0
 209 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_2                                                                 0x005e
 210 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX                                                        0
 211 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2                                                              0x005f
 212 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX                                                     0
 213 #define mmMMSCH_VFID_FIFO_HEAD_2                                                                       0x0060
 214 #define mmMMSCH_VFID_FIFO_HEAD_2_BASE_IDX                                                              0
 215 #define mmMMSCH_VFID_FIFO_TAIL_2                                                                       0x0061
 216 #define mmMMSCH_VFID_FIFO_TAIL_2_BASE_IDX                                                              0
 217 #define mmMMSCH_VM_BUSY_STATUS_0                                                                       0x0062
 218 #define mmMMSCH_VM_BUSY_STATUS_0_BASE_IDX                                                              0
 219 #define mmMMSCH_VM_BUSY_STATUS_1                                                                       0x0063
 220 #define mmMMSCH_VM_BUSY_STATUS_1_BASE_IDX                                                              0
 221 #define mmMMSCH_VM_BUSY_STATUS_2                                                                       0x0064
 222 #define mmMMSCH_VM_BUSY_STATUS_2_BASE_IDX                                                              0
 223
 224 #define MMSCH_VERSION_MAJOR     2
 225 #define MMSCH_VERSION_MINOR     0
 226 #define MMSCH_VERSION   (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
 227
 228 enum mmsch_v2_0_command_type {
 229         MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
 230         MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
 231         MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
 232         MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
 233         MMSCH_COMMAND__END = 0xf
 234 };
 235
 236 struct mmsch_v2_0_init_header {
 237         uint32_t version;
 238         uint32_t header_size;
 239         uint32_t vcn_init_status;
 240         uint32_t vcn_table_offset;
 241         uint32_t vcn_table_size;
 242 };
 243
 244 struct mmsch_v2_0_cmd_direct_reg_header {
 245         uint32_t reg_offset   : 28;
 246         uint32_t command_type : 4;
 247 };
 248
 249 struct mmsch_v2_0_cmd_indirect_reg_header {
 250         uint32_t reg_offset    : 20;
 251         uint32_t reg_idx_space : 8;
 252         uint32_t command_type  : 4;
 253 };
 254
 255 struct mmsch_v2_0_cmd_direct_write {
 256         struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
 257         uint32_t reg_value;
 258 };
 259
 260 struct mmsch_v2_0_cmd_direct_read_modify_write {
 261         struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
 262         uint32_t write_data;
 263         uint32_t mask_value;
 264 };
 265
 266 struct mmsch_v2_0_cmd_direct_polling {
 267         struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
 268         uint32_t mask_value;
 269         uint32_t wait_value;
 270 };
 271
 272 struct mmsch_v2_0_cmd_end {
 273         struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
 274 };
 275
 276 struct mmsch_v2_0_cmd_indirect_write {
 277         struct mmsch_v2_0_cmd_indirect_reg_header cmd_header;
 278         uint32_t reg_value;
 279 };
 280
 281 static inline void mmsch_v2_0_insert_direct_wt(struct mmsch_v2_0_cmd_direct_write *direct_wt,
 282                                                uint32_t *init_table,
 283                                                uint32_t reg_offset,
 284                                                uint32_t value)
 285 {
 286         direct_wt->cmd_header.reg_offset = reg_offset;
 287         direct_wt->reg_value = value;
 288         memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v2_0_cmd_direct_write));
 289 }
 290
 291 static inline void mmsch_v2_0_insert_direct_rd_mod_wt(struct mmsch_v2_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
 292                                                       uint32_t *init_table,
 293                                                       uint32_t reg_offset,
 294                                                       uint32_t mask, uint32_t data)
 295 {
 296         direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
 297         direct_rd_mod_wt->mask_value = mask;
 298         direct_rd_mod_wt->write_data = data;
 299         memcpy((void *)init_table, direct_rd_mod_wt,
 300                sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write));
 301 }
 302
 303 static inline void mmsch_v2_0_insert_direct_poll(struct mmsch_v2_0_cmd_direct_polling *direct_poll,
 304                                                  uint32_t *init_table,
 305                                                  uint32_t reg_offset,
 306                                                  uint32_t mask, uint32_t wait)
 307 {
 308         direct_poll->cmd_header.reg_offset = reg_offset;
 309         direct_poll->mask_value = mask;
 310         direct_poll->wait_value = wait;
 311         memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v2_0_cmd_direct_polling));
 312 }
 313
 314 #define MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
 315         mmsch_v2_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
 316                                            init_table, (reg), \
 317                                            (mask), (data)); \
 318         init_table += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \
 319         table_size += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \
 320 }
 321
 322 #define MMSCH_V2_0_INSERT_DIRECT_WT(reg, value) { \
 323         mmsch_v2_0_insert_direct_wt(&direct_wt, \
 324                                     init_table, (reg), \
 325                                     (value)); \
 326         init_table += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \
 327         table_size += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \
 328 }
 329
 330 #define MMSCH_V2_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
 331         mmsch_v2_0_insert_direct_poll(&direct_poll, \
 332                                       init_table, (reg), \
 333                                       (mask), (wait)); \
 334         init_table += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \
 335         table_size += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \
 336 }
 337
 338 #endif