drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_11_0_0_offset.h"
  30 #include "gc/gc_11_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v11_structs.h"
  33 #include "mes_v11_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
  41
  42 static int mes_v11_0_hw_fini(void *handle);
  43 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
  44 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
  45
  46 #define MES_EOP_SIZE   2048
  47
  48 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
  49 {
  50         struct amdgpu_device *adev = ring->adev;
  51
  52         if (ring->use_doorbell) {
  53                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  54                              ring->wptr);
  55                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  56         } else {
  57                 BUG();
  58         }
  59 }
  60
  61 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
  62 {
  63         return *ring->rptr_cpu_addr;
  64 }
  65
  66 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
  67 {
  68         u64 wptr;
  69
  70         if (ring->use_doorbell)
  71                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  72         else
  73                 BUG();
  74         return wptr;
  75 }
  76
  77 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
  78         .type = AMDGPU_RING_TYPE_MES,
  79         .align_mask = 1,
  80         .nop = 0,
  81         .support_64bit_ptrs = true,
  82         .get_rptr = mes_v11_0_ring_get_rptr,
  83         .get_wptr = mes_v11_0_ring_get_wptr,
  84         .set_wptr = mes_v11_0_ring_set_wptr,
  85         .insert_nop = amdgpu_ring_insert_nop,
  86 };
  87
  88 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
  89                                                     void *pkt, int size)
  90 {
  91         int ndw = size / 4;
  92         signed long r;
  93         union MESAPI__ADD_QUEUE *x_pkt = pkt;
  94         struct amdgpu_device *adev = mes->adev;
  95         struct amdgpu_ring *ring = &mes->ring;
  96
  97         BUG_ON(size % 4 != 0);
  98
  99         if (amdgpu_ring_alloc(ring, ndw))
 100                 return -ENOMEM;
 101
 102         amdgpu_ring_write_multiple(ring, pkt, ndw);
 103         amdgpu_ring_commit(ring);
 104
 105         DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
 106
 107         r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
 108                       adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1));
 109         if (r < 1) {
 110                 DRM_ERROR("MES failed to response msg=%d\n",
 111                           x_pkt->header.opcode);
 112                 return -ETIMEDOUT;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int convert_to_mes_queue_type(int queue_type)
 119 {
 120         if (queue_type == AMDGPU_RING_TYPE_GFX)
 121                 return MES_QUEUE_TYPE_GFX;
 122         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 123                 return MES_QUEUE_TYPE_COMPUTE;
 124         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 125                 return MES_QUEUE_TYPE_SDMA;
 126         else
 127                 BUG();
 128         return -1;
 129 }
 130
 131 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 132                                   struct mes_add_queue_input *input)
 133 {
 134         struct amdgpu_device *adev = mes->adev;
 135         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 136         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 137         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 138
 139         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 140
 141         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 142         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 143         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 144
 145         mes_add_queue_pkt.process_id = input->process_id;
 146         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 147         mes_add_queue_pkt.process_va_start = input->process_va_start;
 148         mes_add_queue_pkt.process_va_end = input->process_va_end;
 149         mes_add_queue_pkt.process_quantum = input->process_quantum;
 150         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 151         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 152         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 153         mes_add_queue_pkt.inprocess_gang_priority =
 154                 input->inprocess_gang_priority;
 155         mes_add_queue_pkt.gang_global_priority_level =
 156                 input->gang_global_priority_level;
 157         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 158         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 159         mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 160         mes_add_queue_pkt.queue_type =
 161                 convert_to_mes_queue_type(input->queue_type);
 162         mes_add_queue_pkt.paging = input->paging;
 163         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 164         mes_add_queue_pkt.gws_base = input->gws_base;
 165         mes_add_queue_pkt.gws_size = input->gws_size;
 166         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 167         mes_add_queue_pkt.tma_addr = input->tma_addr;
 168
 169         mes_add_queue_pkt.api_status.api_completion_fence_addr =
 170                 mes->ring.fence_drv.gpu_addr;
 171         mes_add_queue_pkt.api_status.api_completion_fence_value =
 172                 ++mes->ring.fence_drv.sync_seq;
 173
 174         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 175                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt));
 176 }
 177
 178 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
 179                                      struct mes_remove_queue_input *input)
 180 {
 181         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 182
 183         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 184
 185         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 186         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 187         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 188
 189         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 190         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 191
 192         mes_remove_queue_pkt.api_status.api_completion_fence_addr =
 193                 mes->ring.fence_drv.gpu_addr;
 194         mes_remove_queue_pkt.api_status.api_completion_fence_value =
 195                 ++mes->ring.fence_drv.sync_seq;
 196
 197         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 198                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt));
 199 }
 200
 201 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 202                         struct mes_unmap_legacy_queue_input *input)
 203 {
 204         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 205
 206         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 207
 208         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 209         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 210         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 211
 212         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset << 2;
 213         mes_remove_queue_pkt.gang_context_addr = 0;
 214
 215         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 216         mes_remove_queue_pkt.queue_id = input->queue_id;
 217
 218         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 219                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 220                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 221                 mes_remove_queue_pkt.tf_data =
 222                         lower_32_bits(input->trail_fence_data);
 223         } else {
 224                 if (input->queue_type == AMDGPU_RING_TYPE_GFX)
 225                         mes_remove_queue_pkt.unmap_legacy_gfx_queue = 1;
 226                 else
 227                         mes_remove_queue_pkt.unmap_kiq_utility_queue = 1;
 228         }
 229
 230         mes_remove_queue_pkt.api_status.api_completion_fence_addr =
 231                 mes->ring.fence_drv.gpu_addr;
 232         mes_remove_queue_pkt.api_status.api_completion_fence_value =
 233                 ++mes->ring.fence_drv.sync_seq;
 234
 235         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 236                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt));
 237 }
 238
 239 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
 240                                   struct mes_suspend_gang_input *input)
 241 {
 242         return 0;
 243 }
 244
 245 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
 246                                  struct mes_resume_gang_input *input)
 247 {
 248         return 0;
 249 }
 250
 251 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 252 {
 253         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 254
 255         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 256
 257         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 258         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 259         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 260
 261         mes_status_pkt.api_status.api_completion_fence_addr =
 262                 mes->ring.fence_drv.gpu_addr;
 263         mes_status_pkt.api_status.api_completion_fence_value =
 264                 ++mes->ring.fence_drv.sync_seq;
 265
 266         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 267                         &mes_status_pkt, sizeof(mes_status_pkt));
 268 }
 269
 270 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 271 {
 272         int i;
 273         struct amdgpu_device *adev = mes->adev;
 274         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 275
 276         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 277
 278         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 279         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 280         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 281
 282         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 283         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 284         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 285         mes_set_hw_res_pkt.paging_vmid = 0;
 286         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 287         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 288                 mes->query_status_fence_gpu_addr;
 289
 290         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 291                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 292                         mes->compute_hqd_mask[i];
 293
 294         for (i = 0; i < MAX_GFX_PIPES; i++)
 295                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 296
 297         for (i = 0; i < MAX_SDMA_PIPES; i++)
 298                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 299
 300         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 301                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 302                         mes->agreegated_doorbells[i];
 303
 304         for (i = 0; i < 5; i++) {
 305                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 306                 mes_set_hw_res_pkt.mmhub_base[i] =
 307                                 adev->reg_offset[MMHUB_HWIP][0][i];
 308                 mes_set_hw_res_pkt.osssys_base[i] =
 309                 adev->reg_offset[OSSSYS_HWIP][0][i];
 310         }
 311
 312         mes_set_hw_res_pkt.disable_reset = 1;
 313         mes_set_hw_res_pkt.disable_mes_log = 1;
 314         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 315
 316         mes_set_hw_res_pkt.api_status.api_completion_fence_addr =
 317                 mes->ring.fence_drv.gpu_addr;
 318         mes_set_hw_res_pkt.api_status.api_completion_fence_value =
 319                 ++mes->ring.fence_drv.sync_seq;
 320
 321         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 322                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt));
 323 }
 324
 325 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 326         .add_hw_queue = mes_v11_0_add_hw_queue,
 327         .remove_hw_queue = mes_v11_0_remove_hw_queue,
 328         .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 329         .suspend_gang = mes_v11_0_suspend_gang,
 330         .resume_gang = mes_v11_0_resume_gang,
 331 };
 332
 333 static int mes_v11_0_init_microcode(struct amdgpu_device *adev,
 334                                     enum admgpu_mes_pipe pipe)
 335 {
 336         char fw_name[30];
 337         char ucode_prefix[30];
 338         int err;
 339         const struct mes_firmware_header_v1_0 *mes_hdr;
 340         struct amdgpu_firmware_info *info;
 341
 342         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 343
 344         if (pipe == AMDGPU_MES_SCHED_PIPE)
 345                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
 346                          ucode_prefix);
 347         else
 348                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin",
 349                          ucode_prefix);
 350
 351         err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
 352         if (err)
 353                 return err;
 354
 355         err = amdgpu_ucode_validate(adev->mes.fw[pipe]);
 356         if (err) {
 357                 release_firmware(adev->mes.fw[pipe]);
 358                 adev->mes.fw[pipe] = NULL;
 359                 return err;
 360         }
 361
 362         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 363                 adev->mes.fw[pipe]->data;
 364         adev->mes.ucode_fw_version[pipe] =
 365                 le32_to_cpu(mes_hdr->mes_ucode_version);
 366         adev->mes.ucode_fw_version[pipe] =
 367                 le32_to_cpu(mes_hdr->mes_ucode_data_version);
 368         adev->mes.uc_start_addr[pipe] =
 369                 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
 370                 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
 371         adev->mes.data_start_addr[pipe] =
 372                 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
 373                 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
 374
 375         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 376                 int ucode, ucode_data;
 377
 378                 if (pipe == AMDGPU_MES_SCHED_PIPE) {
 379                         ucode = AMDGPU_UCODE_ID_CP_MES;
 380                         ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
 381                 } else {
 382                         ucode = AMDGPU_UCODE_ID_CP_MES1;
 383                         ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
 384                 }
 385
 386                 info = &adev->firmware.ucode[ucode];
 387                 info->ucode_id = ucode;
 388                 info->fw = adev->mes.fw[pipe];
 389                 adev->firmware.fw_size +=
 390                         ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
 391                               PAGE_SIZE);
 392
 393                 info = &adev->firmware.ucode[ucode_data];
 394                 info->ucode_id = ucode_data;
 395                 info->fw = adev->mes.fw[pipe];
 396                 adev->firmware.fw_size +=
 397                         ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
 398                               PAGE_SIZE);
 399         }
 400
 401         return 0;
 402 }
 403
 404 static void mes_v11_0_free_microcode(struct amdgpu_device *adev,
 405                                      enum admgpu_mes_pipe pipe)
 406 {
 407         release_firmware(adev->mes.fw[pipe]);
 408         adev->mes.fw[pipe] = NULL;
 409 }
 410
 411 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 412                                            enum admgpu_mes_pipe pipe)
 413 {
 414         int r;
 415         const struct mes_firmware_header_v1_0 *mes_hdr;
 416         const __le32 *fw_data;
 417         unsigned fw_size;
 418
 419         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 420                 adev->mes.fw[pipe]->data;
 421
 422         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 423                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 424         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 425
 426         r = amdgpu_bo_create_reserved(adev, fw_size,
 427                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 428                                       &adev->mes.ucode_fw_obj[pipe],
 429                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 430                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 431         if (r) {
 432                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 433                 return r;
 434         }
 435
 436         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 437
 438         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 439         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 440
 441         return 0;
 442 }
 443
 444 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 445                                                 enum admgpu_mes_pipe pipe)
 446 {
 447         int r;
 448         const struct mes_firmware_header_v1_0 *mes_hdr;
 449         const __le32 *fw_data;
 450         unsigned fw_size;
 451
 452         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 453                 adev->mes.fw[pipe]->data;
 454
 455         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 456                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 457         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 458
 459         r = amdgpu_bo_create_reserved(adev, fw_size,
 460                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
 461                                       &adev->mes.data_fw_obj[pipe],
 462                                       &adev->mes.data_fw_gpu_addr[pipe],
 463                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 464         if (r) {
 465                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 466                 return r;
 467         }
 468
 469         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 470
 471         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 472         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 473
 474         return 0;
 475 }
 476
 477 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
 478                                          enum admgpu_mes_pipe pipe)
 479 {
 480         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 481                               &adev->mes.data_fw_gpu_addr[pipe],
 482                               (void **)&adev->mes.data_fw_ptr[pipe]);
 483
 484         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 485                               &adev->mes.ucode_fw_gpu_addr[pipe],
 486                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 487 }
 488
 489 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 490 {
 491         uint64_t ucode_addr;
 492         uint32_t pipe, data = 0;
 493
 494         if (enable) {
 495                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 496                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 497                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 498                              MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
 499                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 500
 501                 mutex_lock(&adev->srbm_mutex);
 502                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 503                         if (!adev->enable_mes_kiq &&
 504                             pipe == AMDGPU_MES_KIQ_PIPE)
 505                                 continue;
 506
 507                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 508
 509                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 510                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 511                                      lower_32_bits(ucode_addr));
 512                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 513                                      upper_32_bits(ucode_addr));
 514                 }
 515                 soc21_grbm_select(adev, 0, 0, 0, 0);
 516                 mutex_unlock(&adev->srbm_mutex);
 517
 518                 /* unhalt MES and activate pipe0 */
 519                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 520                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 521                                      adev->enable_mes_kiq ? 1 : 0);
 522                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 523
 524                 if (amdgpu_emu_mode)
 525                         msleep(100);
 526                 else
 527                         udelay(50);
 528         } else {
 529                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 530                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 531                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 532                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 533                                      MES_INVALIDATE_ICACHE, 1);
 534                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 535                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 536                                      adev->enable_mes_kiq ? 1 : 0);
 537                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 538                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 539         }
 540 }
 541
 542 /* This function is for backdoor MES firmware */
 543 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 544                                     enum admgpu_mes_pipe pipe)
 545 {
 546         int r;
 547         uint32_t data;
 548         uint64_t ucode_addr;
 549
 550         mes_v11_0_enable(adev, false);
 551
 552         if (!adev->mes.fw[pipe])
 553                 return -EINVAL;
 554
 555         r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
 556         if (r)
 557                 return r;
 558
 559         r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
 560         if (r) {
 561                 mes_v11_0_free_ucode_buffers(adev, pipe);
 562                 return r;
 563         }
 564
 565         mutex_lock(&adev->srbm_mutex);
 566         /* me=3, pipe=0, queue=0 */
 567         soc21_grbm_select(adev, 3, pipe, 0, 0);
 568
 569         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 570
 571         /* set ucode start address */
 572         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 573         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 574                      lower_32_bits(ucode_addr));
 575         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 576                      upper_32_bits(ucode_addr));
 577
 578         /* set ucode fimrware address */
 579         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 580                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 581         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 582                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 583
 584         /* set ucode instruction cache boundary to 2M-1 */
 585         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 586
 587         /* set ucode data firmware address */
 588         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 589                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 590         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 591                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 592
 593         /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
 594         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
 595
 596         /* invalidate ICACHE */
 597         data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 598         data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 599         data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 600         WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 601
 602         /* prime the ICACHE. */
 603         data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 604         data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 605         WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 606
 607         soc21_grbm_select(adev, 0, 0, 0, 0);
 608         mutex_unlock(&adev->srbm_mutex);
 609
 610         return 0;
 611 }
 612
 613 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
 614                                       enum admgpu_mes_pipe pipe)
 615 {
 616         int r;
 617         u32 *eop;
 618
 619         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 620                               AMDGPU_GEM_DOMAIN_GTT,
 621                               &adev->mes.eop_gpu_obj[pipe],
 622                               &adev->mes.eop_gpu_addr[pipe],
 623                               (void **)&eop);
 624         if (r) {
 625                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 626                 return r;
 627         }
 628
 629         memset(eop, 0,
 630                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 631
 632         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 633         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 634
 635         return 0;
 636 }
 637
 638 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
 639 {
 640         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 641         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 642         uint32_t tmp;
 643
 644         mqd->header = 0xC0310800;
 645         mqd->compute_pipelinestat_enable = 0x00000001;
 646         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 647         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 648         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 649         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 650         mqd->compute_misc_reserved = 0x00000007;
 651
 652         eop_base_addr = ring->eop_gpu_addr >> 8;
 653
 654         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 655         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 656         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 657                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 658
 659         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 660         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 661         mqd->cp_hqd_eop_control = tmp;
 662
 663         /* disable the queue if it's active */
 664         ring->wptr = 0;
 665         mqd->cp_hqd_pq_rptr = 0;
 666         mqd->cp_hqd_pq_wptr_lo = 0;
 667         mqd->cp_hqd_pq_wptr_hi = 0;
 668
 669         /* set the pointer to the MQD */
 670         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 671         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 672
 673         /* set MQD vmid to 0 */
 674         tmp = regCP_MQD_CONTROL_DEFAULT;
 675         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 676         mqd->cp_mqd_control = tmp;
 677
 678         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 679         hqd_gpu_addr = ring->gpu_addr >> 8;
 680         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 681         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 682
 683         /* set the wb address whether it's enabled or not */
 684         wb_gpu_addr = ring->rptr_gpu_addr;
 685         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 686         mqd->cp_hqd_pq_rptr_report_addr_hi =
 687                 upper_32_bits(wb_gpu_addr) & 0xffff;
 688
 689         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 690         wb_gpu_addr = ring->wptr_gpu_addr;
 691         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 692         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 693
 694         /* set up the HQD, this is similar to CP_RB0_CNTL */
 695         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 696         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 697                             (order_base_2(ring->ring_size / 4) - 1));
 698         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 699                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 700         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 701         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 702         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 703         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 704         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 705         mqd->cp_hqd_pq_control = tmp;
 706
 707         /* enable doorbell */
 708         tmp = 0;
 709         if (ring->use_doorbell) {
 710                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 711                                     DOORBELL_OFFSET, ring->doorbell_index);
 712                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 713                                     DOORBELL_EN, 1);
 714                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 715                                     DOORBELL_SOURCE, 0);
 716                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 717                                     DOORBELL_HIT, 0);
 718         }
 719         else
 720                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 721                                     DOORBELL_EN, 0);
 722         mqd->cp_hqd_pq_doorbell_control = tmp;
 723
 724         mqd->cp_hqd_vmid = 0;
 725         /* activate the queue */
 726         mqd->cp_hqd_active = 1;
 727
 728         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 729         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 730                             PRELOAD_SIZE, 0x55);
 731         mqd->cp_hqd_persistent_state = tmp;
 732
 733         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 734         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 735         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 736
 737         return 0;
 738 }
 739
 740 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
 741 {
 742         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 743         struct amdgpu_device *adev = ring->adev;
 744         uint32_t data = 0;
 745
 746         mutex_lock(&adev->srbm_mutex);
 747         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 748
 749         /* set CP_HQD_VMID.VMID = 0. */
 750         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 751         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
 752         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
 753
 754         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
 755         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
 756         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
 757                              DOORBELL_EN, 0);
 758         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
 759
 760         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
 761         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
 762         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
 763
 764         /* set CP_MQD_CONTROL.VMID=0 */
 765         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
 766         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
 767         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
 768
 769         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
 770         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
 771         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
 772
 773         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
 774         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
 775                      mqd->cp_hqd_pq_rptr_report_addr_lo);
 776         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 777                      mqd->cp_hqd_pq_rptr_report_addr_hi);
 778
 779         /* set CP_HQD_PQ_CONTROL */
 780         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
 781
 782         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
 783         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
 784                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
 785         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 786                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
 787
 788         /* set CP_HQD_PQ_DOORBELL_CONTROL */
 789         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
 790                      mqd->cp_hqd_pq_doorbell_control);
 791
 792         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
 793         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
 794
 795         /* set CP_HQD_ACTIVE.ACTIVE=1 */
 796         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
 797
 798         soc21_grbm_select(adev, 0, 0, 0, 0);
 799         mutex_unlock(&adev->srbm_mutex);
 800 }
 801
 802 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
 803 {
 804         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 805         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 806         int r;
 807
 808         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 809                 return -EINVAL;
 810
 811         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
 812         if (r) {
 813                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 814                 return r;
 815         }
 816
 817         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
 818
 819         r = amdgpu_ring_test_ring(kiq_ring);
 820         if (r) {
 821                 DRM_ERROR("kfq enable failed\n");
 822                 kiq_ring->sched.ready = false;
 823         }
 824         return r;
 825 }
 826
 827 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
 828                                 enum admgpu_mes_pipe pipe)
 829 {
 830         struct amdgpu_ring *ring;
 831         int r;
 832
 833         if (pipe == AMDGPU_MES_KIQ_PIPE)
 834                 ring = &adev->gfx.kiq.ring;
 835         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 836                 ring = &adev->mes.ring;
 837         else
 838                 BUG();
 839
 840         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
 841             (amdgpu_in_reset(adev) || adev->in_suspend)) {
 842                 *(ring->wptr_cpu_addr) = 0;
 843                 *(ring->rptr_cpu_addr) = 0;
 844                 amdgpu_ring_clear_ring(ring);
 845         }
 846
 847         r = mes_v11_0_mqd_init(ring);
 848         if (r)
 849                 return r;
 850
 851         if (pipe == AMDGPU_MES_SCHED_PIPE) {
 852                 r = mes_v11_0_kiq_enable_queue(adev);
 853                 if (r)
 854                         return r;
 855         } else {
 856                 mes_v11_0_queue_init_register(ring);
 857         }
 858
 859         return 0;
 860 }
 861
 862 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
 863 {
 864         struct amdgpu_ring *ring;
 865
 866         ring = &adev->mes.ring;
 867
 868         ring->funcs = &mes_v11_0_ring_funcs;
 869
 870         ring->me = 3;
 871         ring->pipe = 0;
 872         ring->queue = 0;
 873
 874         ring->ring_obj = NULL;
 875         ring->use_doorbell = true;
 876         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
 877         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
 878         ring->no_scheduler = true;
 879         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 880
 881         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
 882                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
 883 }
 884
 885 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
 886 {
 887         struct amdgpu_ring *ring;
 888
 889         spin_lock_init(&adev->gfx.kiq.ring_lock);
 890
 891         ring = &adev->gfx.kiq.ring;
 892
 893         ring->me = 3;
 894         ring->pipe = 1;
 895         ring->queue = 0;
 896
 897         ring->adev = NULL;
 898         ring->ring_obj = NULL;
 899         ring->use_doorbell = true;
 900         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
 901         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
 902         ring->no_scheduler = true;
 903         sprintf(ring->name, "mes_kiq_%d.%d.%d",
 904                 ring->me, ring->pipe, ring->queue);
 905
 906         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
 907                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
 908 }
 909
 910 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
 911                                  enum admgpu_mes_pipe pipe)
 912 {
 913         int r, mqd_size = sizeof(struct v11_compute_mqd);
 914         struct amdgpu_ring *ring;
 915
 916         if (pipe == AMDGPU_MES_KIQ_PIPE)
 917                 ring = &adev->gfx.kiq.ring;
 918         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 919                 ring = &adev->mes.ring;
 920         else
 921                 BUG();
 922
 923         if (ring->mqd_obj)
 924                 return 0;
 925
 926         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 927                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 928                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 929         if (r) {
 930                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 931                 return r;
 932         }
 933
 934         memset(ring->mqd_ptr, 0, mqd_size);
 935
 936         /* prepare MQD backup */
 937         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
 938         if (!adev->mes.mqd_backup[pipe])
 939                 dev_warn(adev->dev,
 940                          "no memory to create MQD backup for ring %s\n",
 941                          ring->name);
 942
 943         return 0;
 944 }
 945
 946 static int mes_v11_0_sw_init(void *handle)
 947 {
 948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 949         int pipe, r;
 950
 951         adev->mes.adev = adev;
 952         adev->mes.funcs = &mes_v11_0_funcs;
 953         adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
 954         adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
 955
 956         r = amdgpu_mes_init(adev);
 957         if (r)
 958                 return r;
 959
 960         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 961                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
 962                         continue;
 963
 964                 r = mes_v11_0_init_microcode(adev, pipe);
 965                 if (r)
 966                         return r;
 967
 968                 r = mes_v11_0_allocate_eop_buf(adev, pipe);
 969                 if (r)
 970                         return r;
 971
 972                 r = mes_v11_0_mqd_sw_init(adev, pipe);
 973                 if (r)
 974                         return r;
 975         }
 976
 977         if (adev->enable_mes_kiq) {
 978                 r = mes_v11_0_kiq_ring_init(adev);
 979                 if (r)
 980                         return r;
 981         }
 982
 983         r = mes_v11_0_ring_init(adev);
 984         if (r)
 985                 return r;
 986
 987         return 0;
 988 }
 989
 990 static int mes_v11_0_sw_fini(void *handle)
 991 {
 992         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 993         int pipe;
 994
 995         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
 996         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
 997
 998         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 999                 kfree(adev->mes.mqd_backup[pipe]);
1000
1001                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1002                                       &adev->mes.eop_gpu_addr[pipe],
1003                                       NULL);
1004
1005                 mes_v11_0_free_microcode(adev, pipe);
1006         }
1007
1008         amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj,
1009                               &adev->gfx.kiq.ring.mqd_gpu_addr,
1010                               &adev->gfx.kiq.ring.mqd_ptr);
1011
1012         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1013                               &adev->mes.ring.mqd_gpu_addr,
1014                               &adev->mes.ring.mqd_ptr);
1015
1016         amdgpu_ring_fini(&adev->gfx.kiq.ring);
1017         amdgpu_ring_fini(&adev->mes.ring);
1018
1019         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1020                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1021                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1022         }
1023
1024         amdgpu_mes_fini(adev);
1025         return 0;
1026 }
1027
1028 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1029 {
1030         uint32_t tmp;
1031         struct amdgpu_device *adev = ring->adev;
1032
1033         /* tell RLC which is KIQ queue */
1034         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1035         tmp &= 0xffffff00;
1036         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1037         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1038         tmp |= 0x80;
1039         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1040 }
1041
1042 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1043 {
1044         int r = 0;
1045
1046         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1047                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE);
1048                 if (r) {
1049                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1050                         return r;
1051                 }
1052
1053                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE);
1054                 if (r) {
1055                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1056                         return r;
1057                 }
1058         }
1059
1060         mes_v11_0_enable(adev, true);
1061
1062         mes_v11_0_kiq_setting(&adev->gfx.kiq.ring);
1063
1064         r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1065         if (r)
1066                 goto failure;
1067
1068         return r;
1069
1070 failure:
1071         mes_v11_0_hw_fini(adev);
1072         return r;
1073 }
1074
1075 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1076 {
1077         mes_v11_0_enable(adev, false);
1078         return 0;
1079 }
1080
1081 static int mes_v11_0_hw_init(void *handle)
1082 {
1083         int r;
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         if (!adev->enable_mes_kiq) {
1087                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1088                         r = mes_v11_0_load_microcode(adev,
1089                                              AMDGPU_MES_SCHED_PIPE);
1090                         if (r) {
1091                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1092                                 return r;
1093                         }
1094                 }
1095
1096                 mes_v11_0_enable(adev, true);
1097         }
1098
1099         r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1100         if (r)
1101                 goto failure;
1102
1103         r = mes_v11_0_set_hw_resources(&adev->mes);
1104         if (r)
1105                 goto failure;
1106
1107         r = mes_v11_0_query_sched_status(&adev->mes);
1108         if (r) {
1109                 DRM_ERROR("MES is busy\n");
1110                 goto failure;
1111         }
1112
1113         /*
1114          * Disable KIQ ring usage from the driver once MES is enabled.
1115          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1116          * with MES enabled.
1117          */
1118         adev->gfx.kiq.ring.sched.ready = false;
1119
1120         return 0;
1121
1122 failure:
1123         mes_v11_0_hw_fini(adev);
1124         return r;
1125 }
1126
1127 static int mes_v11_0_hw_fini(void *handle)
1128 {
1129         return 0;
1130 }
1131
1132 static int mes_v11_0_suspend(void *handle)
1133 {
1134         int r;
1135         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1136
1137         r = amdgpu_mes_suspend(adev);
1138         if (r)
1139                 return r;
1140
1141         return mes_v11_0_hw_fini(adev);
1142 }
1143
1144 static int mes_v11_0_resume(void *handle)
1145 {
1146         int r;
1147         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148
1149         r = mes_v11_0_hw_init(adev);
1150         if (r)
1151                 return r;
1152
1153         return amdgpu_mes_resume(adev);
1154 }
1155
1156 static int mes_v11_0_late_init(void *handle)
1157 {
1158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1159
1160         amdgpu_mes_self_test(adev);
1161
1162         return 0;
1163 }
1164
1165 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1166         .name = "mes_v11_0",
1167         .late_init = mes_v11_0_late_init,
1168         .sw_init = mes_v11_0_sw_init,
1169         .sw_fini = mes_v11_0_sw_fini,
1170         .hw_init = mes_v11_0_hw_init,
1171         .hw_fini = mes_v11_0_hw_fini,
1172         .suspend = mes_v11_0_suspend,
1173         .resume = mes_v11_0_resume,
1174 };
1175
1176 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1177         .type = AMD_IP_BLOCK_TYPE_MES,
1178         .major = 11,
1179         .minor = 0,
1180         .rev = 0,
1181         .funcs = &mes_v11_0_ip_funcs,
1182 };