drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "mmhub_v1_7.h"
  54 #include "umc_v6_1.h"
  55 #include "umc_v6_0.h"
  56 #include "umc_v6_7.h"
  57 #include "hdp_v4_0.h"
  58
  59 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  60
  61 #include "amdgpu_ras.h"
  62 #include "amdgpu_xgmi.h"
  63
  64 /* add these here since we already include dce12 headers and these are for DCN */
  65 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  66 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  71 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  72 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  73
  74
  75 static const char *gfxhub_client_ids[] = {
  76         "CB",
  77         "DB",
  78         "IA",
  79         "WD",
  80         "CPF",
  81         "CPC",
  82         "CPG",
  83         "RLC",
  84         "TCP",
  85         "SQC (inst)",
  86         "SQC (data)",
  87         "SQG",
  88         "PA",
  89 };
  90
  91 static const char *mmhub_client_ids_raven[][2] = {
  92         [0][0] = "MP1",
  93         [1][0] = "MP0",
  94         [2][0] = "VCN",
  95         [3][0] = "VCNU",
  96         [4][0] = "HDP",
  97         [5][0] = "DCE",
  98         [13][0] = "UTCL2",
  99         [19][0] = "TLS",
 100         [26][0] = "OSS",
 101         [27][0] = "SDMA0",
 102         [0][1] = "MP1",
 103         [1][1] = "MP0",
 104         [2][1] = "VCN",
 105         [3][1] = "VCNU",
 106         [4][1] = "HDP",
 107         [5][1] = "XDP",
 108         [6][1] = "DBGU0",
 109         [7][1] = "DCE",
 110         [8][1] = "DCEDWB0",
 111         [9][1] = "DCEDWB1",
 112         [26][1] = "OSS",
 113         [27][1] = "SDMA0",
 114 };
 115
 116 static const char *mmhub_client_ids_renoir[][2] = {
 117         [0][0] = "MP1",
 118         [1][0] = "MP0",
 119         [2][0] = "HDP",
 120         [4][0] = "DCEDMC",
 121         [5][0] = "DCEVGA",
 122         [13][0] = "UTCL2",
 123         [19][0] = "TLS",
 124         [26][0] = "OSS",
 125         [27][0] = "SDMA0",
 126         [28][0] = "VCN",
 127         [29][0] = "VCNU",
 128         [30][0] = "JPEG",
 129         [0][1] = "MP1",
 130         [1][1] = "MP0",
 131         [2][1] = "HDP",
 132         [3][1] = "XDP",
 133         [6][1] = "DBGU0",
 134         [7][1] = "DCEDMC",
 135         [8][1] = "DCEVGA",
 136         [9][1] = "DCEDWB",
 137         [26][1] = "OSS",
 138         [27][1] = "SDMA0",
 139         [28][1] = "VCN",
 140         [29][1] = "VCNU",
 141         [30][1] = "JPEG",
 142 };
 143
 144 static const char *mmhub_client_ids_vega10[][2] = {
 145         [0][0] = "MP0",
 146         [1][0] = "UVD",
 147         [2][0] = "UVDU",
 148         [3][0] = "HDP",
 149         [13][0] = "UTCL2",
 150         [14][0] = "OSS",
 151         [15][0] = "SDMA1",
 152         [32+0][0] = "VCE0",
 153         [32+1][0] = "VCE0U",
 154         [32+2][0] = "XDMA",
 155         [32+3][0] = "DCE",
 156         [32+4][0] = "MP1",
 157         [32+14][0] = "SDMA0",
 158         [0][1] = "MP0",
 159         [1][1] = "UVD",
 160         [2][1] = "UVDU",
 161         [3][1] = "DBGU0",
 162         [4][1] = "HDP",
 163         [5][1] = "XDP",
 164         [14][1] = "OSS",
 165         [15][1] = "SDMA0",
 166         [32+0][1] = "VCE0",
 167         [32+1][1] = "VCE0U",
 168         [32+2][1] = "XDMA",
 169         [32+3][1] = "DCE",
 170         [32+4][1] = "DCEDWB",
 171         [32+5][1] = "MP1",
 172         [32+6][1] = "DBGU1",
 173         [32+14][1] = "SDMA1",
 174 };
 175
 176 static const char *mmhub_client_ids_vega12[][2] = {
 177         [0][0] = "MP0",
 178         [1][0] = "VCE0",
 179         [2][0] = "VCE0U",
 180         [3][0] = "HDP",
 181         [13][0] = "UTCL2",
 182         [14][0] = "OSS",
 183         [15][0] = "SDMA1",
 184         [32+0][0] = "DCE",
 185         [32+1][0] = "XDMA",
 186         [32+2][0] = "UVD",
 187         [32+3][0] = "UVDU",
 188         [32+4][0] = "MP1",
 189         [32+15][0] = "SDMA0",
 190         [0][1] = "MP0",
 191         [1][1] = "VCE0",
 192         [2][1] = "VCE0U",
 193         [3][1] = "DBGU0",
 194         [4][1] = "HDP",
 195         [5][1] = "XDP",
 196         [14][1] = "OSS",
 197         [15][1] = "SDMA0",
 198         [32+0][1] = "DCE",
 199         [32+1][1] = "DCEDWB",
 200         [32+2][1] = "XDMA",
 201         [32+3][1] = "UVD",
 202         [32+4][1] = "UVDU",
 203         [32+5][1] = "MP1",
 204         [32+6][1] = "DBGU1",
 205         [32+15][1] = "SDMA1",
 206 };
 207
 208 static const char *mmhub_client_ids_vega20[][2] = {
 209         [0][0] = "XDMA",
 210         [1][0] = "DCE",
 211         [2][0] = "VCE0",
 212         [3][0] = "VCE0U",
 213         [4][0] = "UVD",
 214         [5][0] = "UVD1U",
 215         [13][0] = "OSS",
 216         [14][0] = "HDP",
 217         [15][0] = "SDMA0",
 218         [32+0][0] = "UVD",
 219         [32+1][0] = "UVDU",
 220         [32+2][0] = "MP1",
 221         [32+3][0] = "MP0",
 222         [32+12][0] = "UTCL2",
 223         [32+14][0] = "SDMA1",
 224         [0][1] = "XDMA",
 225         [1][1] = "DCE",
 226         [2][1] = "DCEDWB",
 227         [3][1] = "VCE0",
 228         [4][1] = "VCE0U",
 229         [5][1] = "UVD1",
 230         [6][1] = "UVD1U",
 231         [7][1] = "DBGU0",
 232         [8][1] = "XDP",
 233         [13][1] = "OSS",
 234         [14][1] = "HDP",
 235         [15][1] = "SDMA0",
 236         [32+0][1] = "UVD",
 237         [32+1][1] = "UVDU",
 238         [32+2][1] = "DBGU1",
 239         [32+3][1] = "MP1",
 240         [32+4][1] = "MP0",
 241         [32+14][1] = "SDMA1",
 242 };
 243
 244 static const char *mmhub_client_ids_arcturus[][2] = {
 245         [0][0] = "DBGU1",
 246         [1][0] = "XDP",
 247         [2][0] = "MP1",
 248         [14][0] = "HDP",
 249         [171][0] = "JPEG",
 250         [172][0] = "VCN",
 251         [173][0] = "VCNU",
 252         [203][0] = "JPEG1",
 253         [204][0] = "VCN1",
 254         [205][0] = "VCN1U",
 255         [256][0] = "SDMA0",
 256         [257][0] = "SDMA1",
 257         [258][0] = "SDMA2",
 258         [259][0] = "SDMA3",
 259         [260][0] = "SDMA4",
 260         [261][0] = "SDMA5",
 261         [262][0] = "SDMA6",
 262         [263][0] = "SDMA7",
 263         [384][0] = "OSS",
 264         [0][1] = "DBGU1",
 265         [1][1] = "XDP",
 266         [2][1] = "MP1",
 267         [14][1] = "HDP",
 268         [171][1] = "JPEG",
 269         [172][1] = "VCN",
 270         [173][1] = "VCNU",
 271         [203][1] = "JPEG1",
 272         [204][1] = "VCN1",
 273         [205][1] = "VCN1U",
 274         [256][1] = "SDMA0",
 275         [257][1] = "SDMA1",
 276         [258][1] = "SDMA2",
 277         [259][1] = "SDMA3",
 278         [260][1] = "SDMA4",
 279         [261][1] = "SDMA5",
 280         [262][1] = "SDMA6",
 281         [263][1] = "SDMA7",
 282         [384][1] = "OSS",
 283 };
 284
 285 static const char *mmhub_client_ids_aldebaran[][2] = {
 286         [2][0] = "MP1",
 287         [3][0] = "MP0",
 288         [32+1][0] = "DBGU_IO0",
 289         [32+2][0] = "DBGU_IO2",
 290         [32+4][0] = "MPIO",
 291         [96+11][0] = "JPEG0",
 292         [96+12][0] = "VCN0",
 293         [96+13][0] = "VCNU0",
 294         [128+11][0] = "JPEG1",
 295         [128+12][0] = "VCN1",
 296         [128+13][0] = "VCNU1",
 297         [160+1][0] = "XDP",
 298         [160+14][0] = "HDP",
 299         [256+0][0] = "SDMA0",
 300         [256+1][0] = "SDMA1",
 301         [256+2][0] = "SDMA2",
 302         [256+3][0] = "SDMA3",
 303         [256+4][0] = "SDMA4",
 304         [384+0][0] = "OSS",
 305         [2][1] = "MP1",
 306         [3][1] = "MP0",
 307         [32+1][1] = "DBGU_IO0",
 308         [32+2][1] = "DBGU_IO2",
 309         [32+4][1] = "MPIO",
 310         [96+11][1] = "JPEG0",
 311         [96+12][1] = "VCN0",
 312         [96+13][1] = "VCNU0",
 313         [128+11][1] = "JPEG1",
 314         [128+12][1] = "VCN1",
 315         [128+13][1] = "VCNU1",
 316         [160+1][1] = "XDP",
 317         [160+14][1] = "HDP",
 318         [256+0][1] = "SDMA0",
 319         [256+1][1] = "SDMA1",
 320         [256+2][1] = "SDMA2",
 321         [256+3][1] = "SDMA3",
 322         [256+4][1] = "SDMA4",
 323         [384+0][1] = "OSS",
 324 };
 325
 326 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
 327 {
 328         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 329         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 330 };
 331
 332 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
 333 {
 334         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 335         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 336 };
 337
 338 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 339         (0x000143c0 + 0x00000000),
 340         (0x000143c0 + 0x00000800),
 341         (0x000143c0 + 0x00001000),
 342         (0x000143c0 + 0x00001800),
 343         (0x000543c0 + 0x00000000),
 344         (0x000543c0 + 0x00000800),
 345         (0x000543c0 + 0x00001000),
 346         (0x000543c0 + 0x00001800),
 347         (0x000943c0 + 0x00000000),
 348         (0x000943c0 + 0x00000800),
 349         (0x000943c0 + 0x00001000),
 350         (0x000943c0 + 0x00001800),
 351         (0x000d43c0 + 0x00000000),
 352         (0x000d43c0 + 0x00000800),
 353         (0x000d43c0 + 0x00001000),
 354         (0x000d43c0 + 0x00001800),
 355         (0x001143c0 + 0x00000000),
 356         (0x001143c0 + 0x00000800),
 357         (0x001143c0 + 0x00001000),
 358         (0x001143c0 + 0x00001800),
 359         (0x001543c0 + 0x00000000),
 360         (0x001543c0 + 0x00000800),
 361         (0x001543c0 + 0x00001000),
 362         (0x001543c0 + 0x00001800),
 363         (0x001943c0 + 0x00000000),
 364         (0x001943c0 + 0x00000800),
 365         (0x001943c0 + 0x00001000),
 366         (0x001943c0 + 0x00001800),
 367         (0x001d43c0 + 0x00000000),
 368         (0x001d43c0 + 0x00000800),
 369         (0x001d43c0 + 0x00001000),
 370         (0x001d43c0 + 0x00001800),
 371 };
 372
 373 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 374         (0x000143e0 + 0x00000000),
 375         (0x000143e0 + 0x00000800),
 376         (0x000143e0 + 0x00001000),
 377         (0x000143e0 + 0x00001800),
 378         (0x000543e0 + 0x00000000),
 379         (0x000543e0 + 0x00000800),
 380         (0x000543e0 + 0x00001000),
 381         (0x000543e0 + 0x00001800),
 382         (0x000943e0 + 0x00000000),
 383         (0x000943e0 + 0x00000800),
 384         (0x000943e0 + 0x00001000),
 385         (0x000943e0 + 0x00001800),
 386         (0x000d43e0 + 0x00000000),
 387         (0x000d43e0 + 0x00000800),
 388         (0x000d43e0 + 0x00001000),
 389         (0x000d43e0 + 0x00001800),
 390         (0x001143e0 + 0x00000000),
 391         (0x001143e0 + 0x00000800),
 392         (0x001143e0 + 0x00001000),
 393         (0x001143e0 + 0x00001800),
 394         (0x001543e0 + 0x00000000),
 395         (0x001543e0 + 0x00000800),
 396         (0x001543e0 + 0x00001000),
 397         (0x001543e0 + 0x00001800),
 398         (0x001943e0 + 0x00000000),
 399         (0x001943e0 + 0x00000800),
 400         (0x001943e0 + 0x00001000),
 401         (0x001943e0 + 0x00001800),
 402         (0x001d43e0 + 0x00000000),
 403         (0x001d43e0 + 0x00000800),
 404         (0x001d43e0 + 0x00001000),
 405         (0x001d43e0 + 0x00001800),
 406 };
 407
 408 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 409                 struct amdgpu_irq_src *src,
 410                 unsigned type,
 411                 enum amdgpu_interrupt_state state)
 412 {
 413         u32 bits, i, tmp, reg;
 414
 415         /* Devices newer then VEGA10/12 shall have these programming
 416              sequences performed by PSP BL */
 417         if (adev->asic_type >= CHIP_VEGA20)
 418                 return 0;
 419
 420         bits = 0x7f;
 421
 422         switch (state) {
 423         case AMDGPU_IRQ_STATE_DISABLE:
 424                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 425                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 426                         tmp = RREG32(reg);
 427                         tmp &= ~bits;
 428                         WREG32(reg, tmp);
 429                 }
 430                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 431                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 432                         tmp = RREG32(reg);
 433                         tmp &= ~bits;
 434                         WREG32(reg, tmp);
 435                 }
 436                 break;
 437         case AMDGPU_IRQ_STATE_ENABLE:
 438                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 439                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 440                         tmp = RREG32(reg);
 441                         tmp |= bits;
 442                         WREG32(reg, tmp);
 443                 }
 444                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 445                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 446                         tmp = RREG32(reg);
 447                         tmp |= bits;
 448                         WREG32(reg, tmp);
 449                 }
 450                 break;
 451         default:
 452                 break;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 459                                         struct amdgpu_irq_src *src,
 460                                         unsigned type,
 461                                         enum amdgpu_interrupt_state state)
 462 {
 463         struct amdgpu_vmhub *hub;
 464         u32 tmp, reg, bits, i, j;
 465
 466         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 467                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 468                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 469                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 470                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 471                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 472                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 473
 474         switch (state) {
 475         case AMDGPU_IRQ_STATE_DISABLE:
 476                 for (j = 0; j < adev->num_vmhubs; j++) {
 477                         hub = &adev->vmhub[j];
 478                         for (i = 0; i < 16; i++) {
 479                                 reg = hub->vm_context0_cntl + i;
 480                                 tmp = RREG32(reg);
 481                                 tmp &= ~bits;
 482                                 WREG32(reg, tmp);
 483                         }
 484                 }
 485                 break;
 486         case AMDGPU_IRQ_STATE_ENABLE:
 487                 for (j = 0; j < adev->num_vmhubs; j++) {
 488                         hub = &adev->vmhub[j];
 489                         for (i = 0; i < 16; i++) {
 490                                 reg = hub->vm_context0_cntl + i;
 491                                 tmp = RREG32(reg);
 492                                 tmp |= bits;
 493                                 WREG32(reg, tmp);
 494                         }
 495                 }
 496                 break;
 497         default:
 498                 break;
 499         }
 500
 501         return 0;
 502 }
 503
 504 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 505                                       struct amdgpu_irq_src *source,
 506                                       struct amdgpu_iv_entry *entry)
 507 {
 508         bool retry_fault = !!(entry->src_data[1] & 0x80);
 509         uint32_t status = 0, cid = 0, rw = 0;
 510         struct amdgpu_task_info task_info;
 511         struct amdgpu_vmhub *hub;
 512         const char *mmhub_cid;
 513         const char *hub_name;
 514         u64 addr;
 515
 516         addr = (u64)entry->src_data[0] << 12;
 517         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 518
 519         if (retry_fault) {
 520                 /* Returning 1 here also prevents sending the IV to the KFD */
 521
 522                 /* Process it onyl if it's the first fault for this address */
 523                 if (entry->ih != &adev->irq.ih_soft &&
 524                     amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 525                                              entry->timestamp))
 526                         return 1;
 527
 528                 /* Delegate it to a different ring if the hardware hasn't
 529                  * already done it.
 530                  */
 531                 if (entry->ih == &adev->irq.ih) {
 532                         amdgpu_irq_delegate(adev, entry, 8);
 533                         return 1;
 534                 }
 535
 536                 /* Try to handle the recoverable page faults by filling page
 537                  * tables
 538                  */
 539                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 540                         return 1;
 541         }
 542
 543         if (!printk_ratelimit())
 544                 return 0;
 545
 546         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 547                 hub_name = "mmhub0";
 548                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 549         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 550                 hub_name = "mmhub1";
 551                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 552         } else {
 553                 hub_name = "gfxhub0";
 554                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 555         }
 556
 557         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 558         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 559
 560         dev_err(adev->dev,
 561                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 562                 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 563                 hub_name, retry_fault ? "retry" : "no-retry",
 564                 entry->src_id, entry->ring_id, entry->vmid,
 565                 entry->pasid, task_info.process_name, task_info.tgid,
 566                 task_info.task_name, task_info.pid);
 567         dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
 568                 addr, entry->client_id,
 569                 soc15_ih_clientid_name[entry->client_id]);
 570
 571         if (amdgpu_sriov_vf(adev))
 572                 return 0;
 573
 574         /*
 575          * Issue a dummy read to wait for the status register to
 576          * be updated to avoid reading an incorrect value due to
 577          * the new fast GRBM interface.
 578          */
 579         if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 580             (adev->asic_type < CHIP_ALDEBARAN))
 581                 RREG32(hub->vm_l2_pro_fault_status);
 582
 583         status = RREG32(hub->vm_l2_pro_fault_status);
 584         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 585         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 586         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 587
 588
 589         dev_err(adev->dev,
 590                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 591                 status);
 592         if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
 593                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 594                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 595                         gfxhub_client_ids[cid],
 596                         cid);
 597         } else {
 598                 switch (adev->asic_type) {
 599                 case CHIP_VEGA10:
 600                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 601                         break;
 602                 case CHIP_VEGA12:
 603                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 604                         break;
 605                 case CHIP_VEGA20:
 606                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 607                         break;
 608                 case CHIP_ARCTURUS:
 609                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 610                         break;
 611                 case CHIP_RAVEN:
 612                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 613                         break;
 614                 case CHIP_RENOIR:
 615                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 616                         break;
 617                 case CHIP_ALDEBARAN:
 618                         mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
 619                         break;
 620                 default:
 621                         mmhub_cid = NULL;
 622                         break;
 623                 }
 624                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 625                         mmhub_cid ? mmhub_cid : "unknown", cid);
 626         }
 627         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 628                 REG_GET_FIELD(status,
 629                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 630         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 631                 REG_GET_FIELD(status,
 632                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 633         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 634                 REG_GET_FIELD(status,
 635                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 636         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 637                 REG_GET_FIELD(status,
 638                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 639         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 640         return 0;
 641 }
 642
 643 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 644         .set = gmc_v9_0_vm_fault_interrupt_state,
 645         .process = gmc_v9_0_process_interrupt,
 646 };
 647
 648
 649 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 650         .set = gmc_v9_0_ecc_interrupt_state,
 651         .process = amdgpu_umc_process_ecc_irq,
 652 };
 653
 654 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 655 {
 656         adev->gmc.vm_fault.num_types = 1;
 657         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 658
 659         if (!amdgpu_sriov_vf(adev) &&
 660             !adev->gmc.xgmi.connected_to_cpu) {
 661                 adev->gmc.ecc_irq.num_types = 1;
 662                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 663         }
 664 }
 665
 666 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 667                                         uint32_t flush_type)
 668 {
 669         u32 req = 0;
 670
 671         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 672                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 673         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 674         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 675         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 676         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 677         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 678         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 679         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 680                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 681
 682         return req;
 683 }
 684
 685 /**
 686  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 687  *
 688  * @adev: amdgpu_device pointer
 689  * @vmhub: vmhub type
 690  *
 691  */
 692 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 693                                        uint32_t vmhub)
 694 {
 695         if (adev->asic_type == CHIP_ALDEBARAN)
 696                 return false;
 697
 698         return ((vmhub == AMDGPU_MMHUB_0 ||
 699                  vmhub == AMDGPU_MMHUB_1) &&
 700                 (!amdgpu_sriov_vf(adev)) &&
 701                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 702                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 703 }
 704
 705 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 706                                         uint8_t vmid, uint16_t *p_pasid)
 707 {
 708         uint32_t value;
 709
 710         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 711                      + vmid);
 712         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 713
 714         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 715 }
 716
 717 /*
 718  * GART
 719  * VMID 0 is the physical GPU addresses as used by the kernel.
 720  * VMIDs 1-15 are used for userspace clients and are handled
 721  * by the amdgpu vm/hsa code.
 722  */
 723
 724 /**
 725  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 726  *
 727  * @adev: amdgpu_device pointer
 728  * @vmid: vm instance to flush
 729  * @vmhub: which hub to flush
 730  * @flush_type: the flush type
 731  *
 732  * Flush the TLB for the requested page table using certain type.
 733  */
 734 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 735                                         uint32_t vmhub, uint32_t flush_type)
 736 {
 737         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 738         const unsigned eng = 17;
 739         u32 j, inv_req, inv_req2, tmp;
 740         struct amdgpu_vmhub *hub;
 741
 742         BUG_ON(vmhub >= adev->num_vmhubs);
 743
 744         hub = &adev->vmhub[vmhub];
 745         if (adev->gmc.xgmi.num_physical_nodes &&
 746             adev->asic_type == CHIP_VEGA20) {
 747                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 748                  * heavy-weight TLB flush (type 2), which flushes
 749                  * both. Due to a race condition with concurrent
 750                  * memory accesses using the same TLB cache line, we
 751                  * still need a second TLB flush after this.
 752                  */
 753                 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
 754                 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 755         } else {
 756                 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 757                 inv_req2 = 0;
 758         }
 759
 760         /* This is necessary for a HW workaround under SRIOV as well
 761          * as GFXOFF under bare metal
 762          */
 763         if (adev->gfx.kiq.ring.sched.ready &&
 764             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 765             down_read_trylock(&adev->reset_sem)) {
 766                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 767                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 768
 769                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 770                                                    1 << vmid);
 771                 up_read(&adev->reset_sem);
 772                 return;
 773         }
 774
 775         spin_lock(&adev->gmc.invalidate_lock);
 776
 777         /*
 778          * It may lose gpuvm invalidate acknowldege state across power-gating
 779          * off cycle, add semaphore acquire before invalidation and semaphore
 780          * release after invalidation to avoid entering power gated state
 781          * to WA the Issue
 782          */
 783
 784         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 785         if (use_semaphore) {
 786                 for (j = 0; j < adev->usec_timeout; j++) {
 787                         /* a read return value of 1 means semaphore acuqire */
 788                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 789                                             hub->eng_distance * eng);
 790                         if (tmp & 0x1)
 791                                 break;
 792                         udelay(1);
 793                 }
 794
 795                 if (j >= adev->usec_timeout)
 796                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 797         }
 798
 799         do {
 800                 WREG32_NO_KIQ(hub->vm_inv_eng0_req +
 801                               hub->eng_distance * eng, inv_req);
 802
 803                 /*
 804                  * Issue a dummy read to wait for the ACK register to
 805                  * be cleared to avoid a false ACK due to the new fast
 806                  * GRBM interface.
 807                  */
 808                 if ((vmhub == AMDGPU_GFXHUB_0) &&
 809                     (adev->asic_type < CHIP_ALDEBARAN))
 810                         RREG32_NO_KIQ(hub->vm_inv_eng0_req +
 811                                       hub->eng_distance * eng);
 812
 813                 for (j = 0; j < adev->usec_timeout; j++) {
 814                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
 815                                             hub->eng_distance * eng);
 816                         if (tmp & (1 << vmid))
 817                                 break;
 818                         udelay(1);
 819                 }
 820
 821                 inv_req = inv_req2;
 822                 inv_req2 = 0;
 823         } while (inv_req);
 824
 825         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 826         if (use_semaphore)
 827                 /*
 828                  * add semaphore release after invalidation,
 829                  * write with 0 means semaphore release
 830                  */
 831                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 832                               hub->eng_distance * eng, 0);
 833
 834         spin_unlock(&adev->gmc.invalidate_lock);
 835
 836         if (j < adev->usec_timeout)
 837                 return;
 838
 839         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 840 }
 841
 842 /**
 843  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 844  *
 845  * @adev: amdgpu_device pointer
 846  * @pasid: pasid to be flush
 847  * @flush_type: the flush type
 848  * @all_hub: flush all hubs
 849  *
 850  * Flush the TLB for the requested pasid.
 851  */
 852 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 853                                         uint16_t pasid, uint32_t flush_type,
 854                                         bool all_hub)
 855 {
 856         int vmid, i;
 857         signed long r;
 858         uint32_t seq;
 859         uint16_t queried_pasid;
 860         bool ret;
 861         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 862         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 863
 864         if (amdgpu_in_reset(adev))
 865                 return -EIO;
 866
 867         if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) {
 868                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 869                  * heavy-weight TLB flush (type 2), which flushes
 870                  * both. Due to a race condition with concurrent
 871                  * memory accesses using the same TLB cache line, we
 872                  * still need a second TLB flush after this.
 873                  */
 874                 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
 875                                        adev->asic_type == CHIP_VEGA20);
 876                 /* 2 dwords flush + 8 dwords fence */
 877                 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
 878
 879                 if (vega20_xgmi_wa)
 880                         ndw += kiq->pmf->invalidate_tlbs_size;
 881
 882                 spin_lock(&adev->gfx.kiq.ring_lock);
 883                 /* 2 dwords flush + 8 dwords fence */
 884                 amdgpu_ring_alloc(ring, ndw);
 885                 if (vega20_xgmi_wa)
 886                         kiq->pmf->kiq_invalidate_tlbs(ring,
 887                                                       pasid, 2, all_hub);
 888                 kiq->pmf->kiq_invalidate_tlbs(ring,
 889                                         pasid, flush_type, all_hub);
 890                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 891                 if (r) {
 892                         amdgpu_ring_undo(ring);
 893                         spin_unlock(&adev->gfx.kiq.ring_lock);
 894                         up_read(&adev->reset_sem);
 895                         return -ETIME;
 896                 }
 897
 898                 amdgpu_ring_commit(ring);
 899                 spin_unlock(&adev->gfx.kiq.ring_lock);
 900                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 901                 if (r < 1) {
 902                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 903                         up_read(&adev->reset_sem);
 904                         return -ETIME;
 905                 }
 906                 up_read(&adev->reset_sem);
 907                 return 0;
 908         }
 909
 910         for (vmid = 1; vmid < 16; vmid++) {
 911
 912                 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 913                                 &queried_pasid);
 914                 if (ret && queried_pasid == pasid) {
 915                         if (all_hub) {
 916                                 for (i = 0; i < adev->num_vmhubs; i++)
 917                                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 918                                                         i, flush_type);
 919                         } else {
 920                                 gmc_v9_0_flush_gpu_tlb(adev, vmid,
 921                                                 AMDGPU_GFXHUB_0, flush_type);
 922                         }
 923                         break;
 924                 }
 925         }
 926
 927         return 0;
 928
 929 }
 930
 931 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 932                                             unsigned vmid, uint64_t pd_addr)
 933 {
 934         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 935         struct amdgpu_device *adev = ring->adev;
 936         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 937         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 938         unsigned eng = ring->vm_inv_eng;
 939
 940         /*
 941          * It may lose gpuvm invalidate acknowldege state across power-gating
 942          * off cycle, add semaphore acquire before invalidation and semaphore
 943          * release after invalidation to avoid entering power gated state
 944          * to WA the Issue
 945          */
 946
 947         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 948         if (use_semaphore)
 949                 /* a read return value of 1 means semaphore acuqire */
 950                 amdgpu_ring_emit_reg_wait(ring,
 951                                           hub->vm_inv_eng0_sem +
 952                                           hub->eng_distance * eng, 0x1, 0x1);
 953
 954         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 955                               (hub->ctx_addr_distance * vmid),
 956                               lower_32_bits(pd_addr));
 957
 958         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 959                               (hub->ctx_addr_distance * vmid),
 960                               upper_32_bits(pd_addr));
 961
 962         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 963                                             hub->eng_distance * eng,
 964                                             hub->vm_inv_eng0_ack +
 965                                             hub->eng_distance * eng,
 966                                             req, 1 << vmid);
 967
 968         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 969         if (use_semaphore)
 970                 /*
 971                  * add semaphore release after invalidation,
 972                  * write with 0 means semaphore release
 973                  */
 974                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 975                                       hub->eng_distance * eng, 0);
 976
 977         return pd_addr;
 978 }
 979
 980 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 981                                         unsigned pasid)
 982 {
 983         struct amdgpu_device *adev = ring->adev;
 984         uint32_t reg;
 985
 986         /* Do nothing because there's no lut register for mmhub1. */
 987         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 988                 return;
 989
 990         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 991                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 992         else
 993                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 994
 995         amdgpu_ring_emit_wreg(ring, reg, pasid);
 996 }
 997
 998 /*
 999  * PTE format on VEGA 10:
1000  * 63:59 reserved
1001  * 58:57 mtype
1002  * 56 F
1003  * 55 L
1004  * 54 P
1005  * 53 SW
1006  * 52 T
1007  * 50:48 reserved
1008  * 47:12 4k physical page base address
1009  * 11:7 fragment
1010  * 6 write
1011  * 5 read
1012  * 4 exe
1013  * 3 Z
1014  * 2 snooped
1015  * 1 system
1016  * 0 valid
1017  *
1018  * PDE format on VEGA 10:
1019  * 63:59 block fragment size
1020  * 58:55 reserved
1021  * 54 P
1022  * 53:48 reserved
1023  * 47:6 physical base address of PD or PTE
1024  * 5:3 reserved
1025  * 2 C
1026  * 1 system
1027  * 0 valid
1028  */
1029
1030 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1031
1032 {
1033         switch (flags) {
1034         case AMDGPU_VM_MTYPE_DEFAULT:
1035                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1036         case AMDGPU_VM_MTYPE_NC:
1037                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1038         case AMDGPU_VM_MTYPE_WC:
1039                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1040         case AMDGPU_VM_MTYPE_RW:
1041                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1042         case AMDGPU_VM_MTYPE_CC:
1043                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1044         case AMDGPU_VM_MTYPE_UC:
1045                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1046         default:
1047                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1048         }
1049 }
1050
1051 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1052                                 uint64_t *addr, uint64_t *flags)
1053 {
1054         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1055                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1056         BUG_ON(*addr & 0xFFFF00000000003FULL);
1057
1058         if (!adev->gmc.translate_further)
1059                 return;
1060
1061         if (level == AMDGPU_VM_PDB1) {
1062                 /* Set the block fragment size */
1063                 if (!(*flags & AMDGPU_PDE_PTE))
1064                         *flags |= AMDGPU_PDE_BFS(0x9);
1065
1066         } else if (level == AMDGPU_VM_PDB0) {
1067                 if (*flags & AMDGPU_PDE_PTE)
1068                         *flags &= ~AMDGPU_PDE_PTE;
1069                 else
1070                         *flags |= AMDGPU_PTE_TF;
1071         }
1072 }
1073
1074 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1075                                 struct amdgpu_bo_va_mapping *mapping,
1076                                 uint64_t *flags)
1077 {
1078         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1079         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1080
1081         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1082         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1083
1084         if (mapping->flags & AMDGPU_PTE_PRT) {
1085                 *flags |= AMDGPU_PTE_PRT;
1086                 *flags &= ~AMDGPU_PTE_VALID;
1087         }
1088
1089         if ((adev->asic_type == CHIP_ARCTURUS ||
1090             adev->asic_type == CHIP_ALDEBARAN) &&
1091             !(*flags & AMDGPU_PTE_SYSTEM) &&
1092             mapping->bo_va->is_xgmi)
1093                 *flags |= AMDGPU_PTE_SNOOPED;
1094
1095         if (adev->asic_type == CHIP_ALDEBARAN)
1096                 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED;
1097 }
1098
1099 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1100 {
1101         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1102         unsigned size;
1103
1104         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1105                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1106         } else {
1107                 u32 viewport;
1108
1109                 switch (adev->asic_type) {
1110                 case CHIP_RAVEN:
1111                 case CHIP_RENOIR:
1112                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1113                         size = (REG_GET_FIELD(viewport,
1114                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1115                                 REG_GET_FIELD(viewport,
1116                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1117                                 4);
1118                         break;
1119                 case CHIP_VEGA10:
1120                 case CHIP_VEGA12:
1121                 case CHIP_VEGA20:
1122                 default:
1123                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1124                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1125                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1126                                 4);
1127                         break;
1128                 }
1129         }
1130
1131         return size;
1132 }
1133
1134 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1135         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1136         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1137         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1138         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1139         .map_mtype = gmc_v9_0_map_mtype,
1140         .get_vm_pde = gmc_v9_0_get_vm_pde,
1141         .get_vm_pte = gmc_v9_0_get_vm_pte,
1142         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1143 };
1144
1145 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1146 {
1147         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1148 }
1149
1150 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1151 {
1152         switch (adev->asic_type) {
1153         case CHIP_VEGA10:
1154                 adev->umc.funcs = &umc_v6_0_funcs;
1155                 break;
1156         case CHIP_VEGA20:
1157                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1158                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1159                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1160                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1161                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1162                 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1163                 break;
1164         case CHIP_ARCTURUS:
1165                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1166                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1167                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1168                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1169                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1170                 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1171                 break;
1172         case CHIP_ALDEBARAN:
1173                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
1174                 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1175                 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1176                 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1177                 if (!adev->gmc.xgmi.connected_to_cpu)
1178                         adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
1179                 if (1 & adev->smuio.funcs->get_die_id(adev))
1180                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1181                 else
1182                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1183                 break;
1184         default:
1185                 break;
1186         }
1187 }
1188
1189 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1190 {
1191         switch (adev->asic_type) {
1192         case CHIP_ARCTURUS:
1193                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1194                 break;
1195         case CHIP_ALDEBARAN:
1196                 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1197                 break;
1198         default:
1199                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1200                 break;
1201         }
1202 }
1203
1204 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1205 {
1206         switch (adev->asic_type) {
1207         case CHIP_VEGA20:
1208                 adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs;
1209                 break;
1210         case CHIP_ARCTURUS:
1211                 adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs;
1212                 break;
1213         case CHIP_ALDEBARAN:
1214                 adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs;
1215                 break;
1216         default:
1217                 /* mmhub ras is not available */
1218                 break;
1219         }
1220 }
1221
1222 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1223 {
1224         adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1225 }
1226
1227 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1228 {
1229         adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs;
1230 }
1231
1232 static int gmc_v9_0_early_init(void *handle)
1233 {
1234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235
1236         if (adev->asic_type == CHIP_VEGA20 ||
1237             adev->asic_type == CHIP_ARCTURUS)
1238                 adev->gmc.xgmi.supported = true;
1239
1240         if (adev->asic_type == CHIP_ALDEBARAN) {
1241                 adev->gmc.xgmi.supported = true;
1242                 adev->gmc.xgmi.connected_to_cpu =
1243                         adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1244         }
1245
1246         gmc_v9_0_set_gmc_funcs(adev);
1247         gmc_v9_0_set_irq_funcs(adev);
1248         gmc_v9_0_set_umc_funcs(adev);
1249         gmc_v9_0_set_mmhub_funcs(adev);
1250         gmc_v9_0_set_mmhub_ras_funcs(adev);
1251         gmc_v9_0_set_gfxhub_funcs(adev);
1252         gmc_v9_0_set_hdp_ras_funcs(adev);
1253
1254         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1255         adev->gmc.shared_aperture_end =
1256                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1257         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1258         adev->gmc.private_aperture_end =
1259                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1260
1261         return 0;
1262 }
1263
1264 static int gmc_v9_0_late_init(void *handle)
1265 {
1266         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1267         int r;
1268
1269         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1270         if (r)
1271                 return r;
1272
1273         /*
1274          * Workaround performance drop issue with VBIOS enables partial
1275          * writes, while disables HBM ECC for vega10.
1276          */
1277         if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
1278                 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1279                         if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
1280                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1281                 }
1282         }
1283
1284         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1285                 if (adev->mmhub.ras_funcs &&
1286                     adev->mmhub.ras_funcs->reset_ras_error_count)
1287                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
1288
1289                 if (adev->hdp.ras_funcs &&
1290                     adev->hdp.ras_funcs->reset_ras_error_count)
1291                         adev->hdp.ras_funcs->reset_ras_error_count(adev);
1292         }
1293
1294         r = amdgpu_gmc_ras_late_init(adev);
1295         if (r)
1296                 return r;
1297
1298         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1299 }
1300
1301 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1302                                         struct amdgpu_gmc *mc)
1303 {
1304         u64 base = adev->mmhub.funcs->get_fb_location(adev);
1305
1306         /* add the xgmi offset of the physical node */
1307         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1308         if (adev->gmc.xgmi.connected_to_cpu) {
1309                 amdgpu_gmc_sysvm_location(adev, mc);
1310         } else {
1311                 amdgpu_gmc_vram_location(adev, mc, base);
1312                 amdgpu_gmc_gart_location(adev, mc);
1313                 amdgpu_gmc_agp_location(adev, mc);
1314         }
1315         /* base offset of vram pages */
1316         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1317
1318         /* XXX: add the xgmi offset of the physical node? */
1319         adev->vm_manager.vram_base_offset +=
1320                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1321 }
1322
1323 /**
1324  * gmc_v9_0_mc_init - initialize the memory controller driver params
1325  *
1326  * @adev: amdgpu_device pointer
1327  *
1328  * Look up the amount of vram, vram width, and decide how to place
1329  * vram and gart within the GPU's physical address space.
1330  * Returns 0 for success.
1331  */
1332 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1333 {
1334         int r;
1335
1336         /* size in MB on si */
1337         adev->gmc.mc_vram_size =
1338                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1339         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1340
1341         if (!(adev->flags & AMD_IS_APU) &&
1342             !adev->gmc.xgmi.connected_to_cpu) {
1343                 r = amdgpu_device_resize_fb_bar(adev);
1344                 if (r)
1345                         return r;
1346         }
1347         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1348         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1349
1350 #ifdef CONFIG_X86_64
1351         /*
1352          * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1353          * interface can use VRAM through here as it appears system reserved
1354          * memory in host address space.
1355          *
1356          * For APUs, VRAM is just the stolen system memory and can be accessed
1357          * directly.
1358          *
1359          * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1360          */
1361
1362         /* check whether both host-gpu and gpu-gpu xgmi links exist */
1363         if ((adev->flags & AMD_IS_APU) ||
1364             (adev->gmc.xgmi.supported &&
1365              adev->gmc.xgmi.connected_to_cpu)) {
1366                 adev->gmc.aper_base =
1367                         adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1368                         adev->gmc.xgmi.physical_node_id *
1369                         adev->gmc.xgmi.node_segment_size;
1370                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1371         }
1372
1373 #endif
1374         /* In case the PCI BAR is larger than the actual amount of vram */
1375         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1376         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1377                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1378
1379         /* set the gart size */
1380         if (amdgpu_gart_size == -1) {
1381                 switch (adev->asic_type) {
1382                 case CHIP_VEGA10:  /* all engines support GPUVM */
1383                 case CHIP_VEGA12:  /* all engines support GPUVM */
1384                 case CHIP_VEGA20:
1385                 case CHIP_ARCTURUS:
1386                 case CHIP_ALDEBARAN:
1387                 default:
1388                         adev->gmc.gart_size = 512ULL << 20;
1389                         break;
1390                 case CHIP_RAVEN:   /* DCE SG support */
1391                 case CHIP_RENOIR:
1392                         adev->gmc.gart_size = 1024ULL << 20;
1393                         break;
1394                 }
1395         } else {
1396                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1397         }
1398
1399         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1400
1401         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1402
1403         return 0;
1404 }
1405
1406 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1407 {
1408         int r;
1409
1410         if (adev->gart.bo) {
1411                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1412                 return 0;
1413         }
1414
1415         if (adev->gmc.xgmi.connected_to_cpu) {
1416                 adev->gmc.vmid0_page_table_depth = 1;
1417                 adev->gmc.vmid0_page_table_block_size = 12;
1418         } else {
1419                 adev->gmc.vmid0_page_table_depth = 0;
1420                 adev->gmc.vmid0_page_table_block_size = 0;
1421         }
1422
1423         /* Initialize common gart structure */
1424         r = amdgpu_gart_init(adev);
1425         if (r)
1426                 return r;
1427         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1428         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1429                                  AMDGPU_PTE_EXECUTABLE;
1430
1431         r = amdgpu_gart_table_vram_alloc(adev);
1432         if (r)
1433                 return r;
1434
1435         if (adev->gmc.xgmi.connected_to_cpu) {
1436                 r = amdgpu_gmc_pdb0_alloc(adev);
1437         }
1438
1439         return r;
1440 }
1441
1442 /**
1443  * gmc_v9_0_save_registers - saves regs
1444  *
1445  * @adev: amdgpu_device pointer
1446  *
1447  * This saves potential register values that should be
1448  * restored upon resume
1449  */
1450 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1451 {
1452         if (adev->asic_type == CHIP_RAVEN)
1453                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1454 }
1455
1456 static int gmc_v9_0_sw_init(void *handle)
1457 {
1458         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1459         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1460
1461         adev->gfxhub.funcs->init(adev);
1462
1463         adev->mmhub.funcs->init(adev);
1464
1465         spin_lock_init(&adev->gmc.invalidate_lock);
1466
1467         r = amdgpu_atomfirmware_get_vram_info(adev,
1468                 &vram_width, &vram_type, &vram_vendor);
1469         if (amdgpu_sriov_vf(adev))
1470                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1471                  * and DF related registers is not readable, seems hardcord is the
1472                  * only way to set the correct vram_width
1473                  */
1474                 adev->gmc.vram_width = 2048;
1475         else if (amdgpu_emu_mode != 1)
1476                 adev->gmc.vram_width = vram_width;
1477
1478         if (!adev->gmc.vram_width) {
1479                 int chansize, numchan;
1480
1481                 /* hbm memory channel size */
1482                 if (adev->flags & AMD_IS_APU)
1483                         chansize = 64;
1484                 else
1485                         chansize = 128;
1486
1487                 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1488                 adev->gmc.vram_width = numchan * chansize;
1489         }
1490
1491         adev->gmc.vram_type = vram_type;
1492         adev->gmc.vram_vendor = vram_vendor;
1493         switch (adev->asic_type) {
1494         case CHIP_RAVEN:
1495                 adev->num_vmhubs = 2;
1496
1497                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1498                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1499                 } else {
1500                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1501                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1502                         adev->gmc.translate_further =
1503                                 adev->vm_manager.num_level > 1;
1504                 }
1505                 break;
1506         case CHIP_VEGA10:
1507         case CHIP_VEGA12:
1508         case CHIP_VEGA20:
1509         case CHIP_RENOIR:
1510         case CHIP_ALDEBARAN:
1511                 adev->num_vmhubs = 2;
1512
1513
1514                 /*
1515                  * To fulfill 4-level page support,
1516                  * vm size is 256TB (48bit), maximum size of Vega10,
1517                  * block size 512 (9bit)
1518                  */
1519                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1520                 if (amdgpu_sriov_vf(adev))
1521                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1522                 else
1523                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1524                 break;
1525         case CHIP_ARCTURUS:
1526                 adev->num_vmhubs = 3;
1527
1528                 /* Keep the vm size same with Vega20 */
1529                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1530                 break;
1531         default:
1532                 break;
1533         }
1534
1535         /* This interrupt is VMC page fault.*/
1536         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1537                                 &adev->gmc.vm_fault);
1538         if (r)
1539                 return r;
1540
1541         if (adev->asic_type == CHIP_ARCTURUS) {
1542                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1543                                         &adev->gmc.vm_fault);
1544                 if (r)
1545                         return r;
1546         }
1547
1548         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1549                                 &adev->gmc.vm_fault);
1550
1551         if (r)
1552                 return r;
1553
1554         if (!amdgpu_sriov_vf(adev) &&
1555             !adev->gmc.xgmi.connected_to_cpu) {
1556                 /* interrupt sent to DF. */
1557                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1558                                       &adev->gmc.ecc_irq);
1559                 if (r)
1560                         return r;
1561         }
1562
1563         /* Set the internal MC address mask
1564          * This is the max address of the GPU's
1565          * internal address space.
1566          */
1567         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1568
1569         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1570         if (r) {
1571                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1572                 return r;
1573         }
1574         adev->need_swiotlb = drm_need_swiotlb(44);
1575
1576         if (adev->gmc.xgmi.supported) {
1577                 r = adev->gfxhub.funcs->get_xgmi_info(adev);
1578                 if (r)
1579                         return r;
1580         }
1581
1582         r = gmc_v9_0_mc_init(adev);
1583         if (r)
1584                 return r;
1585
1586         amdgpu_gmc_get_vbios_allocations(adev);
1587
1588         /* Memory manager */
1589         r = amdgpu_bo_init(adev);
1590         if (r)
1591                 return r;
1592
1593         r = gmc_v9_0_gart_init(adev);
1594         if (r)
1595                 return r;
1596
1597         /*
1598          * number of VMs
1599          * VMID 0 is reserved for System
1600          * amdgpu graphics/compute will use VMIDs 1..n-1
1601          * amdkfd will use VMIDs n..15
1602          *
1603          * The first KFD VMID is 8 for GPUs with graphics, 3 for
1604          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1605          * for video processing.
1606          */
1607         adev->vm_manager.first_kfd_vmid =
1608                 (adev->asic_type == CHIP_ARCTURUS ||
1609                  adev->asic_type == CHIP_ALDEBARAN) ? 3 : 8;
1610
1611         amdgpu_vm_manager_init(adev);
1612
1613         gmc_v9_0_save_registers(adev);
1614
1615         return 0;
1616 }
1617
1618 static int gmc_v9_0_sw_fini(void *handle)
1619 {
1620         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1621
1622         amdgpu_gmc_ras_fini(adev);
1623         amdgpu_gem_force_release(adev);
1624         amdgpu_vm_manager_fini(adev);
1625         amdgpu_gart_table_vram_free(adev);
1626         amdgpu_bo_unref(&adev->gmc.pdb0_bo);
1627         amdgpu_bo_fini(adev);
1628
1629         return 0;
1630 }
1631
1632 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1633 {
1634
1635         switch (adev->asic_type) {
1636         case CHIP_VEGA10:
1637                 if (amdgpu_sriov_vf(adev))
1638                         break;
1639                 fallthrough;
1640         case CHIP_VEGA20:
1641                 soc15_program_register_sequence(adev,
1642                                                 golden_settings_mmhub_1_0_0,
1643                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1644                 soc15_program_register_sequence(adev,
1645                                                 golden_settings_athub_1_0_0,
1646                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1647                 break;
1648         case CHIP_VEGA12:
1649                 break;
1650         case CHIP_RAVEN:
1651                 /* TODO for renoir */
1652                 soc15_program_register_sequence(adev,
1653                                                 golden_settings_athub_1_0_0,
1654                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1655                 break;
1656         default:
1657                 break;
1658         }
1659 }
1660
1661 /**
1662  * gmc_v9_0_restore_registers - restores regs
1663  *
1664  * @adev: amdgpu_device pointer
1665  *
1666  * This restores register values, saved at suspend.
1667  */
1668 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1669 {
1670         if (adev->asic_type == CHIP_RAVEN) {
1671                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1672                 WARN_ON(adev->gmc.sdpif_register !=
1673                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
1674         }
1675 }
1676
1677 /**
1678  * gmc_v9_0_gart_enable - gart enable
1679  *
1680  * @adev: amdgpu_device pointer
1681  */
1682 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1683 {
1684         int r;
1685
1686         if (adev->gmc.xgmi.connected_to_cpu)
1687                 amdgpu_gmc_init_pdb0(adev);
1688
1689         if (adev->gart.bo == NULL) {
1690                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1691                 return -EINVAL;
1692         }
1693
1694         r = amdgpu_gart_table_vram_pin(adev);
1695         if (r)
1696                 return r;
1697
1698         r = adev->gfxhub.funcs->gart_enable(adev);
1699         if (r)
1700                 return r;
1701
1702         r = adev->mmhub.funcs->gart_enable(adev);
1703         if (r)
1704                 return r;
1705
1706         DRM_INFO("PCIE GART of %uM enabled.\n",
1707                  (unsigned)(adev->gmc.gart_size >> 20));
1708         if (adev->gmc.pdb0_bo)
1709                 DRM_INFO("PDB0 located at 0x%016llX\n",
1710                                 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
1711         DRM_INFO("PTB located at 0x%016llX\n",
1712                         (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1713
1714         adev->gart.ready = true;
1715         return 0;
1716 }
1717
1718 static int gmc_v9_0_hw_init(void *handle)
1719 {
1720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1721         bool value;
1722         int r, i;
1723
1724         /* The sequence of these two function calls matters.*/
1725         gmc_v9_0_init_golden_registers(adev);
1726
1727         if (adev->mode_info.num_crtc) {
1728                 /* Lockout access through VGA aperture*/
1729                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1730                 /* disable VGA render */
1731                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1732         }
1733
1734         if (adev->mmhub.funcs->update_power_gating)
1735                 adev->mmhub.funcs->update_power_gating(adev, true);
1736
1737         adev->hdp.funcs->init_registers(adev);
1738
1739         /* After HDP is initialized, flush HDP.*/
1740         adev->hdp.funcs->flush_hdp(adev, NULL);
1741
1742         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1743                 value = false;
1744         else
1745                 value = true;
1746
1747         if (!amdgpu_sriov_vf(adev)) {
1748                 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1749                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1750         }
1751         for (i = 0; i < adev->num_vmhubs; ++i)
1752                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1753
1754         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1755                 adev->umc.funcs->init_registers(adev);
1756
1757         r = gmc_v9_0_gart_enable(adev);
1758
1759         return r;
1760 }
1761
1762 /**
1763  * gmc_v9_0_gart_disable - gart disable
1764  *
1765  * @adev: amdgpu_device pointer
1766  *
1767  * This disables all VM page table.
1768  */
1769 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1770 {
1771         adev->gfxhub.funcs->gart_disable(adev);
1772         adev->mmhub.funcs->gart_disable(adev);
1773         amdgpu_gart_table_vram_unpin(adev);
1774 }
1775
1776 static int gmc_v9_0_hw_fini(void *handle)
1777 {
1778         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1779
1780         if (amdgpu_sriov_vf(adev)) {
1781                 /* full access mode, so don't touch any GMC register */
1782                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1783                 return 0;
1784         }
1785
1786         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1787         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1788         gmc_v9_0_gart_disable(adev);
1789
1790         return 0;
1791 }
1792
1793 static int gmc_v9_0_suspend(void *handle)
1794 {
1795         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1796
1797         return gmc_v9_0_hw_fini(adev);
1798 }
1799
1800 static int gmc_v9_0_resume(void *handle)
1801 {
1802         int r;
1803         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1804
1805         r = gmc_v9_0_hw_init(adev);
1806         if (r)
1807                 return r;
1808
1809         amdgpu_vmid_reset_all(adev);
1810
1811         return 0;
1812 }
1813
1814 static bool gmc_v9_0_is_idle(void *handle)
1815 {
1816         /* MC is always ready in GMC v9.*/
1817         return true;
1818 }
1819
1820 static int gmc_v9_0_wait_for_idle(void *handle)
1821 {
1822         /* There is no need to wait for MC idle in GMC v9.*/
1823         return 0;
1824 }
1825
1826 static int gmc_v9_0_soft_reset(void *handle)
1827 {
1828         /* XXX for emulation.*/
1829         return 0;
1830 }
1831
1832 static int gmc_v9_0_set_clockgating_state(void *handle,
1833                                         enum amd_clockgating_state state)
1834 {
1835         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1836
1837         adev->mmhub.funcs->set_clockgating(adev, state);
1838
1839         athub_v1_0_set_clockgating(adev, state);
1840
1841         return 0;
1842 }
1843
1844 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1845 {
1846         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1847
1848         adev->mmhub.funcs->get_clockgating(adev, flags);
1849
1850         athub_v1_0_get_clockgating(adev, flags);
1851 }
1852
1853 static int gmc_v9_0_set_powergating_state(void *handle,
1854                                         enum amd_powergating_state state)
1855 {
1856         return 0;
1857 }
1858
1859 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1860         .name = "gmc_v9_0",
1861         .early_init = gmc_v9_0_early_init,
1862         .late_init = gmc_v9_0_late_init,
1863         .sw_init = gmc_v9_0_sw_init,
1864         .sw_fini = gmc_v9_0_sw_fini,
1865         .hw_init = gmc_v9_0_hw_init,
1866         .hw_fini = gmc_v9_0_hw_fini,
1867         .suspend = gmc_v9_0_suspend,
1868         .resume = gmc_v9_0_resume,
1869         .is_idle = gmc_v9_0_is_idle,
1870         .wait_for_idle = gmc_v9_0_wait_for_idle,
1871         .soft_reset = gmc_v9_0_soft_reset,
1872         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1873         .set_powergating_state = gmc_v9_0_set_powergating_state,
1874         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1875 };
1876
1877 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1878 {
1879         .type = AMD_IP_BLOCK_TYPE_GMC,
1880         .major = 9,
1881         .minor = 0,
1882         .rev = 0,
1883         .funcs = &gmc_v9_0_ip_funcs,
1884 };