drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "mmhub_v1_7.h"
  54 #include "umc_v6_1.h"
  55 #include "umc_v6_0.h"
  56 #include "umc_v6_7.h"
  57 #include "hdp_v4_0.h"
  58 #include "mca_v3_0.h"
  59
  60 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  61
  62 #include "amdgpu_ras.h"
  63 #include "amdgpu_xgmi.h"
  64
  65 /* add these here since we already include dce12 headers and these are for DCN */
  66 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  67 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  72 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  73 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  74
  75
  76 static const char *gfxhub_client_ids[] = {
  77         "CB",
  78         "DB",
  79         "IA",
  80         "WD",
  81         "CPF",
  82         "CPC",
  83         "CPG",
  84         "RLC",
  85         "TCP",
  86         "SQC (inst)",
  87         "SQC (data)",
  88         "SQG",
  89         "PA",
  90 };
  91
  92 static const char *mmhub_client_ids_raven[][2] = {
  93         [0][0] = "MP1",
  94         [1][0] = "MP0",
  95         [2][0] = "VCN",
  96         [3][0] = "VCNU",
  97         [4][0] = "HDP",
  98         [5][0] = "DCE",
  99         [13][0] = "UTCL2",
 100         [19][0] = "TLS",
 101         [26][0] = "OSS",
 102         [27][0] = "SDMA0",
 103         [0][1] = "MP1",
 104         [1][1] = "MP0",
 105         [2][1] = "VCN",
 106         [3][1] = "VCNU",
 107         [4][1] = "HDP",
 108         [5][1] = "XDP",
 109         [6][1] = "DBGU0",
 110         [7][1] = "DCE",
 111         [8][1] = "DCEDWB0",
 112         [9][1] = "DCEDWB1",
 113         [26][1] = "OSS",
 114         [27][1] = "SDMA0",
 115 };
 116
 117 static const char *mmhub_client_ids_renoir[][2] = {
 118         [0][0] = "MP1",
 119         [1][0] = "MP0",
 120         [2][0] = "HDP",
 121         [4][0] = "DCEDMC",
 122         [5][0] = "DCEVGA",
 123         [13][0] = "UTCL2",
 124         [19][0] = "TLS",
 125         [26][0] = "OSS",
 126         [27][0] = "SDMA0",
 127         [28][0] = "VCN",
 128         [29][0] = "VCNU",
 129         [30][0] = "JPEG",
 130         [0][1] = "MP1",
 131         [1][1] = "MP0",
 132         [2][1] = "HDP",
 133         [3][1] = "XDP",
 134         [6][1] = "DBGU0",
 135         [7][1] = "DCEDMC",
 136         [8][1] = "DCEVGA",
 137         [9][1] = "DCEDWB",
 138         [26][1] = "OSS",
 139         [27][1] = "SDMA0",
 140         [28][1] = "VCN",
 141         [29][1] = "VCNU",
 142         [30][1] = "JPEG",
 143 };
 144
 145 static const char *mmhub_client_ids_vega10[][2] = {
 146         [0][0] = "MP0",
 147         [1][0] = "UVD",
 148         [2][0] = "UVDU",
 149         [3][0] = "HDP",
 150         [13][0] = "UTCL2",
 151         [14][0] = "OSS",
 152         [15][0] = "SDMA1",
 153         [32+0][0] = "VCE0",
 154         [32+1][0] = "VCE0U",
 155         [32+2][0] = "XDMA",
 156         [32+3][0] = "DCE",
 157         [32+4][0] = "MP1",
 158         [32+14][0] = "SDMA0",
 159         [0][1] = "MP0",
 160         [1][1] = "UVD",
 161         [2][1] = "UVDU",
 162         [3][1] = "DBGU0",
 163         [4][1] = "HDP",
 164         [5][1] = "XDP",
 165         [14][1] = "OSS",
 166         [15][1] = "SDMA0",
 167         [32+0][1] = "VCE0",
 168         [32+1][1] = "VCE0U",
 169         [32+2][1] = "XDMA",
 170         [32+3][1] = "DCE",
 171         [32+4][1] = "DCEDWB",
 172         [32+5][1] = "MP1",
 173         [32+6][1] = "DBGU1",
 174         [32+14][1] = "SDMA1",
 175 };
 176
 177 static const char *mmhub_client_ids_vega12[][2] = {
 178         [0][0] = "MP0",
 179         [1][0] = "VCE0",
 180         [2][0] = "VCE0U",
 181         [3][0] = "HDP",
 182         [13][0] = "UTCL2",
 183         [14][0] = "OSS",
 184         [15][0] = "SDMA1",
 185         [32+0][0] = "DCE",
 186         [32+1][0] = "XDMA",
 187         [32+2][0] = "UVD",
 188         [32+3][0] = "UVDU",
 189         [32+4][0] = "MP1",
 190         [32+15][0] = "SDMA0",
 191         [0][1] = "MP0",
 192         [1][1] = "VCE0",
 193         [2][1] = "VCE0U",
 194         [3][1] = "DBGU0",
 195         [4][1] = "HDP",
 196         [5][1] = "XDP",
 197         [14][1] = "OSS",
 198         [15][1] = "SDMA0",
 199         [32+0][1] = "DCE",
 200         [32+1][1] = "DCEDWB",
 201         [32+2][1] = "XDMA",
 202         [32+3][1] = "UVD",
 203         [32+4][1] = "UVDU",
 204         [32+5][1] = "MP1",
 205         [32+6][1] = "DBGU1",
 206         [32+15][1] = "SDMA1",
 207 };
 208
 209 static const char *mmhub_client_ids_vega20[][2] = {
 210         [0][0] = "XDMA",
 211         [1][0] = "DCE",
 212         [2][0] = "VCE0",
 213         [3][0] = "VCE0U",
 214         [4][0] = "UVD",
 215         [5][0] = "UVD1U",
 216         [13][0] = "OSS",
 217         [14][0] = "HDP",
 218         [15][0] = "SDMA0",
 219         [32+0][0] = "UVD",
 220         [32+1][0] = "UVDU",
 221         [32+2][0] = "MP1",
 222         [32+3][0] = "MP0",
 223         [32+12][0] = "UTCL2",
 224         [32+14][0] = "SDMA1",
 225         [0][1] = "XDMA",
 226         [1][1] = "DCE",
 227         [2][1] = "DCEDWB",
 228         [3][1] = "VCE0",
 229         [4][1] = "VCE0U",
 230         [5][1] = "UVD1",
 231         [6][1] = "UVD1U",
 232         [7][1] = "DBGU0",
 233         [8][1] = "XDP",
 234         [13][1] = "OSS",
 235         [14][1] = "HDP",
 236         [15][1] = "SDMA0",
 237         [32+0][1] = "UVD",
 238         [32+1][1] = "UVDU",
 239         [32+2][1] = "DBGU1",
 240         [32+3][1] = "MP1",
 241         [32+4][1] = "MP0",
 242         [32+14][1] = "SDMA1",
 243 };
 244
 245 static const char *mmhub_client_ids_arcturus[][2] = {
 246         [0][0] = "DBGU1",
 247         [1][0] = "XDP",
 248         [2][0] = "MP1",
 249         [14][0] = "HDP",
 250         [171][0] = "JPEG",
 251         [172][0] = "VCN",
 252         [173][0] = "VCNU",
 253         [203][0] = "JPEG1",
 254         [204][0] = "VCN1",
 255         [205][0] = "VCN1U",
 256         [256][0] = "SDMA0",
 257         [257][0] = "SDMA1",
 258         [258][0] = "SDMA2",
 259         [259][0] = "SDMA3",
 260         [260][0] = "SDMA4",
 261         [261][0] = "SDMA5",
 262         [262][0] = "SDMA6",
 263         [263][0] = "SDMA7",
 264         [384][0] = "OSS",
 265         [0][1] = "DBGU1",
 266         [1][1] = "XDP",
 267         [2][1] = "MP1",
 268         [14][1] = "HDP",
 269         [171][1] = "JPEG",
 270         [172][1] = "VCN",
 271         [173][1] = "VCNU",
 272         [203][1] = "JPEG1",
 273         [204][1] = "VCN1",
 274         [205][1] = "VCN1U",
 275         [256][1] = "SDMA0",
 276         [257][1] = "SDMA1",
 277         [258][1] = "SDMA2",
 278         [259][1] = "SDMA3",
 279         [260][1] = "SDMA4",
 280         [261][1] = "SDMA5",
 281         [262][1] = "SDMA6",
 282         [263][1] = "SDMA7",
 283         [384][1] = "OSS",
 284 };
 285
 286 static const char *mmhub_client_ids_aldebaran[][2] = {
 287         [2][0] = "MP1",
 288         [3][0] = "MP0",
 289         [32+1][0] = "DBGU_IO0",
 290         [32+2][0] = "DBGU_IO2",
 291         [32+4][0] = "MPIO",
 292         [96+11][0] = "JPEG0",
 293         [96+12][0] = "VCN0",
 294         [96+13][0] = "VCNU0",
 295         [128+11][0] = "JPEG1",
 296         [128+12][0] = "VCN1",
 297         [128+13][0] = "VCNU1",
 298         [160+1][0] = "XDP",
 299         [160+14][0] = "HDP",
 300         [256+0][0] = "SDMA0",
 301         [256+1][0] = "SDMA1",
 302         [256+2][0] = "SDMA2",
 303         [256+3][0] = "SDMA3",
 304         [256+4][0] = "SDMA4",
 305         [384+0][0] = "OSS",
 306         [2][1] = "MP1",
 307         [3][1] = "MP0",
 308         [32+1][1] = "DBGU_IO0",
 309         [32+2][1] = "DBGU_IO2",
 310         [32+4][1] = "MPIO",
 311         [96+11][1] = "JPEG0",
 312         [96+12][1] = "VCN0",
 313         [96+13][1] = "VCNU0",
 314         [128+11][1] = "JPEG1",
 315         [128+12][1] = "VCN1",
 316         [128+13][1] = "VCNU1",
 317         [160+1][1] = "XDP",
 318         [160+14][1] = "HDP",
 319         [256+0][1] = "SDMA0",
 320         [256+1][1] = "SDMA1",
 321         [256+2][1] = "SDMA2",
 322         [256+3][1] = "SDMA3",
 323         [256+4][1] = "SDMA4",
 324         [384+0][1] = "OSS",
 325 };
 326
 327 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
 328 {
 329         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 330         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 331 };
 332
 333 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
 334 {
 335         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 336         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 337 };
 338
 339 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 340         (0x000143c0 + 0x00000000),
 341         (0x000143c0 + 0x00000800),
 342         (0x000143c0 + 0x00001000),
 343         (0x000143c0 + 0x00001800),
 344         (0x000543c0 + 0x00000000),
 345         (0x000543c0 + 0x00000800),
 346         (0x000543c0 + 0x00001000),
 347         (0x000543c0 + 0x00001800),
 348         (0x000943c0 + 0x00000000),
 349         (0x000943c0 + 0x00000800),
 350         (0x000943c0 + 0x00001000),
 351         (0x000943c0 + 0x00001800),
 352         (0x000d43c0 + 0x00000000),
 353         (0x000d43c0 + 0x00000800),
 354         (0x000d43c0 + 0x00001000),
 355         (0x000d43c0 + 0x00001800),
 356         (0x001143c0 + 0x00000000),
 357         (0x001143c0 + 0x00000800),
 358         (0x001143c0 + 0x00001000),
 359         (0x001143c0 + 0x00001800),
 360         (0x001543c0 + 0x00000000),
 361         (0x001543c0 + 0x00000800),
 362         (0x001543c0 + 0x00001000),
 363         (0x001543c0 + 0x00001800),
 364         (0x001943c0 + 0x00000000),
 365         (0x001943c0 + 0x00000800),
 366         (0x001943c0 + 0x00001000),
 367         (0x001943c0 + 0x00001800),
 368         (0x001d43c0 + 0x00000000),
 369         (0x001d43c0 + 0x00000800),
 370         (0x001d43c0 + 0x00001000),
 371         (0x001d43c0 + 0x00001800),
 372 };
 373
 374 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 375         (0x000143e0 + 0x00000000),
 376         (0x000143e0 + 0x00000800),
 377         (0x000143e0 + 0x00001000),
 378         (0x000143e0 + 0x00001800),
 379         (0x000543e0 + 0x00000000),
 380         (0x000543e0 + 0x00000800),
 381         (0x000543e0 + 0x00001000),
 382         (0x000543e0 + 0x00001800),
 383         (0x000943e0 + 0x00000000),
 384         (0x000943e0 + 0x00000800),
 385         (0x000943e0 + 0x00001000),
 386         (0x000943e0 + 0x00001800),
 387         (0x000d43e0 + 0x00000000),
 388         (0x000d43e0 + 0x00000800),
 389         (0x000d43e0 + 0x00001000),
 390         (0x000d43e0 + 0x00001800),
 391         (0x001143e0 + 0x00000000),
 392         (0x001143e0 + 0x00000800),
 393         (0x001143e0 + 0x00001000),
 394         (0x001143e0 + 0x00001800),
 395         (0x001543e0 + 0x00000000),
 396         (0x001543e0 + 0x00000800),
 397         (0x001543e0 + 0x00001000),
 398         (0x001543e0 + 0x00001800),
 399         (0x001943e0 + 0x00000000),
 400         (0x001943e0 + 0x00000800),
 401         (0x001943e0 + 0x00001000),
 402         (0x001943e0 + 0x00001800),
 403         (0x001d43e0 + 0x00000000),
 404         (0x001d43e0 + 0x00000800),
 405         (0x001d43e0 + 0x00001000),
 406         (0x001d43e0 + 0x00001800),
 407 };
 408
 409 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 410                 struct amdgpu_irq_src *src,
 411                 unsigned type,
 412                 enum amdgpu_interrupt_state state)
 413 {
 414         u32 bits, i, tmp, reg;
 415
 416         /* Devices newer then VEGA10/12 shall have these programming
 417              sequences performed by PSP BL */
 418         if (adev->asic_type >= CHIP_VEGA20)
 419                 return 0;
 420
 421         bits = 0x7f;
 422
 423         switch (state) {
 424         case AMDGPU_IRQ_STATE_DISABLE:
 425                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 426                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 427                         tmp = RREG32(reg);
 428                         tmp &= ~bits;
 429                         WREG32(reg, tmp);
 430                 }
 431                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 432                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 433                         tmp = RREG32(reg);
 434                         tmp &= ~bits;
 435                         WREG32(reg, tmp);
 436                 }
 437                 break;
 438         case AMDGPU_IRQ_STATE_ENABLE:
 439                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 440                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 441                         tmp = RREG32(reg);
 442                         tmp |= bits;
 443                         WREG32(reg, tmp);
 444                 }
 445                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 446                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 447                         tmp = RREG32(reg);
 448                         tmp |= bits;
 449                         WREG32(reg, tmp);
 450                 }
 451                 break;
 452         default:
 453                 break;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 460                                         struct amdgpu_irq_src *src,
 461                                         unsigned type,
 462                                         enum amdgpu_interrupt_state state)
 463 {
 464         struct amdgpu_vmhub *hub;
 465         u32 tmp, reg, bits, i, j;
 466
 467         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 468                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 469                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 470                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 471                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 472                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 473                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 474
 475         switch (state) {
 476         case AMDGPU_IRQ_STATE_DISABLE:
 477                 for (j = 0; j < adev->num_vmhubs; j++) {
 478                         hub = &adev->vmhub[j];
 479                         for (i = 0; i < 16; i++) {
 480                                 reg = hub->vm_context0_cntl + i;
 481                                 tmp = RREG32(reg);
 482                                 tmp &= ~bits;
 483                                 WREG32(reg, tmp);
 484                         }
 485                 }
 486                 break;
 487         case AMDGPU_IRQ_STATE_ENABLE:
 488                 for (j = 0; j < adev->num_vmhubs; j++) {
 489                         hub = &adev->vmhub[j];
 490                         for (i = 0; i < 16; i++) {
 491                                 reg = hub->vm_context0_cntl + i;
 492                                 tmp = RREG32(reg);
 493                                 tmp |= bits;
 494                                 WREG32(reg, tmp);
 495                         }
 496                 }
 497                 break;
 498         default:
 499                 break;
 500         }
 501
 502         return 0;
 503 }
 504
 505 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 506                                       struct amdgpu_irq_src *source,
 507                                       struct amdgpu_iv_entry *entry)
 508 {
 509         bool retry_fault = !!(entry->src_data[1] & 0x80);
 510         uint32_t status = 0, cid = 0, rw = 0;
 511         struct amdgpu_task_info task_info;
 512         struct amdgpu_vmhub *hub;
 513         const char *mmhub_cid;
 514         const char *hub_name;
 515         u64 addr;
 516
 517         addr = (u64)entry->src_data[0] << 12;
 518         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 519
 520         if (retry_fault) {
 521                 /* Returning 1 here also prevents sending the IV to the KFD */
 522
 523                 /* Process it onyl if it's the first fault for this address */
 524                 if (entry->ih != &adev->irq.ih_soft &&
 525                     amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 526                                              entry->timestamp))
 527                         return 1;
 528
 529                 /* Delegate it to a different ring if the hardware hasn't
 530                  * already done it.
 531                  */
 532                 if (entry->ih == &adev->irq.ih) {
 533                         amdgpu_irq_delegate(adev, entry, 8);
 534                         return 1;
 535                 }
 536
 537                 /* Try to handle the recoverable page faults by filling page
 538                  * tables
 539                  */
 540                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 541                         return 1;
 542         }
 543
 544         if (!printk_ratelimit())
 545                 return 0;
 546
 547         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 548                 hub_name = "mmhub0";
 549                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 550         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 551                 hub_name = "mmhub1";
 552                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 553         } else {
 554                 hub_name = "gfxhub0";
 555                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 556         }
 557
 558         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 559         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 560
 561         dev_err(adev->dev,
 562                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 563                 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 564                 hub_name, retry_fault ? "retry" : "no-retry",
 565                 entry->src_id, entry->ring_id, entry->vmid,
 566                 entry->pasid, task_info.process_name, task_info.tgid,
 567                 task_info.task_name, task_info.pid);
 568         dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
 569                 addr, entry->client_id,
 570                 soc15_ih_clientid_name[entry->client_id]);
 571
 572         if (amdgpu_sriov_vf(adev))
 573                 return 0;
 574
 575         /*
 576          * Issue a dummy read to wait for the status register to
 577          * be updated to avoid reading an incorrect value due to
 578          * the new fast GRBM interface.
 579          */
 580         if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 581             (adev->asic_type < CHIP_ALDEBARAN))
 582                 RREG32(hub->vm_l2_pro_fault_status);
 583
 584         status = RREG32(hub->vm_l2_pro_fault_status);
 585         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 586         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 587         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 588
 589
 590         dev_err(adev->dev,
 591                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 592                 status);
 593         if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
 594                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 595                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 596                         gfxhub_client_ids[cid],
 597                         cid);
 598         } else {
 599                 switch (adev->asic_type) {
 600                 case CHIP_VEGA10:
 601                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 602                         break;
 603                 case CHIP_VEGA12:
 604                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 605                         break;
 606                 case CHIP_VEGA20:
 607                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 608                         break;
 609                 case CHIP_ARCTURUS:
 610                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 611                         break;
 612                 case CHIP_RAVEN:
 613                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 614                         break;
 615                 case CHIP_RENOIR:
 616                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 617                         break;
 618                 case CHIP_ALDEBARAN:
 619                         mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
 620                         break;
 621                 default:
 622                         mmhub_cid = NULL;
 623                         break;
 624                 }
 625                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 626                         mmhub_cid ? mmhub_cid : "unknown", cid);
 627         }
 628         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 629                 REG_GET_FIELD(status,
 630                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 631         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 632                 REG_GET_FIELD(status,
 633                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 634         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 635                 REG_GET_FIELD(status,
 636                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 637         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 638                 REG_GET_FIELD(status,
 639                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 640         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 641         return 0;
 642 }
 643
 644 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 645         .set = gmc_v9_0_vm_fault_interrupt_state,
 646         .process = gmc_v9_0_process_interrupt,
 647 };
 648
 649
 650 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 651         .set = gmc_v9_0_ecc_interrupt_state,
 652         .process = amdgpu_umc_process_ecc_irq,
 653 };
 654
 655 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 656 {
 657         adev->gmc.vm_fault.num_types = 1;
 658         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 659
 660         if (!amdgpu_sriov_vf(adev) &&
 661             !adev->gmc.xgmi.connected_to_cpu) {
 662                 adev->gmc.ecc_irq.num_types = 1;
 663                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 664         }
 665 }
 666
 667 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 668                                         uint32_t flush_type)
 669 {
 670         u32 req = 0;
 671
 672         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 673                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 674         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 675         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 676         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 677         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 678         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 679         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 680         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 681                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 682
 683         return req;
 684 }
 685
 686 /**
 687  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 688  *
 689  * @adev: amdgpu_device pointer
 690  * @vmhub: vmhub type
 691  *
 692  */
 693 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 694                                        uint32_t vmhub)
 695 {
 696         if (adev->asic_type == CHIP_ALDEBARAN)
 697                 return false;
 698
 699         return ((vmhub == AMDGPU_MMHUB_0 ||
 700                  vmhub == AMDGPU_MMHUB_1) &&
 701                 (!amdgpu_sriov_vf(adev)) &&
 702                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 703                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 704 }
 705
 706 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 707                                         uint8_t vmid, uint16_t *p_pasid)
 708 {
 709         uint32_t value;
 710
 711         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 712                      + vmid);
 713         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 714
 715         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 716 }
 717
 718 /*
 719  * GART
 720  * VMID 0 is the physical GPU addresses as used by the kernel.
 721  * VMIDs 1-15 are used for userspace clients and are handled
 722  * by the amdgpu vm/hsa code.
 723  */
 724
 725 /**
 726  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 727  *
 728  * @adev: amdgpu_device pointer
 729  * @vmid: vm instance to flush
 730  * @vmhub: which hub to flush
 731  * @flush_type: the flush type
 732  *
 733  * Flush the TLB for the requested page table using certain type.
 734  */
 735 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 736                                         uint32_t vmhub, uint32_t flush_type)
 737 {
 738         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 739         const unsigned eng = 17;
 740         u32 j, inv_req, inv_req2, tmp;
 741         struct amdgpu_vmhub *hub;
 742
 743         BUG_ON(vmhub >= adev->num_vmhubs);
 744
 745         hub = &adev->vmhub[vmhub];
 746         if (adev->gmc.xgmi.num_physical_nodes &&
 747             adev->asic_type == CHIP_VEGA20) {
 748                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 749                  * heavy-weight TLB flush (type 2), which flushes
 750                  * both. Due to a race condition with concurrent
 751                  * memory accesses using the same TLB cache line, we
 752                  * still need a second TLB flush after this.
 753                  */
 754                 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
 755                 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 756         } else {
 757                 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 758                 inv_req2 = 0;
 759         }
 760
 761         /* This is necessary for a HW workaround under SRIOV as well
 762          * as GFXOFF under bare metal
 763          */
 764         if (adev->gfx.kiq.ring.sched.ready &&
 765             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 766             down_read_trylock(&adev->reset_sem)) {
 767                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 768                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 769
 770                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 771                                                    1 << vmid);
 772                 up_read(&adev->reset_sem);
 773                 return;
 774         }
 775
 776         spin_lock(&adev->gmc.invalidate_lock);
 777
 778         /*
 779          * It may lose gpuvm invalidate acknowldege state across power-gating
 780          * off cycle, add semaphore acquire before invalidation and semaphore
 781          * release after invalidation to avoid entering power gated state
 782          * to WA the Issue
 783          */
 784
 785         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 786         if (use_semaphore) {
 787                 for (j = 0; j < adev->usec_timeout; j++) {
 788                         /* a read return value of 1 means semaphore acuqire */
 789                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 790                                             hub->eng_distance * eng);
 791                         if (tmp & 0x1)
 792                                 break;
 793                         udelay(1);
 794                 }
 795
 796                 if (j >= adev->usec_timeout)
 797                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 798         }
 799
 800         do {
 801                 WREG32_NO_KIQ(hub->vm_inv_eng0_req +
 802                               hub->eng_distance * eng, inv_req);
 803
 804                 /*
 805                  * Issue a dummy read to wait for the ACK register to
 806                  * be cleared to avoid a false ACK due to the new fast
 807                  * GRBM interface.
 808                  */
 809                 if ((vmhub == AMDGPU_GFXHUB_0) &&
 810                     (adev->asic_type < CHIP_ALDEBARAN))
 811                         RREG32_NO_KIQ(hub->vm_inv_eng0_req +
 812                                       hub->eng_distance * eng);
 813
 814                 for (j = 0; j < adev->usec_timeout; j++) {
 815                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
 816                                             hub->eng_distance * eng);
 817                         if (tmp & (1 << vmid))
 818                                 break;
 819                         udelay(1);
 820                 }
 821
 822                 inv_req = inv_req2;
 823                 inv_req2 = 0;
 824         } while (inv_req);
 825
 826         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 827         if (use_semaphore)
 828                 /*
 829                  * add semaphore release after invalidation,
 830                  * write with 0 means semaphore release
 831                  */
 832                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 833                               hub->eng_distance * eng, 0);
 834
 835         spin_unlock(&adev->gmc.invalidate_lock);
 836
 837         if (j < adev->usec_timeout)
 838                 return;
 839
 840         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 841 }
 842
 843 /**
 844  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 845  *
 846  * @adev: amdgpu_device pointer
 847  * @pasid: pasid to be flush
 848  * @flush_type: the flush type
 849  * @all_hub: flush all hubs
 850  *
 851  * Flush the TLB for the requested pasid.
 852  */
 853 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 854                                         uint16_t pasid, uint32_t flush_type,
 855                                         bool all_hub)
 856 {
 857         int vmid, i;
 858         signed long r;
 859         uint32_t seq;
 860         uint16_t queried_pasid;
 861         bool ret;
 862         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 863         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 864
 865         if (amdgpu_in_reset(adev))
 866                 return -EIO;
 867
 868         if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) {
 869                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 870                  * heavy-weight TLB flush (type 2), which flushes
 871                  * both. Due to a race condition with concurrent
 872                  * memory accesses using the same TLB cache line, we
 873                  * still need a second TLB flush after this.
 874                  */
 875                 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
 876                                        adev->asic_type == CHIP_VEGA20);
 877                 /* 2 dwords flush + 8 dwords fence */
 878                 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
 879
 880                 if (vega20_xgmi_wa)
 881                         ndw += kiq->pmf->invalidate_tlbs_size;
 882
 883                 spin_lock(&adev->gfx.kiq.ring_lock);
 884                 /* 2 dwords flush + 8 dwords fence */
 885                 amdgpu_ring_alloc(ring, ndw);
 886                 if (vega20_xgmi_wa)
 887                         kiq->pmf->kiq_invalidate_tlbs(ring,
 888                                                       pasid, 2, all_hub);
 889                 kiq->pmf->kiq_invalidate_tlbs(ring,
 890                                         pasid, flush_type, all_hub);
 891                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 892                 if (r) {
 893                         amdgpu_ring_undo(ring);
 894                         spin_unlock(&adev->gfx.kiq.ring_lock);
 895                         up_read(&adev->reset_sem);
 896                         return -ETIME;
 897                 }
 898
 899                 amdgpu_ring_commit(ring);
 900                 spin_unlock(&adev->gfx.kiq.ring_lock);
 901                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 902                 if (r < 1) {
 903                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 904                         up_read(&adev->reset_sem);
 905                         return -ETIME;
 906                 }
 907                 up_read(&adev->reset_sem);
 908                 return 0;
 909         }
 910
 911         for (vmid = 1; vmid < 16; vmid++) {
 912
 913                 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 914                                 &queried_pasid);
 915                 if (ret && queried_pasid == pasid) {
 916                         if (all_hub) {
 917                                 for (i = 0; i < adev->num_vmhubs; i++)
 918                                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 919                                                         i, flush_type);
 920                         } else {
 921                                 gmc_v9_0_flush_gpu_tlb(adev, vmid,
 922                                                 AMDGPU_GFXHUB_0, flush_type);
 923                         }
 924                         break;
 925                 }
 926         }
 927
 928         return 0;
 929
 930 }
 931
 932 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 933                                             unsigned vmid, uint64_t pd_addr)
 934 {
 935         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 936         struct amdgpu_device *adev = ring->adev;
 937         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 938         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 939         unsigned eng = ring->vm_inv_eng;
 940
 941         /*
 942          * It may lose gpuvm invalidate acknowldege state across power-gating
 943          * off cycle, add semaphore acquire before invalidation and semaphore
 944          * release after invalidation to avoid entering power gated state
 945          * to WA the Issue
 946          */
 947
 948         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 949         if (use_semaphore)
 950                 /* a read return value of 1 means semaphore acuqire */
 951                 amdgpu_ring_emit_reg_wait(ring,
 952                                           hub->vm_inv_eng0_sem +
 953                                           hub->eng_distance * eng, 0x1, 0x1);
 954
 955         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 956                               (hub->ctx_addr_distance * vmid),
 957                               lower_32_bits(pd_addr));
 958
 959         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 960                               (hub->ctx_addr_distance * vmid),
 961                               upper_32_bits(pd_addr));
 962
 963         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 964                                             hub->eng_distance * eng,
 965                                             hub->vm_inv_eng0_ack +
 966                                             hub->eng_distance * eng,
 967                                             req, 1 << vmid);
 968
 969         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 970         if (use_semaphore)
 971                 /*
 972                  * add semaphore release after invalidation,
 973                  * write with 0 means semaphore release
 974                  */
 975                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 976                                       hub->eng_distance * eng, 0);
 977
 978         return pd_addr;
 979 }
 980
 981 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 982                                         unsigned pasid)
 983 {
 984         struct amdgpu_device *adev = ring->adev;
 985         uint32_t reg;
 986
 987         /* Do nothing because there's no lut register for mmhub1. */
 988         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 989                 return;
 990
 991         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 992                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 993         else
 994                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 995
 996         amdgpu_ring_emit_wreg(ring, reg, pasid);
 997 }
 998
 999 /*
1000  * PTE format on VEGA 10:
1001  * 63:59 reserved
1002  * 58:57 mtype
1003  * 56 F
1004  * 55 L
1005  * 54 P
1006  * 53 SW
1007  * 52 T
1008  * 50:48 reserved
1009  * 47:12 4k physical page base address
1010  * 11:7 fragment
1011  * 6 write
1012  * 5 read
1013  * 4 exe
1014  * 3 Z
1015  * 2 snooped
1016  * 1 system
1017  * 0 valid
1018  *
1019  * PDE format on VEGA 10:
1020  * 63:59 block fragment size
1021  * 58:55 reserved
1022  * 54 P
1023  * 53:48 reserved
1024  * 47:6 physical base address of PD or PTE
1025  * 5:3 reserved
1026  * 2 C
1027  * 1 system
1028  * 0 valid
1029  */
1030
1031 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1032
1033 {
1034         switch (flags) {
1035         case AMDGPU_VM_MTYPE_DEFAULT:
1036                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1037         case AMDGPU_VM_MTYPE_NC:
1038                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1039         case AMDGPU_VM_MTYPE_WC:
1040                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1041         case AMDGPU_VM_MTYPE_RW:
1042                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1043         case AMDGPU_VM_MTYPE_CC:
1044                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1045         case AMDGPU_VM_MTYPE_UC:
1046                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1047         default:
1048                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1049         }
1050 }
1051
1052 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1053                                 uint64_t *addr, uint64_t *flags)
1054 {
1055         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1056                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1057         BUG_ON(*addr & 0xFFFF00000000003FULL);
1058
1059         if (!adev->gmc.translate_further)
1060                 return;
1061
1062         if (level == AMDGPU_VM_PDB1) {
1063                 /* Set the block fragment size */
1064                 if (!(*flags & AMDGPU_PDE_PTE))
1065                         *flags |= AMDGPU_PDE_BFS(0x9);
1066
1067         } else if (level == AMDGPU_VM_PDB0) {
1068                 if (*flags & AMDGPU_PDE_PTE)
1069                         *flags &= ~AMDGPU_PDE_PTE;
1070                 else
1071                         *flags |= AMDGPU_PTE_TF;
1072         }
1073 }
1074
1075 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1076                                 struct amdgpu_bo_va_mapping *mapping,
1077                                 uint64_t *flags)
1078 {
1079         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1080         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1081
1082         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1083         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1084
1085         if (mapping->flags & AMDGPU_PTE_PRT) {
1086                 *flags |= AMDGPU_PTE_PRT;
1087                 *flags &= ~AMDGPU_PTE_VALID;
1088         }
1089
1090         if ((adev->asic_type == CHIP_ARCTURUS ||
1091             adev->asic_type == CHIP_ALDEBARAN) &&
1092             !(*flags & AMDGPU_PTE_SYSTEM) &&
1093             mapping->bo_va->is_xgmi)
1094                 *flags |= AMDGPU_PTE_SNOOPED;
1095
1096         if (adev->asic_type == CHIP_ALDEBARAN)
1097                 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED;
1098 }
1099
1100 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1101 {
1102         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1103         unsigned size;
1104
1105         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1106                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1107         } else {
1108                 u32 viewport;
1109
1110                 switch (adev->asic_type) {
1111                 case CHIP_RAVEN:
1112                 case CHIP_RENOIR:
1113                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1114                         size = (REG_GET_FIELD(viewport,
1115                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1116                                 REG_GET_FIELD(viewport,
1117                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1118                                 4);
1119                         break;
1120                 case CHIP_VEGA10:
1121                 case CHIP_VEGA12:
1122                 case CHIP_VEGA20:
1123                 default:
1124                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1125                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1126                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1127                                 4);
1128                         break;
1129                 }
1130         }
1131
1132         return size;
1133 }
1134
1135 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1136         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1137         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1138         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1139         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1140         .map_mtype = gmc_v9_0_map_mtype,
1141         .get_vm_pde = gmc_v9_0_get_vm_pde,
1142         .get_vm_pte = gmc_v9_0_get_vm_pte,
1143         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1144 };
1145
1146 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1147 {
1148         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1149 }
1150
1151 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1152 {
1153         switch (adev->asic_type) {
1154         case CHIP_VEGA10:
1155                 adev->umc.funcs = &umc_v6_0_funcs;
1156                 break;
1157         case CHIP_VEGA20:
1158                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1159                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1160                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1161                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1162                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1163                 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1164                 break;
1165         case CHIP_ARCTURUS:
1166                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1167                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1168                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1169                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1170                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1171                 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1172                 break;
1173         case CHIP_ALDEBARAN:
1174                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
1175                 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1176                 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1177                 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1178                 if (!adev->gmc.xgmi.connected_to_cpu)
1179                         adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
1180                 if (1 & adev->smuio.funcs->get_die_id(adev))
1181                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1182                 else
1183                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1184                 break;
1185         default:
1186                 break;
1187         }
1188 }
1189
1190 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1191 {
1192         switch (adev->asic_type) {
1193         case CHIP_ARCTURUS:
1194                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1195                 break;
1196         case CHIP_ALDEBARAN:
1197                 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1198                 break;
1199         default:
1200                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1201                 break;
1202         }
1203 }
1204
1205 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1206 {
1207         switch (adev->asic_type) {
1208         case CHIP_VEGA20:
1209                 adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs;
1210                 break;
1211         case CHIP_ARCTURUS:
1212                 adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs;
1213                 break;
1214         case CHIP_ALDEBARAN:
1215                 adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs;
1216                 break;
1217         default:
1218                 /* mmhub ras is not available */
1219                 break;
1220         }
1221 }
1222
1223 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1224 {
1225         adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1226 }
1227
1228 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1229 {
1230         adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs;
1231 }
1232
1233 static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev)
1234 {
1235         switch (adev->asic_type) {
1236         case CHIP_ALDEBARAN:
1237                 if (!adev->gmc.xgmi.connected_to_cpu)
1238                         adev->mca.funcs = &mca_v3_0_funcs;
1239                 break;
1240         default:
1241                 break;
1242         }
1243 }
1244
1245 static int gmc_v9_0_early_init(void *handle)
1246 {
1247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1248
1249         if (adev->asic_type == CHIP_VEGA20 ||
1250             adev->asic_type == CHIP_ARCTURUS)
1251                 adev->gmc.xgmi.supported = true;
1252
1253         if (adev->asic_type == CHIP_ALDEBARAN) {
1254                 adev->gmc.xgmi.supported = true;
1255                 adev->gmc.xgmi.connected_to_cpu =
1256                         adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1257         }
1258
1259         gmc_v9_0_set_gmc_funcs(adev);
1260         gmc_v9_0_set_irq_funcs(adev);
1261         gmc_v9_0_set_umc_funcs(adev);
1262         gmc_v9_0_set_mmhub_funcs(adev);
1263         gmc_v9_0_set_mmhub_ras_funcs(adev);
1264         gmc_v9_0_set_gfxhub_funcs(adev);
1265         gmc_v9_0_set_hdp_ras_funcs(adev);
1266         gmc_v9_0_set_mca_funcs(adev);
1267
1268         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1269         adev->gmc.shared_aperture_end =
1270                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1271         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1272         adev->gmc.private_aperture_end =
1273                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1274
1275         return 0;
1276 }
1277
1278 static int gmc_v9_0_late_init(void *handle)
1279 {
1280         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281         int r;
1282
1283         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1284         if (r)
1285                 return r;
1286
1287         /*
1288          * Workaround performance drop issue with VBIOS enables partial
1289          * writes, while disables HBM ECC for vega10.
1290          */
1291         if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
1292                 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1293                         if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
1294                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1295                 }
1296         }
1297
1298         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1299                 if (adev->mmhub.ras_funcs &&
1300                     adev->mmhub.ras_funcs->reset_ras_error_count)
1301                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
1302
1303                 if (adev->hdp.ras_funcs &&
1304                     adev->hdp.ras_funcs->reset_ras_error_count)
1305                         adev->hdp.ras_funcs->reset_ras_error_count(adev);
1306         }
1307
1308         r = amdgpu_gmc_ras_late_init(adev);
1309         if (r)
1310                 return r;
1311
1312         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1313 }
1314
1315 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1316                                         struct amdgpu_gmc *mc)
1317 {
1318         u64 base = adev->mmhub.funcs->get_fb_location(adev);
1319
1320         /* add the xgmi offset of the physical node */
1321         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1322         if (adev->gmc.xgmi.connected_to_cpu) {
1323                 amdgpu_gmc_sysvm_location(adev, mc);
1324         } else {
1325                 amdgpu_gmc_vram_location(adev, mc, base);
1326                 amdgpu_gmc_gart_location(adev, mc);
1327                 amdgpu_gmc_agp_location(adev, mc);
1328         }
1329         /* base offset of vram pages */
1330         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1331
1332         /* XXX: add the xgmi offset of the physical node? */
1333         adev->vm_manager.vram_base_offset +=
1334                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1335 }
1336
1337 /**
1338  * gmc_v9_0_mc_init - initialize the memory controller driver params
1339  *
1340  * @adev: amdgpu_device pointer
1341  *
1342  * Look up the amount of vram, vram width, and decide how to place
1343  * vram and gart within the GPU's physical address space.
1344  * Returns 0 for success.
1345  */
1346 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1347 {
1348         int r;
1349
1350         /* size in MB on si */
1351         adev->gmc.mc_vram_size =
1352                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1353         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1354
1355         if (!(adev->flags & AMD_IS_APU) &&
1356             !adev->gmc.xgmi.connected_to_cpu) {
1357                 r = amdgpu_device_resize_fb_bar(adev);
1358                 if (r)
1359                         return r;
1360         }
1361         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1362         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1363
1364 #ifdef CONFIG_X86_64
1365         /*
1366          * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1367          * interface can use VRAM through here as it appears system reserved
1368          * memory in host address space.
1369          *
1370          * For APUs, VRAM is just the stolen system memory and can be accessed
1371          * directly.
1372          *
1373          * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1374          */
1375
1376         /* check whether both host-gpu and gpu-gpu xgmi links exist */
1377         if ((adev->flags & AMD_IS_APU) ||
1378             (adev->gmc.xgmi.supported &&
1379              adev->gmc.xgmi.connected_to_cpu)) {
1380                 adev->gmc.aper_base =
1381                         adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1382                         adev->gmc.xgmi.physical_node_id *
1383                         adev->gmc.xgmi.node_segment_size;
1384                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1385         }
1386
1387 #endif
1388         /* In case the PCI BAR is larger than the actual amount of vram */
1389         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1390         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1391                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1392
1393         /* set the gart size */
1394         if (amdgpu_gart_size == -1) {
1395                 switch (adev->asic_type) {
1396                 case CHIP_VEGA10:  /* all engines support GPUVM */
1397                 case CHIP_VEGA12:  /* all engines support GPUVM */
1398                 case CHIP_VEGA20:
1399                 case CHIP_ARCTURUS:
1400                 case CHIP_ALDEBARAN:
1401                 default:
1402                         adev->gmc.gart_size = 512ULL << 20;
1403                         break;
1404                 case CHIP_RAVEN:   /* DCE SG support */
1405                 case CHIP_RENOIR:
1406                         adev->gmc.gart_size = 1024ULL << 20;
1407                         break;
1408                 }
1409         } else {
1410                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1411         }
1412
1413         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1414
1415         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1416
1417         return 0;
1418 }
1419
1420 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1421 {
1422         int r;
1423
1424         if (adev->gart.bo) {
1425                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1426                 return 0;
1427         }
1428
1429         if (adev->gmc.xgmi.connected_to_cpu) {
1430                 adev->gmc.vmid0_page_table_depth = 1;
1431                 adev->gmc.vmid0_page_table_block_size = 12;
1432         } else {
1433                 adev->gmc.vmid0_page_table_depth = 0;
1434                 adev->gmc.vmid0_page_table_block_size = 0;
1435         }
1436
1437         /* Initialize common gart structure */
1438         r = amdgpu_gart_init(adev);
1439         if (r)
1440                 return r;
1441         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1442         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1443                                  AMDGPU_PTE_EXECUTABLE;
1444
1445         r = amdgpu_gart_table_vram_alloc(adev);
1446         if (r)
1447                 return r;
1448
1449         if (adev->gmc.xgmi.connected_to_cpu) {
1450                 r = amdgpu_gmc_pdb0_alloc(adev);
1451         }
1452
1453         return r;
1454 }
1455
1456 /**
1457  * gmc_v9_0_save_registers - saves regs
1458  *
1459  * @adev: amdgpu_device pointer
1460  *
1461  * This saves potential register values that should be
1462  * restored upon resume
1463  */
1464 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1465 {
1466         if (adev->asic_type == CHIP_RAVEN)
1467                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1468 }
1469
1470 static int gmc_v9_0_sw_init(void *handle)
1471 {
1472         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1473         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1474
1475         adev->gfxhub.funcs->init(adev);
1476
1477         adev->mmhub.funcs->init(adev);
1478         if (adev->mca.funcs)
1479                 adev->mca.funcs->init(adev);
1480
1481         spin_lock_init(&adev->gmc.invalidate_lock);
1482
1483         r = amdgpu_atomfirmware_get_vram_info(adev,
1484                 &vram_width, &vram_type, &vram_vendor);
1485         if (amdgpu_sriov_vf(adev))
1486                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1487                  * and DF related registers is not readable, seems hardcord is the
1488                  * only way to set the correct vram_width
1489                  */
1490                 adev->gmc.vram_width = 2048;
1491         else if (amdgpu_emu_mode != 1)
1492                 adev->gmc.vram_width = vram_width;
1493
1494         if (!adev->gmc.vram_width) {
1495                 int chansize, numchan;
1496
1497                 /* hbm memory channel size */
1498                 if (adev->flags & AMD_IS_APU)
1499                         chansize = 64;
1500                 else
1501                         chansize = 128;
1502
1503                 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1504                 adev->gmc.vram_width = numchan * chansize;
1505         }
1506
1507         adev->gmc.vram_type = vram_type;
1508         adev->gmc.vram_vendor = vram_vendor;
1509         switch (adev->asic_type) {
1510         case CHIP_RAVEN:
1511                 adev->num_vmhubs = 2;
1512
1513                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1514                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1515                 } else {
1516                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1517                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1518                         adev->gmc.translate_further =
1519                                 adev->vm_manager.num_level > 1;
1520                 }
1521                 break;
1522         case CHIP_VEGA10:
1523         case CHIP_VEGA12:
1524         case CHIP_VEGA20:
1525         case CHIP_RENOIR:
1526         case CHIP_ALDEBARAN:
1527                 adev->num_vmhubs = 2;
1528
1529
1530                 /*
1531                  * To fulfill 4-level page support,
1532                  * vm size is 256TB (48bit), maximum size of Vega10,
1533                  * block size 512 (9bit)
1534                  */
1535                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1536                 if (amdgpu_sriov_vf(adev))
1537                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1538                 else
1539                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1540                 break;
1541         case CHIP_ARCTURUS:
1542                 adev->num_vmhubs = 3;
1543
1544                 /* Keep the vm size same with Vega20 */
1545                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1546                 break;
1547         default:
1548                 break;
1549         }
1550
1551         /* This interrupt is VMC page fault.*/
1552         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1553                                 &adev->gmc.vm_fault);
1554         if (r)
1555                 return r;
1556
1557         if (adev->asic_type == CHIP_ARCTURUS) {
1558                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1559                                         &adev->gmc.vm_fault);
1560                 if (r)
1561                         return r;
1562         }
1563
1564         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1565                                 &adev->gmc.vm_fault);
1566
1567         if (r)
1568                 return r;
1569
1570         if (!amdgpu_sriov_vf(adev) &&
1571             !adev->gmc.xgmi.connected_to_cpu) {
1572                 /* interrupt sent to DF. */
1573                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1574                                       &adev->gmc.ecc_irq);
1575                 if (r)
1576                         return r;
1577         }
1578
1579         /* Set the internal MC address mask
1580          * This is the max address of the GPU's
1581          * internal address space.
1582          */
1583         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1584
1585         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1586         if (r) {
1587                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1588                 return r;
1589         }
1590         adev->need_swiotlb = drm_need_swiotlb(44);
1591
1592         if (adev->gmc.xgmi.supported) {
1593                 r = adev->gfxhub.funcs->get_xgmi_info(adev);
1594                 if (r)
1595                         return r;
1596         }
1597
1598         r = gmc_v9_0_mc_init(adev);
1599         if (r)
1600                 return r;
1601
1602         amdgpu_gmc_get_vbios_allocations(adev);
1603
1604         /* Memory manager */
1605         r = amdgpu_bo_init(adev);
1606         if (r)
1607                 return r;
1608
1609         r = gmc_v9_0_gart_init(adev);
1610         if (r)
1611                 return r;
1612
1613         /*
1614          * number of VMs
1615          * VMID 0 is reserved for System
1616          * amdgpu graphics/compute will use VMIDs 1..n-1
1617          * amdkfd will use VMIDs n..15
1618          *
1619          * The first KFD VMID is 8 for GPUs with graphics, 3 for
1620          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1621          * for video processing.
1622          */
1623         adev->vm_manager.first_kfd_vmid =
1624                 (adev->asic_type == CHIP_ARCTURUS ||
1625                  adev->asic_type == CHIP_ALDEBARAN) ? 3 : 8;
1626
1627         amdgpu_vm_manager_init(adev);
1628
1629         gmc_v9_0_save_registers(adev);
1630
1631         return 0;
1632 }
1633
1634 static int gmc_v9_0_sw_fini(void *handle)
1635 {
1636         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1637
1638         amdgpu_gmc_ras_fini(adev);
1639         amdgpu_gem_force_release(adev);
1640         amdgpu_vm_manager_fini(adev);
1641         amdgpu_gart_table_vram_free(adev);
1642         amdgpu_bo_unref(&adev->gmc.pdb0_bo);
1643         amdgpu_bo_fini(adev);
1644
1645         return 0;
1646 }
1647
1648 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1649 {
1650
1651         switch (adev->asic_type) {
1652         case CHIP_VEGA10:
1653                 if (amdgpu_sriov_vf(adev))
1654                         break;
1655                 fallthrough;
1656         case CHIP_VEGA20:
1657                 soc15_program_register_sequence(adev,
1658                                                 golden_settings_mmhub_1_0_0,
1659                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1660                 soc15_program_register_sequence(adev,
1661                                                 golden_settings_athub_1_0_0,
1662                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1663                 break;
1664         case CHIP_VEGA12:
1665                 break;
1666         case CHIP_RAVEN:
1667                 /* TODO for renoir */
1668                 soc15_program_register_sequence(adev,
1669                                                 golden_settings_athub_1_0_0,
1670                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1671                 break;
1672         default:
1673                 break;
1674         }
1675 }
1676
1677 /**
1678  * gmc_v9_0_restore_registers - restores regs
1679  *
1680  * @adev: amdgpu_device pointer
1681  *
1682  * This restores register values, saved at suspend.
1683  */
1684 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1685 {
1686         if (adev->asic_type == CHIP_RAVEN) {
1687                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1688                 WARN_ON(adev->gmc.sdpif_register !=
1689                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
1690         }
1691 }
1692
1693 /**
1694  * gmc_v9_0_gart_enable - gart enable
1695  *
1696  * @adev: amdgpu_device pointer
1697  */
1698 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1699 {
1700         int r;
1701
1702         if (adev->gmc.xgmi.connected_to_cpu)
1703                 amdgpu_gmc_init_pdb0(adev);
1704
1705         if (adev->gart.bo == NULL) {
1706                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1707                 return -EINVAL;
1708         }
1709
1710         r = amdgpu_gart_table_vram_pin(adev);
1711         if (r)
1712                 return r;
1713
1714         r = adev->gfxhub.funcs->gart_enable(adev);
1715         if (r)
1716                 return r;
1717
1718         r = adev->mmhub.funcs->gart_enable(adev);
1719         if (r)
1720                 return r;
1721
1722         DRM_INFO("PCIE GART of %uM enabled.\n",
1723                  (unsigned)(adev->gmc.gart_size >> 20));
1724         if (adev->gmc.pdb0_bo)
1725                 DRM_INFO("PDB0 located at 0x%016llX\n",
1726                                 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
1727         DRM_INFO("PTB located at 0x%016llX\n",
1728                         (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1729
1730         adev->gart.ready = true;
1731         return 0;
1732 }
1733
1734 static int gmc_v9_0_hw_init(void *handle)
1735 {
1736         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1737         bool value;
1738         int r, i;
1739
1740         /* The sequence of these two function calls matters.*/
1741         gmc_v9_0_init_golden_registers(adev);
1742
1743         if (adev->mode_info.num_crtc) {
1744                 /* Lockout access through VGA aperture*/
1745                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1746                 /* disable VGA render */
1747                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1748         }
1749
1750         if (adev->mmhub.funcs->update_power_gating)
1751                 adev->mmhub.funcs->update_power_gating(adev, true);
1752
1753         adev->hdp.funcs->init_registers(adev);
1754
1755         /* After HDP is initialized, flush HDP.*/
1756         adev->hdp.funcs->flush_hdp(adev, NULL);
1757
1758         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1759                 value = false;
1760         else
1761                 value = true;
1762
1763         if (!amdgpu_sriov_vf(adev)) {
1764                 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1765                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1766         }
1767         for (i = 0; i < adev->num_vmhubs; ++i)
1768                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1769
1770         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1771                 adev->umc.funcs->init_registers(adev);
1772
1773         r = gmc_v9_0_gart_enable(adev);
1774
1775         return r;
1776 }
1777
1778 /**
1779  * gmc_v9_0_gart_disable - gart disable
1780  *
1781  * @adev: amdgpu_device pointer
1782  *
1783  * This disables all VM page table.
1784  */
1785 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1786 {
1787         adev->gfxhub.funcs->gart_disable(adev);
1788         adev->mmhub.funcs->gart_disable(adev);
1789         amdgpu_gart_table_vram_unpin(adev);
1790 }
1791
1792 static int gmc_v9_0_hw_fini(void *handle)
1793 {
1794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1795
1796         if (amdgpu_sriov_vf(adev)) {
1797                 /* full access mode, so don't touch any GMC register */
1798                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1799                 return 0;
1800         }
1801
1802         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1803         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1804         gmc_v9_0_gart_disable(adev);
1805
1806         return 0;
1807 }
1808
1809 static int gmc_v9_0_suspend(void *handle)
1810 {
1811         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1812
1813         return gmc_v9_0_hw_fini(adev);
1814 }
1815
1816 static int gmc_v9_0_resume(void *handle)
1817 {
1818         int r;
1819         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1820
1821         r = gmc_v9_0_hw_init(adev);
1822         if (r)
1823                 return r;
1824
1825         amdgpu_vmid_reset_all(adev);
1826
1827         return 0;
1828 }
1829
1830 static bool gmc_v9_0_is_idle(void *handle)
1831 {
1832         /* MC is always ready in GMC v9.*/
1833         return true;
1834 }
1835
1836 static int gmc_v9_0_wait_for_idle(void *handle)
1837 {
1838         /* There is no need to wait for MC idle in GMC v9.*/
1839         return 0;
1840 }
1841
1842 static int gmc_v9_0_soft_reset(void *handle)
1843 {
1844         /* XXX for emulation.*/
1845         return 0;
1846 }
1847
1848 static int gmc_v9_0_set_clockgating_state(void *handle,
1849                                         enum amd_clockgating_state state)
1850 {
1851         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1852
1853         adev->mmhub.funcs->set_clockgating(adev, state);
1854
1855         athub_v1_0_set_clockgating(adev, state);
1856
1857         return 0;
1858 }
1859
1860 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1861 {
1862         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1863
1864         adev->mmhub.funcs->get_clockgating(adev, flags);
1865
1866         athub_v1_0_get_clockgating(adev, flags);
1867 }
1868
1869 static int gmc_v9_0_set_powergating_state(void *handle,
1870                                         enum amd_powergating_state state)
1871 {
1872         return 0;
1873 }
1874
1875 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1876         .name = "gmc_v9_0",
1877         .early_init = gmc_v9_0_early_init,
1878         .late_init = gmc_v9_0_late_init,
1879         .sw_init = gmc_v9_0_sw_init,
1880         .sw_fini = gmc_v9_0_sw_fini,
1881         .hw_init = gmc_v9_0_hw_init,
1882         .hw_fini = gmc_v9_0_hw_fini,
1883         .suspend = gmc_v9_0_suspend,
1884         .resume = gmc_v9_0_resume,
1885         .is_idle = gmc_v9_0_is_idle,
1886         .wait_for_idle = gmc_v9_0_wait_for_idle,
1887         .soft_reset = gmc_v9_0_soft_reset,
1888         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1889         .set_powergating_state = gmc_v9_0_set_powergating_state,
1890         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1891 };
1892
1893 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1894 {
1895         .type = AMD_IP_BLOCK_TYPE_GMC,
1896         .major = 9,
1897         .minor = 0,
1898         .rev = 0,
1899         .funcs = &gmc_v9_0_ip_funcs,
1900 };