drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "mmhub_v1_7.h"
  54 #include "umc_v6_1.h"
  55 #include "umc_v6_0.h"
  56 #include "umc_v6_7.h"
  57 #include "hdp_v4_0.h"
  58 #include "mca_v3_0.h"
  59
  60 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  61
  62 #include "amdgpu_ras.h"
  63 #include "amdgpu_xgmi.h"
  64
  65 #include "amdgpu_reset.h"
  66
  67 /* add these here since we already include dce12 headers and these are for DCN */
  68 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  74 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  76
  77 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2                                                          0x05ea
  78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX                                                 2
  79
  80
  81 static const char *gfxhub_client_ids[] = {
  82         "CB",
  83         "DB",
  84         "IA",
  85         "WD",
  86         "CPF",
  87         "CPC",
  88         "CPG",
  89         "RLC",
  90         "TCP",
  91         "SQC (inst)",
  92         "SQC (data)",
  93         "SQG",
  94         "PA",
  95 };
  96
  97 static const char *mmhub_client_ids_raven[][2] = {
  98         [0][0] = "MP1",
  99         [1][0] = "MP0",
 100         [2][0] = "VCN",
 101         [3][0] = "VCNU",
 102         [4][0] = "HDP",
 103         [5][0] = "DCE",
 104         [13][0] = "UTCL2",
 105         [19][0] = "TLS",
 106         [26][0] = "OSS",
 107         [27][0] = "SDMA0",
 108         [0][1] = "MP1",
 109         [1][1] = "MP0",
 110         [2][1] = "VCN",
 111         [3][1] = "VCNU",
 112         [4][1] = "HDP",
 113         [5][1] = "XDP",
 114         [6][1] = "DBGU0",
 115         [7][1] = "DCE",
 116         [8][1] = "DCEDWB0",
 117         [9][1] = "DCEDWB1",
 118         [26][1] = "OSS",
 119         [27][1] = "SDMA0",
 120 };
 121
 122 static const char *mmhub_client_ids_renoir[][2] = {
 123         [0][0] = "MP1",
 124         [1][0] = "MP0",
 125         [2][0] = "HDP",
 126         [4][0] = "DCEDMC",
 127         [5][0] = "DCEVGA",
 128         [13][0] = "UTCL2",
 129         [19][0] = "TLS",
 130         [26][0] = "OSS",
 131         [27][0] = "SDMA0",
 132         [28][0] = "VCN",
 133         [29][0] = "VCNU",
 134         [30][0] = "JPEG",
 135         [0][1] = "MP1",
 136         [1][1] = "MP0",
 137         [2][1] = "HDP",
 138         [3][1] = "XDP",
 139         [6][1] = "DBGU0",
 140         [7][1] = "DCEDMC",
 141         [8][1] = "DCEVGA",
 142         [9][1] = "DCEDWB",
 143         [26][1] = "OSS",
 144         [27][1] = "SDMA0",
 145         [28][1] = "VCN",
 146         [29][1] = "VCNU",
 147         [30][1] = "JPEG",
 148 };
 149
 150 static const char *mmhub_client_ids_vega10[][2] = {
 151         [0][0] = "MP0",
 152         [1][0] = "UVD",
 153         [2][0] = "UVDU",
 154         [3][0] = "HDP",
 155         [13][0] = "UTCL2",
 156         [14][0] = "OSS",
 157         [15][0] = "SDMA1",
 158         [32+0][0] = "VCE0",
 159         [32+1][0] = "VCE0U",
 160         [32+2][0] = "XDMA",
 161         [32+3][0] = "DCE",
 162         [32+4][0] = "MP1",
 163         [32+14][0] = "SDMA0",
 164         [0][1] = "MP0",
 165         [1][1] = "UVD",
 166         [2][1] = "UVDU",
 167         [3][1] = "DBGU0",
 168         [4][1] = "HDP",
 169         [5][1] = "XDP",
 170         [14][1] = "OSS",
 171         [15][1] = "SDMA0",
 172         [32+0][1] = "VCE0",
 173         [32+1][1] = "VCE0U",
 174         [32+2][1] = "XDMA",
 175         [32+3][1] = "DCE",
 176         [32+4][1] = "DCEDWB",
 177         [32+5][1] = "MP1",
 178         [32+6][1] = "DBGU1",
 179         [32+14][1] = "SDMA1",
 180 };
 181
 182 static const char *mmhub_client_ids_vega12[][2] = {
 183         [0][0] = "MP0",
 184         [1][0] = "VCE0",
 185         [2][0] = "VCE0U",
 186         [3][0] = "HDP",
 187         [13][0] = "UTCL2",
 188         [14][0] = "OSS",
 189         [15][0] = "SDMA1",
 190         [32+0][0] = "DCE",
 191         [32+1][0] = "XDMA",
 192         [32+2][0] = "UVD",
 193         [32+3][0] = "UVDU",
 194         [32+4][0] = "MP1",
 195         [32+15][0] = "SDMA0",
 196         [0][1] = "MP0",
 197         [1][1] = "VCE0",
 198         [2][1] = "VCE0U",
 199         [3][1] = "DBGU0",
 200         [4][1] = "HDP",
 201         [5][1] = "XDP",
 202         [14][1] = "OSS",
 203         [15][1] = "SDMA0",
 204         [32+0][1] = "DCE",
 205         [32+1][1] = "DCEDWB",
 206         [32+2][1] = "XDMA",
 207         [32+3][1] = "UVD",
 208         [32+4][1] = "UVDU",
 209         [32+5][1] = "MP1",
 210         [32+6][1] = "DBGU1",
 211         [32+15][1] = "SDMA1",
 212 };
 213
 214 static const char *mmhub_client_ids_vega20[][2] = {
 215         [0][0] = "XDMA",
 216         [1][0] = "DCE",
 217         [2][0] = "VCE0",
 218         [3][0] = "VCE0U",
 219         [4][0] = "UVD",
 220         [5][0] = "UVD1U",
 221         [13][0] = "OSS",
 222         [14][0] = "HDP",
 223         [15][0] = "SDMA0",
 224         [32+0][0] = "UVD",
 225         [32+1][0] = "UVDU",
 226         [32+2][0] = "MP1",
 227         [32+3][0] = "MP0",
 228         [32+12][0] = "UTCL2",
 229         [32+14][0] = "SDMA1",
 230         [0][1] = "XDMA",
 231         [1][1] = "DCE",
 232         [2][1] = "DCEDWB",
 233         [3][1] = "VCE0",
 234         [4][1] = "VCE0U",
 235         [5][1] = "UVD1",
 236         [6][1] = "UVD1U",
 237         [7][1] = "DBGU0",
 238         [8][1] = "XDP",
 239         [13][1] = "OSS",
 240         [14][1] = "HDP",
 241         [15][1] = "SDMA0",
 242         [32+0][1] = "UVD",
 243         [32+1][1] = "UVDU",
 244         [32+2][1] = "DBGU1",
 245         [32+3][1] = "MP1",
 246         [32+4][1] = "MP0",
 247         [32+14][1] = "SDMA1",
 248 };
 249
 250 static const char *mmhub_client_ids_arcturus[][2] = {
 251         [0][0] = "DBGU1",
 252         [1][0] = "XDP",
 253         [2][0] = "MP1",
 254         [14][0] = "HDP",
 255         [171][0] = "JPEG",
 256         [172][0] = "VCN",
 257         [173][0] = "VCNU",
 258         [203][0] = "JPEG1",
 259         [204][0] = "VCN1",
 260         [205][0] = "VCN1U",
 261         [256][0] = "SDMA0",
 262         [257][0] = "SDMA1",
 263         [258][0] = "SDMA2",
 264         [259][0] = "SDMA3",
 265         [260][0] = "SDMA4",
 266         [261][0] = "SDMA5",
 267         [262][0] = "SDMA6",
 268         [263][0] = "SDMA7",
 269         [384][0] = "OSS",
 270         [0][1] = "DBGU1",
 271         [1][1] = "XDP",
 272         [2][1] = "MP1",
 273         [14][1] = "HDP",
 274         [171][1] = "JPEG",
 275         [172][1] = "VCN",
 276         [173][1] = "VCNU",
 277         [203][1] = "JPEG1",
 278         [204][1] = "VCN1",
 279         [205][1] = "VCN1U",
 280         [256][1] = "SDMA0",
 281         [257][1] = "SDMA1",
 282         [258][1] = "SDMA2",
 283         [259][1] = "SDMA3",
 284         [260][1] = "SDMA4",
 285         [261][1] = "SDMA5",
 286         [262][1] = "SDMA6",
 287         [263][1] = "SDMA7",
 288         [384][1] = "OSS",
 289 };
 290
 291 static const char *mmhub_client_ids_aldebaran[][2] = {
 292         [2][0] = "MP1",
 293         [3][0] = "MP0",
 294         [32+1][0] = "DBGU_IO0",
 295         [32+2][0] = "DBGU_IO2",
 296         [32+4][0] = "MPIO",
 297         [96+11][0] = "JPEG0",
 298         [96+12][0] = "VCN0",
 299         [96+13][0] = "VCNU0",
 300         [128+11][0] = "JPEG1",
 301         [128+12][0] = "VCN1",
 302         [128+13][0] = "VCNU1",
 303         [160+1][0] = "XDP",
 304         [160+14][0] = "HDP",
 305         [256+0][0] = "SDMA0",
 306         [256+1][0] = "SDMA1",
 307         [256+2][0] = "SDMA2",
 308         [256+3][0] = "SDMA3",
 309         [256+4][0] = "SDMA4",
 310         [384+0][0] = "OSS",
 311         [2][1] = "MP1",
 312         [3][1] = "MP0",
 313         [32+1][1] = "DBGU_IO0",
 314         [32+2][1] = "DBGU_IO2",
 315         [32+4][1] = "MPIO",
 316         [96+11][1] = "JPEG0",
 317         [96+12][1] = "VCN0",
 318         [96+13][1] = "VCNU0",
 319         [128+11][1] = "JPEG1",
 320         [128+12][1] = "VCN1",
 321         [128+13][1] = "VCNU1",
 322         [160+1][1] = "XDP",
 323         [160+14][1] = "HDP",
 324         [256+0][1] = "SDMA0",
 325         [256+1][1] = "SDMA1",
 326         [256+2][1] = "SDMA2",
 327         [256+3][1] = "SDMA3",
 328         [256+4][1] = "SDMA4",
 329         [384+0][1] = "OSS",
 330 };
 331
 332 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
 333 {
 334         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 335         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 336 };
 337
 338 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
 339 {
 340         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 341         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 342 };
 343
 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 345         (0x000143c0 + 0x00000000),
 346         (0x000143c0 + 0x00000800),
 347         (0x000143c0 + 0x00001000),
 348         (0x000143c0 + 0x00001800),
 349         (0x000543c0 + 0x00000000),
 350         (0x000543c0 + 0x00000800),
 351         (0x000543c0 + 0x00001000),
 352         (0x000543c0 + 0x00001800),
 353         (0x000943c0 + 0x00000000),
 354         (0x000943c0 + 0x00000800),
 355         (0x000943c0 + 0x00001000),
 356         (0x000943c0 + 0x00001800),
 357         (0x000d43c0 + 0x00000000),
 358         (0x000d43c0 + 0x00000800),
 359         (0x000d43c0 + 0x00001000),
 360         (0x000d43c0 + 0x00001800),
 361         (0x001143c0 + 0x00000000),
 362         (0x001143c0 + 0x00000800),
 363         (0x001143c0 + 0x00001000),
 364         (0x001143c0 + 0x00001800),
 365         (0x001543c0 + 0x00000000),
 366         (0x001543c0 + 0x00000800),
 367         (0x001543c0 + 0x00001000),
 368         (0x001543c0 + 0x00001800),
 369         (0x001943c0 + 0x00000000),
 370         (0x001943c0 + 0x00000800),
 371         (0x001943c0 + 0x00001000),
 372         (0x001943c0 + 0x00001800),
 373         (0x001d43c0 + 0x00000000),
 374         (0x001d43c0 + 0x00000800),
 375         (0x001d43c0 + 0x00001000),
 376         (0x001d43c0 + 0x00001800),
 377 };
 378
 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 380         (0x000143e0 + 0x00000000),
 381         (0x000143e0 + 0x00000800),
 382         (0x000143e0 + 0x00001000),
 383         (0x000143e0 + 0x00001800),
 384         (0x000543e0 + 0x00000000),
 385         (0x000543e0 + 0x00000800),
 386         (0x000543e0 + 0x00001000),
 387         (0x000543e0 + 0x00001800),
 388         (0x000943e0 + 0x00000000),
 389         (0x000943e0 + 0x00000800),
 390         (0x000943e0 + 0x00001000),
 391         (0x000943e0 + 0x00001800),
 392         (0x000d43e0 + 0x00000000),
 393         (0x000d43e0 + 0x00000800),
 394         (0x000d43e0 + 0x00001000),
 395         (0x000d43e0 + 0x00001800),
 396         (0x001143e0 + 0x00000000),
 397         (0x001143e0 + 0x00000800),
 398         (0x001143e0 + 0x00001000),
 399         (0x001143e0 + 0x00001800),
 400         (0x001543e0 + 0x00000000),
 401         (0x001543e0 + 0x00000800),
 402         (0x001543e0 + 0x00001000),
 403         (0x001543e0 + 0x00001800),
 404         (0x001943e0 + 0x00000000),
 405         (0x001943e0 + 0x00000800),
 406         (0x001943e0 + 0x00001000),
 407         (0x001943e0 + 0x00001800),
 408         (0x001d43e0 + 0x00000000),
 409         (0x001d43e0 + 0x00000800),
 410         (0x001d43e0 + 0x00001000),
 411         (0x001d43e0 + 0x00001800),
 412 };
 413
 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 415                 struct amdgpu_irq_src *src,
 416                 unsigned type,
 417                 enum amdgpu_interrupt_state state)
 418 {
 419         u32 bits, i, tmp, reg;
 420
 421         /* Devices newer then VEGA10/12 shall have these programming
 422              sequences performed by PSP BL */
 423         if (adev->asic_type >= CHIP_VEGA20)
 424                 return 0;
 425
 426         bits = 0x7f;
 427
 428         switch (state) {
 429         case AMDGPU_IRQ_STATE_DISABLE:
 430                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 431                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 432                         tmp = RREG32(reg);
 433                         tmp &= ~bits;
 434                         WREG32(reg, tmp);
 435                 }
 436                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 437                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 438                         tmp = RREG32(reg);
 439                         tmp &= ~bits;
 440                         WREG32(reg, tmp);
 441                 }
 442                 break;
 443         case AMDGPU_IRQ_STATE_ENABLE:
 444                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 445                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 446                         tmp = RREG32(reg);
 447                         tmp |= bits;
 448                         WREG32(reg, tmp);
 449                 }
 450                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 451                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 452                         tmp = RREG32(reg);
 453                         tmp |= bits;
 454                         WREG32(reg, tmp);
 455                 }
 456                 break;
 457         default:
 458                 break;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 465                                         struct amdgpu_irq_src *src,
 466                                         unsigned type,
 467                                         enum amdgpu_interrupt_state state)
 468 {
 469         struct amdgpu_vmhub *hub;
 470         u32 tmp, reg, bits, i, j;
 471
 472         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 473                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 474                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 475                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 476                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 477                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 478                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 479
 480         switch (state) {
 481         case AMDGPU_IRQ_STATE_DISABLE:
 482                 for (j = 0; j < adev->num_vmhubs; j++) {
 483                         hub = &adev->vmhub[j];
 484                         for (i = 0; i < 16; i++) {
 485                                 reg = hub->vm_context0_cntl + i;
 486
 487                                 if (j == AMDGPU_GFXHUB_0)
 488                                         tmp = RREG32_SOC15_IP(GC, reg);
 489                                 else
 490                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 491
 492                                 tmp &= ~bits;
 493
 494                                 if (j == AMDGPU_GFXHUB_0)
 495                                         WREG32_SOC15_IP(GC, reg, tmp);
 496                                 else
 497                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 498                         }
 499                 }
 500                 break;
 501         case AMDGPU_IRQ_STATE_ENABLE:
 502                 for (j = 0; j < adev->num_vmhubs; j++) {
 503                         hub = &adev->vmhub[j];
 504                         for (i = 0; i < 16; i++) {
 505                                 reg = hub->vm_context0_cntl + i;
 506
 507                                 if (j == AMDGPU_GFXHUB_0)
 508                                         tmp = RREG32_SOC15_IP(GC, reg);
 509                                 else
 510                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 511
 512                                 tmp |= bits;
 513
 514                                 if (j == AMDGPU_GFXHUB_0)
 515                                         WREG32_SOC15_IP(GC, reg, tmp);
 516                                 else
 517                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 518                         }
 519                 }
 520                 break;
 521         default:
 522                 break;
 523         }
 524
 525         return 0;
 526 }
 527
 528 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 529                                       struct amdgpu_irq_src *source,
 530                                       struct amdgpu_iv_entry *entry)
 531 {
 532         bool retry_fault = !!(entry->src_data[1] & 0x80);
 533         bool write_fault = !!(entry->src_data[1] & 0x20);
 534         uint32_t status = 0, cid = 0, rw = 0;
 535         struct amdgpu_task_info task_info;
 536         struct amdgpu_vmhub *hub;
 537         const char *mmhub_cid;
 538         const char *hub_name;
 539         u64 addr;
 540
 541         addr = (u64)entry->src_data[0] << 12;
 542         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 543
 544         if (retry_fault) {
 545                 /* Returning 1 here also prevents sending the IV to the KFD */
 546
 547                 /* Process it onyl if it's the first fault for this address */
 548                 if (entry->ih != &adev->irq.ih_soft &&
 549                     amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
 550                                              entry->timestamp))
 551                         return 1;
 552
 553                 /* Delegate it to a different ring if the hardware hasn't
 554                  * already done it.
 555                  */
 556                 if (entry->ih == &adev->irq.ih) {
 557                         amdgpu_irq_delegate(adev, entry, 8);
 558                         return 1;
 559                 }
 560
 561                 /* Try to handle the recoverable page faults by filling page
 562                  * tables
 563                  */
 564                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
 565                         return 1;
 566         }
 567
 568         if (!printk_ratelimit())
 569                 return 0;
 570
 571         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 572                 hub_name = "mmhub0";
 573                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 574         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 575                 hub_name = "mmhub1";
 576                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 577         } else {
 578                 hub_name = "gfxhub0";
 579                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 580         }
 581
 582         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 583         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 584
 585         dev_err(adev->dev,
 586                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 587                 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 588                 hub_name, retry_fault ? "retry" : "no-retry",
 589                 entry->src_id, entry->ring_id, entry->vmid,
 590                 entry->pasid, task_info.process_name, task_info.tgid,
 591                 task_info.task_name, task_info.pid);
 592         dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
 593                 addr, entry->client_id,
 594                 soc15_ih_clientid_name[entry->client_id]);
 595
 596         if (amdgpu_sriov_vf(adev))
 597                 return 0;
 598
 599         /*
 600          * Issue a dummy read to wait for the status register to
 601          * be updated to avoid reading an incorrect value due to
 602          * the new fast GRBM interface.
 603          */
 604         if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 605             (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2)))
 606                 RREG32(hub->vm_l2_pro_fault_status);
 607
 608         status = RREG32(hub->vm_l2_pro_fault_status);
 609         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 610         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 611         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 612
 613
 614         dev_err(adev->dev,
 615                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 616                 status);
 617         if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
 618                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 619                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 620                         gfxhub_client_ids[cid],
 621                         cid);
 622         } else {
 623                 switch (adev->ip_versions[MMHUB_HWIP][0]) {
 624                 case IP_VERSION(9, 0, 0):
 625                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 626                         break;
 627                 case IP_VERSION(9, 3, 0):
 628                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 629                         break;
 630                 case IP_VERSION(9, 4, 0):
 631                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 632                         break;
 633                 case IP_VERSION(9, 4, 1):
 634                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 635                         break;
 636                 case IP_VERSION(9, 1, 0):
 637                 case IP_VERSION(9, 2, 0):
 638                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 639                         break;
 640                 case IP_VERSION(1, 5, 0):
 641                 case IP_VERSION(2, 4, 0):
 642                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 643                         break;
 644                 case IP_VERSION(9, 4, 2):
 645                         mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
 646                         break;
 647                 default:
 648                         mmhub_cid = NULL;
 649                         break;
 650                 }
 651                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 652                         mmhub_cid ? mmhub_cid : "unknown", cid);
 653         }
 654         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 655                 REG_GET_FIELD(status,
 656                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 657         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 658                 REG_GET_FIELD(status,
 659                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 660         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 661                 REG_GET_FIELD(status,
 662                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 663         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 664                 REG_GET_FIELD(status,
 665                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 666         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 667         return 0;
 668 }
 669
 670 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 671         .set = gmc_v9_0_vm_fault_interrupt_state,
 672         .process = gmc_v9_0_process_interrupt,
 673 };
 674
 675
 676 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 677         .set = gmc_v9_0_ecc_interrupt_state,
 678         .process = amdgpu_umc_process_ecc_irq,
 679 };
 680
 681 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 682 {
 683         adev->gmc.vm_fault.num_types = 1;
 684         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 685
 686         if (!amdgpu_sriov_vf(adev) &&
 687             !adev->gmc.xgmi.connected_to_cpu) {
 688                 adev->gmc.ecc_irq.num_types = 1;
 689                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 690         }
 691 }
 692
 693 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 694                                         uint32_t flush_type)
 695 {
 696         u32 req = 0;
 697
 698         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 699                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 700         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 701         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 702         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 703         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 704         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 705         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 706         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 707                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 708
 709         return req;
 710 }
 711
 712 /**
 713  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 714  *
 715  * @adev: amdgpu_device pointer
 716  * @vmhub: vmhub type
 717  *
 718  */
 719 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 720                                        uint32_t vmhub)
 721 {
 722         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
 723                 return false;
 724
 725         return ((vmhub == AMDGPU_MMHUB_0 ||
 726                  vmhub == AMDGPU_MMHUB_1) &&
 727                 (!amdgpu_sriov_vf(adev)) &&
 728                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 729                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 730 }
 731
 732 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 733                                         uint8_t vmid, uint16_t *p_pasid)
 734 {
 735         uint32_t value;
 736
 737         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 738                      + vmid);
 739         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 740
 741         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 742 }
 743
 744 /*
 745  * GART
 746  * VMID 0 is the physical GPU addresses as used by the kernel.
 747  * VMIDs 1-15 are used for userspace clients and are handled
 748  * by the amdgpu vm/hsa code.
 749  */
 750
 751 /**
 752  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 753  *
 754  * @adev: amdgpu_device pointer
 755  * @vmid: vm instance to flush
 756  * @vmhub: which hub to flush
 757  * @flush_type: the flush type
 758  *
 759  * Flush the TLB for the requested page table using certain type.
 760  */
 761 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 762                                         uint32_t vmhub, uint32_t flush_type)
 763 {
 764         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 765         const unsigned eng = 17;
 766         u32 j, inv_req, inv_req2, tmp;
 767         struct amdgpu_vmhub *hub;
 768
 769         BUG_ON(vmhub >= adev->num_vmhubs);
 770
 771         hub = &adev->vmhub[vmhub];
 772         if (adev->gmc.xgmi.num_physical_nodes &&
 773             adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) {
 774                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 775                  * heavy-weight TLB flush (type 2), which flushes
 776                  * both. Due to a race condition with concurrent
 777                  * memory accesses using the same TLB cache line, we
 778                  * still need a second TLB flush after this.
 779                  */
 780                 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
 781                 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 782         } else {
 783                 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 784                 inv_req2 = 0;
 785         }
 786
 787         /* This is necessary for a HW workaround under SRIOV as well
 788          * as GFXOFF under bare metal
 789          */
 790         if (adev->gfx.kiq.ring.sched.ready &&
 791             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 792             down_read_trylock(&adev->reset_domain->sem)) {
 793                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 794                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 795
 796                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 797                                                    1 << vmid);
 798                 up_read(&adev->reset_domain->sem);
 799                 return;
 800         }
 801
 802         spin_lock(&adev->gmc.invalidate_lock);
 803
 804         /*
 805          * It may lose gpuvm invalidate acknowldege state across power-gating
 806          * off cycle, add semaphore acquire before invalidation and semaphore
 807          * release after invalidation to avoid entering power gated state
 808          * to WA the Issue
 809          */
 810
 811         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 812         if (use_semaphore) {
 813                 for (j = 0; j < adev->usec_timeout; j++) {
 814                         /* a read return value of 1 means semaphore acquire */
 815                         if (vmhub == AMDGPU_GFXHUB_0)
 816                                 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
 817                         else
 818                                 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
 819
 820                         if (tmp & 0x1)
 821                                 break;
 822                         udelay(1);
 823                 }
 824
 825                 if (j >= adev->usec_timeout)
 826                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 827         }
 828
 829         do {
 830                 if (vmhub == AMDGPU_GFXHUB_0)
 831                         WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
 832                 else
 833                         WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
 834
 835                 /*
 836                  * Issue a dummy read to wait for the ACK register to
 837                  * be cleared to avoid a false ACK due to the new fast
 838                  * GRBM interface.
 839                  */
 840                 if ((vmhub == AMDGPU_GFXHUB_0) &&
 841                     (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2)))
 842                         RREG32_NO_KIQ(hub->vm_inv_eng0_req +
 843                                       hub->eng_distance * eng);
 844
 845                 for (j = 0; j < adev->usec_timeout; j++) {
 846                         if (vmhub == AMDGPU_GFXHUB_0)
 847                                 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
 848                         else
 849                                 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
 850
 851                         if (tmp & (1 << vmid))
 852                                 break;
 853                         udelay(1);
 854                 }
 855
 856                 inv_req = inv_req2;
 857                 inv_req2 = 0;
 858         } while (inv_req);
 859
 860         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 861         if (use_semaphore) {
 862                 /*
 863                  * add semaphore release after invalidation,
 864                  * write with 0 means semaphore release
 865                  */
 866                 if (vmhub == AMDGPU_GFXHUB_0)
 867                         WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
 868                 else
 869                         WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
 870         }
 871
 872         spin_unlock(&adev->gmc.invalidate_lock);
 873
 874         if (j < adev->usec_timeout)
 875                 return;
 876
 877         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 878 }
 879
 880 /**
 881  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 882  *
 883  * @adev: amdgpu_device pointer
 884  * @pasid: pasid to be flush
 885  * @flush_type: the flush type
 886  * @all_hub: flush all hubs
 887  *
 888  * Flush the TLB for the requested pasid.
 889  */
 890 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 891                                         uint16_t pasid, uint32_t flush_type,
 892                                         bool all_hub)
 893 {
 894         int vmid, i;
 895         signed long r;
 896         uint32_t seq;
 897         uint16_t queried_pasid;
 898         bool ret;
 899         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 900         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 901
 902         if (amdgpu_in_reset(adev))
 903                 return -EIO;
 904
 905         if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) {
 906                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 907                  * heavy-weight TLB flush (type 2), which flushes
 908                  * both. Due to a race condition with concurrent
 909                  * memory accesses using the same TLB cache line, we
 910                  * still need a second TLB flush after this.
 911                  */
 912                 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
 913                                        adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0));
 914                 /* 2 dwords flush + 8 dwords fence */
 915                 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
 916
 917                 if (vega20_xgmi_wa)
 918                         ndw += kiq->pmf->invalidate_tlbs_size;
 919
 920                 spin_lock(&adev->gfx.kiq.ring_lock);
 921                 /* 2 dwords flush + 8 dwords fence */
 922                 amdgpu_ring_alloc(ring, ndw);
 923                 if (vega20_xgmi_wa)
 924                         kiq->pmf->kiq_invalidate_tlbs(ring,
 925                                                       pasid, 2, all_hub);
 926                 kiq->pmf->kiq_invalidate_tlbs(ring,
 927                                         pasid, flush_type, all_hub);
 928                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 929                 if (r) {
 930                         amdgpu_ring_undo(ring);
 931                         spin_unlock(&adev->gfx.kiq.ring_lock);
 932                         up_read(&adev->reset_domain->sem);
 933                         return -ETIME;
 934                 }
 935
 936                 amdgpu_ring_commit(ring);
 937                 spin_unlock(&adev->gfx.kiq.ring_lock);
 938                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 939                 if (r < 1) {
 940                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 941                         up_read(&adev->reset_domain->sem);
 942                         return -ETIME;
 943                 }
 944                 up_read(&adev->reset_domain->sem);
 945                 return 0;
 946         }
 947
 948         for (vmid = 1; vmid < 16; vmid++) {
 949
 950                 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 951                                 &queried_pasid);
 952                 if (ret && queried_pasid == pasid) {
 953                         if (all_hub) {
 954                                 for (i = 0; i < adev->num_vmhubs; i++)
 955                                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 956                                                         i, flush_type);
 957                         } else {
 958                                 gmc_v9_0_flush_gpu_tlb(adev, vmid,
 959                                                 AMDGPU_GFXHUB_0, flush_type);
 960                         }
 961                         break;
 962                 }
 963         }
 964
 965         return 0;
 966
 967 }
 968
 969 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 970                                             unsigned vmid, uint64_t pd_addr)
 971 {
 972         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 973         struct amdgpu_device *adev = ring->adev;
 974         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 975         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 976         unsigned eng = ring->vm_inv_eng;
 977
 978         /*
 979          * It may lose gpuvm invalidate acknowldege state across power-gating
 980          * off cycle, add semaphore acquire before invalidation and semaphore
 981          * release after invalidation to avoid entering power gated state
 982          * to WA the Issue
 983          */
 984
 985         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 986         if (use_semaphore)
 987                 /* a read return value of 1 means semaphore acuqire */
 988                 amdgpu_ring_emit_reg_wait(ring,
 989                                           hub->vm_inv_eng0_sem +
 990                                           hub->eng_distance * eng, 0x1, 0x1);
 991
 992         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 993                               (hub->ctx_addr_distance * vmid),
 994                               lower_32_bits(pd_addr));
 995
 996         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 997                               (hub->ctx_addr_distance * vmid),
 998                               upper_32_bits(pd_addr));
 999
1000         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
1001                                             hub->eng_distance * eng,
1002                                             hub->vm_inv_eng0_ack +
1003                                             hub->eng_distance * eng,
1004                                             req, 1 << vmid);
1005
1006         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1007         if (use_semaphore)
1008                 /*
1009                  * add semaphore release after invalidation,
1010                  * write with 0 means semaphore release
1011                  */
1012                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
1013                                       hub->eng_distance * eng, 0);
1014
1015         return pd_addr;
1016 }
1017
1018 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
1019                                         unsigned pasid)
1020 {
1021         struct amdgpu_device *adev = ring->adev;
1022         uint32_t reg;
1023
1024         /* Do nothing because there's no lut register for mmhub1. */
1025         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
1026                 return;
1027
1028         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
1029                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1030         else
1031                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1032
1033         amdgpu_ring_emit_wreg(ring, reg, pasid);
1034 }
1035
1036 /*
1037  * PTE format on VEGA 10:
1038  * 63:59 reserved
1039  * 58:57 mtype
1040  * 56 F
1041  * 55 L
1042  * 54 P
1043  * 53 SW
1044  * 52 T
1045  * 50:48 reserved
1046  * 47:12 4k physical page base address
1047  * 11:7 fragment
1048  * 6 write
1049  * 5 read
1050  * 4 exe
1051  * 3 Z
1052  * 2 snooped
1053  * 1 system
1054  * 0 valid
1055  *
1056  * PDE format on VEGA 10:
1057  * 63:59 block fragment size
1058  * 58:55 reserved
1059  * 54 P
1060  * 53:48 reserved
1061  * 47:6 physical base address of PD or PTE
1062  * 5:3 reserved
1063  * 2 C
1064  * 1 system
1065  * 0 valid
1066  */
1067
1068 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1069
1070 {
1071         switch (flags) {
1072         case AMDGPU_VM_MTYPE_DEFAULT:
1073                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1074         case AMDGPU_VM_MTYPE_NC:
1075                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1076         case AMDGPU_VM_MTYPE_WC:
1077                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1078         case AMDGPU_VM_MTYPE_RW:
1079                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1080         case AMDGPU_VM_MTYPE_CC:
1081                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1082         case AMDGPU_VM_MTYPE_UC:
1083                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1084         default:
1085                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1086         }
1087 }
1088
1089 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1090                                 uint64_t *addr, uint64_t *flags)
1091 {
1092         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1093                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1094         BUG_ON(*addr & 0xFFFF00000000003FULL);
1095
1096         if (!adev->gmc.translate_further)
1097                 return;
1098
1099         if (level == AMDGPU_VM_PDB1) {
1100                 /* Set the block fragment size */
1101                 if (!(*flags & AMDGPU_PDE_PTE))
1102                         *flags |= AMDGPU_PDE_BFS(0x9);
1103
1104         } else if (level == AMDGPU_VM_PDB0) {
1105                 if (*flags & AMDGPU_PDE_PTE)
1106                         *flags &= ~AMDGPU_PDE_PTE;
1107                 else
1108                         *flags |= AMDGPU_PTE_TF;
1109         }
1110 }
1111
1112 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1113                                 struct amdgpu_bo_va_mapping *mapping,
1114                                 uint64_t *flags)
1115 {
1116         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1117         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1118
1119         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1120         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1121
1122         if (mapping->flags & AMDGPU_PTE_PRT) {
1123                 *flags |= AMDGPU_PTE_PRT;
1124                 *flags &= ~AMDGPU_PTE_VALID;
1125         }
1126
1127         if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
1128              adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) &&
1129             !(*flags & AMDGPU_PTE_SYSTEM) &&
1130             mapping->bo_va->is_xgmi)
1131                 *flags |= AMDGPU_PTE_SNOOPED;
1132
1133         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
1134                 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED;
1135 }
1136
1137 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1138 {
1139         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1140         unsigned size;
1141
1142         /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1143
1144         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1145                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1146         } else {
1147                 u32 viewport;
1148
1149                 switch (adev->ip_versions[DCE_HWIP][0]) {
1150                 case IP_VERSION(1, 0, 0):
1151                 case IP_VERSION(1, 0, 1):
1152                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1153                         size = (REG_GET_FIELD(viewport,
1154                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1155                                 REG_GET_FIELD(viewport,
1156                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1157                                 4);
1158                         break;
1159                 case IP_VERSION(2, 1, 0):
1160                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1161                         size = (REG_GET_FIELD(viewport,
1162                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1163                                 REG_GET_FIELD(viewport,
1164                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1165                                 4);
1166                         break;
1167                 default:
1168                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1169                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1170                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1171                                 4);
1172                         break;
1173                 }
1174         }
1175
1176         return size;
1177 }
1178
1179 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1180         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1181         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1182         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1183         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1184         .map_mtype = gmc_v9_0_map_mtype,
1185         .get_vm_pde = gmc_v9_0_get_vm_pde,
1186         .get_vm_pte = gmc_v9_0_get_vm_pte,
1187         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1188 };
1189
1190 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1191 {
1192         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1193 }
1194
1195 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1196 {
1197         switch (adev->ip_versions[UMC_HWIP][0]) {
1198         case IP_VERSION(6, 0, 0):
1199                 adev->umc.funcs = &umc_v6_0_funcs;
1200                 break;
1201         case IP_VERSION(6, 1, 1):
1202                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1203                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1204                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1205                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1206                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1207                 adev->umc.ras = &umc_v6_1_ras;
1208                 break;
1209         case IP_VERSION(6, 1, 2):
1210                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1211                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1212                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1213                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1214                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1215                 adev->umc.ras = &umc_v6_1_ras;
1216                 break;
1217         case IP_VERSION(6, 7, 0):
1218                 adev->umc.max_ras_err_cnt_per_query =
1219                         UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1220                 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1221                 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1222                 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1223                 if (!adev->gmc.xgmi.connected_to_cpu)
1224                         adev->umc.ras = &umc_v6_7_ras;
1225                 if (1 & adev->smuio.funcs->get_die_id(adev))
1226                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1227                 else
1228                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1229                 break;
1230         default:
1231                 break;
1232         }
1233
1234         if (adev->umc.ras) {
1235                 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
1236
1237                 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
1238                 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
1239                 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1240                 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
1241
1242                 /* If don't define special ras_late_init function, use default ras_late_init */
1243                 if (!adev->umc.ras->ras_block.ras_late_init)
1244                                 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
1245
1246                 /* If not defined special ras_cb function, use default ras_cb */
1247                 if (!adev->umc.ras->ras_block.ras_cb)
1248                         adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
1249         }
1250 }
1251
1252 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1253 {
1254         switch (adev->ip_versions[MMHUB_HWIP][0]) {
1255         case IP_VERSION(9, 4, 1):
1256                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1257                 break;
1258         case IP_VERSION(9, 4, 2):
1259                 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1260                 break;
1261         default:
1262                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1263                 break;
1264         }
1265 }
1266
1267 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1268 {
1269         switch (adev->ip_versions[MMHUB_HWIP][0]) {
1270         case IP_VERSION(9, 4, 0):
1271                 adev->mmhub.ras = &mmhub_v1_0_ras;
1272                 break;
1273         case IP_VERSION(9, 4, 1):
1274                 adev->mmhub.ras = &mmhub_v9_4_ras;
1275                 break;
1276         case IP_VERSION(9, 4, 2):
1277                 adev->mmhub.ras = &mmhub_v1_7_ras;
1278                 break;
1279         default:
1280                 /* mmhub ras is not available */
1281                 break;
1282         }
1283
1284         if (adev->mmhub.ras) {
1285                 amdgpu_ras_register_ras_block(adev, &adev->mmhub.ras->ras_block);
1286
1287                 strcpy(adev->mmhub.ras->ras_block.ras_comm.name, "mmhub");
1288                 adev->mmhub.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB;
1289                 adev->mmhub.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1290                 adev->mmhub.ras_if = &adev->mmhub.ras->ras_block.ras_comm;
1291         }
1292 }
1293
1294 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1295 {
1296         adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1297 }
1298
1299 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1300 {
1301         adev->hdp.ras = &hdp_v4_0_ras;
1302         amdgpu_ras_register_ras_block(adev, &adev->hdp.ras->ras_block);
1303         adev->hdp.ras_if = &adev->hdp.ras->ras_block.ras_comm;
1304 }
1305
1306 static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev)
1307 {
1308         /* is UMC the right IP to check for MCA?  Maybe DF? */
1309         switch (adev->ip_versions[UMC_HWIP][0]) {
1310         case IP_VERSION(6, 7, 0):
1311                 if (!adev->gmc.xgmi.connected_to_cpu)
1312                         adev->mca.funcs = &mca_v3_0_funcs;
1313                 break;
1314         default:
1315                 break;
1316         }
1317 }
1318
1319 static int gmc_v9_0_early_init(void *handle)
1320 {
1321         int r;
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323
1324         /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */
1325         if (adev->asic_type == CHIP_VEGA20 ||
1326             adev->asic_type == CHIP_ARCTURUS)
1327                 adev->gmc.xgmi.supported = true;
1328
1329         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) {
1330                 adev->gmc.xgmi.supported = true;
1331                 adev->gmc.xgmi.connected_to_cpu =
1332                         adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1333         }
1334
1335         gmc_v9_0_set_gmc_funcs(adev);
1336         gmc_v9_0_set_irq_funcs(adev);
1337         gmc_v9_0_set_umc_funcs(adev);
1338         gmc_v9_0_set_mmhub_funcs(adev);
1339         gmc_v9_0_set_mmhub_ras_funcs(adev);
1340         gmc_v9_0_set_gfxhub_funcs(adev);
1341         gmc_v9_0_set_hdp_ras_funcs(adev);
1342         gmc_v9_0_set_mca_funcs(adev);
1343
1344         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1345         adev->gmc.shared_aperture_end =
1346                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1347         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1348         adev->gmc.private_aperture_end =
1349                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1350
1351         r = amdgpu_gmc_ras_early_init(adev);
1352         if (r)
1353                 return r;
1354
1355         return 0;
1356 }
1357
1358 static int gmc_v9_0_late_init(void *handle)
1359 {
1360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1361         int r;
1362
1363         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1364         if (r)
1365                 return r;
1366
1367         /*
1368          * Workaround performance drop issue with VBIOS enables partial
1369          * writes, while disables HBM ECC for vega10.
1370          */
1371         if (!amdgpu_sriov_vf(adev) &&
1372             (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) {
1373                 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1374                         if (adev->df.funcs &&
1375                             adev->df.funcs->enable_ecc_force_par_wr_rmw)
1376                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1377                 }
1378         }
1379
1380         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1381                 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
1382                     adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
1383                         adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1384
1385                 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops &&
1386                     adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count)
1387                         adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1388         }
1389
1390         r = amdgpu_gmc_ras_late_init(adev);
1391         if (r)
1392                 return r;
1393
1394         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1395 }
1396
1397 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1398                                         struct amdgpu_gmc *mc)
1399 {
1400         u64 base = adev->mmhub.funcs->get_fb_location(adev);
1401
1402         /* add the xgmi offset of the physical node */
1403         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1404         if (adev->gmc.xgmi.connected_to_cpu) {
1405                 amdgpu_gmc_sysvm_location(adev, mc);
1406         } else {
1407                 amdgpu_gmc_vram_location(adev, mc, base);
1408                 amdgpu_gmc_gart_location(adev, mc);
1409                 amdgpu_gmc_agp_location(adev, mc);
1410         }
1411         /* base offset of vram pages */
1412         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1413
1414         /* XXX: add the xgmi offset of the physical node? */
1415         adev->vm_manager.vram_base_offset +=
1416                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1417 }
1418
1419 /**
1420  * gmc_v9_0_mc_init - initialize the memory controller driver params
1421  *
1422  * @adev: amdgpu_device pointer
1423  *
1424  * Look up the amount of vram, vram width, and decide how to place
1425  * vram and gart within the GPU's physical address space.
1426  * Returns 0 for success.
1427  */
1428 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1429 {
1430         int r;
1431
1432         /* size in MB on si */
1433         adev->gmc.mc_vram_size =
1434                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1435         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1436
1437         if (!(adev->flags & AMD_IS_APU) &&
1438             !adev->gmc.xgmi.connected_to_cpu) {
1439                 r = amdgpu_device_resize_fb_bar(adev);
1440                 if (r)
1441                         return r;
1442         }
1443         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1444         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1445
1446 #ifdef CONFIG_X86_64
1447         /*
1448          * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1449          * interface can use VRAM through here as it appears system reserved
1450          * memory in host address space.
1451          *
1452          * For APUs, VRAM is just the stolen system memory and can be accessed
1453          * directly.
1454          *
1455          * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1456          */
1457
1458         /* check whether both host-gpu and gpu-gpu xgmi links exist */
1459         if ((adev->flags & AMD_IS_APU) ||
1460             (adev->gmc.xgmi.supported &&
1461              adev->gmc.xgmi.connected_to_cpu)) {
1462                 adev->gmc.aper_base =
1463                         adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1464                         adev->gmc.xgmi.physical_node_id *
1465                         adev->gmc.xgmi.node_segment_size;
1466                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1467         }
1468
1469 #endif
1470         /* In case the PCI BAR is larger than the actual amount of vram */
1471         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1472         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1473                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1474
1475         /* set the gart size */
1476         if (amdgpu_gart_size == -1) {
1477                 switch (adev->ip_versions[GC_HWIP][0]) {
1478                 case IP_VERSION(9, 0, 1):  /* all engines support GPUVM */
1479                 case IP_VERSION(9, 2, 1):  /* all engines support GPUVM */
1480                 case IP_VERSION(9, 4, 0):
1481                 case IP_VERSION(9, 4, 1):
1482                 case IP_VERSION(9, 4, 2):
1483                 default:
1484                         adev->gmc.gart_size = 512ULL << 20;
1485                         break;
1486                 case IP_VERSION(9, 1, 0):   /* DCE SG support */
1487                 case IP_VERSION(9, 2, 2):   /* DCE SG support */
1488                 case IP_VERSION(9, 3, 0):
1489                         adev->gmc.gart_size = 1024ULL << 20;
1490                         break;
1491                 }
1492         } else {
1493                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1494         }
1495
1496         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1497
1498         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1499
1500         return 0;
1501 }
1502
1503 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1504 {
1505         int r;
1506
1507         if (adev->gart.bo) {
1508                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1509                 return 0;
1510         }
1511
1512         if (adev->gmc.xgmi.connected_to_cpu) {
1513                 adev->gmc.vmid0_page_table_depth = 1;
1514                 adev->gmc.vmid0_page_table_block_size = 12;
1515         } else {
1516                 adev->gmc.vmid0_page_table_depth = 0;
1517                 adev->gmc.vmid0_page_table_block_size = 0;
1518         }
1519
1520         /* Initialize common gart structure */
1521         r = amdgpu_gart_init(adev);
1522         if (r)
1523                 return r;
1524         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1525         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1526                                  AMDGPU_PTE_EXECUTABLE;
1527
1528         r = amdgpu_gart_table_vram_alloc(adev);
1529         if (r)
1530                 return r;
1531
1532         if (adev->gmc.xgmi.connected_to_cpu) {
1533                 r = amdgpu_gmc_pdb0_alloc(adev);
1534         }
1535
1536         return r;
1537 }
1538
1539 /**
1540  * gmc_v9_0_save_registers - saves regs
1541  *
1542  * @adev: amdgpu_device pointer
1543  *
1544  * This saves potential register values that should be
1545  * restored upon resume
1546  */
1547 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1548 {
1549         if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) ||
1550             (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1)))
1551                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1552 }
1553
1554 static int gmc_v9_0_sw_init(void *handle)
1555 {
1556         int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
1557         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1558
1559         adev->gfxhub.funcs->init(adev);
1560
1561         adev->mmhub.funcs->init(adev);
1562         if (adev->mca.funcs)
1563                 adev->mca.funcs->init(adev);
1564
1565         spin_lock_init(&adev->gmc.invalidate_lock);
1566
1567         r = amdgpu_atomfirmware_get_vram_info(adev,
1568                 &vram_width, &vram_type, &vram_vendor);
1569         if (amdgpu_sriov_vf(adev))
1570                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1571                  * and DF related registers is not readable, seems hardcord is the
1572                  * only way to set the correct vram_width
1573                  */
1574                 adev->gmc.vram_width = 2048;
1575         else if (amdgpu_emu_mode != 1)
1576                 adev->gmc.vram_width = vram_width;
1577
1578         if (!adev->gmc.vram_width) {
1579                 int chansize, numchan;
1580
1581                 /* hbm memory channel size */
1582                 if (adev->flags & AMD_IS_APU)
1583                         chansize = 64;
1584                 else
1585                         chansize = 128;
1586                 if (adev->df.funcs &&
1587                     adev->df.funcs->get_hbm_channel_number) {
1588                         numchan = adev->df.funcs->get_hbm_channel_number(adev);
1589                         adev->gmc.vram_width = numchan * chansize;
1590                 }
1591         }
1592
1593         adev->gmc.vram_type = vram_type;
1594         adev->gmc.vram_vendor = vram_vendor;
1595         switch (adev->ip_versions[GC_HWIP][0]) {
1596         case IP_VERSION(9, 1, 0):
1597         case IP_VERSION(9, 2, 2):
1598                 adev->num_vmhubs = 2;
1599
1600                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1601                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1602                 } else {
1603                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1604                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1605                         adev->gmc.translate_further =
1606                                 adev->vm_manager.num_level > 1;
1607                 }
1608                 break;
1609         case IP_VERSION(9, 0, 1):
1610         case IP_VERSION(9, 2, 1):
1611         case IP_VERSION(9, 4, 0):
1612         case IP_VERSION(9, 3, 0):
1613         case IP_VERSION(9, 4, 2):
1614                 adev->num_vmhubs = 2;
1615
1616
1617                 /*
1618                  * To fulfill 4-level page support,
1619                  * vm size is 256TB (48bit), maximum size of Vega10,
1620                  * block size 512 (9bit)
1621                  */
1622                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1623                 if (amdgpu_sriov_vf(adev))
1624                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1625                 else
1626                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1627                 break;
1628         case IP_VERSION(9, 4, 1):
1629                 adev->num_vmhubs = 3;
1630
1631                 /* Keep the vm size same with Vega20 */
1632                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1633                 break;
1634         default:
1635                 break;
1636         }
1637
1638         /* This interrupt is VMC page fault.*/
1639         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1640                                 &adev->gmc.vm_fault);
1641         if (r)
1642                 return r;
1643
1644         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
1645                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1646                                         &adev->gmc.vm_fault);
1647                 if (r)
1648                         return r;
1649         }
1650
1651         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1652                                 &adev->gmc.vm_fault);
1653
1654         if (r)
1655                 return r;
1656
1657         if (!amdgpu_sriov_vf(adev) &&
1658             !adev->gmc.xgmi.connected_to_cpu) {
1659                 /* interrupt sent to DF. */
1660                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1661                                       &adev->gmc.ecc_irq);
1662                 if (r)
1663                         return r;
1664         }
1665
1666         /* Set the internal MC address mask
1667          * This is the max address of the GPU's
1668          * internal address space.
1669          */
1670         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1671
1672         dma_addr_bits = adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ? 48:44;
1673         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
1674         if (r) {
1675                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1676                 return r;
1677         }
1678         adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
1679
1680         r = gmc_v9_0_mc_init(adev);
1681         if (r)
1682                 return r;
1683
1684         amdgpu_gmc_get_vbios_allocations(adev);
1685
1686         /* Memory manager */
1687         r = amdgpu_bo_init(adev);
1688         if (r)
1689                 return r;
1690
1691         r = gmc_v9_0_gart_init(adev);
1692         if (r)
1693                 return r;
1694
1695         /*
1696          * number of VMs
1697          * VMID 0 is reserved for System
1698          * amdgpu graphics/compute will use VMIDs 1..n-1
1699          * amdkfd will use VMIDs n..15
1700          *
1701          * The first KFD VMID is 8 for GPUs with graphics, 3 for
1702          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1703          * for video processing.
1704          */
1705         adev->vm_manager.first_kfd_vmid =
1706                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
1707                  adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) ? 3 : 8;
1708
1709         amdgpu_vm_manager_init(adev);
1710
1711         gmc_v9_0_save_registers(adev);
1712
1713         return 0;
1714 }
1715
1716 static int gmc_v9_0_sw_fini(void *handle)
1717 {
1718         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1719
1720         amdgpu_gmc_ras_fini(adev);
1721         amdgpu_gem_force_release(adev);
1722         amdgpu_vm_manager_fini(adev);
1723         amdgpu_gart_table_vram_free(adev);
1724         amdgpu_bo_unref(&adev->gmc.pdb0_bo);
1725         amdgpu_bo_fini(adev);
1726
1727         return 0;
1728 }
1729
1730 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1731 {
1732
1733         switch (adev->ip_versions[MMHUB_HWIP][0]) {
1734         case IP_VERSION(9, 0, 0):
1735                 if (amdgpu_sriov_vf(adev))
1736                         break;
1737                 fallthrough;
1738         case IP_VERSION(9, 4, 0):
1739                 soc15_program_register_sequence(adev,
1740                                                 golden_settings_mmhub_1_0_0,
1741                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1742                 soc15_program_register_sequence(adev,
1743                                                 golden_settings_athub_1_0_0,
1744                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1745                 break;
1746         case IP_VERSION(9, 1, 0):
1747         case IP_VERSION(9, 2, 0):
1748                 /* TODO for renoir */
1749                 soc15_program_register_sequence(adev,
1750                                                 golden_settings_athub_1_0_0,
1751                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1752                 break;
1753         default:
1754                 break;
1755         }
1756 }
1757
1758 /**
1759  * gmc_v9_0_restore_registers - restores regs
1760  *
1761  * @adev: amdgpu_device pointer
1762  *
1763  * This restores register values, saved at suspend.
1764  */
1765 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1766 {
1767         if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) ||
1768             (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) {
1769                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1770                 WARN_ON(adev->gmc.sdpif_register !=
1771                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
1772         }
1773 }
1774
1775 /**
1776  * gmc_v9_0_gart_enable - gart enable
1777  *
1778  * @adev: amdgpu_device pointer
1779  */
1780 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1781 {
1782         int r;
1783
1784         if (adev->gmc.xgmi.connected_to_cpu)
1785                 amdgpu_gmc_init_pdb0(adev);
1786
1787         if (adev->gart.bo == NULL) {
1788                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1789                 return -EINVAL;
1790         }
1791
1792         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1793         r = adev->gfxhub.funcs->gart_enable(adev);
1794         if (r)
1795                 return r;
1796
1797         r = adev->mmhub.funcs->gart_enable(adev);
1798         if (r)
1799                 return r;
1800
1801         DRM_INFO("PCIE GART of %uM enabled.\n",
1802                  (unsigned)(adev->gmc.gart_size >> 20));
1803         if (adev->gmc.pdb0_bo)
1804                 DRM_INFO("PDB0 located at 0x%016llX\n",
1805                                 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
1806         DRM_INFO("PTB located at 0x%016llX\n",
1807                         (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1808
1809         return 0;
1810 }
1811
1812 static int gmc_v9_0_hw_init(void *handle)
1813 {
1814         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1815         bool value;
1816         int i, r;
1817
1818         /* The sequence of these two function calls matters.*/
1819         gmc_v9_0_init_golden_registers(adev);
1820
1821         if (adev->mode_info.num_crtc) {
1822                 /* Lockout access through VGA aperture*/
1823                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1824                 /* disable VGA render */
1825                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1826         }
1827
1828         if (adev->mmhub.funcs->update_power_gating)
1829                 adev->mmhub.funcs->update_power_gating(adev, true);
1830
1831         adev->hdp.funcs->init_registers(adev);
1832
1833         /* After HDP is initialized, flush HDP.*/
1834         adev->hdp.funcs->flush_hdp(adev, NULL);
1835
1836         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1837                 value = false;
1838         else
1839                 value = true;
1840
1841         if (!amdgpu_sriov_vf(adev)) {
1842                 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1843                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1844         }
1845         for (i = 0; i < adev->num_vmhubs; ++i)
1846                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1847
1848         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1849                 adev->umc.funcs->init_registers(adev);
1850
1851         r = gmc_v9_0_gart_enable(adev);
1852         if (r)
1853                 return r;
1854
1855         if (amdgpu_emu_mode == 1)
1856                 return amdgpu_gmc_vram_checking(adev);
1857         else
1858                 return r;
1859 }
1860
1861 /**
1862  * gmc_v9_0_gart_disable - gart disable
1863  *
1864  * @adev: amdgpu_device pointer
1865  *
1866  * This disables all VM page table.
1867  */
1868 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1869 {
1870         adev->gfxhub.funcs->gart_disable(adev);
1871         adev->mmhub.funcs->gart_disable(adev);
1872 }
1873
1874 static int gmc_v9_0_hw_fini(void *handle)
1875 {
1876         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1877
1878         gmc_v9_0_gart_disable(adev);
1879
1880         if (amdgpu_sriov_vf(adev)) {
1881                 /* full access mode, so don't touch any GMC register */
1882                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1883                 return 0;
1884         }
1885
1886         /*
1887          * Pair the operations did in gmc_v9_0_hw_init and thus maintain
1888          * a correct cached state for GMC. Otherwise, the "gate" again
1889          * operation on S3 resuming will fail due to wrong cached state.
1890          */
1891         if (adev->mmhub.funcs->update_power_gating)
1892                 adev->mmhub.funcs->update_power_gating(adev, false);
1893
1894         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1895         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1896
1897         return 0;
1898 }
1899
1900 static int gmc_v9_0_suspend(void *handle)
1901 {
1902         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1903
1904         return gmc_v9_0_hw_fini(adev);
1905 }
1906
1907 static int gmc_v9_0_resume(void *handle)
1908 {
1909         int r;
1910         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1911
1912         r = gmc_v9_0_hw_init(adev);
1913         if (r)
1914                 return r;
1915
1916         amdgpu_vmid_reset_all(adev);
1917
1918         return 0;
1919 }
1920
1921 static bool gmc_v9_0_is_idle(void *handle)
1922 {
1923         /* MC is always ready in GMC v9.*/
1924         return true;
1925 }
1926
1927 static int gmc_v9_0_wait_for_idle(void *handle)
1928 {
1929         /* There is no need to wait for MC idle in GMC v9.*/
1930         return 0;
1931 }
1932
1933 static int gmc_v9_0_soft_reset(void *handle)
1934 {
1935         /* XXX for emulation.*/
1936         return 0;
1937 }
1938
1939 static int gmc_v9_0_set_clockgating_state(void *handle,
1940                                         enum amd_clockgating_state state)
1941 {
1942         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1943
1944         adev->mmhub.funcs->set_clockgating(adev, state);
1945
1946         athub_v1_0_set_clockgating(adev, state);
1947
1948         return 0;
1949 }
1950
1951 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1952 {
1953         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1954
1955         adev->mmhub.funcs->get_clockgating(adev, flags);
1956
1957         athub_v1_0_get_clockgating(adev, flags);
1958 }
1959
1960 static int gmc_v9_0_set_powergating_state(void *handle,
1961                                         enum amd_powergating_state state)
1962 {
1963         return 0;
1964 }
1965
1966 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1967         .name = "gmc_v9_0",
1968         .early_init = gmc_v9_0_early_init,
1969         .late_init = gmc_v9_0_late_init,
1970         .sw_init = gmc_v9_0_sw_init,
1971         .sw_fini = gmc_v9_0_sw_fini,
1972         .hw_init = gmc_v9_0_hw_init,
1973         .hw_fini = gmc_v9_0_hw_fini,
1974         .suspend = gmc_v9_0_suspend,
1975         .resume = gmc_v9_0_resume,
1976         .is_idle = gmc_v9_0_is_idle,
1977         .wait_for_idle = gmc_v9_0_wait_for_idle,
1978         .soft_reset = gmc_v9_0_soft_reset,
1979         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1980         .set_powergating_state = gmc_v9_0_set_powergating_state,
1981         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1982 };
1983
1984 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1985 {
1986         .type = AMD_IP_BLOCK_TYPE_GMC,
1987         .major = 9,
1988         .minor = 0,
1989         .rev = 0,
1990         .funcs = &gmc_v9_0_ip_funcs,
1991 };