drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_atomfirmware.h"
  27 #include "gmc_v10_0.h"
  28 #include "umc_v8_7.h"
  29
  30 #include "athub/athub_2_0_0_sh_mask.h"
  31 #include "athub/athub_2_0_0_offset.h"
  32 #include "dcn/dcn_2_0_0_offset.h"
  33 #include "dcn/dcn_2_0_0_sh_mask.h"
  34 #include "oss/osssys_5_0_0_offset.h"
  35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  36 #include "navi10_enum.h"
  37
  38 #include "soc15.h"
  39 #include "soc15d.h"
  40 #include "soc15_common.h"
  41
  42 #include "nbio_v2_3.h"
  43
  44 #include "gfxhub_v2_0.h"
  45 #include "gfxhub_v2_1.h"
  46 #include "mmhub_v2_0.h"
  47 #include "mmhub_v2_3.h"
  48 #include "athub_v2_0.h"
  49 #include "athub_v2_1.h"
  50
  51 #include "amdgpu_reset.h"
  52
  53 #if 0
  54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
  55 {
  56         /* TODO add golden setting for hdp */
  57 };
  58 #endif
  59
  60 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
  61                                          struct amdgpu_irq_src *src,
  62                                          unsigned type,
  63                                          enum amdgpu_interrupt_state state)
  64 {
  65         return 0;
  66 }
  67
  68 static int
  69 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  70                                    struct amdgpu_irq_src *src, unsigned type,
  71                                    enum amdgpu_interrupt_state state)
  72 {
  73         switch (state) {
  74         case AMDGPU_IRQ_STATE_DISABLE:
  75                 /* MM HUB */
  76                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
  77                 /* GFX HUB */
  78                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
  79                 break;
  80         case AMDGPU_IRQ_STATE_ENABLE:
  81                 /* MM HUB */
  82                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
  83                 /* GFX HUB */
  84                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
  85                 break;
  86         default:
  87                 break;
  88         }
  89
  90         return 0;
  91 }
  92
  93 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
  94                                        struct amdgpu_irq_src *source,
  95                                        struct amdgpu_iv_entry *entry)
  96 {
  97         bool retry_fault = !!(entry->src_data[1] & 0x80);
  98         bool write_fault = !!(entry->src_data[1] & 0x20);
  99         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 100         struct amdgpu_task_info task_info;
 101         uint32_t status = 0;
 102         u64 addr;
 103
 104         addr = (u64)entry->src_data[0] << 12;
 105         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 106
 107         if (retry_fault) {
 108                 /* Returning 1 here also prevents sending the IV to the KFD */
 109
 110                 /* Process it onyl if it's the first fault for this address */
 111                 if (entry->ih != &adev->irq.ih_soft &&
 112                     amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
 113                                              entry->timestamp))
 114                         return 1;
 115
 116                 /* Delegate it to a different ring if the hardware hasn't
 117                  * already done it.
 118                  */
 119                 if (entry->ih == &adev->irq.ih) {
 120                         amdgpu_irq_delegate(adev, entry, 8);
 121                         return 1;
 122                 }
 123
 124                 /* Try to handle the recoverable page faults by filling page
 125                  * tables
 126                  */
 127                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
 128                         return 1;
 129         }
 130
 131         if (!amdgpu_sriov_vf(adev)) {
 132                 /*
 133                  * Issue a dummy read to wait for the status register to
 134                  * be updated to avoid reading an incorrect value due to
 135                  * the new fast GRBM interface.
 136                  */
 137                 if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 138                     (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
 139                         RREG32(hub->vm_l2_pro_fault_status);
 140
 141                 status = RREG32(hub->vm_l2_pro_fault_status);
 142                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 143         }
 144
 145         if (!printk_ratelimit())
 146                 return 0;
 147
 148         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 149         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 150
 151         dev_err(adev->dev,
 152                 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
 153                 "for process %s pid %d thread %s pid %d)\n",
 154                 entry->vmid_src ? "mmhub" : "gfxhub",
 155                 entry->src_id, entry->ring_id, entry->vmid,
 156                 entry->pasid, task_info.process_name, task_info.tgid,
 157                 task_info.task_name, task_info.pid);
 158         dev_err(adev->dev, "  in page starting at address 0x%016llx from client 0x%x (%s)\n",
 159                 addr, entry->client_id,
 160                 soc15_ih_clientid_name[entry->client_id]);
 161
 162         if (!amdgpu_sriov_vf(adev))
 163                 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
 164                                                                    status);
 165
 166         return 0;
 167 }
 168
 169 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
 170         .set = gmc_v10_0_vm_fault_interrupt_state,
 171         .process = gmc_v10_0_process_interrupt,
 172 };
 173
 174 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
 175         .set = gmc_v10_0_ecc_interrupt_state,
 176         .process = amdgpu_umc_process_ecc_irq,
 177 };
 178
 179 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 180 {
 181         adev->gmc.vm_fault.num_types = 1;
 182         adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
 183
 184         if (!amdgpu_sriov_vf(adev)) {
 185                 adev->gmc.ecc_irq.num_types = 1;
 186                 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
 187         }
 188 }
 189
 190 /**
 191  * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
 192  *
 193  * @adev: amdgpu_device pointer
 194  * @vmhub: vmhub type
 195  *
 196  */
 197 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 198                                        uint32_t vmhub)
 199 {
 200         return ((vmhub == AMDGPU_MMHUB_0 ||
 201                  vmhub == AMDGPU_MMHUB_1) &&
 202                 (!amdgpu_sriov_vf(adev)));
 203 }
 204
 205 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
 206                                         struct amdgpu_device *adev,
 207                                         uint8_t vmid, uint16_t *p_pasid)
 208 {
 209         uint32_t value;
 210
 211         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 212                      + vmid);
 213         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 214
 215         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 216 }
 217
 218 /*
 219  * GART
 220  * VMID 0 is the physical GPU addresses as used by the kernel.
 221  * VMIDs 1-15 are used for userspace clients and are handled
 222  * by the amdgpu vm/hsa code.
 223  */
 224
 225 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 226                                    unsigned int vmhub, uint32_t flush_type)
 227 {
 228         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
 229         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 230         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 231         u32 tmp;
 232         /* Use register 17 for GART */
 233         const unsigned eng = 17;
 234         unsigned int i;
 235         unsigned char hub_ip = 0;
 236
 237         hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
 238                    GC_HWIP : MMHUB_HWIP;
 239
 240         spin_lock(&adev->gmc.invalidate_lock);
 241         /*
 242          * It may lose gpuvm invalidate acknowldege state across power-gating
 243          * off cycle, add semaphore acquire before invalidation and semaphore
 244          * release after invalidation to avoid entering power gated state
 245          * to WA the Issue
 246          */
 247
 248         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 249         if (use_semaphore) {
 250                 for (i = 0; i < adev->usec_timeout; i++) {
 251                         /* a read return value of 1 means semaphore acuqire */
 252                         tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 253                                          hub->eng_distance * eng, hub_ip);
 254
 255                         if (tmp & 0x1)
 256                                 break;
 257                         udelay(1);
 258                 }
 259
 260                 if (i >= adev->usec_timeout)
 261                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 262         }
 263
 264         WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
 265                           hub->eng_distance * eng,
 266                           inv_req, hub_ip);
 267
 268         /*
 269          * Issue a dummy read to wait for the ACK register to be cleared
 270          * to avoid a false ACK due to the new fast GRBM interface.
 271          */
 272         if ((vmhub == AMDGPU_GFXHUB_0) &&
 273             (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
 274                 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
 275                                   hub->eng_distance * eng, hub_ip);
 276
 277         /* Wait for ACK with a delay.*/
 278         for (i = 0; i < adev->usec_timeout; i++) {
 279                 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
 280                                   hub->eng_distance * eng, hub_ip);
 281
 282                 tmp &= 1 << vmid;
 283                 if (tmp)
 284                         break;
 285
 286                 udelay(1);
 287         }
 288
 289         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 290         if (use_semaphore)
 291                 /*
 292                  * add semaphore release after invalidation,
 293                  * write with 0 means semaphore release
 294                  */
 295                 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 296                                   hub->eng_distance * eng, 0, hub_ip);
 297
 298         spin_unlock(&adev->gmc.invalidate_lock);
 299
 300         if (i < adev->usec_timeout)
 301                 return;
 302
 303         DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
 304 }
 305
 306 /**
 307  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
 308  *
 309  * @adev: amdgpu_device pointer
 310  * @vmid: vm instance to flush
 311  * @vmhub: vmhub type
 312  * @flush_type: the flush type
 313  *
 314  * Flush the TLB for the requested page table.
 315  */
 316 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 317                                         uint32_t vmhub, uint32_t flush_type)
 318 {
 319         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 320         struct dma_fence *fence;
 321         struct amdgpu_job *job;
 322
 323         int r;
 324
 325         /* flush hdp cache */
 326         adev->hdp.funcs->flush_hdp(adev, NULL);
 327
 328         /* For SRIOV run time, driver shouldn't access the register through MMIO
 329          * Directly use kiq to do the vm invalidation instead
 330          */
 331         if (adev->gfx.kiq.ring.sched.ready &&
 332             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 333             down_read_trylock(&adev->reset_domain->sem)) {
 334                 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 335                 const unsigned eng = 17;
 336                 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 337                 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 338                 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 339
 340                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 341                                 1 << vmid);
 342
 343                 up_read(&adev->reset_domain->sem);
 344                 return;
 345         }
 346
 347         mutex_lock(&adev->mman.gtt_window_lock);
 348
 349         if (vmhub == AMDGPU_MMHUB_0) {
 350                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
 351                 mutex_unlock(&adev->mman.gtt_window_lock);
 352                 return;
 353         }
 354
 355         BUG_ON(vmhub != AMDGPU_GFXHUB_0);
 356
 357         if (!adev->mman.buffer_funcs_enabled ||
 358             !adev->ib_pool_ready ||
 359             amdgpu_in_reset(adev) ||
 360             ring->sched.ready == false) {
 361                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
 362                 mutex_unlock(&adev->mman.gtt_window_lock);
 363                 return;
 364         }
 365
 366         /* The SDMA on Navi has a bug which can theoretically result in memory
 367          * corruption if an invalidation happens at the same time as an VA
 368          * translation. Avoid this by doing the invalidation from the SDMA
 369          * itself.
 370          */
 371         r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
 372                                      &job);
 373         if (r)
 374                 goto error_alloc;
 375
 376         job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
 377         job->vm_needs_flush = true;
 378         job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
 379         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 380         r = amdgpu_job_submit(job, &adev->mman.entity,
 381                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 382         if (r)
 383                 goto error_submit;
 384
 385         mutex_unlock(&adev->mman.gtt_window_lock);
 386
 387         dma_fence_wait(fence, false);
 388         dma_fence_put(fence);
 389
 390         return;
 391
 392 error_submit:
 393         amdgpu_job_free(job);
 394
 395 error_alloc:
 396         mutex_unlock(&adev->mman.gtt_window_lock);
 397         DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 398 }
 399
 400 /**
 401  * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
 402  *
 403  * @adev: amdgpu_device pointer
 404  * @pasid: pasid to be flush
 405  * @flush_type: the flush type
 406  * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
 407  *
 408  * Flush the TLB for the requested pasid.
 409  */
 410 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 411                                         uint16_t pasid, uint32_t flush_type,
 412                                         bool all_hub)
 413 {
 414         int vmid, i;
 415         signed long r;
 416         uint32_t seq;
 417         uint16_t queried_pasid;
 418         bool ret;
 419         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 420         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 421
 422         if (amdgpu_emu_mode == 0 && ring->sched.ready) {
 423                 spin_lock(&adev->gfx.kiq.ring_lock);
 424                 /* 2 dwords flush + 8 dwords fence */
 425                 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
 426                 kiq->pmf->kiq_invalidate_tlbs(ring,
 427                                         pasid, flush_type, all_hub);
 428                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 429                 if (r) {
 430                         amdgpu_ring_undo(ring);
 431                         spin_unlock(&adev->gfx.kiq.ring_lock);
 432                         return -ETIME;
 433                 }
 434
 435                 amdgpu_ring_commit(ring);
 436                 spin_unlock(&adev->gfx.kiq.ring_lock);
 437                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 438                 if (r < 1) {
 439                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 440                         return -ETIME;
 441                 }
 442
 443                 return 0;
 444         }
 445
 446         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
 447
 448                 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 449                                 &queried_pasid);
 450                 if (ret && queried_pasid == pasid) {
 451                         if (all_hub) {
 452                                 for (i = 0; i < adev->num_vmhubs; i++)
 453                                         gmc_v10_0_flush_gpu_tlb(adev, vmid,
 454                                                         i, flush_type);
 455                         } else {
 456                                 gmc_v10_0_flush_gpu_tlb(adev, vmid,
 457                                                 AMDGPU_GFXHUB_0, flush_type);
 458                         }
 459                         break;
 460                 }
 461         }
 462
 463         return 0;
 464 }
 465
 466 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 467                                              unsigned vmid, uint64_t pd_addr)
 468 {
 469         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 470         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 471         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
 472         unsigned eng = ring->vm_inv_eng;
 473
 474         /*
 475          * It may lose gpuvm invalidate acknowldege state across power-gating
 476          * off cycle, add semaphore acquire before invalidation and semaphore
 477          * release after invalidation to avoid entering power gated state
 478          * to WA the Issue
 479          */
 480
 481         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 482         if (use_semaphore)
 483                 /* a read return value of 1 means semaphore acuqire */
 484                 amdgpu_ring_emit_reg_wait(ring,
 485                                           hub->vm_inv_eng0_sem +
 486                                           hub->eng_distance * eng, 0x1, 0x1);
 487
 488         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 489                               (hub->ctx_addr_distance * vmid),
 490                               lower_32_bits(pd_addr));
 491
 492         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 493                               (hub->ctx_addr_distance * vmid),
 494                               upper_32_bits(pd_addr));
 495
 496         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 497                                             hub->eng_distance * eng,
 498                                             hub->vm_inv_eng0_ack +
 499                                             hub->eng_distance * eng,
 500                                             req, 1 << vmid);
 501
 502         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 503         if (use_semaphore)
 504                 /*
 505                  * add semaphore release after invalidation,
 506                  * write with 0 means semaphore release
 507                  */
 508                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 509                                       hub->eng_distance * eng, 0);
 510
 511         return pd_addr;
 512 }
 513
 514 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 515                                          unsigned pasid)
 516 {
 517         struct amdgpu_device *adev = ring->adev;
 518         uint32_t reg;
 519
 520         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 521                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 522         else
 523                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 524
 525         amdgpu_ring_emit_wreg(ring, reg, pasid);
 526 }
 527
 528 /*
 529  * PTE format on NAVI 10:
 530  * 63:59 reserved
 531  * 58 reserved and for sienna_cichlid is used for MALL noalloc
 532  * 57 reserved
 533  * 56 F
 534  * 55 L
 535  * 54 reserved
 536  * 53:52 SW
 537  * 51 T
 538  * 50:48 mtype
 539  * 47:12 4k physical page base address
 540  * 11:7 fragment
 541  * 6 write
 542  * 5 read
 543  * 4 exe
 544  * 3 Z
 545  * 2 snooped
 546  * 1 system
 547  * 0 valid
 548  *
 549  * PDE format on NAVI 10:
 550  * 63:59 block fragment size
 551  * 58:55 reserved
 552  * 54 P
 553  * 53:48 reserved
 554  * 47:6 physical base address of PD or PTE
 555  * 5:3 reserved
 556  * 2 C
 557  * 1 system
 558  * 0 valid
 559  */
 560
 561 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 562 {
 563         switch (flags) {
 564         case AMDGPU_VM_MTYPE_DEFAULT:
 565                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 566         case AMDGPU_VM_MTYPE_NC:
 567                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 568         case AMDGPU_VM_MTYPE_WC:
 569                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 570         case AMDGPU_VM_MTYPE_CC:
 571                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 572         case AMDGPU_VM_MTYPE_UC:
 573                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 574         default:
 575                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 576         }
 577 }
 578
 579 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
 580                                  uint64_t *addr, uint64_t *flags)
 581 {
 582         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 583                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
 584         BUG_ON(*addr & 0xFFFF00000000003FULL);
 585
 586         if (!adev->gmc.translate_further)
 587                 return;
 588
 589         if (level == AMDGPU_VM_PDB1) {
 590                 /* Set the block fragment size */
 591                 if (!(*flags & AMDGPU_PDE_PTE))
 592                         *flags |= AMDGPU_PDE_BFS(0x9);
 593
 594         } else if (level == AMDGPU_VM_PDB0) {
 595                 if (*flags & AMDGPU_PDE_PTE)
 596                         *flags &= ~AMDGPU_PDE_PTE;
 597                 else
 598                         *flags |= AMDGPU_PTE_TF;
 599         }
 600 }
 601
 602 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
 603                                  struct amdgpu_bo_va_mapping *mapping,
 604                                  uint64_t *flags)
 605 {
 606         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 607         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 608
 609         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 610         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 611
 612         if (mapping->flags & AMDGPU_PTE_PRT) {
 613                 *flags |= AMDGPU_PTE_PRT;
 614                 *flags |= AMDGPU_PTE_SNOOPED;
 615                 *flags |= AMDGPU_PTE_LOG;
 616                 *flags |= AMDGPU_PTE_SYSTEM;
 617                 *flags &= ~AMDGPU_PTE_VALID;
 618         }
 619 }
 620
 621 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
 622 {
 623         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 624         unsigned size;
 625
 626         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 627                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 628         } else {
 629                 u32 viewport;
 630                 u32 pitch;
 631
 632                 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 633                 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
 634                 size = (REG_GET_FIELD(viewport,
 635                                         HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 636                                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
 637                                 4);
 638         }
 639
 640         return size;
 641 }
 642
 643 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
 644         .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
 645         .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
 646         .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
 647         .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
 648         .map_mtype = gmc_v10_0_map_mtype,
 649         .get_vm_pde = gmc_v10_0_get_vm_pde,
 650         .get_vm_pte = gmc_v10_0_get_vm_pte,
 651         .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
 652 };
 653
 654 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
 655 {
 656         if (adev->gmc.gmc_funcs == NULL)
 657                 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
 658 }
 659
 660 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
 661 {
 662         switch (adev->ip_versions[UMC_HWIP][0]) {
 663         case IP_VERSION(8, 7, 0):
 664                 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
 665                 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
 666                 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
 667                 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
 668                 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
 669                 adev->umc.ras = &umc_v8_7_ras;
 670                 break;
 671         default:
 672                 break;
 673         }
 674         if (adev->umc.ras) {
 675                 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
 676
 677                 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
 678                 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
 679                 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 680                 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
 681
 682                 /* If don't define special ras_late_init function, use default ras_late_init */
 683                 if (!adev->umc.ras->ras_block.ras_late_init)
 684                                 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
 685
 686                 /* If not defined special ras_cb function, use default ras_cb */
 687                 if (!adev->umc.ras->ras_block.ras_cb)
 688                         adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
 689         }
 690 }
 691
 692
 693 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
 694 {
 695         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 696         case IP_VERSION(2, 3, 0):
 697         case IP_VERSION(2, 4, 0):
 698         case IP_VERSION(2, 4, 1):
 699                 adev->mmhub.funcs = &mmhub_v2_3_funcs;
 700                 break;
 701         default:
 702                 adev->mmhub.funcs = &mmhub_v2_0_funcs;
 703                 break;
 704         }
 705 }
 706
 707 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 708 {
 709         switch (adev->ip_versions[GC_HWIP][0]) {
 710         case IP_VERSION(10, 3, 0):
 711         case IP_VERSION(10, 3, 2):
 712         case IP_VERSION(10, 3, 1):
 713         case IP_VERSION(10, 3, 4):
 714         case IP_VERSION(10, 3, 5):
 715         case IP_VERSION(10, 3, 6):
 716         case IP_VERSION(10, 3, 3):
 717         case IP_VERSION(10, 3, 7):
 718                 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
 719                 break;
 720         default:
 721                 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
 722                 break;
 723         }
 724 }
 725
 726
 727 static int gmc_v10_0_early_init(void *handle)
 728 {
 729         int r;
 730         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 731
 732         gmc_v10_0_set_mmhub_funcs(adev);
 733         gmc_v10_0_set_gfxhub_funcs(adev);
 734         gmc_v10_0_set_gmc_funcs(adev);
 735         gmc_v10_0_set_irq_funcs(adev);
 736         gmc_v10_0_set_umc_funcs(adev);
 737
 738         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 739         adev->gmc.shared_aperture_end =
 740                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 741         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 742         adev->gmc.private_aperture_end =
 743                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 744
 745         r = amdgpu_gmc_ras_early_init(adev);
 746         if (r)
 747                 return r;
 748
 749         return 0;
 750 }
 751
 752 static int gmc_v10_0_late_init(void *handle)
 753 {
 754         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 755         int r;
 756
 757         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 758         if (r)
 759                 return r;
 760
 761         r = amdgpu_gmc_ras_late_init(adev);
 762         if (r)
 763                 return r;
 764
 765         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 766 }
 767
 768 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 769                                         struct amdgpu_gmc *mc)
 770 {
 771         u64 base = 0;
 772
 773         base = adev->gfxhub.funcs->get_fb_location(adev);
 774
 775         /* add the xgmi offset of the physical node */
 776         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 777
 778         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 779         amdgpu_gmc_gart_location(adev, mc);
 780         amdgpu_gmc_agp_location(adev, mc);
 781
 782         /* base offset of vram pages */
 783         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
 784
 785         /* add the xgmi offset of the physical node */
 786         adev->vm_manager.vram_base_offset +=
 787                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 788 }
 789
 790 /**
 791  * gmc_v10_0_mc_init - initialize the memory controller driver params
 792  *
 793  * @adev: amdgpu_device pointer
 794  *
 795  * Look up the amount of vram, vram width, and decide how to place
 796  * vram and gart within the GPU's physical address space.
 797  * Returns 0 for success.
 798  */
 799 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 800 {
 801         int r;
 802
 803         /* size in MB on si */
 804         adev->gmc.mc_vram_size =
 805                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 806         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 807
 808         if (!(adev->flags & AMD_IS_APU)) {
 809                 r = amdgpu_device_resize_fb_bar(adev);
 810                 if (r)
 811                         return r;
 812         }
 813         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 814         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 815
 816 #ifdef CONFIG_X86_64
 817         if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
 818                 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
 819                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 820         }
 821 #endif
 822
 823         /* In case the PCI BAR is larger than the actual amount of vram */
 824         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 825         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 826                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 827
 828         /* set the gart size */
 829         if (amdgpu_gart_size == -1)
 830                 adev->gmc.gart_size = 512ULL << 20;
 831         else
 832                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 833
 834         gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
 835
 836         return 0;
 837 }
 838
 839 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
 840 {
 841         int r;
 842
 843         if (adev->gart.bo) {
 844                 WARN(1, "NAVI10 PCIE GART already initialized\n");
 845                 return 0;
 846         }
 847
 848         /* Initialize common gart structure */
 849         r = amdgpu_gart_init(adev);
 850         if (r)
 851                 return r;
 852
 853         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 854         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 855                                  AMDGPU_PTE_EXECUTABLE;
 856
 857         return amdgpu_gart_table_vram_alloc(adev);
 858 }
 859
 860 static int gmc_v10_0_sw_init(void *handle)
 861 {
 862         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 863         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 864
 865         adev->gfxhub.funcs->init(adev);
 866
 867         adev->mmhub.funcs->init(adev);
 868
 869         spin_lock_init(&adev->gmc.invalidate_lock);
 870
 871         if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
 872                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
 873                 adev->gmc.vram_width = 64;
 874         } else if (amdgpu_emu_mode == 1) {
 875                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 876                 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
 877         } else {
 878                 r = amdgpu_atomfirmware_get_vram_info(adev,
 879                                 &vram_width, &vram_type, &vram_vendor);
 880                 adev->gmc.vram_width = vram_width;
 881
 882                 adev->gmc.vram_type = vram_type;
 883                 adev->gmc.vram_vendor = vram_vendor;
 884         }
 885
 886         switch (adev->ip_versions[GC_HWIP][0]) {
 887         case IP_VERSION(10, 1, 10):
 888         case IP_VERSION(10, 1, 1):
 889         case IP_VERSION(10, 1, 2):
 890         case IP_VERSION(10, 1, 3):
 891         case IP_VERSION(10, 1, 4):
 892         case IP_VERSION(10, 3, 0):
 893         case IP_VERSION(10, 3, 2):
 894         case IP_VERSION(10, 3, 1):
 895         case IP_VERSION(10, 3, 4):
 896         case IP_VERSION(10, 3, 5):
 897         case IP_VERSION(10, 3, 6):
 898         case IP_VERSION(10, 3, 3):
 899         case IP_VERSION(10, 3, 7):
 900                 adev->num_vmhubs = 2;
 901                 /*
 902                  * To fulfill 4-level page support,
 903                  * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
 904                  * block size 512 (9bit)
 905                  */
 906                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 907                 break;
 908         default:
 909                 break;
 910         }
 911
 912         /* This interrupt is VMC page fault.*/
 913         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
 914                               VMC_1_0__SRCID__VM_FAULT,
 915                               &adev->gmc.vm_fault);
 916
 917         if (r)
 918                 return r;
 919
 920         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
 921                               UTCL2_1_0__SRCID__FAULT,
 922                               &adev->gmc.vm_fault);
 923         if (r)
 924                 return r;
 925
 926         if (!amdgpu_sriov_vf(adev)) {
 927                 /* interrupt sent to DF. */
 928                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
 929                                       &adev->gmc.ecc_irq);
 930                 if (r)
 931                         return r;
 932         }
 933
 934         /*
 935          * Set the internal MC address mask This is the max address of the GPU's
 936          * internal address space.
 937          */
 938         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 939
 940         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 941         if (r) {
 942                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 943                 return r;
 944         }
 945
 946         r = gmc_v10_0_mc_init(adev);
 947         if (r)
 948                 return r;
 949
 950         amdgpu_gmc_get_vbios_allocations(adev);
 951
 952         /* Memory manager */
 953         r = amdgpu_bo_init(adev);
 954         if (r)
 955                 return r;
 956
 957         r = gmc_v10_0_gart_init(adev);
 958         if (r)
 959                 return r;
 960
 961         /*
 962          * number of VMs
 963          * VMID 0 is reserved for System
 964          * amdgpu graphics/compute will use VMIDs 1-7
 965          * amdkfd will use VMIDs 8-15
 966          */
 967         adev->vm_manager.first_kfd_vmid = 8;
 968
 969         amdgpu_vm_manager_init(adev);
 970
 971         return 0;
 972 }
 973
 974 /**
 975  * gmc_v10_0_gart_fini - vm fini callback
 976  *
 977  * @adev: amdgpu_device pointer
 978  *
 979  * Tears down the driver GART/VM setup (CIK).
 980  */
 981 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
 982 {
 983         amdgpu_gart_table_vram_free(adev);
 984 }
 985
 986 static int gmc_v10_0_sw_fini(void *handle)
 987 {
 988         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 989
 990         amdgpu_vm_manager_fini(adev);
 991         gmc_v10_0_gart_fini(adev);
 992         amdgpu_gem_force_release(adev);
 993         amdgpu_bo_fini(adev);
 994
 995         return 0;
 996 }
 997
 998 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 999 {
1000 }
1001
1002 /**
1003  * gmc_v10_0_gart_enable - gart enable
1004  *
1005  * @adev: amdgpu_device pointer
1006  */
1007 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1008 {
1009         int r;
1010         bool value;
1011
1012         if (adev->gart.bo == NULL) {
1013                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1014                 return -EINVAL;
1015         }
1016
1017         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1018         r = adev->gfxhub.funcs->gart_enable(adev);
1019         if (r)
1020                 return r;
1021
1022         r = adev->mmhub.funcs->gart_enable(adev);
1023         if (r)
1024                 return r;
1025
1026         adev->hdp.funcs->init_registers(adev);
1027
1028         /* Flush HDP after it is initialized */
1029         adev->hdp.funcs->flush_hdp(adev, NULL);
1030
1031         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1032                 false : true;
1033
1034         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1035         adev->mmhub.funcs->set_fault_enable_default(adev, value);
1036         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1037         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1038
1039         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1040                  (unsigned)(adev->gmc.gart_size >> 20),
1041                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1042
1043         return 0;
1044 }
1045
1046 static int gmc_v10_0_hw_init(void *handle)
1047 {
1048         int r;
1049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050
1051         /* The sequence of these two function calls matters.*/
1052         gmc_v10_0_init_golden_registers(adev);
1053
1054         /*
1055          * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1056          * register setup within GMC, or else system hang when harvesting SA.
1057          */
1058         if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1059                 adev->gfxhub.funcs->utcl2_harvest(adev);
1060
1061         r = gmc_v10_0_gart_enable(adev);
1062         if (r)
1063                 return r;
1064
1065         if (amdgpu_emu_mode == 1) {
1066                 r = amdgpu_gmc_vram_checking(adev);
1067                 if (r)
1068                         return r;
1069         }
1070
1071         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1072                 adev->umc.funcs->init_registers(adev);
1073
1074         return 0;
1075 }
1076
1077 /**
1078  * gmc_v10_0_gart_disable - gart disable
1079  *
1080  * @adev: amdgpu_device pointer
1081  *
1082  * This disables all VM page table.
1083  */
1084 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1085 {
1086         adev->gfxhub.funcs->gart_disable(adev);
1087         adev->mmhub.funcs->gart_disable(adev);
1088 }
1089
1090 static int gmc_v10_0_hw_fini(void *handle)
1091 {
1092         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1093
1094         gmc_v10_0_gart_disable(adev);
1095
1096         if (amdgpu_sriov_vf(adev)) {
1097                 /* full access mode, so don't touch any GMC register */
1098                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1099                 return 0;
1100         }
1101
1102         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1103         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1104
1105         return 0;
1106 }
1107
1108 static int gmc_v10_0_suspend(void *handle)
1109 {
1110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111
1112         gmc_v10_0_hw_fini(adev);
1113
1114         return 0;
1115 }
1116
1117 static int gmc_v10_0_resume(void *handle)
1118 {
1119         int r;
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122         r = gmc_v10_0_hw_init(adev);
1123         if (r)
1124                 return r;
1125
1126         amdgpu_vmid_reset_all(adev);
1127
1128         return 0;
1129 }
1130
1131 static bool gmc_v10_0_is_idle(void *handle)
1132 {
1133         /* MC is always ready in GMC v10.*/
1134         return true;
1135 }
1136
1137 static int gmc_v10_0_wait_for_idle(void *handle)
1138 {
1139         /* There is no need to wait for MC idle in GMC v10.*/
1140         return 0;
1141 }
1142
1143 static int gmc_v10_0_soft_reset(void *handle)
1144 {
1145         return 0;
1146 }
1147
1148 static int gmc_v10_0_set_clockgating_state(void *handle,
1149                                            enum amd_clockgating_state state)
1150 {
1151         int r;
1152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153
1154         r = adev->mmhub.funcs->set_clockgating(adev, state);
1155         if (r)
1156                 return r;
1157
1158         if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1159                 return athub_v2_1_set_clockgating(adev, state);
1160         else
1161                 return athub_v2_0_set_clockgating(adev, state);
1162 }
1163
1164 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1165 {
1166         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167
1168         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) ||
1169             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4))
1170                 return;
1171
1172         adev->mmhub.funcs->get_clockgating(adev, flags);
1173
1174         if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1175                 athub_v2_1_get_clockgating(adev, flags);
1176         else
1177                 athub_v2_0_get_clockgating(adev, flags);
1178 }
1179
1180 static int gmc_v10_0_set_powergating_state(void *handle,
1181                                            enum amd_powergating_state state)
1182 {
1183         return 0;
1184 }
1185
1186 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1187         .name = "gmc_v10_0",
1188         .early_init = gmc_v10_0_early_init,
1189         .late_init = gmc_v10_0_late_init,
1190         .sw_init = gmc_v10_0_sw_init,
1191         .sw_fini = gmc_v10_0_sw_fini,
1192         .hw_init = gmc_v10_0_hw_init,
1193         .hw_fini = gmc_v10_0_hw_fini,
1194         .suspend = gmc_v10_0_suspend,
1195         .resume = gmc_v10_0_resume,
1196         .is_idle = gmc_v10_0_is_idle,
1197         .wait_for_idle = gmc_v10_0_wait_for_idle,
1198         .soft_reset = gmc_v10_0_soft_reset,
1199         .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1200         .set_powergating_state = gmc_v10_0_set_powergating_state,
1201         .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1202 };
1203
1204 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1205 {
1206         .type = AMD_IP_BLOCK_TYPE_GMC,
1207         .major = 10,
1208         .minor = 0,
1209         .rev = 0,
1210         .funcs = &gmc_v10_0_ip_funcs,
1211 };