drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /**
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 #define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 177 #define GFX_RLCG_GC_WRITE       (0x0 << 28)
 178 #define GFX_RLCG_GC_READ        (0x1 << 28)
 179 #define GFX_RLCG_MMHUB_WRITE    (0x2 << 28)
 180
 181 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 182 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 183 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 184 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 185 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 187
 188 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 199
 200 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 201 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 202 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 203 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 204 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 206
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 209 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 213
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 215 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 216 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 217 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 220
 221 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 222 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 223 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 224 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 225 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 227
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 230 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 234
 235 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 236 {
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 277 };
 278
 279 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 280 {
 281         /* Pending on emulation bring up */
 282 };
 283
 284 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 285 {
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1338 };
1339
1340 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1341 {
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1380 };
1381
1382 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1383 {
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1426 };
1427
1428 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write)
1429 {
1430         /* always programed by rlcg, only for gc */
1431         if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
1432             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
1433             offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
1434             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
1435             offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
1436             offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
1437                 if (!amdgpu_sriov_reg_indirect_gc(adev))
1438                         *flag = GFX_RLCG_GC_WRITE_OLD;
1439                 else
1440                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1441
1442                 return true;
1443         }
1444
1445         /* currently support gc read/write, mmhub write */
1446         if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
1447             offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
1448                 if (amdgpu_sriov_reg_indirect_gc(adev))
1449                         *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1450                 else
1451                         return false;
1452         } else {
1453                 if (amdgpu_sriov_reg_indirect_mmhub(adev))
1454                         *flag = GFX_RLCG_MMHUB_WRITE;
1455                 else
1456                         return false;
1457         }
1458
1459         return true;
1460 }
1461
1462 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1463 {
1464         static void *scratch_reg0;
1465         static void *scratch_reg1;
1466         static void *scratch_reg2;
1467         static void *scratch_reg3;
1468         static void *spare_int;
1469         static uint32_t grbm_cntl;
1470         static uint32_t grbm_idx;
1471         uint32_t i = 0;
1472         uint32_t retries = 50000;
1473         u32 ret = 0;
1474
1475         scratch_reg0 = adev->rmmio +
1476                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1477         scratch_reg1 = adev->rmmio +
1478                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1479         scratch_reg2 = adev->rmmio +
1480                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1481         scratch_reg3 = adev->rmmio +
1482                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1483         spare_int = adev->rmmio +
1484                     (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1485
1486         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1487         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1488
1489         if (offset == grbm_cntl || offset == grbm_idx) {
1490                 if (offset  == grbm_cntl)
1491                         writel(v, scratch_reg2);
1492                 else if (offset == grbm_idx)
1493                         writel(v, scratch_reg3);
1494
1495                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1496         } else {
1497                 writel(v, scratch_reg0);
1498                 writel(offset | flag, scratch_reg1);
1499                 writel(1, spare_int);
1500                 for (i = 0; i < retries; i++) {
1501                         u32 tmp;
1502
1503                         tmp = readl(scratch_reg1);
1504                         if (!(tmp & flag))
1505                                 break;
1506
1507                         udelay(10);
1508                 }
1509
1510                 if (i >= retries)
1511                         pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1512         }
1513
1514         ret = readl(scratch_reg0);
1515
1516         return ret;
1517 }
1518
1519 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag)
1520 {
1521         uint32_t rlcg_flag;
1522
1523         if (amdgpu_sriov_fullaccess(adev) &&
1524             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
1525                 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1526
1527                 return;
1528         }
1529         if (flag & AMDGPU_REGS_NO_KIQ)
1530                 WREG32_NO_KIQ(offset, value);
1531         else
1532                 WREG32(offset, value);
1533 }
1534
1535 static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag)
1536 {
1537         uint32_t rlcg_flag;
1538
1539         if (amdgpu_sriov_fullaccess(adev) &&
1540             gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
1541                 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1542
1543         if (flag & AMDGPU_REGS_NO_KIQ)
1544                 return RREG32_NO_KIQ(offset);
1545         else
1546                 return RREG32(offset);
1547
1548         return 0;
1549 }
1550
1551 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1552 {
1553         /* Pending on emulation bring up */
1554 };
1555
1556 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1557 {
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2178 };
2179
2180 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2181 {
2182         /* Pending on emulation bring up */
2183 };
2184
2185 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2186 {
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3239 };
3240
3241 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3242 {
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3285 };
3286
3287 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3288 {
3289         /* Pending on emulation bring up */
3290 };
3291
3292 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3293 {
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3335
3336         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3338 };
3339
3340 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3341 {
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3365
3366         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3368 };
3369
3370 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3371 {
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3407 };
3408
3409 #define DEFAULT_SH_MEM_CONFIG \
3410         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3411          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3412          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3413          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3414
3415
3416 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3417 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3418 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3419 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3420 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3421                                  struct amdgpu_cu_info *cu_info);
3422 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3423 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3424                                    u32 sh_num, u32 instance);
3425 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3426
3427 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3428 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3429 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3430 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3431 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3432 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3433 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3434 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3435 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3436 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3437
3438 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3439 {
3440         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3441         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3442                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3443         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3444         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3445         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3446         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3447         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3448         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3449 }
3450
3451 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3452                                  struct amdgpu_ring *ring)
3453 {
3454         struct amdgpu_device *adev = kiq_ring->adev;
3455         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3456         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3457         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3458
3459         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3460         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3461         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3462                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3463                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3464                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3465                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3466                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3467                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3468                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3469                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3470                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3471         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3472         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3473         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3474         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3475         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3476 }
3477
3478 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3479                                    struct amdgpu_ring *ring,
3480                                    enum amdgpu_unmap_queues_action action,
3481                                    u64 gpu_addr, u64 seq)
3482 {
3483         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3484
3485         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3486         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3487                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3488                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3489                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3490                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3491         amdgpu_ring_write(kiq_ring,
3492                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3493
3494         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3495                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3496                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3497                 amdgpu_ring_write(kiq_ring, seq);
3498         } else {
3499                 amdgpu_ring_write(kiq_ring, 0);
3500                 amdgpu_ring_write(kiq_ring, 0);
3501                 amdgpu_ring_write(kiq_ring, 0);
3502         }
3503 }
3504
3505 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3506                                    struct amdgpu_ring *ring,
3507                                    u64 addr,
3508                                    u64 seq)
3509 {
3510         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3511
3512         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3513         amdgpu_ring_write(kiq_ring,
3514                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3515                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3516                           PACKET3_QUERY_STATUS_COMMAND(2));
3517         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3518                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3519                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3520         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3521         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3522         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3523         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3524 }
3525
3526 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3527                                 uint16_t pasid, uint32_t flush_type,
3528                                 bool all_hub)
3529 {
3530         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3531         amdgpu_ring_write(kiq_ring,
3532                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3533                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3534                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3535                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3536 }
3537
3538 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3539         .kiq_set_resources = gfx10_kiq_set_resources,
3540         .kiq_map_queues = gfx10_kiq_map_queues,
3541         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3542         .kiq_query_status = gfx10_kiq_query_status,
3543         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3544         .set_resources_size = 8,
3545         .map_queues_size = 7,
3546         .unmap_queues_size = 6,
3547         .query_status_size = 7,
3548         .invalidate_tlbs_size = 2,
3549 };
3550
3551 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3552 {
3553         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3554 }
3555
3556 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3557 {
3558         switch (adev->asic_type) {
3559         case CHIP_NAVI10:
3560                 soc15_program_register_sequence(adev,
3561                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3562                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3563                 break;
3564         case CHIP_NAVI14:
3565                 soc15_program_register_sequence(adev,
3566                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3567                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3568                 break;
3569         case CHIP_NAVI12:
3570                 soc15_program_register_sequence(adev,
3571                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3572                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3573                 break;
3574         default:
3575                 break;
3576         }
3577 }
3578
3579 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3580 {
3581         switch (adev->asic_type) {
3582         case CHIP_NAVI10:
3583                 soc15_program_register_sequence(adev,
3584                                                 golden_settings_gc_10_1,
3585                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3586                 soc15_program_register_sequence(adev,
3587                                                 golden_settings_gc_10_0_nv10,
3588                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3589                 break;
3590         case CHIP_NAVI14:
3591                 soc15_program_register_sequence(adev,
3592                                                 golden_settings_gc_10_1_1,
3593                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3594                 soc15_program_register_sequence(adev,
3595                                                 golden_settings_gc_10_1_nv14,
3596                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3597                 break;
3598         case CHIP_NAVI12:
3599                 soc15_program_register_sequence(adev,
3600                                                 golden_settings_gc_10_1_2,
3601                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3602                 soc15_program_register_sequence(adev,
3603                                                 golden_settings_gc_10_1_2_nv12,
3604                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3605                 break;
3606         case CHIP_SIENNA_CICHLID:
3607                 soc15_program_register_sequence(adev,
3608                                                 golden_settings_gc_10_3,
3609                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3610                 soc15_program_register_sequence(adev,
3611                                                 golden_settings_gc_10_3_sienna_cichlid,
3612                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3613                 break;
3614         case CHIP_NAVY_FLOUNDER:
3615                 soc15_program_register_sequence(adev,
3616                                                 golden_settings_gc_10_3_2,
3617                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3618                 break;
3619         case CHIP_VANGOGH:
3620                 soc15_program_register_sequence(adev,
3621                                                 golden_settings_gc_10_3_vangogh,
3622                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3623                 break;
3624         case CHIP_DIMGREY_CAVEFISH:
3625                 soc15_program_register_sequence(adev,
3626                                                 golden_settings_gc_10_3_4,
3627                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3628                 break;
3629         default:
3630                 break;
3631         }
3632         gfx_v10_0_init_spm_golden_registers(adev);
3633 }
3634
3635 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3636 {
3637         adev->gfx.scratch.num_reg = 8;
3638         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3639         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3640 }
3641
3642 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3643                                        bool wc, uint32_t reg, uint32_t val)
3644 {
3645         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3646         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3647                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3648         amdgpu_ring_write(ring, reg);
3649         amdgpu_ring_write(ring, 0);
3650         amdgpu_ring_write(ring, val);
3651 }
3652
3653 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3654                                   int mem_space, int opt, uint32_t addr0,
3655                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3656                                   uint32_t inv)
3657 {
3658         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3659         amdgpu_ring_write(ring,
3660                           /* memory (1) or register (0) */
3661                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3662                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3663                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3664                            WAIT_REG_MEM_ENGINE(eng_sel)));
3665
3666         if (mem_space)
3667                 BUG_ON(addr0 & 0x3); /* Dword align */
3668         amdgpu_ring_write(ring, addr0);
3669         amdgpu_ring_write(ring, addr1);
3670         amdgpu_ring_write(ring, ref);
3671         amdgpu_ring_write(ring, mask);
3672         amdgpu_ring_write(ring, inv); /* poll interval */
3673 }
3674
3675 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3676 {
3677         struct amdgpu_device *adev = ring->adev;
3678         uint32_t scratch;
3679         uint32_t tmp = 0;
3680         unsigned i;
3681         int r;
3682
3683         r = amdgpu_gfx_scratch_get(adev, &scratch);
3684         if (r) {
3685                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3686                 return r;
3687         }
3688
3689         WREG32(scratch, 0xCAFEDEAD);
3690
3691         r = amdgpu_ring_alloc(ring, 3);
3692         if (r) {
3693                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3694                           ring->idx, r);
3695                 amdgpu_gfx_scratch_free(adev, scratch);
3696                 return r;
3697         }
3698
3699         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3700         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3701         amdgpu_ring_write(ring, 0xDEADBEEF);
3702         amdgpu_ring_commit(ring);
3703
3704         for (i = 0; i < adev->usec_timeout; i++) {
3705                 tmp = RREG32(scratch);
3706                 if (tmp == 0xDEADBEEF)
3707                         break;
3708                 if (amdgpu_emu_mode == 1)
3709                         msleep(1);
3710                 else
3711                         udelay(1);
3712         }
3713
3714         if (i >= adev->usec_timeout)
3715                 r = -ETIMEDOUT;
3716
3717         amdgpu_gfx_scratch_free(adev, scratch);
3718
3719         return r;
3720 }
3721
3722 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3723 {
3724         struct amdgpu_device *adev = ring->adev;
3725         struct amdgpu_ib ib;
3726         struct dma_fence *f = NULL;
3727         unsigned index;
3728         uint64_t gpu_addr;
3729         uint32_t tmp;
3730         long r;
3731
3732         r = amdgpu_device_wb_get(adev, &index);
3733         if (r)
3734                 return r;
3735
3736         gpu_addr = adev->wb.gpu_addr + (index * 4);
3737         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3738         memset(&ib, 0, sizeof(ib));
3739         r = amdgpu_ib_get(adev, NULL, 16,
3740                                         AMDGPU_IB_POOL_DIRECT, &ib);
3741         if (r)
3742                 goto err1;
3743
3744         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3745         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3746         ib.ptr[2] = lower_32_bits(gpu_addr);
3747         ib.ptr[3] = upper_32_bits(gpu_addr);
3748         ib.ptr[4] = 0xDEADBEEF;
3749         ib.length_dw = 5;
3750
3751         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3752         if (r)
3753                 goto err2;
3754
3755         r = dma_fence_wait_timeout(f, false, timeout);
3756         if (r == 0) {
3757                 r = -ETIMEDOUT;
3758                 goto err2;
3759         } else if (r < 0) {
3760                 goto err2;
3761         }
3762
3763         tmp = adev->wb.wb[index];
3764         if (tmp == 0xDEADBEEF)
3765                 r = 0;
3766         else
3767                 r = -EINVAL;
3768 err2:
3769         amdgpu_ib_free(adev, &ib, NULL);
3770         dma_fence_put(f);
3771 err1:
3772         amdgpu_device_wb_free(adev, index);
3773         return r;
3774 }
3775
3776 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3777 {
3778         release_firmware(adev->gfx.pfp_fw);
3779         adev->gfx.pfp_fw = NULL;
3780         release_firmware(adev->gfx.me_fw);
3781         adev->gfx.me_fw = NULL;
3782         release_firmware(adev->gfx.ce_fw);
3783         adev->gfx.ce_fw = NULL;
3784         release_firmware(adev->gfx.rlc_fw);
3785         adev->gfx.rlc_fw = NULL;
3786         release_firmware(adev->gfx.mec_fw);
3787         adev->gfx.mec_fw = NULL;
3788         release_firmware(adev->gfx.mec2_fw);
3789         adev->gfx.mec2_fw = NULL;
3790
3791         kfree(adev->gfx.rlc.register_list_format);
3792 }
3793
3794 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3795 {
3796         adev->gfx.cp_fw_write_wait = false;
3797
3798         switch (adev->asic_type) {
3799         case CHIP_NAVI10:
3800         case CHIP_NAVI12:
3801         case CHIP_NAVI14:
3802                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3803                     (adev->gfx.me_feature_version >= 27) &&
3804                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3805                     (adev->gfx.pfp_feature_version >= 27) &&
3806                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3807                     (adev->gfx.mec_feature_version >= 27))
3808                         adev->gfx.cp_fw_write_wait = true;
3809                 break;
3810         case CHIP_SIENNA_CICHLID:
3811         case CHIP_NAVY_FLOUNDER:
3812         case CHIP_VANGOGH:
3813         case CHIP_DIMGREY_CAVEFISH:
3814                 adev->gfx.cp_fw_write_wait = true;
3815                 break;
3816         default:
3817                 break;
3818         }
3819
3820         if (!adev->gfx.cp_fw_write_wait)
3821                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3822 }
3823
3824
3825 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3826 {
3827         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3828
3829         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3830         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3831         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3832         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3833         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3834         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3835         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3836         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3837         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3838         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3839         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3840         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3841         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3842         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3843                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3844 }
3845
3846 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3847 {
3848         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3849
3850         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3851         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3852         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3853         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3854         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3855 }
3856
3857 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3858 {
3859         bool ret = false;
3860
3861         switch (adev->pdev->revision) {
3862         case 0xc2:
3863         case 0xc3:
3864                 ret = true;
3865                 break;
3866         default:
3867                 ret = false;
3868                 break;
3869         }
3870
3871         return ret ;
3872 }
3873
3874 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3875 {
3876         switch (adev->asic_type) {
3877         case CHIP_NAVI10:
3878                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3879                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3880                 break;
3881         default:
3882                 break;
3883         }
3884 }
3885
3886 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3887 {
3888         const char *chip_name;
3889         char fw_name[40];
3890         char wks[10];
3891         int err;
3892         struct amdgpu_firmware_info *info = NULL;
3893         const struct common_firmware_header *header = NULL;
3894         const struct gfx_firmware_header_v1_0 *cp_hdr;
3895         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3896         unsigned int *tmp = NULL;
3897         unsigned int i = 0;
3898         uint16_t version_major;
3899         uint16_t version_minor;
3900
3901         DRM_DEBUG("\n");
3902
3903         memset(wks, 0, sizeof(wks));
3904         switch (adev->asic_type) {
3905         case CHIP_NAVI10:
3906                 chip_name = "navi10";
3907                 break;
3908         case CHIP_NAVI14:
3909                 chip_name = "navi14";
3910                 if (!(adev->pdev->device == 0x7340 &&
3911                       adev->pdev->revision != 0x00))
3912                         snprintf(wks, sizeof(wks), "_wks");
3913                 break;
3914         case CHIP_NAVI12:
3915                 chip_name = "navi12";
3916                 break;
3917         case CHIP_SIENNA_CICHLID:
3918                 chip_name = "sienna_cichlid";
3919                 break;
3920         case CHIP_NAVY_FLOUNDER:
3921                 chip_name = "navy_flounder";
3922                 break;
3923         case CHIP_VANGOGH:
3924                 chip_name = "vangogh";
3925                 break;
3926         case CHIP_DIMGREY_CAVEFISH:
3927                 chip_name = "dimgrey_cavefish";
3928                 break;
3929         default:
3930                 BUG();
3931         }
3932
3933         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3934         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3935         if (err)
3936                 goto out;
3937         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3938         if (err)
3939                 goto out;
3940         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3941         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3942         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3943
3944         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3945         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3946         if (err)
3947                 goto out;
3948         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3949         if (err)
3950                 goto out;
3951         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3952         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3953         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3954
3955         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3956         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3957         if (err)
3958                 goto out;
3959         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3960         if (err)
3961                 goto out;
3962         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3963         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3964         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3965
3966         if (!amdgpu_sriov_vf(adev)) {
3967                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3968                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3969                 if (err)
3970                         goto out;
3971                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3972                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3973                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3974                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3975
3976                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3977                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3978                 adev->gfx.rlc.save_and_restore_offset =
3979                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3980                 adev->gfx.rlc.clear_state_descriptor_offset =
3981                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3982                 adev->gfx.rlc.avail_scratch_ram_locations =
3983                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3984                 adev->gfx.rlc.reg_restore_list_size =
3985                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3986                 adev->gfx.rlc.reg_list_format_start =
3987                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3988                 adev->gfx.rlc.reg_list_format_separate_start =
3989                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3990                 adev->gfx.rlc.starting_offsets_start =
3991                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3992                 adev->gfx.rlc.reg_list_format_size_bytes =
3993                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3994                 adev->gfx.rlc.reg_list_size_bytes =
3995                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3996                 adev->gfx.rlc.register_list_format =
3997                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3998                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3999                 if (!adev->gfx.rlc.register_list_format) {
4000                         err = -ENOMEM;
4001                         goto out;
4002                 }
4003
4004                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4005                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4006                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4007                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4008
4009                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4010
4011                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4012                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4013                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4014                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4015
4016                 if (version_major == 2) {
4017                         if (version_minor >= 1)
4018                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4019                         if (version_minor == 2)
4020                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4021                 }
4022         }
4023
4024         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4025         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4026         if (err)
4027                 goto out;
4028         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4029         if (err)
4030                 goto out;
4031         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4032         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4033         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4034
4035         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4036         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4037         if (!err) {
4038                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4039                 if (err)
4040                         goto out;
4041                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4042                 adev->gfx.mec2_fw->data;
4043                 adev->gfx.mec2_fw_version =
4044                 le32_to_cpu(cp_hdr->header.ucode_version);
4045                 adev->gfx.mec2_feature_version =
4046                 le32_to_cpu(cp_hdr->ucode_feature_version);
4047         } else {
4048                 err = 0;
4049                 adev->gfx.mec2_fw = NULL;
4050         }
4051
4052         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4053                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4054                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4055                 info->fw = adev->gfx.pfp_fw;
4056                 header = (const struct common_firmware_header *)info->fw->data;
4057                 adev->firmware.fw_size +=
4058                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4059
4060                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4061                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4062                 info->fw = adev->gfx.me_fw;
4063                 header = (const struct common_firmware_header *)info->fw->data;
4064                 adev->firmware.fw_size +=
4065                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4066
4067                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4068                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4069                 info->fw = adev->gfx.ce_fw;
4070                 header = (const struct common_firmware_header *)info->fw->data;
4071                 adev->firmware.fw_size +=
4072                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4073
4074                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4075                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4076                 info->fw = adev->gfx.rlc_fw;
4077                 if (info->fw) {
4078                         header = (const struct common_firmware_header *)info->fw->data;
4079                         adev->firmware.fw_size +=
4080                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4081                 }
4082                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4083                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4084                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4085                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4086                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4087                         info->fw = adev->gfx.rlc_fw;
4088                         adev->firmware.fw_size +=
4089                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4090
4091                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4092                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4093                         info->fw = adev->gfx.rlc_fw;
4094                         adev->firmware.fw_size +=
4095                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4096
4097                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4098                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4099                         info->fw = adev->gfx.rlc_fw;
4100                         adev->firmware.fw_size +=
4101                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4102
4103                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4104                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4105                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4106                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4107                                 info->fw = adev->gfx.rlc_fw;
4108                                 adev->firmware.fw_size +=
4109                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4110
4111                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4112                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4113                                 info->fw = adev->gfx.rlc_fw;
4114                                 adev->firmware.fw_size +=
4115                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4116                         }
4117                 }
4118
4119                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4120                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4121                 info->fw = adev->gfx.mec_fw;
4122                 header = (const struct common_firmware_header *)info->fw->data;
4123                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4124                 adev->firmware.fw_size +=
4125                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4126                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4127
4128                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4129                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4130                 info->fw = adev->gfx.mec_fw;
4131                 adev->firmware.fw_size +=
4132                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4133
4134                 if (adev->gfx.mec2_fw) {
4135                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4136                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4137                         info->fw = adev->gfx.mec2_fw;
4138                         header = (const struct common_firmware_header *)info->fw->data;
4139                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4140                         adev->firmware.fw_size +=
4141                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4142                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4143                                       PAGE_SIZE);
4144                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4145                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4146                         info->fw = adev->gfx.mec2_fw;
4147                         adev->firmware.fw_size +=
4148                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4149                                       PAGE_SIZE);
4150                 }
4151         }
4152
4153         gfx_v10_0_check_fw_write_wait(adev);
4154 out:
4155         if (err) {
4156                 dev_err(adev->dev,
4157                         "gfx10: Failed to load firmware \"%s\"\n",
4158                         fw_name);
4159                 release_firmware(adev->gfx.pfp_fw);
4160                 adev->gfx.pfp_fw = NULL;
4161                 release_firmware(adev->gfx.me_fw);
4162                 adev->gfx.me_fw = NULL;
4163                 release_firmware(adev->gfx.ce_fw);
4164                 adev->gfx.ce_fw = NULL;
4165                 release_firmware(adev->gfx.rlc_fw);
4166                 adev->gfx.rlc_fw = NULL;
4167                 release_firmware(adev->gfx.mec_fw);
4168                 adev->gfx.mec_fw = NULL;
4169                 release_firmware(adev->gfx.mec2_fw);
4170                 adev->gfx.mec2_fw = NULL;
4171         }
4172
4173         gfx_v10_0_check_gfxoff_flag(adev);
4174
4175         return err;
4176 }
4177
4178 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4179 {
4180         u32 count = 0;
4181         const struct cs_section_def *sect = NULL;
4182         const struct cs_extent_def *ext = NULL;
4183
4184         /* begin clear state */
4185         count += 2;
4186         /* context control state */
4187         count += 3;
4188
4189         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4190                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4191                         if (sect->id == SECT_CONTEXT)
4192                                 count += 2 + ext->reg_count;
4193                         else
4194                                 return 0;
4195                 }
4196         }
4197
4198         /* set PA_SC_TILE_STEERING_OVERRIDE */
4199         count += 3;
4200         /* end clear state */
4201         count += 2;
4202         /* clear state */
4203         count += 2;
4204
4205         return count;
4206 }
4207
4208 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4209                                     volatile u32 *buffer)
4210 {
4211         u32 count = 0, i;
4212         const struct cs_section_def *sect = NULL;
4213         const struct cs_extent_def *ext = NULL;
4214         int ctx_reg_offset;
4215
4216         if (adev->gfx.rlc.cs_data == NULL)
4217                 return;
4218         if (buffer == NULL)
4219                 return;
4220
4221         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4222         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4223
4224         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4225         buffer[count++] = cpu_to_le32(0x80000000);
4226         buffer[count++] = cpu_to_le32(0x80000000);
4227
4228         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4229                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4230                         if (sect->id == SECT_CONTEXT) {
4231                                 buffer[count++] =
4232                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4233                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4234                                                 PACKET3_SET_CONTEXT_REG_START);
4235                                 for (i = 0; i < ext->reg_count; i++)
4236                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4237                         } else {
4238                                 return;
4239                         }
4240                 }
4241         }
4242
4243         ctx_reg_offset =
4244                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4245         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4246         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4247         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4248
4249         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4250         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4251
4252         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4253         buffer[count++] = cpu_to_le32(0);
4254 }
4255
4256 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4257 {
4258         /* clear state block */
4259         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4260                         &adev->gfx.rlc.clear_state_gpu_addr,
4261                         (void **)&adev->gfx.rlc.cs_ptr);
4262
4263         /* jump table block */
4264         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4265                         &adev->gfx.rlc.cp_table_gpu_addr,
4266                         (void **)&adev->gfx.rlc.cp_table_ptr);
4267 }
4268
4269 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4270 {
4271         const struct cs_section_def *cs_data;
4272         int r;
4273
4274         adev->gfx.rlc.cs_data = gfx10_cs_data;
4275
4276         cs_data = adev->gfx.rlc.cs_data;
4277
4278         if (cs_data) {
4279                 /* init clear state block */
4280                 r = amdgpu_gfx_rlc_init_csb(adev);
4281                 if (r)
4282                         return r;
4283         }
4284
4285         /* init spm vmid with 0xf */
4286         if (adev->gfx.rlc.funcs->update_spm_vmid)
4287                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4288
4289         return 0;
4290 }
4291
4292 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4293 {
4294         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4295         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4296 }
4297
4298 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4299 {
4300         int r;
4301
4302         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4303
4304         amdgpu_gfx_graphics_queue_acquire(adev);
4305
4306         r = gfx_v10_0_init_microcode(adev);
4307         if (r)
4308                 DRM_ERROR("Failed to load gfx firmware!\n");
4309
4310         return r;
4311 }
4312
4313 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4314 {
4315         int r;
4316         u32 *hpd;
4317         const __le32 *fw_data = NULL;
4318         unsigned fw_size;
4319         u32 *fw = NULL;
4320         size_t mec_hpd_size;
4321
4322         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4323
4324         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4325
4326         /* take ownership of the relevant compute queues */
4327         amdgpu_gfx_compute_queue_acquire(adev);
4328         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4329
4330         if (mec_hpd_size) {
4331                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4332                                               AMDGPU_GEM_DOMAIN_GTT,
4333                                               &adev->gfx.mec.hpd_eop_obj,
4334                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4335                                               (void **)&hpd);
4336                 if (r) {
4337                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4338                         gfx_v10_0_mec_fini(adev);
4339                         return r;
4340                 }
4341
4342                 memset(hpd, 0, mec_hpd_size);
4343
4344                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4345                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4346         }
4347
4348         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4349                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4350
4351                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4352                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4353                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4354
4355                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4356                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4357                                               &adev->gfx.mec.mec_fw_obj,
4358                                               &adev->gfx.mec.mec_fw_gpu_addr,
4359                                               (void **)&fw);
4360                 if (r) {
4361                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4362                         gfx_v10_0_mec_fini(adev);
4363                         return r;
4364                 }
4365
4366                 memcpy(fw, fw_data, fw_size);
4367
4368                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4369                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4370         }
4371
4372         return 0;
4373 }
4374
4375 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4376 {
4377         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4378                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4379                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4380         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4381 }
4382
4383 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4384                            uint32_t thread, uint32_t regno,
4385                            uint32_t num, uint32_t *out)
4386 {
4387         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4388                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4389                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4390                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4391                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4392         while (num--)
4393                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4394 }
4395
4396 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4397 {
4398         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4399          * field when performing a select_se_sh so it should be
4400          * zero here */
4401         WARN_ON(simd != 0);
4402
4403         /* type 2 wave data */
4404         dst[(*no_fields)++] = 2;
4405         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4406         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4407         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4408         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4409         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4410         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4411         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4412         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4413         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4414         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4415         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4416         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4417         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4418         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4419         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4420 }
4421
4422 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4423                                      uint32_t wave, uint32_t start,
4424                                      uint32_t size, uint32_t *dst)
4425 {
4426         WARN_ON(simd != 0);
4427
4428         wave_read_regs(
4429                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4430                 dst);
4431 }
4432
4433 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4434                                       uint32_t wave, uint32_t thread,
4435                                       uint32_t start, uint32_t size,
4436                                       uint32_t *dst)
4437 {
4438         wave_read_regs(
4439                 adev, wave, thread,
4440                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4441 }
4442
4443 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4444                                        u32 me, u32 pipe, u32 q, u32 vm)
4445 {
4446         nv_grbm_select(adev, me, pipe, q, vm);
4447 }
4448
4449 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4450                                           bool enable)
4451 {
4452         uint32_t data, def;
4453
4454         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4455
4456         if (enable)
4457                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4458         else
4459                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4460
4461         if (data != def)
4462                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4463 }
4464
4465 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4466         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4467         .select_se_sh = &gfx_v10_0_select_se_sh,
4468         .read_wave_data = &gfx_v10_0_read_wave_data,
4469         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4470         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4471         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4472         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4473         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4474 };
4475
4476 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4477 {
4478         u32 gb_addr_config;
4479
4480         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4481
4482         switch (adev->asic_type) {
4483         case CHIP_NAVI10:
4484         case CHIP_NAVI14:
4485         case CHIP_NAVI12:
4486                 adev->gfx.config.max_hw_contexts = 8;
4487                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4488                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4489                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4490                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4491                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4492                 break;
4493         case CHIP_SIENNA_CICHLID:
4494         case CHIP_NAVY_FLOUNDER:
4495         case CHIP_VANGOGH:
4496         case CHIP_DIMGREY_CAVEFISH:
4497                 adev->gfx.config.max_hw_contexts = 8;
4498                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4499                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4500                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4501                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4502                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4503                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4504                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4505                 break;
4506         default:
4507                 BUG();
4508                 break;
4509         }
4510
4511         adev->gfx.config.gb_addr_config = gb_addr_config;
4512
4513         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4514                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4515                                       GB_ADDR_CONFIG, NUM_PIPES);
4516
4517         adev->gfx.config.max_tile_pipes =
4518                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4519
4520         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4521                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4522                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4523         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4524                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4525                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4526         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4527                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4528                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4529         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4530                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4531                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4532 }
4533
4534 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4535                                    int me, int pipe, int queue)
4536 {
4537         int r;
4538         struct amdgpu_ring *ring;
4539         unsigned int irq_type;
4540
4541         ring = &adev->gfx.gfx_ring[ring_id];
4542
4543         ring->me = me;
4544         ring->pipe = pipe;
4545         ring->queue = queue;
4546
4547         ring->ring_obj = NULL;
4548         ring->use_doorbell = true;
4549
4550         if (!ring_id)
4551                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4552         else
4553                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4554         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4555
4556         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4557         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4558                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4559         if (r)
4560                 return r;
4561         return 0;
4562 }
4563
4564 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4565                                        int mec, int pipe, int queue)
4566 {
4567         int r;
4568         unsigned irq_type;
4569         struct amdgpu_ring *ring;
4570         unsigned int hw_prio;
4571
4572         ring = &adev->gfx.compute_ring[ring_id];
4573
4574         /* mec0 is me1 */
4575         ring->me = mec + 1;
4576         ring->pipe = pipe;
4577         ring->queue = queue;
4578
4579         ring->ring_obj = NULL;
4580         ring->use_doorbell = true;
4581         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4582         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4583                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4584         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4585
4586         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4587                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4588                 + ring->pipe;
4589         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4590                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4591         /* type-2 packets are deprecated on MEC, use type-3 instead */
4592         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4593                              hw_prio, NULL);
4594         if (r)
4595                 return r;
4596
4597         return 0;
4598 }
4599
4600 static int gfx_v10_0_sw_init(void *handle)
4601 {
4602         int i, j, k, r, ring_id = 0;
4603         struct amdgpu_kiq *kiq;
4604         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4605
4606         switch (adev->asic_type) {
4607         case CHIP_NAVI10:
4608         case CHIP_NAVI14:
4609         case CHIP_NAVI12:
4610                 adev->gfx.me.num_me = 1;
4611                 adev->gfx.me.num_pipe_per_me = 1;
4612                 adev->gfx.me.num_queue_per_pipe = 1;
4613                 adev->gfx.mec.num_mec = 2;
4614                 adev->gfx.mec.num_pipe_per_mec = 4;
4615                 adev->gfx.mec.num_queue_per_pipe = 8;
4616                 break;
4617         case CHIP_SIENNA_CICHLID:
4618         case CHIP_NAVY_FLOUNDER:
4619         case CHIP_VANGOGH:
4620         case CHIP_DIMGREY_CAVEFISH:
4621                 adev->gfx.me.num_me = 1;
4622                 adev->gfx.me.num_pipe_per_me = 1;
4623                 adev->gfx.me.num_queue_per_pipe = 1;
4624                 adev->gfx.mec.num_mec = 2;
4625                 adev->gfx.mec.num_pipe_per_mec = 4;
4626                 adev->gfx.mec.num_queue_per_pipe = 4;
4627                 break;
4628         default:
4629                 adev->gfx.me.num_me = 1;
4630                 adev->gfx.me.num_pipe_per_me = 1;
4631                 adev->gfx.me.num_queue_per_pipe = 1;
4632                 adev->gfx.mec.num_mec = 1;
4633                 adev->gfx.mec.num_pipe_per_mec = 4;
4634                 adev->gfx.mec.num_queue_per_pipe = 8;
4635                 break;
4636         }
4637
4638         /* KIQ event */
4639         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4640                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4641                               &adev->gfx.kiq.irq);
4642         if (r)
4643                 return r;
4644
4645         /* EOP Event */
4646         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4647                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4648                               &adev->gfx.eop_irq);
4649         if (r)
4650                 return r;
4651
4652         /* Privileged reg */
4653         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4654                               &adev->gfx.priv_reg_irq);
4655         if (r)
4656                 return r;
4657
4658         /* Privileged inst */
4659         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4660                               &adev->gfx.priv_inst_irq);
4661         if (r)
4662                 return r;
4663
4664         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4665
4666         gfx_v10_0_scratch_init(adev);
4667
4668         r = gfx_v10_0_me_init(adev);
4669         if (r)
4670                 return r;
4671
4672         r = gfx_v10_0_rlc_init(adev);
4673         if (r) {
4674                 DRM_ERROR("Failed to init rlc BOs!\n");
4675                 return r;
4676         }
4677
4678         r = gfx_v10_0_mec_init(adev);
4679         if (r) {
4680                 DRM_ERROR("Failed to init MEC BOs!\n");
4681                 return r;
4682         }
4683
4684         /* set up the gfx ring */
4685         for (i = 0; i < adev->gfx.me.num_me; i++) {
4686                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4687                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4688                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4689                                         continue;
4690
4691                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4692                                                             i, k, j);
4693                                 if (r)
4694                                         return r;
4695                                 ring_id++;
4696                         }
4697                 }
4698         }
4699
4700         ring_id = 0;
4701         /* set up the compute queues - allocate horizontally across pipes */
4702         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4703                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4704                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4705                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4706                                                                      j))
4707                                         continue;
4708
4709                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4710                                                                 i, k, j);
4711                                 if (r)
4712                                         return r;
4713
4714                                 ring_id++;
4715                         }
4716                 }
4717         }
4718
4719         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4720         if (r) {
4721                 DRM_ERROR("Failed to init KIQ BOs!\n");
4722                 return r;
4723         }
4724
4725         kiq = &adev->gfx.kiq;
4726         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4727         if (r)
4728                 return r;
4729
4730         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4731         if (r)
4732                 return r;
4733
4734         /* allocate visible FB for rlc auto-loading fw */
4735         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4736                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4737                 if (r)
4738                         return r;
4739         }
4740
4741         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4742
4743         gfx_v10_0_gpu_early_init(adev);
4744
4745         return 0;
4746 }
4747
4748 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4749 {
4750         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4751                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4752                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4753 }
4754
4755 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4756 {
4757         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4758                               &adev->gfx.ce.ce_fw_gpu_addr,
4759                               (void **)&adev->gfx.ce.ce_fw_ptr);
4760 }
4761
4762 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4763 {
4764         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4765                               &adev->gfx.me.me_fw_gpu_addr,
4766                               (void **)&adev->gfx.me.me_fw_ptr);
4767 }
4768
4769 static int gfx_v10_0_sw_fini(void *handle)
4770 {
4771         int i;
4772         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4773
4774         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4775                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4776         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4777                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4778
4779         amdgpu_gfx_mqd_sw_fini(adev);
4780         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4781         amdgpu_gfx_kiq_fini(adev);
4782
4783         gfx_v10_0_pfp_fini(adev);
4784         gfx_v10_0_ce_fini(adev);
4785         gfx_v10_0_me_fini(adev);
4786         gfx_v10_0_rlc_fini(adev);
4787         gfx_v10_0_mec_fini(adev);
4788
4789         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4790                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4791
4792         gfx_v10_0_free_microcode(adev);
4793
4794         return 0;
4795 }
4796
4797 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4798                                    u32 sh_num, u32 instance)
4799 {
4800         u32 data;
4801
4802         if (instance == 0xffffffff)
4803                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4804                                      INSTANCE_BROADCAST_WRITES, 1);
4805         else
4806                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4807                                      instance);
4808
4809         if (se_num == 0xffffffff)
4810                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4811                                      1);
4812         else
4813                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4814
4815         if (sh_num == 0xffffffff)
4816                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4817                                      1);
4818         else
4819                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4820
4821         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4822 }
4823
4824 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4825 {
4826         u32 data, mask;
4827
4828         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4829         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4830
4831         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4832         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4833
4834         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4835                                          adev->gfx.config.max_sh_per_se);
4836
4837         return (~data) & mask;
4838 }
4839
4840 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4841 {
4842         int i, j;
4843         u32 data;
4844         u32 active_rbs = 0;
4845         u32 bitmap;
4846         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4847                                         adev->gfx.config.max_sh_per_se;
4848
4849         mutex_lock(&adev->grbm_idx_mutex);
4850         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4851                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4852                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4853                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4854                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4855                                 continue;
4856                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4857                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4858                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4859                                                rb_bitmap_width_per_sh);
4860                 }
4861         }
4862         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4863         mutex_unlock(&adev->grbm_idx_mutex);
4864
4865         adev->gfx.config.backend_enable_mask = active_rbs;
4866         adev->gfx.config.num_rbs = hweight32(active_rbs);
4867 }
4868
4869 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4870 {
4871         uint32_t num_sc;
4872         uint32_t enabled_rb_per_sh;
4873         uint32_t active_rb_bitmap;
4874         uint32_t num_rb_per_sc;
4875         uint32_t num_packer_per_sc;
4876         uint32_t pa_sc_tile_steering_override;
4877
4878         /* for ASICs that integrates GFX v10.3
4879          * pa_sc_tile_steering_override should be set to 0 */
4880         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4881                 return 0;
4882
4883         /* init num_sc */
4884         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4885                         adev->gfx.config.num_sc_per_sh;
4886         /* init num_rb_per_sc */
4887         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4888         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4889         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4890         /* init num_packer_per_sc */
4891         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4892
4893         pa_sc_tile_steering_override = 0;
4894         pa_sc_tile_steering_override |=
4895                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4896                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4897         pa_sc_tile_steering_override |=
4898                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4899                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4900         pa_sc_tile_steering_override |=
4901                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4902                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4903
4904         return pa_sc_tile_steering_override;
4905 }
4906
4907 #define DEFAULT_SH_MEM_BASES    (0x6000)
4908
4909 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4910 {
4911         int i;
4912         uint32_t sh_mem_bases;
4913
4914         /*
4915          * Configure apertures:
4916          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4917          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4918          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4919          */
4920         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4921
4922         mutex_lock(&adev->srbm_mutex);
4923         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4924                 nv_grbm_select(adev, 0, 0, 0, i);
4925                 /* CP and shaders */
4926                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4927                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4928         }
4929         nv_grbm_select(adev, 0, 0, 0, 0);
4930         mutex_unlock(&adev->srbm_mutex);
4931
4932         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4933            acccess. These should be enabled by FW for target VMIDs. */
4934         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4935                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4936                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4937                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4938                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4939         }
4940 }
4941
4942 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4943 {
4944         int vmid;
4945
4946         /*
4947          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4948          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4949          * the driver can enable them for graphics. VMID0 should maintain
4950          * access so that HWS firmware can save/restore entries.
4951          */
4952         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4953                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4954                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4955                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4956                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4957         }
4958 }
4959
4960
4961 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4962 {
4963         int i, j, k;
4964         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4965         u32 tmp, wgp_active_bitmap = 0;
4966         u32 gcrd_targets_disable_tcp = 0;
4967         u32 utcl_invreq_disable = 0;
4968         /*
4969          * GCRD_TARGETS_DISABLE field contains
4970          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4971          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4972          */
4973         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4974                 2 * max_wgp_per_sh + /* TCP */
4975                 max_wgp_per_sh + /* SQC */
4976                 4); /* GL1C */
4977         /*
4978          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4979          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4980          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4981          */
4982         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4983                 2 * max_wgp_per_sh + /* TCP */
4984                 2 * max_wgp_per_sh + /* SQC */
4985                 4 + /* RMI */
4986                 1); /* SQG */
4987
4988         if (adev->asic_type == CHIP_NAVI10 ||
4989             adev->asic_type == CHIP_NAVI14 ||
4990             adev->asic_type == CHIP_NAVI12) {
4991                 mutex_lock(&adev->grbm_idx_mutex);
4992                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4993                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4994                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4995                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4996                                 /*
4997                                  * Set corresponding TCP bits for the inactive WGPs in
4998                                  * GCRD_SA_TARGETS_DISABLE
4999                                  */
5000                                 gcrd_targets_disable_tcp = 0;
5001                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5002                                 utcl_invreq_disable = 0;
5003
5004                                 for (k = 0; k < max_wgp_per_sh; k++) {
5005                                         if (!(wgp_active_bitmap & (1 << k))) {
5006                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
5007                                                 utcl_invreq_disable |= (3 << (2 * k)) |
5008                                                         (3 << (2 * (max_wgp_per_sh + k)));
5009                                         }
5010                                 }
5011
5012                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5013                                 /* only override TCP & SQC bits */
5014                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
5015                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5016                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5017
5018                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5019                                 /* only override TCP bits */
5020                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
5021                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5022                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5023                         }
5024                 }
5025
5026                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5027                 mutex_unlock(&adev->grbm_idx_mutex);
5028         }
5029 }
5030
5031 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5032 {
5033         /* TCCs are global (not instanced). */
5034         uint32_t tcc_disable;
5035
5036         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5037                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5038                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5039         } else {
5040                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5041                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5042         }
5043
5044         adev->gfx.config.tcc_disabled_mask =
5045                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5046                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5047 }
5048
5049 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5050 {
5051         u32 tmp;
5052         int i;
5053
5054         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5055
5056         gfx_v10_0_setup_rb(adev);
5057         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5058         gfx_v10_0_get_tcc_info(adev);
5059         adev->gfx.config.pa_sc_tile_steering_override =
5060                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5061
5062         /* XXX SH_MEM regs */
5063         /* where to put LDS, scratch, GPUVM in FSA64 space */
5064         mutex_lock(&adev->srbm_mutex);
5065         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5066                 nv_grbm_select(adev, 0, 0, 0, i);
5067                 /* CP and shaders */
5068                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5069                 if (i != 0) {
5070                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5071                                 (adev->gmc.private_aperture_start >> 48));
5072                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5073                                 (adev->gmc.shared_aperture_start >> 48));
5074                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5075                 }
5076         }
5077         nv_grbm_select(adev, 0, 0, 0, 0);
5078
5079         mutex_unlock(&adev->srbm_mutex);
5080
5081         gfx_v10_0_init_compute_vmid(adev);
5082         gfx_v10_0_init_gds_vmid(adev);
5083
5084 }
5085
5086 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5087                                                bool enable)
5088 {
5089         u32 tmp;
5090
5091         if (amdgpu_sriov_vf(adev))
5092                 return;
5093
5094         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5095
5096         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5097                             enable ? 1 : 0);
5098         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5099                             enable ? 1 : 0);
5100         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5101                             enable ? 1 : 0);
5102         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5103                             enable ? 1 : 0);
5104
5105         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5106 }
5107
5108 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5109 {
5110         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5111
5112         /* csib */
5113         if (adev->asic_type == CHIP_NAVI12) {
5114                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5115                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5116                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5117                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5118                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5119         } else {
5120                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5121                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5122                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5123                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5124                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5125         }
5126         return 0;
5127 }
5128
5129 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5130 {
5131         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5132
5133         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5134         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5135 }
5136
5137 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5138 {
5139         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5140         udelay(50);
5141         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5142         udelay(50);
5143 }
5144
5145 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5146                                              bool enable)
5147 {
5148         uint32_t rlc_pg_cntl;
5149
5150         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5151
5152         if (!enable) {
5153                 /* RLC_PG_CNTL[23] = 0 (default)
5154                  * RLC will wait for handshake acks with SMU
5155                  * GFXOFF will be enabled
5156                  * RLC_PG_CNTL[23] = 1
5157                  * RLC will not issue any message to SMU
5158                  * hence no handshake between SMU & RLC
5159                  * GFXOFF will be disabled
5160                  */
5161                 rlc_pg_cntl |= 0x800000;
5162         } else
5163                 rlc_pg_cntl &= ~0x800000;
5164         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5165 }
5166
5167 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5168 {
5169         /* TODO: enable rlc & smu handshake until smu
5170          * and gfxoff feature works as expected */
5171         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5172                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5173
5174         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5175         udelay(50);
5176 }
5177
5178 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5179 {
5180         uint32_t tmp;
5181
5182         /* enable Save Restore Machine */
5183         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5184         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5185         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5186         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5187 }
5188
5189 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5190 {
5191         const struct rlc_firmware_header_v2_0 *hdr;
5192         const __le32 *fw_data;
5193         unsigned i, fw_size;
5194
5195         if (!adev->gfx.rlc_fw)
5196                 return -EINVAL;
5197
5198         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5199         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5200
5201         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5202                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5203         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5204
5205         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5206                      RLCG_UCODE_LOADING_START_ADDRESS);
5207
5208         for (i = 0; i < fw_size; i++)
5209                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5210                              le32_to_cpup(fw_data++));
5211
5212         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5213
5214         return 0;
5215 }
5216
5217 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5218 {
5219         int r;
5220
5221         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5222
5223                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5224                 if (r)
5225                         return r;
5226
5227                 gfx_v10_0_init_csb(adev);
5228
5229                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5230                         gfx_v10_0_rlc_enable_srm(adev);
5231         } else {
5232                 if (amdgpu_sriov_vf(adev)) {
5233                         gfx_v10_0_init_csb(adev);
5234                         return 0;
5235                 }
5236
5237                 adev->gfx.rlc.funcs->stop(adev);
5238
5239                 /* disable CG */
5240                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5241
5242                 /* disable PG */
5243                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5244
5245                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5246                         /* legacy rlc firmware loading */
5247                         r = gfx_v10_0_rlc_load_microcode(adev);
5248                         if (r)
5249                                 return r;
5250                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5251                         /* rlc backdoor autoload firmware */
5252                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5253                         if (r)
5254                                 return r;
5255                 }
5256
5257                 gfx_v10_0_init_csb(adev);
5258
5259                 adev->gfx.rlc.funcs->start(adev);
5260
5261                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5262                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5263                         if (r)
5264                                 return r;
5265                 }
5266         }
5267         return 0;
5268 }
5269
5270 static struct {
5271         FIRMWARE_ID     id;
5272         unsigned int    offset;
5273         unsigned int    size;
5274 } rlc_autoload_info[FIRMWARE_ID_MAX];
5275
5276 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5277 {
5278         int ret;
5279         RLC_TABLE_OF_CONTENT *rlc_toc;
5280
5281         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5282                                         AMDGPU_GEM_DOMAIN_GTT,
5283                                         &adev->gfx.rlc.rlc_toc_bo,
5284                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5285                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5286         if (ret) {
5287                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5288                 return ret;
5289         }
5290
5291         /* Copy toc from psp sos fw to rlc toc buffer */
5292         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5293
5294         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5295         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5296                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5297                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5298                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5299                         /* Offset needs 4KB alignment */
5300                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5301                 }
5302
5303                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5304                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5305                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5306
5307                 rlc_toc++;
5308         }
5309
5310         return 0;
5311 }
5312
5313 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5314 {
5315         uint32_t total_size = 0;
5316         FIRMWARE_ID id;
5317         int ret;
5318
5319         ret = gfx_v10_0_parse_rlc_toc(adev);
5320         if (ret) {
5321                 dev_err(adev->dev, "failed to parse rlc toc\n");
5322                 return 0;
5323         }
5324
5325         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5326                 total_size += rlc_autoload_info[id].size;
5327
5328         /* In case the offset in rlc toc ucode is aligned */
5329         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5330                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5331                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5332
5333         return total_size;
5334 }
5335
5336 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5337 {
5338         int r;
5339         uint32_t total_size;
5340
5341         total_size = gfx_v10_0_calc_toc_total_size(adev);
5342
5343         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5344                                       AMDGPU_GEM_DOMAIN_GTT,
5345                                       &adev->gfx.rlc.rlc_autoload_bo,
5346                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5347                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5348         if (r) {
5349                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5350                 return r;
5351         }
5352
5353         return 0;
5354 }
5355
5356 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5357 {
5358         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5359                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5360                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5361         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5362                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5363                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5364 }
5365
5366 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5367                                                        FIRMWARE_ID id,
5368                                                        const void *fw_data,
5369                                                        uint32_t fw_size)
5370 {
5371         uint32_t toc_offset;
5372         uint32_t toc_fw_size;
5373         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5374
5375         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5376                 return;
5377
5378         toc_offset = rlc_autoload_info[id].offset;
5379         toc_fw_size = rlc_autoload_info[id].size;
5380
5381         if (fw_size == 0)
5382                 fw_size = toc_fw_size;
5383
5384         if (fw_size > toc_fw_size)
5385                 fw_size = toc_fw_size;
5386
5387         memcpy(ptr + toc_offset, fw_data, fw_size);
5388
5389         if (fw_size < toc_fw_size)
5390                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5391 }
5392
5393 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5394 {
5395         void *data;
5396         uint32_t size;
5397
5398         data = adev->gfx.rlc.rlc_toc_buf;
5399         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5400
5401         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5402                                                    FIRMWARE_ID_RLC_TOC,
5403                                                    data, size);
5404 }
5405
5406 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5407 {
5408         const __le32 *fw_data;
5409         uint32_t fw_size;
5410         const struct gfx_firmware_header_v1_0 *cp_hdr;
5411         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5412
5413         /* pfp ucode */
5414         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5415                 adev->gfx.pfp_fw->data;
5416         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5417                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5418         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5419         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5420                                                    FIRMWARE_ID_CP_PFP,
5421                                                    fw_data, fw_size);
5422
5423         /* ce ucode */
5424         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5425                 adev->gfx.ce_fw->data;
5426         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5427                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5428         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5429         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5430                                                    FIRMWARE_ID_CP_CE,
5431                                                    fw_data, fw_size);
5432
5433         /* me ucode */
5434         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5435                 adev->gfx.me_fw->data;
5436         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5437                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5438         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5439         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5440                                                    FIRMWARE_ID_CP_ME,
5441                                                    fw_data, fw_size);
5442
5443         /* rlc ucode */
5444         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5445                 adev->gfx.rlc_fw->data;
5446         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5447                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5448         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5449         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5450                                                    FIRMWARE_ID_RLC_G_UCODE,
5451                                                    fw_data, fw_size);
5452
5453         /* mec1 ucode */
5454         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5455                 adev->gfx.mec_fw->data;
5456         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5457                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5458         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5459                 cp_hdr->jt_size * 4;
5460         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5461                                                    FIRMWARE_ID_CP_MEC,
5462                                                    fw_data, fw_size);
5463         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5464 }
5465
5466 /* Temporarily put sdma part here */
5467 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5468 {
5469         const __le32 *fw_data;
5470         uint32_t fw_size;
5471         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5472         int i;
5473
5474         for (i = 0; i < adev->sdma.num_instances; i++) {
5475                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5476                         adev->sdma.instance[i].fw->data;
5477                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5478                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5479                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5480
5481                 if (i == 0) {
5482                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5483                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5484                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5485                                 FIRMWARE_ID_SDMA0_JT,
5486                                 (uint32_t *)fw_data +
5487                                 sdma_hdr->jt_offset,
5488                                 sdma_hdr->jt_size * 4);
5489                 } else if (i == 1) {
5490                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5491                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5492                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5493                                 FIRMWARE_ID_SDMA1_JT,
5494                                 (uint32_t *)fw_data +
5495                                 sdma_hdr->jt_offset,
5496                                 sdma_hdr->jt_size * 4);
5497                 }
5498         }
5499 }
5500
5501 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5502 {
5503         uint32_t rlc_g_offset, rlc_g_size, tmp;
5504         uint64_t gpu_addr;
5505
5506         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5507         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5508         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5509
5510         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5511         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5512         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5513
5514         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5515         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5516         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5517
5518         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5519         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5520                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5521                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5522                 return -EINVAL;
5523         }
5524
5525         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5526         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5527                 DRM_ERROR("RLC ROM should halt itself\n");
5528                 return -EINVAL;
5529         }
5530
5531         return 0;
5532 }
5533
5534 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5535 {
5536         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5537         uint32_t tmp;
5538         int i;
5539         uint64_t addr;
5540
5541         /* Trigger an invalidation of the L1 instruction caches */
5542         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5543         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5544         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5545
5546         /* Wait for invalidation complete */
5547         for (i = 0; i < usec_timeout; i++) {
5548                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5549                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5550                         INVALIDATE_CACHE_COMPLETE))
5551                         break;
5552                 udelay(1);
5553         }
5554
5555         if (i >= usec_timeout) {
5556                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5557                 return -EINVAL;
5558         }
5559
5560         /* Program me ucode address into intruction cache address register */
5561         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5562                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5563         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5564                         lower_32_bits(addr) & 0xFFFFF000);
5565         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5566                         upper_32_bits(addr));
5567
5568         return 0;
5569 }
5570
5571 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5572 {
5573         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5574         uint32_t tmp;
5575         int i;
5576         uint64_t addr;
5577
5578         /* Trigger an invalidation of the L1 instruction caches */
5579         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5580         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5581         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5582
5583         /* Wait for invalidation complete */
5584         for (i = 0; i < usec_timeout; i++) {
5585                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5586                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5587                         INVALIDATE_CACHE_COMPLETE))
5588                         break;
5589                 udelay(1);
5590         }
5591
5592         if (i >= usec_timeout) {
5593                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5594                 return -EINVAL;
5595         }
5596
5597         /* Program ce ucode address into intruction cache address register */
5598         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5599                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5600         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5601                         lower_32_bits(addr) & 0xFFFFF000);
5602         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5603                         upper_32_bits(addr));
5604
5605         return 0;
5606 }
5607
5608 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5609 {
5610         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5611         uint32_t tmp;
5612         int i;
5613         uint64_t addr;
5614
5615         /* Trigger an invalidation of the L1 instruction caches */
5616         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5617         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5618         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5619
5620         /* Wait for invalidation complete */
5621         for (i = 0; i < usec_timeout; i++) {
5622                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5623                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5624                         INVALIDATE_CACHE_COMPLETE))
5625                         break;
5626                 udelay(1);
5627         }
5628
5629         if (i >= usec_timeout) {
5630                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5631                 return -EINVAL;
5632         }
5633
5634         /* Program pfp ucode address into intruction cache address register */
5635         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5636                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5637         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5638                         lower_32_bits(addr) & 0xFFFFF000);
5639         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5640                         upper_32_bits(addr));
5641
5642         return 0;
5643 }
5644
5645 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5646 {
5647         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5648         uint32_t tmp;
5649         int i;
5650         uint64_t addr;
5651
5652         /* Trigger an invalidation of the L1 instruction caches */
5653         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5654         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5655         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5656
5657         /* Wait for invalidation complete */
5658         for (i = 0; i < usec_timeout; i++) {
5659                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5660                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5661                         INVALIDATE_CACHE_COMPLETE))
5662                         break;
5663                 udelay(1);
5664         }
5665
5666         if (i >= usec_timeout) {
5667                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5668                 return -EINVAL;
5669         }
5670
5671         /* Program mec1 ucode address into intruction cache address register */
5672         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5673                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5674         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5675                         lower_32_bits(addr) & 0xFFFFF000);
5676         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5677                         upper_32_bits(addr));
5678
5679         return 0;
5680 }
5681
5682 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5683 {
5684         uint32_t cp_status;
5685         uint32_t bootload_status;
5686         int i, r;
5687
5688         for (i = 0; i < adev->usec_timeout; i++) {
5689                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5690                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5691                 if ((cp_status == 0) &&
5692                     (REG_GET_FIELD(bootload_status,
5693                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5694                         break;
5695                 }
5696                 udelay(1);
5697         }
5698
5699         if (i >= adev->usec_timeout) {
5700                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5701                 return -ETIMEDOUT;
5702         }
5703
5704         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5705                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5706                 if (r)
5707                         return r;
5708
5709                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5710                 if (r)
5711                         return r;
5712
5713                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5714                 if (r)
5715                         return r;
5716
5717                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5718                 if (r)
5719                         return r;
5720         }
5721
5722         return 0;
5723 }
5724
5725 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5726 {
5727         int i;
5728         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5729
5730         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5731         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5732         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5733
5734         if (adev->asic_type == CHIP_NAVI12) {
5735                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5736         } else {
5737                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5738         }
5739
5740         for (i = 0; i < adev->usec_timeout; i++) {
5741                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5742                         break;
5743                 udelay(1);
5744         }
5745
5746         if (i >= adev->usec_timeout)
5747                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5748
5749         return 0;
5750 }
5751
5752 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5753 {
5754         int r;
5755         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5756         const __le32 *fw_data;
5757         unsigned i, fw_size;
5758         uint32_t tmp;
5759         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5760
5761         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5762                 adev->gfx.pfp_fw->data;
5763
5764         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5765
5766         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5767                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5768         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5769
5770         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5771                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5772                                       &adev->gfx.pfp.pfp_fw_obj,
5773                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5774                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5775         if (r) {
5776                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5777                 gfx_v10_0_pfp_fini(adev);
5778                 return r;
5779         }
5780
5781         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5782
5783         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5784         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5785
5786         /* Trigger an invalidation of the L1 instruction caches */
5787         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5788         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5789         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5790
5791         /* Wait for invalidation complete */
5792         for (i = 0; i < usec_timeout; i++) {
5793                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5794                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5795                         INVALIDATE_CACHE_COMPLETE))
5796                         break;
5797                 udelay(1);
5798         }
5799
5800         if (i >= usec_timeout) {
5801                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5802                 return -EINVAL;
5803         }
5804
5805         if (amdgpu_emu_mode == 1)
5806                 adev->hdp.funcs->flush_hdp(adev, NULL);
5807
5808         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5809         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5810         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5811         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5812         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5813         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5814         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5815                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5816         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5817                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5818
5819         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5820
5821         for (i = 0; i < pfp_hdr->jt_size; i++)
5822                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5823                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5824
5825         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5826
5827         return 0;
5828 }
5829
5830 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5831 {
5832         int r;
5833         const struct gfx_firmware_header_v1_0 *ce_hdr;
5834         const __le32 *fw_data;
5835         unsigned i, fw_size;
5836         uint32_t tmp;
5837         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5838
5839         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5840                 adev->gfx.ce_fw->data;
5841
5842         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5843
5844         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5845                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5846         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5847
5848         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5849                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5850                                       &adev->gfx.ce.ce_fw_obj,
5851                                       &adev->gfx.ce.ce_fw_gpu_addr,
5852                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5853         if (r) {
5854                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5855                 gfx_v10_0_ce_fini(adev);
5856                 return r;
5857         }
5858
5859         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5860
5861         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5862         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5863
5864         /* Trigger an invalidation of the L1 instruction caches */
5865         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5866         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5867         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5868
5869         /* Wait for invalidation complete */
5870         for (i = 0; i < usec_timeout; i++) {
5871                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5872                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5873                         INVALIDATE_CACHE_COMPLETE))
5874                         break;
5875                 udelay(1);
5876         }
5877
5878         if (i >= usec_timeout) {
5879                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5880                 return -EINVAL;
5881         }
5882
5883         if (amdgpu_emu_mode == 1)
5884                 adev->hdp.funcs->flush_hdp(adev, NULL);
5885
5886         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5887         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5888         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5889         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5890         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5891         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5892                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5893         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5894                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5895
5896         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5897
5898         for (i = 0; i < ce_hdr->jt_size; i++)
5899                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5900                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5901
5902         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5903
5904         return 0;
5905 }
5906
5907 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5908 {
5909         int r;
5910         const struct gfx_firmware_header_v1_0 *me_hdr;
5911         const __le32 *fw_data;
5912         unsigned i, fw_size;
5913         uint32_t tmp;
5914         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5915
5916         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5917                 adev->gfx.me_fw->data;
5918
5919         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5920
5921         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5922                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5923         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5924
5925         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5926                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5927                                       &adev->gfx.me.me_fw_obj,
5928                                       &adev->gfx.me.me_fw_gpu_addr,
5929                                       (void **)&adev->gfx.me.me_fw_ptr);
5930         if (r) {
5931                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5932                 gfx_v10_0_me_fini(adev);
5933                 return r;
5934         }
5935
5936         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5937
5938         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5939         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5940
5941         /* Trigger an invalidation of the L1 instruction caches */
5942         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5943         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5944         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5945
5946         /* Wait for invalidation complete */
5947         for (i = 0; i < usec_timeout; i++) {
5948                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5949                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5950                         INVALIDATE_CACHE_COMPLETE))
5951                         break;
5952                 udelay(1);
5953         }
5954
5955         if (i >= usec_timeout) {
5956                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5957                 return -EINVAL;
5958         }
5959
5960         if (amdgpu_emu_mode == 1)
5961                 adev->hdp.funcs->flush_hdp(adev, NULL);
5962
5963         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5964         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5965         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5966         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5967         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5968         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5969                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5970         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5971                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5972
5973         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5974
5975         for (i = 0; i < me_hdr->jt_size; i++)
5976                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5977                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5978
5979         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5980
5981         return 0;
5982 }
5983
5984 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5985 {
5986         int r;
5987
5988         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5989                 return -EINVAL;
5990
5991         gfx_v10_0_cp_gfx_enable(adev, false);
5992
5993         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5994         if (r) {
5995                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5996                 return r;
5997         }
5998
5999         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6000         if (r) {
6001                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6002                 return r;
6003         }
6004
6005         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6006         if (r) {
6007                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6008                 return r;
6009         }
6010
6011         return 0;
6012 }
6013
6014 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6015 {
6016         struct amdgpu_ring *ring;
6017         const struct cs_section_def *sect = NULL;
6018         const struct cs_extent_def *ext = NULL;
6019         int r, i;
6020         int ctx_reg_offset;
6021
6022         /* init the CP */
6023         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6024                      adev->gfx.config.max_hw_contexts - 1);
6025         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6026
6027         gfx_v10_0_cp_gfx_enable(adev, true);
6028
6029         ring = &adev->gfx.gfx_ring[0];
6030         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6031         if (r) {
6032                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6033                 return r;
6034         }
6035
6036         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6037         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6038
6039         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6040         amdgpu_ring_write(ring, 0x80000000);
6041         amdgpu_ring_write(ring, 0x80000000);
6042
6043         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6044                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6045                         if (sect->id == SECT_CONTEXT) {
6046                                 amdgpu_ring_write(ring,
6047                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6048                                                           ext->reg_count));
6049                                 amdgpu_ring_write(ring, ext->reg_index -
6050                                                   PACKET3_SET_CONTEXT_REG_START);
6051                                 for (i = 0; i < ext->reg_count; i++)
6052                                         amdgpu_ring_write(ring, ext->extent[i]);
6053                         }
6054                 }
6055         }
6056
6057         ctx_reg_offset =
6058                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6059         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6060         amdgpu_ring_write(ring, ctx_reg_offset);
6061         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6062
6063         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6064         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6065
6066         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6067         amdgpu_ring_write(ring, 0);
6068
6069         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6070         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6071         amdgpu_ring_write(ring, 0x8000);
6072         amdgpu_ring_write(ring, 0x8000);
6073
6074         amdgpu_ring_commit(ring);
6075
6076         /* submit cs packet to copy state 0 to next available state */
6077         if (adev->gfx.num_gfx_rings > 1) {
6078                 /* maximum supported gfx ring is 2 */
6079                 ring = &adev->gfx.gfx_ring[1];
6080                 r = amdgpu_ring_alloc(ring, 2);
6081                 if (r) {
6082                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6083                         return r;
6084                 }
6085
6086                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6087                 amdgpu_ring_write(ring, 0);
6088
6089                 amdgpu_ring_commit(ring);
6090         }
6091         return 0;
6092 }
6093
6094 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6095                                          CP_PIPE_ID pipe)
6096 {
6097         u32 tmp;
6098
6099         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6100         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6101
6102         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6103 }
6104
6105 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6106                                           struct amdgpu_ring *ring)
6107 {
6108         u32 tmp;
6109
6110         if (!amdgpu_async_gfx_ring) {
6111                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6112                 if (ring->use_doorbell) {
6113                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6114                                                 DOORBELL_OFFSET, ring->doorbell_index);
6115                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6116                                                 DOORBELL_EN, 1);
6117                 } else {
6118                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6119                                                 DOORBELL_EN, 0);
6120                 }
6121                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6122         }
6123         switch (adev->asic_type) {
6124         case CHIP_SIENNA_CICHLID:
6125         case CHIP_NAVY_FLOUNDER:
6126         case CHIP_VANGOGH:
6127         case CHIP_DIMGREY_CAVEFISH:
6128                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6129                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6130                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6131
6132                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6133                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6134                 break;
6135         default:
6136                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6137                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6138                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6139
6140                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6141                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6142                 break;
6143         }
6144 }
6145
6146 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6147 {
6148         struct amdgpu_ring *ring;
6149         u32 tmp;
6150         u32 rb_bufsz;
6151         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6152         u32 i;
6153
6154         /* Set the write pointer delay */
6155         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6156
6157         /* set the RB to use vmid 0 */
6158         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6159
6160         /* Init gfx ring 0 for pipe 0 */
6161         mutex_lock(&adev->srbm_mutex);
6162         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6163
6164         /* Set ring buffer size */
6165         ring = &adev->gfx.gfx_ring[0];
6166         rb_bufsz = order_base_2(ring->ring_size / 8);
6167         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6168         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6169 #ifdef __BIG_ENDIAN
6170         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6171 #endif
6172         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6173
6174         /* Initialize the ring buffer's write pointers */
6175         ring->wptr = 0;
6176         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6177         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6178
6179         /* set the wb address wether it's enabled or not */
6180         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6181         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6182         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6183                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6184
6185         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6186         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6187                      lower_32_bits(wptr_gpu_addr));
6188         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6189                      upper_32_bits(wptr_gpu_addr));
6190
6191         mdelay(1);
6192         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6193
6194         rb_addr = ring->gpu_addr >> 8;
6195         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6196         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6197
6198         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6199
6200         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6201         mutex_unlock(&adev->srbm_mutex);
6202
6203         /* Init gfx ring 1 for pipe 1 */
6204         if (adev->gfx.num_gfx_rings > 1) {
6205                 mutex_lock(&adev->srbm_mutex);
6206                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6207                 /* maximum supported gfx ring is 2 */
6208                 ring = &adev->gfx.gfx_ring[1];
6209                 rb_bufsz = order_base_2(ring->ring_size / 8);
6210                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6211                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6212                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6213                 /* Initialize the ring buffer's write pointers */
6214                 ring->wptr = 0;
6215                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6216                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6217                 /* Set the wb address wether it's enabled or not */
6218                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6219                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6220                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6221                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6222                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6223                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6224                              lower_32_bits(wptr_gpu_addr));
6225                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6226                              upper_32_bits(wptr_gpu_addr));
6227
6228                 mdelay(1);
6229                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6230
6231                 rb_addr = ring->gpu_addr >> 8;
6232                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6233                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6234                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6235
6236                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6237                 mutex_unlock(&adev->srbm_mutex);
6238         }
6239         /* Switch to pipe 0 */
6240         mutex_lock(&adev->srbm_mutex);
6241         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6242         mutex_unlock(&adev->srbm_mutex);
6243
6244         /* start the ring */
6245         gfx_v10_0_cp_gfx_start(adev);
6246
6247         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6248                 ring = &adev->gfx.gfx_ring[i];
6249                 ring->sched.ready = true;
6250         }
6251
6252         return 0;
6253 }
6254
6255 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6256 {
6257         if (enable) {
6258                 switch (adev->asic_type) {
6259                 case CHIP_SIENNA_CICHLID:
6260                 case CHIP_NAVY_FLOUNDER:
6261                 case CHIP_VANGOGH:
6262                 case CHIP_DIMGREY_CAVEFISH:
6263                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6264                         break;
6265                 default:
6266                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6267                         break;
6268                 }
6269         } else {
6270                 switch (adev->asic_type) {
6271                 case CHIP_SIENNA_CICHLID:
6272                 case CHIP_NAVY_FLOUNDER:
6273                 case CHIP_VANGOGH:
6274                 case CHIP_DIMGREY_CAVEFISH:
6275                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6276                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6277                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6278                         break;
6279                 default:
6280                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6281                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6282                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6283                         break;
6284                 }
6285                 adev->gfx.kiq.ring.sched.ready = false;
6286         }
6287         udelay(50);
6288 }
6289
6290 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6291 {
6292         const struct gfx_firmware_header_v1_0 *mec_hdr;
6293         const __le32 *fw_data;
6294         unsigned i;
6295         u32 tmp;
6296         u32 usec_timeout = 50000; /* Wait for 50 ms */
6297
6298         if (!adev->gfx.mec_fw)
6299                 return -EINVAL;
6300
6301         gfx_v10_0_cp_compute_enable(adev, false);
6302
6303         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6304         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6305
6306         fw_data = (const __le32 *)
6307                 (adev->gfx.mec_fw->data +
6308                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6309
6310         /* Trigger an invalidation of the L1 instruction caches */
6311         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6312         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6313         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6314
6315         /* Wait for invalidation complete */
6316         for (i = 0; i < usec_timeout; i++) {
6317                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6318                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6319                                        INVALIDATE_CACHE_COMPLETE))
6320                         break;
6321                 udelay(1);
6322         }
6323
6324         if (i >= usec_timeout) {
6325                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6326                 return -EINVAL;
6327         }
6328
6329         if (amdgpu_emu_mode == 1)
6330                 adev->hdp.funcs->flush_hdp(adev, NULL);
6331
6332         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6333         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6334         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6335         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6336         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6337
6338         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6339                      0xFFFFF000);
6340         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6341                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6342
6343         /* MEC1 */
6344         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6345
6346         for (i = 0; i < mec_hdr->jt_size; i++)
6347                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6348                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6349
6350         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6351
6352         /*
6353          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6354          * different microcode than MEC1.
6355          */
6356
6357         return 0;
6358 }
6359
6360 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6361 {
6362         uint32_t tmp;
6363         struct amdgpu_device *adev = ring->adev;
6364
6365         /* tell RLC which is KIQ queue */
6366         switch (adev->asic_type) {
6367         case CHIP_SIENNA_CICHLID:
6368         case CHIP_NAVY_FLOUNDER:
6369         case CHIP_VANGOGH:
6370         case CHIP_DIMGREY_CAVEFISH:
6371                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6372                 tmp &= 0xffffff00;
6373                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6374                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6375                 tmp |= 0x80;
6376                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6377                 break;
6378         default:
6379                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6380                 tmp &= 0xffffff00;
6381                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6382                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6383                 tmp |= 0x80;
6384                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6385                 break;
6386         }
6387 }
6388
6389 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6390 {
6391         struct amdgpu_device *adev = ring->adev;
6392         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6393         uint64_t hqd_gpu_addr, wb_gpu_addr;
6394         uint32_t tmp;
6395         uint32_t rb_bufsz;
6396
6397         /* set up gfx hqd wptr */
6398         mqd->cp_gfx_hqd_wptr = 0;
6399         mqd->cp_gfx_hqd_wptr_hi = 0;
6400
6401         /* set the pointer to the MQD */
6402         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6403         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6404
6405         /* set up mqd control */
6406         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6407         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6408         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6409         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6410         mqd->cp_gfx_mqd_control = tmp;
6411
6412         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6413         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6414         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6415         mqd->cp_gfx_hqd_vmid = 0;
6416
6417         /* set up default queue priority level
6418          * 0x0 = low priority, 0x1 = high priority */
6419         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6420         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6421         mqd->cp_gfx_hqd_queue_priority = tmp;
6422
6423         /* set up time quantum */
6424         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6425         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6426         mqd->cp_gfx_hqd_quantum = tmp;
6427
6428         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6429         hqd_gpu_addr = ring->gpu_addr >> 8;
6430         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6431         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6432
6433         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6434         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6435         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6436         mqd->cp_gfx_hqd_rptr_addr_hi =
6437                 upper_32_bits(wb_gpu_addr) & 0xffff;
6438
6439         /* set up rb_wptr_poll addr */
6440         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6441         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6442         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6443
6444         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6445         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6446         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6447         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6448         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6449 #ifdef __BIG_ENDIAN
6450         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6451 #endif
6452         mqd->cp_gfx_hqd_cntl = tmp;
6453
6454         /* set up cp_doorbell_control */
6455         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6456         if (ring->use_doorbell) {
6457                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6458                                     DOORBELL_OFFSET, ring->doorbell_index);
6459                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6460                                     DOORBELL_EN, 1);
6461         } else
6462                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6463                                     DOORBELL_EN, 0);
6464         mqd->cp_rb_doorbell_control = tmp;
6465
6466         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6467          *otherwise the range of the second ring will override the first ring */
6468         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6469                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6470
6471         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6472         ring->wptr = 0;
6473         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6474
6475         /* active the queue */
6476         mqd->cp_gfx_hqd_active = 1;
6477
6478         return 0;
6479 }
6480
6481 #ifdef BRING_UP_DEBUG
6482 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6483 {
6484         struct amdgpu_device *adev = ring->adev;
6485         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6486
6487         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6488         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6489         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6490
6491         /* set GFX_MQD_BASE */
6492         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6493         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6494
6495         /* set GFX_MQD_CONTROL */
6496         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6497
6498         /* set GFX_HQD_VMID to 0 */
6499         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6500
6501         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6502                         mqd->cp_gfx_hqd_queue_priority);
6503         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6504
6505         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6506         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6507         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6508
6509         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6510         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6511         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6512
6513         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6514         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6515
6516         /* set RB_WPTR_POLL_ADDR */
6517         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6518         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6519
6520         /* set RB_DOORBELL_CONTROL */
6521         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6522
6523         /* active the queue */
6524         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6525
6526         return 0;
6527 }
6528 #endif
6529
6530 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6531 {
6532         struct amdgpu_device *adev = ring->adev;
6533         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6534         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6535
6536         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6537                 memset((void *)mqd, 0, sizeof(*mqd));
6538                 mutex_lock(&adev->srbm_mutex);
6539                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6540                 gfx_v10_0_gfx_mqd_init(ring);
6541 #ifdef BRING_UP_DEBUG
6542                 gfx_v10_0_gfx_queue_init_register(ring);
6543 #endif
6544                 nv_grbm_select(adev, 0, 0, 0, 0);
6545                 mutex_unlock(&adev->srbm_mutex);
6546                 if (adev->gfx.me.mqd_backup[mqd_idx])
6547                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6548         } else if (amdgpu_in_reset(adev)) {
6549                 /* reset mqd with the backup copy */
6550                 if (adev->gfx.me.mqd_backup[mqd_idx])
6551                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6552                 /* reset the ring */
6553                 ring->wptr = 0;
6554                 adev->wb.wb[ring->wptr_offs] = 0;
6555                 amdgpu_ring_clear_ring(ring);
6556 #ifdef BRING_UP_DEBUG
6557                 mutex_lock(&adev->srbm_mutex);
6558                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6559                 gfx_v10_0_gfx_queue_init_register(ring);
6560                 nv_grbm_select(adev, 0, 0, 0, 0);
6561                 mutex_unlock(&adev->srbm_mutex);
6562 #endif
6563         } else {
6564                 amdgpu_ring_clear_ring(ring);
6565         }
6566
6567         return 0;
6568 }
6569
6570 #ifndef BRING_UP_DEBUG
6571 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6572 {
6573         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6574         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6575         int r, i;
6576
6577         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6578                 return -EINVAL;
6579
6580         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6581                                         adev->gfx.num_gfx_rings);
6582         if (r) {
6583                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6584                 return r;
6585         }
6586
6587         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6588                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6589
6590         return amdgpu_ring_test_helper(kiq_ring);
6591 }
6592 #endif
6593
6594 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6595 {
6596         int r, i;
6597         struct amdgpu_ring *ring;
6598
6599         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6600                 ring = &adev->gfx.gfx_ring[i];
6601
6602                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6603                 if (unlikely(r != 0))
6604                         goto done;
6605
6606                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6607                 if (!r) {
6608                         r = gfx_v10_0_gfx_init_queue(ring);
6609                         amdgpu_bo_kunmap(ring->mqd_obj);
6610                         ring->mqd_ptr = NULL;
6611                 }
6612                 amdgpu_bo_unreserve(ring->mqd_obj);
6613                 if (r)
6614                         goto done;
6615         }
6616 #ifndef BRING_UP_DEBUG
6617         r = gfx_v10_0_kiq_enable_kgq(adev);
6618         if (r)
6619                 goto done;
6620 #endif
6621         r = gfx_v10_0_cp_gfx_start(adev);
6622         if (r)
6623                 goto done;
6624
6625         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6626                 ring = &adev->gfx.gfx_ring[i];
6627                 ring->sched.ready = true;
6628         }
6629 done:
6630         return r;
6631 }
6632
6633 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6634 {
6635         struct amdgpu_device *adev = ring->adev;
6636
6637         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6638                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6639                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6640                         mqd->cp_hqd_queue_priority =
6641                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6642                 }
6643         }
6644 }
6645
6646 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6647 {
6648         struct amdgpu_device *adev = ring->adev;
6649         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6650         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6651         uint32_t tmp;
6652
6653         mqd->header = 0xC0310800;
6654         mqd->compute_pipelinestat_enable = 0x00000001;
6655         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6656         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6657         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6658         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6659         mqd->compute_misc_reserved = 0x00000003;
6660
6661         eop_base_addr = ring->eop_gpu_addr >> 8;
6662         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6663         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6664
6665         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6666         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6667         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6668                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6669
6670         mqd->cp_hqd_eop_control = tmp;
6671
6672         /* enable doorbell? */
6673         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6674
6675         if (ring->use_doorbell) {
6676                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6677                                     DOORBELL_OFFSET, ring->doorbell_index);
6678                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6679                                     DOORBELL_EN, 1);
6680                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6681                                     DOORBELL_SOURCE, 0);
6682                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6683                                     DOORBELL_HIT, 0);
6684         } else {
6685                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6686                                     DOORBELL_EN, 0);
6687         }
6688
6689         mqd->cp_hqd_pq_doorbell_control = tmp;
6690
6691         /* disable the queue if it's active */
6692         ring->wptr = 0;
6693         mqd->cp_hqd_dequeue_request = 0;
6694         mqd->cp_hqd_pq_rptr = 0;
6695         mqd->cp_hqd_pq_wptr_lo = 0;
6696         mqd->cp_hqd_pq_wptr_hi = 0;
6697
6698         /* set the pointer to the MQD */
6699         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6700         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6701
6702         /* set MQD vmid to 0 */
6703         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6704         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6705         mqd->cp_mqd_control = tmp;
6706
6707         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6708         hqd_gpu_addr = ring->gpu_addr >> 8;
6709         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6710         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6711
6712         /* set up the HQD, this is similar to CP_RB0_CNTL */
6713         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6714         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6715                             (order_base_2(ring->ring_size / 4) - 1));
6716         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6717                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6718 #ifdef __BIG_ENDIAN
6719         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6720 #endif
6721         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6722         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6723         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6724         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6725         mqd->cp_hqd_pq_control = tmp;
6726
6727         /* set the wb address whether it's enabled or not */
6728         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6729         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6730         mqd->cp_hqd_pq_rptr_report_addr_hi =
6731                 upper_32_bits(wb_gpu_addr) & 0xffff;
6732
6733         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6734         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6735         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6736         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6737
6738         tmp = 0;
6739         /* enable the doorbell if requested */
6740         if (ring->use_doorbell) {
6741                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6742                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6743                                 DOORBELL_OFFSET, ring->doorbell_index);
6744
6745                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6746                                     DOORBELL_EN, 1);
6747                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6748                                     DOORBELL_SOURCE, 0);
6749                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6750                                     DOORBELL_HIT, 0);
6751         }
6752
6753         mqd->cp_hqd_pq_doorbell_control = tmp;
6754
6755         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6756         ring->wptr = 0;
6757         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6758
6759         /* set the vmid for the queue */
6760         mqd->cp_hqd_vmid = 0;
6761
6762         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6763         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6764         mqd->cp_hqd_persistent_state = tmp;
6765
6766         /* set MIN_IB_AVAIL_SIZE */
6767         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6768         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6769         mqd->cp_hqd_ib_control = tmp;
6770
6771         /* set static priority for a compute queue/ring */
6772         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6773
6774         /* map_queues packet doesn't need activate the queue,
6775          * so only kiq need set this field.
6776          */
6777         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6778                 mqd->cp_hqd_active = 1;
6779
6780         return 0;
6781 }
6782
6783 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6784 {
6785         struct amdgpu_device *adev = ring->adev;
6786         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6787         int j;
6788
6789         /* inactivate the queue */
6790         if (amdgpu_sriov_vf(adev))
6791                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6792
6793         /* disable wptr polling */
6794         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6795
6796         /* write the EOP addr */
6797         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6798                mqd->cp_hqd_eop_base_addr_lo);
6799         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6800                mqd->cp_hqd_eop_base_addr_hi);
6801
6802         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6803         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6804                mqd->cp_hqd_eop_control);
6805
6806         /* enable doorbell? */
6807         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6808                mqd->cp_hqd_pq_doorbell_control);
6809
6810         /* disable the queue if it's active */
6811         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6812                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6813                 for (j = 0; j < adev->usec_timeout; j++) {
6814                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6815                                 break;
6816                         udelay(1);
6817                 }
6818                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6819                        mqd->cp_hqd_dequeue_request);
6820                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6821                        mqd->cp_hqd_pq_rptr);
6822                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6823                        mqd->cp_hqd_pq_wptr_lo);
6824                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6825                        mqd->cp_hqd_pq_wptr_hi);
6826         }
6827
6828         /* set the pointer to the MQD */
6829         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6830                mqd->cp_mqd_base_addr_lo);
6831         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6832                mqd->cp_mqd_base_addr_hi);
6833
6834         /* set MQD vmid to 0 */
6835         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6836                mqd->cp_mqd_control);
6837
6838         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6839         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6840                mqd->cp_hqd_pq_base_lo);
6841         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6842                mqd->cp_hqd_pq_base_hi);
6843
6844         /* set up the HQD, this is similar to CP_RB0_CNTL */
6845         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6846                mqd->cp_hqd_pq_control);
6847
6848         /* set the wb address whether it's enabled or not */
6849         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6850                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6851         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6852                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6853
6854         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6855         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6856                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6857         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6858                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6859
6860         /* enable the doorbell if requested */
6861         if (ring->use_doorbell) {
6862                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6863                         (adev->doorbell_index.kiq * 2) << 2);
6864                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6865                         (adev->doorbell_index.userqueue_end * 2) << 2);
6866         }
6867
6868         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6869                mqd->cp_hqd_pq_doorbell_control);
6870
6871         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6872         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6873                mqd->cp_hqd_pq_wptr_lo);
6874         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6875                mqd->cp_hqd_pq_wptr_hi);
6876
6877         /* set the vmid for the queue */
6878         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6879
6880         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6881                mqd->cp_hqd_persistent_state);
6882
6883         /* activate the queue */
6884         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6885                mqd->cp_hqd_active);
6886
6887         if (ring->use_doorbell)
6888                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6889
6890         return 0;
6891 }
6892
6893 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6894 {
6895         struct amdgpu_device *adev = ring->adev;
6896         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6897         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6898
6899         gfx_v10_0_kiq_setting(ring);
6900
6901         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6902                 /* reset MQD to a clean status */
6903                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6904                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6905
6906                 /* reset ring buffer */
6907                 ring->wptr = 0;
6908                 amdgpu_ring_clear_ring(ring);
6909
6910                 mutex_lock(&adev->srbm_mutex);
6911                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6912                 gfx_v10_0_kiq_init_register(ring);
6913                 nv_grbm_select(adev, 0, 0, 0, 0);
6914                 mutex_unlock(&adev->srbm_mutex);
6915         } else {
6916                 memset((void *)mqd, 0, sizeof(*mqd));
6917                 mutex_lock(&adev->srbm_mutex);
6918                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6919                 gfx_v10_0_compute_mqd_init(ring);
6920                 gfx_v10_0_kiq_init_register(ring);
6921                 nv_grbm_select(adev, 0, 0, 0, 0);
6922                 mutex_unlock(&adev->srbm_mutex);
6923
6924                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6925                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6926         }
6927
6928         return 0;
6929 }
6930
6931 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6932 {
6933         struct amdgpu_device *adev = ring->adev;
6934         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6935         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6936
6937         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6938                 memset((void *)mqd, 0, sizeof(*mqd));
6939                 mutex_lock(&adev->srbm_mutex);
6940                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6941                 gfx_v10_0_compute_mqd_init(ring);
6942                 nv_grbm_select(adev, 0, 0, 0, 0);
6943                 mutex_unlock(&adev->srbm_mutex);
6944
6945                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6946                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6947         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6948                 /* reset MQD to a clean status */
6949                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6950                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6951
6952                 /* reset ring buffer */
6953                 ring->wptr = 0;
6954                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6955                 amdgpu_ring_clear_ring(ring);
6956         } else {
6957                 amdgpu_ring_clear_ring(ring);
6958         }
6959
6960         return 0;
6961 }
6962
6963 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6964 {
6965         struct amdgpu_ring *ring;
6966         int r;
6967
6968         ring = &adev->gfx.kiq.ring;
6969
6970         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6971         if (unlikely(r != 0))
6972                 return r;
6973
6974         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6975         if (unlikely(r != 0))
6976                 return r;
6977
6978         gfx_v10_0_kiq_init_queue(ring);
6979         amdgpu_bo_kunmap(ring->mqd_obj);
6980         ring->mqd_ptr = NULL;
6981         amdgpu_bo_unreserve(ring->mqd_obj);
6982         ring->sched.ready = true;
6983         return 0;
6984 }
6985
6986 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6987 {
6988         struct amdgpu_ring *ring = NULL;
6989         int r = 0, i;
6990
6991         gfx_v10_0_cp_compute_enable(adev, true);
6992
6993         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6994                 ring = &adev->gfx.compute_ring[i];
6995
6996                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6997                 if (unlikely(r != 0))
6998                         goto done;
6999                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7000                 if (!r) {
7001                         r = gfx_v10_0_kcq_init_queue(ring);
7002                         amdgpu_bo_kunmap(ring->mqd_obj);
7003                         ring->mqd_ptr = NULL;
7004                 }
7005                 amdgpu_bo_unreserve(ring->mqd_obj);
7006                 if (r)
7007                         goto done;
7008         }
7009
7010         r = amdgpu_gfx_enable_kcq(adev);
7011 done:
7012         return r;
7013 }
7014
7015 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7016 {
7017         int r, i;
7018         struct amdgpu_ring *ring;
7019
7020         if (!(adev->flags & AMD_IS_APU))
7021                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7022
7023         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7024                 /* legacy firmware loading */
7025                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7026                 if (r)
7027                         return r;
7028
7029                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7030                 if (r)
7031                         return r;
7032         }
7033
7034         r = gfx_v10_0_kiq_resume(adev);
7035         if (r)
7036                 return r;
7037
7038         r = gfx_v10_0_kcq_resume(adev);
7039         if (r)
7040                 return r;
7041
7042         if (!amdgpu_async_gfx_ring) {
7043                 r = gfx_v10_0_cp_gfx_resume(adev);
7044                 if (r)
7045                         return r;
7046         } else {
7047                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7048                 if (r)
7049                         return r;
7050         }
7051
7052         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7053                 ring = &adev->gfx.gfx_ring[i];
7054                 r = amdgpu_ring_test_helper(ring);
7055                 if (r)
7056                         return r;
7057         }
7058
7059         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7060                 ring = &adev->gfx.compute_ring[i];
7061                 r = amdgpu_ring_test_helper(ring);
7062                 if (r)
7063                         return r;
7064         }
7065
7066         return 0;
7067 }
7068
7069 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7070 {
7071         gfx_v10_0_cp_gfx_enable(adev, enable);
7072         gfx_v10_0_cp_compute_enable(adev, enable);
7073 }
7074
7075 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7076 {
7077         uint32_t data, pattern = 0xDEADBEEF;
7078
7079         /* check if mmVGT_ESGS_RING_SIZE_UMD
7080          * has been remapped to mmVGT_ESGS_RING_SIZE */
7081         switch (adev->asic_type) {
7082         case CHIP_SIENNA_CICHLID:
7083         case CHIP_NAVY_FLOUNDER:
7084         case CHIP_DIMGREY_CAVEFISH:
7085                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7086                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7087                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7088
7089                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7090                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7091                         return true;
7092                 } else {
7093                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7094                         return false;
7095                 }
7096                 break;
7097         case CHIP_VANGOGH:
7098                 return true;
7099         default:
7100                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7101                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7102                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7103
7104                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7105                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7106                         return true;
7107                 } else {
7108                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7109                         return false;
7110                 }
7111                 break;
7112         }
7113 }
7114
7115 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7116 {
7117         uint32_t data;
7118
7119         /* initialize cam_index to 0
7120          * index will auto-inc after each data writting */
7121         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7122
7123         switch (adev->asic_type) {
7124         case CHIP_SIENNA_CICHLID:
7125         case CHIP_NAVY_FLOUNDER:
7126         case CHIP_VANGOGH:
7127         case CHIP_DIMGREY_CAVEFISH:
7128                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7129                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7130                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7131                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7132                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7133                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7134                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7135
7136                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7137                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7138                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7139                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7140                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7141                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7142                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7143
7144                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7145                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7146                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7147                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7148                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7149                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7150                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7151
7152                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7153                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7154                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7155                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7156                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7157                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7158                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7159
7160                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7161                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7162                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7163                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7164                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7165                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7166                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7167
7168                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7169                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7170                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7171                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7172                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7173                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7174                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7175
7176                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7177                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7178                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7179                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7180                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7181                 break;
7182         default:
7183                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7184                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7185                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7186                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7187                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7188                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7189                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7190
7191                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7192                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7193                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7194                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7195                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7196                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7197                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7198
7199                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7200                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7201                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7202                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7203                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7204                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7205                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7206
7207                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7208                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7209                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7210                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7211                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7212                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7213                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7214
7215                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7216                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7217                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7218                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7219                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7220                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7221                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7222
7223                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7224                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7225                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7226                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7227                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7228                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7229                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7230
7231                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7232                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7233                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7234                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7235                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7236                 break;
7237         }
7238
7239         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7240         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7241 }
7242
7243 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7244 {
7245         uint32_t data;
7246         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7247         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7248         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7249
7250         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7251         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7252         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7253 }
7254
7255 static int gfx_v10_0_hw_init(void *handle)
7256 {
7257         int r;
7258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7259
7260         if (!amdgpu_emu_mode)
7261                 gfx_v10_0_init_golden_registers(adev);
7262
7263         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7264                 /**
7265                  * For gfx 10, rlc firmware loading relies on smu firmware is
7266                  * loaded firstly, so in direct type, it has to load smc ucode
7267                  * here before rlc.
7268                  */
7269                 if (!(adev->flags & AMD_IS_APU)) {
7270                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7271                         if (r)
7272                                 return r;
7273                 }
7274                 gfx_v10_0_disable_gpa_mode(adev);
7275         }
7276
7277         /* if GRBM CAM not remapped, set up the remapping */
7278         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7279                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7280
7281         gfx_v10_0_constants_init(adev);
7282
7283         r = gfx_v10_0_rlc_resume(adev);
7284         if (r)
7285                 return r;
7286
7287         /*
7288          * init golden registers and rlc resume may override some registers,
7289          * reconfig them here
7290          */
7291         gfx_v10_0_tcp_harvest(adev);
7292
7293         r = gfx_v10_0_cp_resume(adev);
7294         if (r)
7295                 return r;
7296
7297         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7298                 gfx_v10_3_program_pbb_mode(adev);
7299
7300         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7301                 gfx_v10_3_set_power_brake_sequence(adev);
7302
7303         return r;
7304 }
7305
7306 #ifndef BRING_UP_DEBUG
7307 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7308 {
7309         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7310         struct amdgpu_ring *kiq_ring = &kiq->ring;
7311         int i;
7312
7313         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7314                 return -EINVAL;
7315
7316         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7317                                         adev->gfx.num_gfx_rings))
7318                 return -ENOMEM;
7319
7320         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7321                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7322                                            PREEMPT_QUEUES, 0, 0);
7323
7324         return amdgpu_ring_test_helper(kiq_ring);
7325 }
7326 #endif
7327
7328 static int gfx_v10_0_hw_fini(void *handle)
7329 {
7330         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7331         int r;
7332         uint32_t tmp;
7333
7334         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7335         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7336
7337         if (!adev->in_pci_err_recovery) {
7338 #ifndef BRING_UP_DEBUG
7339                 if (amdgpu_async_gfx_ring) {
7340                         r = gfx_v10_0_kiq_disable_kgq(adev);
7341                         if (r)
7342                                 DRM_ERROR("KGQ disable failed\n");
7343                 }
7344 #endif
7345                 if (amdgpu_gfx_disable_kcq(adev))
7346                         DRM_ERROR("KCQ disable failed\n");
7347         }
7348
7349         if (amdgpu_sriov_vf(adev)) {
7350                 gfx_v10_0_cp_gfx_enable(adev, false);
7351                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7352                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7353                 tmp &= 0xffffff00;
7354                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7355
7356                 return 0;
7357         }
7358         gfx_v10_0_cp_enable(adev, false);
7359         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7360
7361         return 0;
7362 }
7363
7364 static int gfx_v10_0_suspend(void *handle)
7365 {
7366         return gfx_v10_0_hw_fini(handle);
7367 }
7368
7369 static int gfx_v10_0_resume(void *handle)
7370 {
7371         return gfx_v10_0_hw_init(handle);
7372 }
7373
7374 static bool gfx_v10_0_is_idle(void *handle)
7375 {
7376         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7377
7378         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7379                                 GRBM_STATUS, GUI_ACTIVE))
7380                 return false;
7381         else
7382                 return true;
7383 }
7384
7385 static int gfx_v10_0_wait_for_idle(void *handle)
7386 {
7387         unsigned i;
7388         u32 tmp;
7389         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7390
7391         for (i = 0; i < adev->usec_timeout; i++) {
7392                 /* read MC_STATUS */
7393                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7394                         GRBM_STATUS__GUI_ACTIVE_MASK;
7395
7396                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7397                         return 0;
7398                 udelay(1);
7399         }
7400         return -ETIMEDOUT;
7401 }
7402
7403 static int gfx_v10_0_soft_reset(void *handle)
7404 {
7405         u32 grbm_soft_reset = 0;
7406         u32 tmp;
7407         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7408
7409         /* GRBM_STATUS */
7410         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7411         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7412                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7413                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7414                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7415                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7416                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7417                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7418                                                 1);
7419                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7420                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7421                                                 1);
7422         }
7423
7424         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7425                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7426                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7427                                                 1);
7428         }
7429
7430         /* GRBM_STATUS2 */
7431         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7432         switch (adev->asic_type) {
7433         case CHIP_SIENNA_CICHLID:
7434         case CHIP_NAVY_FLOUNDER:
7435         case CHIP_VANGOGH:
7436         case CHIP_DIMGREY_CAVEFISH:
7437                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7438                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7439                                                         GRBM_SOFT_RESET,
7440                                                         SOFT_RESET_RLC,
7441                                                         1);
7442                 break;
7443         default:
7444                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7445                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7446                                                         GRBM_SOFT_RESET,
7447                                                         SOFT_RESET_RLC,
7448                                                         1);
7449                 break;
7450         }
7451
7452         if (grbm_soft_reset) {
7453                 /* stop the rlc */
7454                 gfx_v10_0_rlc_stop(adev);
7455
7456                 /* Disable GFX parsing/prefetching */
7457                 gfx_v10_0_cp_gfx_enable(adev, false);
7458
7459                 /* Disable MEC parsing/prefetching */
7460                 gfx_v10_0_cp_compute_enable(adev, false);
7461
7462                 if (grbm_soft_reset) {
7463                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7464                         tmp |= grbm_soft_reset;
7465                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7466                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7467                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7468
7469                         udelay(50);
7470
7471                         tmp &= ~grbm_soft_reset;
7472                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7473                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7474                 }
7475
7476                 /* Wait a little for things to settle down */
7477                 udelay(50);
7478         }
7479         return 0;
7480 }
7481
7482 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7483 {
7484         uint64_t clock;
7485
7486         amdgpu_gfx_off_ctrl(adev, false);
7487         mutex_lock(&adev->gfx.gpu_clock_mutex);
7488         switch (adev->asic_type) {
7489         case CHIP_VANGOGH:
7490                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7491                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7492                 break;
7493         default:
7494                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7495                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7496                 break;
7497         }
7498         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7499         amdgpu_gfx_off_ctrl(adev, true);
7500         return clock;
7501 }
7502
7503 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7504                                            uint32_t vmid,
7505                                            uint32_t gds_base, uint32_t gds_size,
7506                                            uint32_t gws_base, uint32_t gws_size,
7507                                            uint32_t oa_base, uint32_t oa_size)
7508 {
7509         struct amdgpu_device *adev = ring->adev;
7510
7511         /* GDS Base */
7512         gfx_v10_0_write_data_to_reg(ring, 0, false,
7513                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7514                                     gds_base);
7515
7516         /* GDS Size */
7517         gfx_v10_0_write_data_to_reg(ring, 0, false,
7518                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7519                                     gds_size);
7520
7521         /* GWS */
7522         gfx_v10_0_write_data_to_reg(ring, 0, false,
7523                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7524                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7525
7526         /* OA */
7527         gfx_v10_0_write_data_to_reg(ring, 0, false,
7528                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7529                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7530 }
7531
7532 static int gfx_v10_0_early_init(void *handle)
7533 {
7534         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7535
7536         switch (adev->asic_type) {
7537         case CHIP_NAVI10:
7538         case CHIP_NAVI14:
7539         case CHIP_NAVI12:
7540                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7541                 break;
7542         case CHIP_SIENNA_CICHLID:
7543         case CHIP_NAVY_FLOUNDER:
7544         case CHIP_VANGOGH:
7545         case CHIP_DIMGREY_CAVEFISH:
7546                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7547                 break;
7548         default:
7549                 break;
7550         }
7551
7552         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7553                                           AMDGPU_MAX_COMPUTE_RINGS);
7554
7555         gfx_v10_0_set_kiq_pm4_funcs(adev);
7556         gfx_v10_0_set_ring_funcs(adev);
7557         gfx_v10_0_set_irq_funcs(adev);
7558         gfx_v10_0_set_gds_init(adev);
7559         gfx_v10_0_set_rlc_funcs(adev);
7560
7561         return 0;
7562 }
7563
7564 static int gfx_v10_0_late_init(void *handle)
7565 {
7566         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7567         int r;
7568
7569         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7570         if (r)
7571                 return r;
7572
7573         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7574         if (r)
7575                 return r;
7576
7577         return 0;
7578 }
7579
7580 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7581 {
7582         uint32_t rlc_cntl;
7583
7584         /* if RLC is not enabled, do nothing */
7585         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7586         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7587 }
7588
7589 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7590 {
7591         uint32_t data;
7592         unsigned i;
7593
7594         data = RLC_SAFE_MODE__CMD_MASK;
7595         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7596
7597         switch (adev->asic_type) {
7598         case CHIP_SIENNA_CICHLID:
7599         case CHIP_NAVY_FLOUNDER:
7600         case CHIP_VANGOGH:
7601         case CHIP_DIMGREY_CAVEFISH:
7602                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7603
7604                 /* wait for RLC_SAFE_MODE */
7605                 for (i = 0; i < adev->usec_timeout; i++) {
7606                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7607                                            RLC_SAFE_MODE, CMD))
7608                                 break;
7609                         udelay(1);
7610                 }
7611                 break;
7612         default:
7613                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7614
7615                 /* wait for RLC_SAFE_MODE */
7616                 for (i = 0; i < adev->usec_timeout; i++) {
7617                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7618                                            RLC_SAFE_MODE, CMD))
7619                                 break;
7620                         udelay(1);
7621                 }
7622                 break;
7623         }
7624 }
7625
7626 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7627 {
7628         uint32_t data;
7629
7630         data = RLC_SAFE_MODE__CMD_MASK;
7631         switch (adev->asic_type) {
7632         case CHIP_SIENNA_CICHLID:
7633         case CHIP_NAVY_FLOUNDER:
7634         case CHIP_VANGOGH:
7635         case CHIP_DIMGREY_CAVEFISH:
7636                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7637                 break;
7638         default:
7639                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7640                 break;
7641         }
7642 }
7643
7644 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7645                                                       bool enable)
7646 {
7647         uint32_t data, def;
7648
7649         /* It is disabled by HW by default */
7650         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7651                 /* 0 - Disable some blocks' MGCG */
7652                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7653                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7654                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7655                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7656
7657                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7658                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7659                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7660                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7661                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7662                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7663                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7664
7665                 if (def != data)
7666                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7667
7668                 /* MGLS is a global flag to control all MGLS in GFX */
7669                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7670                         /* 2 - RLC memory Light sleep */
7671                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7672                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7673                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7674                                 if (def != data)
7675                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7676                         }
7677                         /* 3 - CP memory Light sleep */
7678                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7679                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7680                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7681                                 if (def != data)
7682                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7683                         }
7684                 }
7685         } else {
7686                 /* 1 - MGCG_OVERRIDE */
7687                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7688                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7689                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7690                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7691                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7692                 if (def != data)
7693                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7694
7695                 /* 2 - disable MGLS in CP */
7696                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7697                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7698                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7699                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7700                 }
7701
7702                 /* 3 - disable MGLS in RLC */
7703                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7704                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7705                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7706                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7707                 }
7708
7709         }
7710 }
7711
7712 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7713                                            bool enable)
7714 {
7715         uint32_t data, def;
7716
7717         /* Enable 3D CGCG/CGLS */
7718         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7719                 /* write cmd to clear cgcg/cgls ov */
7720                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7721                 /* unset CGCG override */
7722                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7723                 /* update CGCG and CGLS override bits */
7724                 if (def != data)
7725                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7726                 /* enable 3Dcgcg FSM(0x0000363f) */
7727                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7728                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7729                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7730                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7731                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7732                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7733                 if (def != data)
7734                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7735
7736                 /* set IDLE_POLL_COUNT(0x00900100) */
7737                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7738                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7739                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7740                 if (def != data)
7741                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7742         } else {
7743                 /* Disable CGCG/CGLS */
7744                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7745                 /* disable cgcg, cgls should be disabled */
7746                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7747                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7748                 /* disable cgcg and cgls in FSM */
7749                 if (def != data)
7750                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7751         }
7752 }
7753
7754 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7755                                                       bool enable)
7756 {
7757         uint32_t def, data;
7758
7759         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7760                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7761                 /* unset CGCG override */
7762                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7763                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7764                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7765                 else
7766                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7767                 /* update CGCG and CGLS override bits */
7768                 if (def != data)
7769                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7770
7771                 /* enable cgcg FSM(0x0000363F) */
7772                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7773                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7774                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7775                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7776                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7777                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7778                 if (def != data)
7779                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7780
7781                 /* set IDLE_POLL_COUNT(0x00900100) */
7782                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7783                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7784                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7785                 if (def != data)
7786                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7787         } else {
7788                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7789                 /* reset CGCG/CGLS bits */
7790                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7791                 /* disable cgcg and cgls in FSM */
7792                 if (def != data)
7793                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7794         }
7795 }
7796
7797 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7798                                                       bool enable)
7799 {
7800         uint32_t def, data;
7801
7802         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7803                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7804                 /* unset FGCG override */
7805                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7806                 /* update FGCG override bits */
7807                 if (def != data)
7808                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7809
7810                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7811                 /* unset RLC SRAM CLK GATER override */
7812                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7813                 /* update RLC SRAM CLK GATER override bits */
7814                 if (def != data)
7815                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7816         } else {
7817                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7818                 /* reset FGCG bits */
7819                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7820                 /* disable FGCG*/
7821                 if (def != data)
7822                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7823
7824                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7825                 /* reset RLC SRAM CLK GATER bits */
7826                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7827                 /* disable RLC SRAM CLK*/
7828                 if (def != data)
7829                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7830         }
7831 }
7832
7833 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7834                                             bool enable)
7835 {
7836         amdgpu_gfx_rlc_enter_safe_mode(adev);
7837
7838         if (enable) {
7839                 /* enable FGCG firstly*/
7840                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7841                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7842                  * ===  MGCG + MGLS ===
7843                  */
7844                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7845                 /* ===  CGCG /CGLS for GFX 3D Only === */
7846                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7847                 /* ===  CGCG + CGLS === */
7848                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7849         } else {
7850                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7851                  * ===  CGCG + CGLS ===
7852                  */
7853                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7854                 /* ===  CGCG /CGLS for GFX 3D Only === */
7855                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7856                 /* ===  MGCG + MGLS === */
7857                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7858                 /* disable fgcg at last*/
7859                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7860         }
7861
7862         if (adev->cg_flags &
7863             (AMD_CG_SUPPORT_GFX_MGCG |
7864              AMD_CG_SUPPORT_GFX_CGLS |
7865              AMD_CG_SUPPORT_GFX_CGCG |
7866              AMD_CG_SUPPORT_GFX_3D_CGCG |
7867              AMD_CG_SUPPORT_GFX_3D_CGLS))
7868                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7869
7870         amdgpu_gfx_rlc_exit_safe_mode(adev);
7871
7872         return 0;
7873 }
7874
7875 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7876 {
7877         u32 reg, data;
7878
7879         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7880         if (amdgpu_sriov_is_pp_one_vf(adev))
7881                 data = RREG32_NO_KIQ(reg);
7882         else
7883                 data = RREG32(reg);
7884
7885         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7886         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7887
7888         if (amdgpu_sriov_is_pp_one_vf(adev))
7889                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7890         else
7891                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7892 }
7893
7894 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7895                                         uint32_t offset,
7896                                         struct soc15_reg_rlcg *entries, int arr_size)
7897 {
7898         int i;
7899         uint32_t reg;
7900
7901         if (!entries)
7902                 return false;
7903
7904         for (i = 0; i < arr_size; i++) {
7905                 const struct soc15_reg_rlcg *entry;
7906
7907                 entry = &entries[i];
7908                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7909                 if (offset == reg)
7910                         return true;
7911         }
7912
7913         return false;
7914 }
7915
7916 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7917 {
7918         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7919 }
7920
7921 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7922 {
7923         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7924
7925         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7926                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7927         else
7928                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7929
7930         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7931
7932         /*
7933          * CGPG enablement required and the register to program the hysteresis value
7934          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7935          * in refclk count. Note that RLC FW is modified to take 16 bits from
7936          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
7937          *
7938          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
7939          * as part of CGPG enablement starting point.
7940          */
7941         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
7942                 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
7943                 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
7944         }
7945 }
7946
7947 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7948 {
7949         amdgpu_gfx_rlc_enter_safe_mode(adev);
7950
7951         gfx_v10_cntl_power_gating(adev, enable);
7952
7953         amdgpu_gfx_rlc_exit_safe_mode(adev);
7954 }
7955
7956 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7957         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7958         .set_safe_mode = gfx_v10_0_set_safe_mode,
7959         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7960         .init = gfx_v10_0_rlc_init,
7961         .get_csb_size = gfx_v10_0_get_csb_size,
7962         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7963         .resume = gfx_v10_0_rlc_resume,
7964         .stop = gfx_v10_0_rlc_stop,
7965         .reset = gfx_v10_0_rlc_reset,
7966         .start = gfx_v10_0_rlc_start,
7967         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7968 };
7969
7970 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7971         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7972         .set_safe_mode = gfx_v10_0_set_safe_mode,
7973         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7974         .init = gfx_v10_0_rlc_init,
7975         .get_csb_size = gfx_v10_0_get_csb_size,
7976         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7977         .resume = gfx_v10_0_rlc_resume,
7978         .stop = gfx_v10_0_rlc_stop,
7979         .reset = gfx_v10_0_rlc_reset,
7980         .start = gfx_v10_0_rlc_start,
7981         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7982         .rlcg_wreg = gfx_v10_rlcg_wreg,
7983         .rlcg_rreg = gfx_v10_rlcg_rreg,
7984         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7985 };
7986
7987 static int gfx_v10_0_set_powergating_state(void *handle,
7988                                           enum amd_powergating_state state)
7989 {
7990         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7991         bool enable = (state == AMD_PG_STATE_GATE);
7992
7993         if (amdgpu_sriov_vf(adev))
7994                 return 0;
7995
7996         switch (adev->asic_type) {
7997         case CHIP_NAVI10:
7998         case CHIP_NAVI14:
7999         case CHIP_NAVI12:
8000         case CHIP_SIENNA_CICHLID:
8001         case CHIP_NAVY_FLOUNDER:
8002         case CHIP_DIMGREY_CAVEFISH:
8003                 amdgpu_gfx_off_ctrl(adev, enable);
8004                 break;
8005         case CHIP_VANGOGH:
8006                 gfx_v10_cntl_pg(adev, enable);
8007                 amdgpu_gfx_off_ctrl(adev, enable);
8008                 break;
8009         default:
8010                 break;
8011         }
8012         return 0;
8013 }
8014
8015 static int gfx_v10_0_set_clockgating_state(void *handle,
8016                                           enum amd_clockgating_state state)
8017 {
8018         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8019
8020         if (amdgpu_sriov_vf(adev))
8021                 return 0;
8022
8023         switch (adev->asic_type) {
8024         case CHIP_NAVI10:
8025         case CHIP_NAVI14:
8026         case CHIP_NAVI12:
8027         case CHIP_SIENNA_CICHLID:
8028         case CHIP_NAVY_FLOUNDER:
8029         case CHIP_VANGOGH:
8030         case CHIP_DIMGREY_CAVEFISH:
8031                 gfx_v10_0_update_gfx_clock_gating(adev,
8032                                                  state == AMD_CG_STATE_GATE);
8033                 break;
8034         default:
8035                 break;
8036         }
8037         return 0;
8038 }
8039
8040 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8041 {
8042         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8043         int data;
8044
8045         /* AMD_CG_SUPPORT_GFX_FGCG */
8046         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8047         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8048                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8049
8050         /* AMD_CG_SUPPORT_GFX_MGCG */
8051         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8052         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8053                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8054
8055         /* AMD_CG_SUPPORT_GFX_CGCG */
8056         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8057         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8058                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8059
8060         /* AMD_CG_SUPPORT_GFX_CGLS */
8061         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8062                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8063
8064         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8065         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8066         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8067                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8068
8069         /* AMD_CG_SUPPORT_GFX_CP_LS */
8070         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8071         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8072                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8073
8074         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8075         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8076         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8077                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8078
8079         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8080         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8081                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8082 }
8083
8084 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8085 {
8086         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8087 }
8088
8089 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8090 {
8091         struct amdgpu_device *adev = ring->adev;
8092         u64 wptr;
8093
8094         /* XXX check if swapping is necessary on BE */
8095         if (ring->use_doorbell) {
8096                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8097         } else {
8098                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8099                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8100         }
8101
8102         return wptr;
8103 }
8104
8105 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8106 {
8107         struct amdgpu_device *adev = ring->adev;
8108
8109         if (ring->use_doorbell) {
8110                 /* XXX check if swapping is necessary on BE */
8111                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8112                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8113         } else {
8114                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8115                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8116         }
8117 }
8118
8119 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8120 {
8121         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8122 }
8123
8124 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8125 {
8126         u64 wptr;
8127
8128         /* XXX check if swapping is necessary on BE */
8129         if (ring->use_doorbell)
8130                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8131         else
8132                 BUG();
8133         return wptr;
8134 }
8135
8136 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8137 {
8138         struct amdgpu_device *adev = ring->adev;
8139
8140         /* XXX check if swapping is necessary on BE */
8141         if (ring->use_doorbell) {
8142                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8143                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8144         } else {
8145                 BUG(); /* only DOORBELL method supported on gfx10 now */
8146         }
8147 }
8148
8149 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8150 {
8151         struct amdgpu_device *adev = ring->adev;
8152         u32 ref_and_mask, reg_mem_engine;
8153         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8154
8155         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8156                 switch (ring->me) {
8157                 case 1:
8158                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8159                         break;
8160                 case 2:
8161                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8162                         break;
8163                 default:
8164                         return;
8165                 }
8166                 reg_mem_engine = 0;
8167         } else {
8168                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8169                 reg_mem_engine = 1; /* pfp */
8170         }
8171
8172         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8173                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8174                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8175                                ref_and_mask, ref_and_mask, 0x20);
8176 }
8177
8178 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8179                                        struct amdgpu_job *job,
8180                                        struct amdgpu_ib *ib,
8181                                        uint32_t flags)
8182 {
8183         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8184         u32 header, control = 0;
8185
8186         if (ib->flags & AMDGPU_IB_FLAG_CE)
8187                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8188         else
8189                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8190
8191         control |= ib->length_dw | (vmid << 24);
8192
8193         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8194                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8195
8196                 if (flags & AMDGPU_IB_PREEMPTED)
8197                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8198
8199                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8200                         gfx_v10_0_ring_emit_de_meta(ring,
8201                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8202         }
8203
8204         amdgpu_ring_write(ring, header);
8205         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8206         amdgpu_ring_write(ring,
8207 #ifdef __BIG_ENDIAN
8208                 (2 << 0) |
8209 #endif
8210                 lower_32_bits(ib->gpu_addr));
8211         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8212         amdgpu_ring_write(ring, control);
8213 }
8214
8215 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8216                                            struct amdgpu_job *job,
8217                                            struct amdgpu_ib *ib,
8218                                            uint32_t flags)
8219 {
8220         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8221         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8222
8223         /* Currently, there is a high possibility to get wave ID mismatch
8224          * between ME and GDS, leading to a hw deadlock, because ME generates
8225          * different wave IDs than the GDS expects. This situation happens
8226          * randomly when at least 5 compute pipes use GDS ordered append.
8227          * The wave IDs generated by ME are also wrong after suspend/resume.
8228          * Those are probably bugs somewhere else in the kernel driver.
8229          *
8230          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8231          * GDS to 0 for this ring (me/pipe).
8232          */
8233         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8234                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8235                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8236                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8237         }
8238
8239         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8240         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8241         amdgpu_ring_write(ring,
8242 #ifdef __BIG_ENDIAN
8243                                 (2 << 0) |
8244 #endif
8245                                 lower_32_bits(ib->gpu_addr));
8246         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8247         amdgpu_ring_write(ring, control);
8248 }
8249
8250 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8251                                      u64 seq, unsigned flags)
8252 {
8253         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8254         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8255
8256         /* RELEASE_MEM - flush caches, send int */
8257         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8258         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8259                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8260                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8261                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8262                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8263                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8264                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8265         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8266                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8267
8268         /*
8269          * the address should be Qword aligned if 64bit write, Dword
8270          * aligned if only send 32bit data low (discard data high)
8271          */
8272         if (write64bit)
8273                 BUG_ON(addr & 0x7);
8274         else
8275                 BUG_ON(addr & 0x3);
8276         amdgpu_ring_write(ring, lower_32_bits(addr));
8277         amdgpu_ring_write(ring, upper_32_bits(addr));
8278         amdgpu_ring_write(ring, lower_32_bits(seq));
8279         amdgpu_ring_write(ring, upper_32_bits(seq));
8280         amdgpu_ring_write(ring, 0);
8281 }
8282
8283 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8284 {
8285         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8286         uint32_t seq = ring->fence_drv.sync_seq;
8287         uint64_t addr = ring->fence_drv.gpu_addr;
8288
8289         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8290                                upper_32_bits(addr), seq, 0xffffffff, 4);
8291 }
8292
8293 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8294                                          unsigned vmid, uint64_t pd_addr)
8295 {
8296         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8297
8298         /* compute doesn't have PFP */
8299         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8300                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8301                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8302                 amdgpu_ring_write(ring, 0x0);
8303         }
8304 }
8305
8306 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8307                                           u64 seq, unsigned int flags)
8308 {
8309         struct amdgpu_device *adev = ring->adev;
8310
8311         /* we only allocate 32bit for each seq wb address */
8312         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8313
8314         /* write fence seq to the "addr" */
8315         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8316         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8317                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8318         amdgpu_ring_write(ring, lower_32_bits(addr));
8319         amdgpu_ring_write(ring, upper_32_bits(addr));
8320         amdgpu_ring_write(ring, lower_32_bits(seq));
8321
8322         if (flags & AMDGPU_FENCE_FLAG_INT) {
8323                 /* set register to trigger INT */
8324                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8325                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8326                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8327                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8328                 amdgpu_ring_write(ring, 0);
8329                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8330         }
8331 }
8332
8333 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8334 {
8335         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8336         amdgpu_ring_write(ring, 0);
8337 }
8338
8339 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8340                                          uint32_t flags)
8341 {
8342         uint32_t dw2 = 0;
8343
8344         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8345                 gfx_v10_0_ring_emit_ce_meta(ring,
8346                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8347
8348         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8349         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8350                 /* set load_global_config & load_global_uconfig */
8351                 dw2 |= 0x8001;
8352                 /* set load_cs_sh_regs */
8353                 dw2 |= 0x01000000;
8354                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8355                 dw2 |= 0x10002;
8356
8357                 /* set load_ce_ram if preamble presented */
8358                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8359                         dw2 |= 0x10000000;
8360         } else {
8361                 /* still load_ce_ram if this is the first time preamble presented
8362                  * although there is no context switch happens.
8363                  */
8364                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8365                         dw2 |= 0x10000000;
8366         }
8367
8368         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8369         amdgpu_ring_write(ring, dw2);
8370         amdgpu_ring_write(ring, 0);
8371 }
8372
8373 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8374 {
8375         unsigned ret;
8376
8377         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8378         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8379         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8380         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8381         ret = ring->wptr & ring->buf_mask;
8382         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8383
8384         return ret;
8385 }
8386
8387 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8388 {
8389         unsigned cur;
8390         BUG_ON(offset > ring->buf_mask);
8391         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8392
8393         cur = (ring->wptr - 1) & ring->buf_mask;
8394         if (likely(cur > offset))
8395                 ring->ring[offset] = cur - offset;
8396         else
8397                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8398 }
8399
8400 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8401 {
8402         int i, r = 0;
8403         struct amdgpu_device *adev = ring->adev;
8404         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8405         struct amdgpu_ring *kiq_ring = &kiq->ring;
8406         unsigned long flags;
8407
8408         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8409                 return -EINVAL;
8410
8411         spin_lock_irqsave(&kiq->ring_lock, flags);
8412
8413         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8414                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8415                 return -ENOMEM;
8416         }
8417
8418         /* assert preemption condition */
8419         amdgpu_ring_set_preempt_cond_exec(ring, false);
8420
8421         /* assert IB preemption, emit the trailing fence */
8422         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8423                                    ring->trail_fence_gpu_addr,
8424                                    ++ring->trail_seq);
8425         amdgpu_ring_commit(kiq_ring);
8426
8427         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8428
8429         /* poll the trailing fence */
8430         for (i = 0; i < adev->usec_timeout; i++) {
8431                 if (ring->trail_seq ==
8432                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8433                         break;
8434                 udelay(1);
8435         }
8436
8437         if (i >= adev->usec_timeout) {
8438                 r = -EINVAL;
8439                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8440         }
8441
8442         /* deassert preemption condition */
8443         amdgpu_ring_set_preempt_cond_exec(ring, true);
8444         return r;
8445 }
8446
8447 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8448 {
8449         struct amdgpu_device *adev = ring->adev;
8450         struct v10_ce_ib_state ce_payload = {0};
8451         uint64_t csa_addr;
8452         int cnt;
8453
8454         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8455         csa_addr = amdgpu_csa_vaddr(ring->adev);
8456
8457         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8458         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8459                                  WRITE_DATA_DST_SEL(8) |
8460                                  WR_CONFIRM) |
8461                                  WRITE_DATA_CACHE_POLICY(0));
8462         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8463                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8464         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8465                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8466
8467         if (resume)
8468                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8469                                            offsetof(struct v10_gfx_meta_data,
8470                                                     ce_payload),
8471                                            sizeof(ce_payload) >> 2);
8472         else
8473                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8474                                            sizeof(ce_payload) >> 2);
8475 }
8476
8477 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8478 {
8479         struct amdgpu_device *adev = ring->adev;
8480         struct v10_de_ib_state de_payload = {0};
8481         uint64_t csa_addr, gds_addr;
8482         int cnt;
8483
8484         csa_addr = amdgpu_csa_vaddr(ring->adev);
8485         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8486                          PAGE_SIZE);
8487         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8488         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8489
8490         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8491         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8492         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8493                                  WRITE_DATA_DST_SEL(8) |
8494                                  WR_CONFIRM) |
8495                                  WRITE_DATA_CACHE_POLICY(0));
8496         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8497                               offsetof(struct v10_gfx_meta_data, de_payload)));
8498         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8499                               offsetof(struct v10_gfx_meta_data, de_payload)));
8500
8501         if (resume)
8502                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8503                                            offsetof(struct v10_gfx_meta_data,
8504                                                     de_payload),
8505                                            sizeof(de_payload) >> 2);
8506         else
8507                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8508                                            sizeof(de_payload) >> 2);
8509 }
8510
8511 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8512                                     bool secure)
8513 {
8514         uint32_t v = secure ? FRAME_TMZ : 0;
8515
8516         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8517         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8518 }
8519
8520 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8521                                      uint32_t reg_val_offs)
8522 {
8523         struct amdgpu_device *adev = ring->adev;
8524
8525         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8526         amdgpu_ring_write(ring, 0 |     /* src: register*/
8527                                 (5 << 8) |      /* dst: memory */
8528                                 (1 << 20));     /* write confirm */
8529         amdgpu_ring_write(ring, reg);
8530         amdgpu_ring_write(ring, 0);
8531         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8532                                 reg_val_offs * 4));
8533         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8534                                 reg_val_offs * 4));
8535 }
8536
8537 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8538                                    uint32_t val)
8539 {
8540         uint32_t cmd = 0;
8541
8542         switch (ring->funcs->type) {
8543         case AMDGPU_RING_TYPE_GFX:
8544                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8545                 break;
8546         case AMDGPU_RING_TYPE_KIQ:
8547                 cmd = (1 << 16); /* no inc addr */
8548                 break;
8549         default:
8550                 cmd = WR_CONFIRM;
8551                 break;
8552         }
8553         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8554         amdgpu_ring_write(ring, cmd);
8555         amdgpu_ring_write(ring, reg);
8556         amdgpu_ring_write(ring, 0);
8557         amdgpu_ring_write(ring, val);
8558 }
8559
8560 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8561                                         uint32_t val, uint32_t mask)
8562 {
8563         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8564 }
8565
8566 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8567                                                    uint32_t reg0, uint32_t reg1,
8568                                                    uint32_t ref, uint32_t mask)
8569 {
8570         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8571         struct amdgpu_device *adev = ring->adev;
8572         bool fw_version_ok = false;
8573
8574         fw_version_ok = adev->gfx.cp_fw_write_wait;
8575
8576         if (fw_version_ok)
8577                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8578                                        ref, mask, 0x20);
8579         else
8580                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8581                                                            ref, mask);
8582 }
8583
8584 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8585                                          unsigned vmid)
8586 {
8587         struct amdgpu_device *adev = ring->adev;
8588         uint32_t value = 0;
8589
8590         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8591         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8592         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8593         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8594         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8595 }
8596
8597 static void
8598 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8599                                       uint32_t me, uint32_t pipe,
8600                                       enum amdgpu_interrupt_state state)
8601 {
8602         uint32_t cp_int_cntl, cp_int_cntl_reg;
8603
8604         if (!me) {
8605                 switch (pipe) {
8606                 case 0:
8607                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8608                         break;
8609                 case 1:
8610                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8611                         break;
8612                 default:
8613                         DRM_DEBUG("invalid pipe %d\n", pipe);
8614                         return;
8615                 }
8616         } else {
8617                 DRM_DEBUG("invalid me %d\n", me);
8618                 return;
8619         }
8620
8621         switch (state) {
8622         case AMDGPU_IRQ_STATE_DISABLE:
8623                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8624                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8625                                             TIME_STAMP_INT_ENABLE, 0);
8626                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8627                 break;
8628         case AMDGPU_IRQ_STATE_ENABLE:
8629                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8630                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8631                                             TIME_STAMP_INT_ENABLE, 1);
8632                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8633                 break;
8634         default:
8635                 break;
8636         }
8637 }
8638
8639 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8640                                                      int me, int pipe,
8641                                                      enum amdgpu_interrupt_state state)
8642 {
8643         u32 mec_int_cntl, mec_int_cntl_reg;
8644
8645         /*
8646          * amdgpu controls only the first MEC. That's why this function only
8647          * handles the setting of interrupts for this specific MEC. All other
8648          * pipes' interrupts are set by amdkfd.
8649          */
8650
8651         if (me == 1) {
8652                 switch (pipe) {
8653                 case 0:
8654                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8655                         break;
8656                 case 1:
8657                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8658                         break;
8659                 case 2:
8660                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8661                         break;
8662                 case 3:
8663                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8664                         break;
8665                 default:
8666                         DRM_DEBUG("invalid pipe %d\n", pipe);
8667                         return;
8668                 }
8669         } else {
8670                 DRM_DEBUG("invalid me %d\n", me);
8671                 return;
8672         }
8673
8674         switch (state) {
8675         case AMDGPU_IRQ_STATE_DISABLE:
8676                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8677                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8678                                              TIME_STAMP_INT_ENABLE, 0);
8679                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8680                 break;
8681         case AMDGPU_IRQ_STATE_ENABLE:
8682                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8683                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8684                                              TIME_STAMP_INT_ENABLE, 1);
8685                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8686                 break;
8687         default:
8688                 break;
8689         }
8690 }
8691
8692 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8693                                             struct amdgpu_irq_src *src,
8694                                             unsigned type,
8695                                             enum amdgpu_interrupt_state state)
8696 {
8697         switch (type) {
8698         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8699                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8700                 break;
8701         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8702                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8703                 break;
8704         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8705                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8706                 break;
8707         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8708                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8709                 break;
8710         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8711                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8712                 break;
8713         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8714                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8715                 break;
8716         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8717                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8718                 break;
8719         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8720                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8721                 break;
8722         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8723                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8724                 break;
8725         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8726                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8727                 break;
8728         default:
8729                 break;
8730         }
8731         return 0;
8732 }
8733
8734 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8735                              struct amdgpu_irq_src *source,
8736                              struct amdgpu_iv_entry *entry)
8737 {
8738         int i;
8739         u8 me_id, pipe_id, queue_id;
8740         struct amdgpu_ring *ring;
8741
8742         DRM_DEBUG("IH: CP EOP\n");
8743         me_id = (entry->ring_id & 0x0c) >> 2;
8744         pipe_id = (entry->ring_id & 0x03) >> 0;
8745         queue_id = (entry->ring_id & 0x70) >> 4;
8746
8747         switch (me_id) {
8748         case 0:
8749                 if (pipe_id == 0)
8750                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8751                 else
8752                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8753                 break;
8754         case 1:
8755         case 2:
8756                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8757                         ring = &adev->gfx.compute_ring[i];
8758                         /* Per-queue interrupt is supported for MEC starting from VI.
8759                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8760                           */
8761                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8762                                 amdgpu_fence_process(ring);
8763                 }
8764                 break;
8765         }
8766         return 0;
8767 }
8768
8769 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8770                                               struct amdgpu_irq_src *source,
8771                                               unsigned type,
8772                                               enum amdgpu_interrupt_state state)
8773 {
8774         switch (state) {
8775         case AMDGPU_IRQ_STATE_DISABLE:
8776         case AMDGPU_IRQ_STATE_ENABLE:
8777                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8778                                PRIV_REG_INT_ENABLE,
8779                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8780                 break;
8781         default:
8782                 break;
8783         }
8784
8785         return 0;
8786 }
8787
8788 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8789                                                struct amdgpu_irq_src *source,
8790                                                unsigned type,
8791                                                enum amdgpu_interrupt_state state)
8792 {
8793         switch (state) {
8794         case AMDGPU_IRQ_STATE_DISABLE:
8795         case AMDGPU_IRQ_STATE_ENABLE:
8796                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8797                                PRIV_INSTR_INT_ENABLE,
8798                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8799                 break;
8800         default:
8801                 break;
8802         }
8803
8804         return 0;
8805 }
8806
8807 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8808                                         struct amdgpu_iv_entry *entry)
8809 {
8810         u8 me_id, pipe_id, queue_id;
8811         struct amdgpu_ring *ring;
8812         int i;
8813
8814         me_id = (entry->ring_id & 0x0c) >> 2;
8815         pipe_id = (entry->ring_id & 0x03) >> 0;
8816         queue_id = (entry->ring_id & 0x70) >> 4;
8817
8818         switch (me_id) {
8819         case 0:
8820                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8821                         ring = &adev->gfx.gfx_ring[i];
8822                         /* we only enabled 1 gfx queue per pipe for now */
8823                         if (ring->me == me_id && ring->pipe == pipe_id)
8824                                 drm_sched_fault(&ring->sched);
8825                 }
8826                 break;
8827         case 1:
8828         case 2:
8829                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8830                         ring = &adev->gfx.compute_ring[i];
8831                         if (ring->me == me_id && ring->pipe == pipe_id &&
8832                             ring->queue == queue_id)
8833                                 drm_sched_fault(&ring->sched);
8834                 }
8835                 break;
8836         default:
8837                 BUG();
8838         }
8839 }
8840
8841 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8842                                   struct amdgpu_irq_src *source,
8843                                   struct amdgpu_iv_entry *entry)
8844 {
8845         DRM_ERROR("Illegal register access in command stream\n");
8846         gfx_v10_0_handle_priv_fault(adev, entry);
8847         return 0;
8848 }
8849
8850 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8851                                    struct amdgpu_irq_src *source,
8852                                    struct amdgpu_iv_entry *entry)
8853 {
8854         DRM_ERROR("Illegal instruction in command stream\n");
8855         gfx_v10_0_handle_priv_fault(adev, entry);
8856         return 0;
8857 }
8858
8859 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8860                                              struct amdgpu_irq_src *src,
8861                                              unsigned int type,
8862                                              enum amdgpu_interrupt_state state)
8863 {
8864         uint32_t tmp, target;
8865         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8866
8867         if (ring->me == 1)
8868                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8869         else
8870                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8871         target += ring->pipe;
8872
8873         switch (type) {
8874         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8875                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8876                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8877                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8878                                             GENERIC2_INT_ENABLE, 0);
8879                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8880
8881                         tmp = RREG32(target);
8882                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8883                                             GENERIC2_INT_ENABLE, 0);
8884                         WREG32(target, tmp);
8885                 } else {
8886                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8887                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8888                                             GENERIC2_INT_ENABLE, 1);
8889                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8890
8891                         tmp = RREG32(target);
8892                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8893                                             GENERIC2_INT_ENABLE, 1);
8894                         WREG32(target, tmp);
8895                 }
8896                 break;
8897         default:
8898                 BUG(); /* kiq only support GENERIC2_INT now */
8899                 break;
8900         }
8901         return 0;
8902 }
8903
8904 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8905                              struct amdgpu_irq_src *source,
8906                              struct amdgpu_iv_entry *entry)
8907 {
8908         u8 me_id, pipe_id, queue_id;
8909         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8910
8911         me_id = (entry->ring_id & 0x0c) >> 2;
8912         pipe_id = (entry->ring_id & 0x03) >> 0;
8913         queue_id = (entry->ring_id & 0x70) >> 4;
8914         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8915                    me_id, pipe_id, queue_id);
8916
8917         amdgpu_fence_process(ring);
8918         return 0;
8919 }
8920
8921 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8922 {
8923         const unsigned int gcr_cntl =
8924                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8925                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8926                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8927                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8928                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8929                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8930                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8931                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8932
8933         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8934         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8935         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8936         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8937         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8938         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8939         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8940         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8941         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8942 }
8943
8944 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8945         .name = "gfx_v10_0",
8946         .early_init = gfx_v10_0_early_init,
8947         .late_init = gfx_v10_0_late_init,
8948         .sw_init = gfx_v10_0_sw_init,
8949         .sw_fini = gfx_v10_0_sw_fini,
8950         .hw_init = gfx_v10_0_hw_init,
8951         .hw_fini = gfx_v10_0_hw_fini,
8952         .suspend = gfx_v10_0_suspend,
8953         .resume = gfx_v10_0_resume,
8954         .is_idle = gfx_v10_0_is_idle,
8955         .wait_for_idle = gfx_v10_0_wait_for_idle,
8956         .soft_reset = gfx_v10_0_soft_reset,
8957         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8958         .set_powergating_state = gfx_v10_0_set_powergating_state,
8959         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8960 };
8961
8962 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8963         .type = AMDGPU_RING_TYPE_GFX,
8964         .align_mask = 0xff,
8965         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8966         .support_64bit_ptrs = true,
8967         .vmhub = AMDGPU_GFXHUB_0,
8968         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8969         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8970         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8971         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8972                 5 + /* COND_EXEC */
8973                 7 + /* PIPELINE_SYNC */
8974                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8975                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8976                 2 + /* VM_FLUSH */
8977                 8 + /* FENCE for VM_FLUSH */
8978                 20 + /* GDS switch */
8979                 4 + /* double SWITCH_BUFFER,
8980                      * the first COND_EXEC jump to the place
8981                      * just prior to this double SWITCH_BUFFER
8982                      */
8983                 5 + /* COND_EXEC */
8984                 7 + /* HDP_flush */
8985                 4 + /* VGT_flush */
8986                 14 + /* CE_META */
8987                 31 + /* DE_META */
8988                 3 + /* CNTX_CTRL */
8989                 5 + /* HDP_INVL */
8990                 8 + 8 + /* FENCE x2 */
8991                 2 + /* SWITCH_BUFFER */
8992                 8, /* gfx_v10_0_emit_mem_sync */
8993         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8994         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8995         .emit_fence = gfx_v10_0_ring_emit_fence,
8996         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8997         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8998         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8999         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9000         .test_ring = gfx_v10_0_ring_test_ring,
9001         .test_ib = gfx_v10_0_ring_test_ib,
9002         .insert_nop = amdgpu_ring_insert_nop,
9003         .pad_ib = amdgpu_ring_generic_pad_ib,
9004         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9005         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9006         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9007         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9008         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9009         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9010         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9011         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9012         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9013         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9014         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9015 };
9016
9017 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9018         .type = AMDGPU_RING_TYPE_COMPUTE,
9019         .align_mask = 0xff,
9020         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9021         .support_64bit_ptrs = true,
9022         .vmhub = AMDGPU_GFXHUB_0,
9023         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9024         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9025         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9026         .emit_frame_size =
9027                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9028                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9029                 5 + /* hdp invalidate */
9030                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9031                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9032                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9033                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9034                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9035                 8, /* gfx_v10_0_emit_mem_sync */
9036         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9037         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9038         .emit_fence = gfx_v10_0_ring_emit_fence,
9039         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9040         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9041         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9042         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9043         .test_ring = gfx_v10_0_ring_test_ring,
9044         .test_ib = gfx_v10_0_ring_test_ib,
9045         .insert_nop = amdgpu_ring_insert_nop,
9046         .pad_ib = amdgpu_ring_generic_pad_ib,
9047         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9048         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9049         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9050         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9051 };
9052
9053 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9054         .type = AMDGPU_RING_TYPE_KIQ,
9055         .align_mask = 0xff,
9056         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9057         .support_64bit_ptrs = true,
9058         .vmhub = AMDGPU_GFXHUB_0,
9059         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9060         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9061         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9062         .emit_frame_size =
9063                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9064                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9065                 5 + /*hdp invalidate */
9066                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9067                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9068                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9069                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9070                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9071         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9072         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9073         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9074         .test_ring = gfx_v10_0_ring_test_ring,
9075         .test_ib = gfx_v10_0_ring_test_ib,
9076         .insert_nop = amdgpu_ring_insert_nop,
9077         .pad_ib = amdgpu_ring_generic_pad_ib,
9078         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9079         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9080         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9081         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9082 };
9083
9084 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9085 {
9086         int i;
9087
9088         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9089
9090         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9091                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9092
9093         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9094                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9095 }
9096
9097 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9098         .set = gfx_v10_0_set_eop_interrupt_state,
9099         .process = gfx_v10_0_eop_irq,
9100 };
9101
9102 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9103         .set = gfx_v10_0_set_priv_reg_fault_state,
9104         .process = gfx_v10_0_priv_reg_irq,
9105 };
9106
9107 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9108         .set = gfx_v10_0_set_priv_inst_fault_state,
9109         .process = gfx_v10_0_priv_inst_irq,
9110 };
9111
9112 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9113         .set = gfx_v10_0_kiq_set_interrupt_state,
9114         .process = gfx_v10_0_kiq_irq,
9115 };
9116
9117 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9118 {
9119         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9120         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9121
9122         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9123         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9124
9125         adev->gfx.priv_reg_irq.num_types = 1;
9126         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9127
9128         adev->gfx.priv_inst_irq.num_types = 1;
9129         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9130 }
9131
9132 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9133 {
9134         switch (adev->asic_type) {
9135         case CHIP_NAVI10:
9136         case CHIP_NAVI14:
9137         case CHIP_SIENNA_CICHLID:
9138         case CHIP_NAVY_FLOUNDER:
9139         case CHIP_VANGOGH:
9140         case CHIP_DIMGREY_CAVEFISH:
9141                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9142                 break;
9143         case CHIP_NAVI12:
9144                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9145                 break;
9146         default:
9147                 break;
9148         }
9149 }
9150
9151 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9152 {
9153         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9154                             adev->gfx.config.max_sh_per_se *
9155                             adev->gfx.config.max_shader_engines;
9156
9157         adev->gds.gds_size = 0x10000;
9158         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9159         adev->gds.gws_size = 64;
9160         adev->gds.oa_size = 16;
9161 }
9162
9163 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9164                                                           u32 bitmap)
9165 {
9166         u32 data;
9167
9168         if (!bitmap)
9169                 return;
9170
9171         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9172         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9173
9174         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9175 }
9176
9177 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9178 {
9179         u32 data, wgp_bitmask;
9180         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9181         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9182
9183         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9184         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9185
9186         wgp_bitmask =
9187                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9188
9189         return (~data) & wgp_bitmask;
9190 }
9191
9192 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9193 {
9194         u32 wgp_idx, wgp_active_bitmap;
9195         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9196
9197         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9198         cu_active_bitmap = 0;
9199
9200         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9201                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9202                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9203                 if (wgp_active_bitmap & (1 << wgp_idx))
9204                         cu_active_bitmap |= cu_bitmap_per_wgp;
9205         }
9206
9207         return cu_active_bitmap;
9208 }
9209
9210 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9211                                  struct amdgpu_cu_info *cu_info)
9212 {
9213         int i, j, k, counter, active_cu_number = 0;
9214         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9215         unsigned disable_masks[4 * 2];
9216
9217         if (!adev || !cu_info)
9218                 return -EINVAL;
9219
9220         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9221
9222         mutex_lock(&adev->grbm_idx_mutex);
9223         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9224                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9225                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9226                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9227                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9228                                 continue;
9229                         mask = 1;
9230                         ao_bitmap = 0;
9231                         counter = 0;
9232                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9233                         if (i < 4 && j < 2)
9234                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9235                                         adev, disable_masks[i * 2 + j]);
9236                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9237                         cu_info->bitmap[i][j] = bitmap;
9238
9239                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9240                                 if (bitmap & mask) {
9241                                         if (counter < adev->gfx.config.max_cu_per_sh)
9242                                                 ao_bitmap |= mask;
9243                                         counter++;
9244                                 }
9245                                 mask <<= 1;
9246                         }
9247                         active_cu_number += counter;
9248                         if (i < 2 && j < 2)
9249                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9250                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9251                 }
9252         }
9253         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9254         mutex_unlock(&adev->grbm_idx_mutex);
9255
9256         cu_info->number = active_cu_number;
9257         cu_info->ao_cu_mask = ao_cu_mask;
9258         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9259
9260         return 0;
9261 }
9262
9263 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9264 {
9265         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9266
9267         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9268         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9269         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9270
9271         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9272         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9273         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9274
9275         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9276                                                 adev->gfx.config.max_shader_engines);
9277         disabled_sa = efuse_setting | vbios_setting;
9278         disabled_sa &= max_sa_mask;
9279
9280         return disabled_sa;
9281 }
9282
9283 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9284 {
9285         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9286         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9287
9288         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9289
9290         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9291         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9292         max_shader_engines = adev->gfx.config.max_shader_engines;
9293
9294         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9295                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9296                 disabled_sa_per_se &= max_sa_per_se_mask;
9297                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9298                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9299                         break;
9300                 }
9301         }
9302 }
9303
9304 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9305 {
9306         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9307                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9308                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9309                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9310
9311         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9312         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9313                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9314                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9315                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9316                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9317
9318         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9319                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9320                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9321                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9322
9323         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9324
9325         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9326                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9327 }
9328
9329 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9330 {
9331         .type = AMD_IP_BLOCK_TYPE_GFX,
9332         .major = 10,
9333         .minor = 0,
9334         .rev = 0,
9335         .funcs = &gfx_v10_0_ip_funcs,
9336 };