drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 177 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 178
 179 #define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 180 #define GFX_RLCG_GC_WRITE       (0x0 << 28)
 181 #define GFX_RLCG_GC_READ        (0x1 << 28)
 182 #define GFX_RLCG_MMHUB_WRITE    (0x2 << 28)
 183
 184 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 185 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 187 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 188 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 189 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 190
 191 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 202
 203 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 204 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 206 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 207 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 208 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 209
 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 216
 217 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 220 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 222 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 223
 224 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 225 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 227 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 228 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 229 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 230
 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 237
 238 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 239 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 240 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 241 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 243 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 244
 245 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 246 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 247 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 248 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 250 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 251
 252 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 253 {
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 294 };
 295
 296 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 297 {
 298         /* Pending on emulation bring up */
 299 };
 300
 301 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 302 {
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1355 };
1356
1357 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1358 {
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1397 };
1398
1399 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1400 {
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1443 };
1444
1445 static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
1446                                  int write, u32 *rlcg_flag)
1447 {
1448         switch (hwip) {
1449         case GC_HWIP:
1450                 if (amdgpu_sriov_reg_indirect_gc(adev)) {
1451                         *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1452
1453                         return true;
1454                 /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
1455                 } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
1456                         *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
1457
1458                         return true;
1459                 }
1460
1461                 break;
1462         case MMHUB_HWIP:
1463                 if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
1464                     (acc_flags & AMDGPU_REGS_RLC) && write) {
1465                         *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
1466                         return true;
1467                 }
1468
1469                 break;
1470         default:
1471                 DRM_DEBUG("Not program register by RLCG\n");
1472         }
1473
1474         return false;
1475 }
1476
1477 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1478 {
1479         static void *scratch_reg0;
1480         static void *scratch_reg1;
1481         static void *scratch_reg2;
1482         static void *scratch_reg3;
1483         static void *spare_int;
1484         static uint32_t grbm_cntl;
1485         static uint32_t grbm_idx;
1486         uint32_t i = 0;
1487         uint32_t retries = 50000;
1488         u32 ret = 0;
1489
1490         scratch_reg0 = adev->rmmio +
1491                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1492         scratch_reg1 = adev->rmmio +
1493                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1494         scratch_reg2 = adev->rmmio +
1495                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1496         scratch_reg3 = adev->rmmio +
1497                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1498
1499         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
1500                 spare_int = adev->rmmio +
1501                             (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
1502                              + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
1503         } else {
1504                 spare_int = adev->rmmio +
1505                             (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1506         }
1507
1508         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1509         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1510
1511         if (offset == grbm_cntl || offset == grbm_idx) {
1512                 if (offset  == grbm_cntl)
1513                         writel(v, scratch_reg2);
1514                 else if (offset == grbm_idx)
1515                         writel(v, scratch_reg3);
1516
1517                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1518         } else {
1519                 writel(v, scratch_reg0);
1520                 writel(offset | flag, scratch_reg1);
1521                 writel(1, spare_int);
1522                 for (i = 0; i < retries; i++) {
1523                         u32 tmp;
1524
1525                         tmp = readl(scratch_reg1);
1526                         if (!(tmp & flag))
1527                                 break;
1528
1529                         udelay(10);
1530                 }
1531
1532                 if (i >= retries)
1533                         pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1534         }
1535
1536         ret = readl(scratch_reg0);
1537
1538         return ret;
1539 }
1540
1541 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
1542 {
1543         u32 rlcg_flag;
1544
1545         if (!amdgpu_sriov_runtime(adev) &&
1546             gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
1547                 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1548                 return;
1549         }
1550
1551         if (acc_flags & AMDGPU_REGS_NO_KIQ)
1552                 WREG32_NO_KIQ(offset, value);
1553         else
1554                 WREG32(offset, value);
1555 }
1556
1557 static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
1558 {
1559         u32 rlcg_flag;
1560
1561         if (!amdgpu_sriov_runtime(adev) &&
1562             gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
1563                 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1564
1565         if (acc_flags & AMDGPU_REGS_NO_KIQ)
1566                 return RREG32_NO_KIQ(offset);
1567         else
1568                 return RREG32(offset);
1569 }
1570
1571 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1572 {
1573         /* Pending on emulation bring up */
1574 };
1575
1576 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1577 {
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2198 };
2199
2200 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2201 {
2202         /* Pending on emulation bring up */
2203 };
2204
2205 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2206 {
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3259 };
3260
3261 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3262 {
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3305 };
3306
3307 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3308 {
3309         /* Pending on emulation bring up */
3310 };
3311
3312 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3313 {
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3355
3356         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3358 };
3359
3360 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3361 {
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3385
3386         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3388 };
3389
3390 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3391 {
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3412 };
3413
3414 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3415 {
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3451 };
3452
3453 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3486 };
3487
3488 #define DEFAULT_SH_MEM_CONFIG \
3489         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3490          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3491          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3492          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3493
3494
3495 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3496 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3497 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3498 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3499 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3500                                  struct amdgpu_cu_info *cu_info);
3501 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3502 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3503                                    u32 sh_num, u32 instance);
3504 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3505
3506 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3507 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3508 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3509 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3510 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3511 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3512 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3513 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3514 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3515 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3516
3517 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3518 {
3519         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3520         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3521                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3522         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3523         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3524         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3525         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3526         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3527         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3528 }
3529
3530 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3531                                  struct amdgpu_ring *ring)
3532 {
3533         struct amdgpu_device *adev = kiq_ring->adev;
3534         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3535         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3536         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3537
3538         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3539         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3540         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3541                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3542                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3543                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3544                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3545                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3546                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3547                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3548                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3549                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3550         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3551         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3552         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3553         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3554         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3555 }
3556
3557 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3558                                    struct amdgpu_ring *ring,
3559                                    enum amdgpu_unmap_queues_action action,
3560                                    u64 gpu_addr, u64 seq)
3561 {
3562         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3563
3564         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3565         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3566                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3567                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3568                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3569                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3570         amdgpu_ring_write(kiq_ring,
3571                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3572
3573         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3574                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3575                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3576                 amdgpu_ring_write(kiq_ring, seq);
3577         } else {
3578                 amdgpu_ring_write(kiq_ring, 0);
3579                 amdgpu_ring_write(kiq_ring, 0);
3580                 amdgpu_ring_write(kiq_ring, 0);
3581         }
3582 }
3583
3584 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3585                                    struct amdgpu_ring *ring,
3586                                    u64 addr,
3587                                    u64 seq)
3588 {
3589         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3590
3591         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3592         amdgpu_ring_write(kiq_ring,
3593                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3594                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3595                           PACKET3_QUERY_STATUS_COMMAND(2));
3596         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3597                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3598                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3599         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3600         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3601         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3602         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3603 }
3604
3605 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3606                                 uint16_t pasid, uint32_t flush_type,
3607                                 bool all_hub)
3608 {
3609         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3610         amdgpu_ring_write(kiq_ring,
3611                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3612                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3613                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3614                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3615 }
3616
3617 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3618         .kiq_set_resources = gfx10_kiq_set_resources,
3619         .kiq_map_queues = gfx10_kiq_map_queues,
3620         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3621         .kiq_query_status = gfx10_kiq_query_status,
3622         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3623         .set_resources_size = 8,
3624         .map_queues_size = 7,
3625         .unmap_queues_size = 6,
3626         .query_status_size = 7,
3627         .invalidate_tlbs_size = 2,
3628 };
3629
3630 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3631 {
3632         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3633 }
3634
3635 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3636 {
3637         switch (adev->asic_type) {
3638         case CHIP_NAVI10:
3639                 soc15_program_register_sequence(adev,
3640                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3641                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3642                 break;
3643         case CHIP_NAVI14:
3644                 soc15_program_register_sequence(adev,
3645                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3646                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3647                 break;
3648         case CHIP_NAVI12:
3649                 soc15_program_register_sequence(adev,
3650                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3651                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3652                 break;
3653         default:
3654                 break;
3655         }
3656 }
3657
3658 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3659 {
3660         switch (adev->asic_type) {
3661         case CHIP_NAVI10:
3662                 soc15_program_register_sequence(adev,
3663                                                 golden_settings_gc_10_1,
3664                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3665                 soc15_program_register_sequence(adev,
3666                                                 golden_settings_gc_10_0_nv10,
3667                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3668                 break;
3669         case CHIP_NAVI14:
3670                 soc15_program_register_sequence(adev,
3671                                                 golden_settings_gc_10_1_1,
3672                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3673                 soc15_program_register_sequence(adev,
3674                                                 golden_settings_gc_10_1_nv14,
3675                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3676                 break;
3677         case CHIP_NAVI12:
3678                 soc15_program_register_sequence(adev,
3679                                                 golden_settings_gc_10_1_2,
3680                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3681                 soc15_program_register_sequence(adev,
3682                                                 golden_settings_gc_10_1_2_nv12,
3683                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3684                 break;
3685         case CHIP_SIENNA_CICHLID:
3686                 soc15_program_register_sequence(adev,
3687                                                 golden_settings_gc_10_3,
3688                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3689                 soc15_program_register_sequence(adev,
3690                                                 golden_settings_gc_10_3_sienna_cichlid,
3691                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3692                 break;
3693         case CHIP_NAVY_FLOUNDER:
3694                 soc15_program_register_sequence(adev,
3695                                                 golden_settings_gc_10_3_2,
3696                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3697                 break;
3698         case CHIP_VANGOGH:
3699                 soc15_program_register_sequence(adev,
3700                                                 golden_settings_gc_10_3_vangogh,
3701                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3702                 break;
3703         case CHIP_YELLOW_CARP:
3704                 soc15_program_register_sequence(adev,
3705                                                 golden_settings_gc_10_3_3,
3706                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3707                 break;
3708         case CHIP_DIMGREY_CAVEFISH:
3709                 soc15_program_register_sequence(adev,
3710                                                 golden_settings_gc_10_3_4,
3711                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3712                 break;
3713         case CHIP_BEIGE_GOBY:
3714                 soc15_program_register_sequence(adev,
3715                                                 golden_settings_gc_10_3_5,
3716                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3717                 break;
3718         default:
3719                 break;
3720         }
3721         gfx_v10_0_init_spm_golden_registers(adev);
3722 }
3723
3724 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3725 {
3726         adev->gfx.scratch.num_reg = 8;
3727         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3728         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3729 }
3730
3731 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3732                                        bool wc, uint32_t reg, uint32_t val)
3733 {
3734         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3735         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3736                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3737         amdgpu_ring_write(ring, reg);
3738         amdgpu_ring_write(ring, 0);
3739         amdgpu_ring_write(ring, val);
3740 }
3741
3742 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3743                                   int mem_space, int opt, uint32_t addr0,
3744                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3745                                   uint32_t inv)
3746 {
3747         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3748         amdgpu_ring_write(ring,
3749                           /* memory (1) or register (0) */
3750                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3751                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3752                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3753                            WAIT_REG_MEM_ENGINE(eng_sel)));
3754
3755         if (mem_space)
3756                 BUG_ON(addr0 & 0x3); /* Dword align */
3757         amdgpu_ring_write(ring, addr0);
3758         amdgpu_ring_write(ring, addr1);
3759         amdgpu_ring_write(ring, ref);
3760         amdgpu_ring_write(ring, mask);
3761         amdgpu_ring_write(ring, inv); /* poll interval */
3762 }
3763
3764 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3765 {
3766         struct amdgpu_device *adev = ring->adev;
3767         uint32_t scratch;
3768         uint32_t tmp = 0;
3769         unsigned i;
3770         int r;
3771
3772         r = amdgpu_gfx_scratch_get(adev, &scratch);
3773         if (r) {
3774                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3775                 return r;
3776         }
3777
3778         WREG32(scratch, 0xCAFEDEAD);
3779
3780         r = amdgpu_ring_alloc(ring, 3);
3781         if (r) {
3782                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3783                           ring->idx, r);
3784                 amdgpu_gfx_scratch_free(adev, scratch);
3785                 return r;
3786         }
3787
3788         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3789         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3790         amdgpu_ring_write(ring, 0xDEADBEEF);
3791         amdgpu_ring_commit(ring);
3792
3793         for (i = 0; i < adev->usec_timeout; i++) {
3794                 tmp = RREG32(scratch);
3795                 if (tmp == 0xDEADBEEF)
3796                         break;
3797                 if (amdgpu_emu_mode == 1)
3798                         msleep(1);
3799                 else
3800                         udelay(1);
3801         }
3802
3803         if (i >= adev->usec_timeout)
3804                 r = -ETIMEDOUT;
3805
3806         amdgpu_gfx_scratch_free(adev, scratch);
3807
3808         return r;
3809 }
3810
3811 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3812 {
3813         struct amdgpu_device *adev = ring->adev;
3814         struct amdgpu_ib ib;
3815         struct dma_fence *f = NULL;
3816         unsigned index;
3817         uint64_t gpu_addr;
3818         uint32_t tmp;
3819         long r;
3820
3821         r = amdgpu_device_wb_get(adev, &index);
3822         if (r)
3823                 return r;
3824
3825         gpu_addr = adev->wb.gpu_addr + (index * 4);
3826         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3827         memset(&ib, 0, sizeof(ib));
3828         r = amdgpu_ib_get(adev, NULL, 16,
3829                                         AMDGPU_IB_POOL_DIRECT, &ib);
3830         if (r)
3831                 goto err1;
3832
3833         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3834         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3835         ib.ptr[2] = lower_32_bits(gpu_addr);
3836         ib.ptr[3] = upper_32_bits(gpu_addr);
3837         ib.ptr[4] = 0xDEADBEEF;
3838         ib.length_dw = 5;
3839
3840         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3841         if (r)
3842                 goto err2;
3843
3844         r = dma_fence_wait_timeout(f, false, timeout);
3845         if (r == 0) {
3846                 r = -ETIMEDOUT;
3847                 goto err2;
3848         } else if (r < 0) {
3849                 goto err2;
3850         }
3851
3852         tmp = adev->wb.wb[index];
3853         if (tmp == 0xDEADBEEF)
3854                 r = 0;
3855         else
3856                 r = -EINVAL;
3857 err2:
3858         amdgpu_ib_free(adev, &ib, NULL);
3859         dma_fence_put(f);
3860 err1:
3861         amdgpu_device_wb_free(adev, index);
3862         return r;
3863 }
3864
3865 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3866 {
3867         release_firmware(adev->gfx.pfp_fw);
3868         adev->gfx.pfp_fw = NULL;
3869         release_firmware(adev->gfx.me_fw);
3870         adev->gfx.me_fw = NULL;
3871         release_firmware(adev->gfx.ce_fw);
3872         adev->gfx.ce_fw = NULL;
3873         release_firmware(adev->gfx.rlc_fw);
3874         adev->gfx.rlc_fw = NULL;
3875         release_firmware(adev->gfx.mec_fw);
3876         adev->gfx.mec_fw = NULL;
3877         release_firmware(adev->gfx.mec2_fw);
3878         adev->gfx.mec2_fw = NULL;
3879
3880         kfree(adev->gfx.rlc.register_list_format);
3881 }
3882
3883 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3884 {
3885         adev->gfx.cp_fw_write_wait = false;
3886
3887         switch (adev->asic_type) {
3888         case CHIP_NAVI10:
3889         case CHIP_NAVI12:
3890         case CHIP_NAVI14:
3891                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3892                     (adev->gfx.me_feature_version >= 27) &&
3893                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3894                     (adev->gfx.pfp_feature_version >= 27) &&
3895                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3896                     (adev->gfx.mec_feature_version >= 27))
3897                         adev->gfx.cp_fw_write_wait = true;
3898                 break;
3899         case CHIP_SIENNA_CICHLID:
3900         case CHIP_NAVY_FLOUNDER:
3901         case CHIP_VANGOGH:
3902         case CHIP_DIMGREY_CAVEFISH:
3903         case CHIP_BEIGE_GOBY:
3904         case CHIP_YELLOW_CARP:
3905                 adev->gfx.cp_fw_write_wait = true;
3906                 break;
3907         default:
3908                 break;
3909         }
3910
3911         if (!adev->gfx.cp_fw_write_wait)
3912                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3913 }
3914
3915
3916 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3917 {
3918         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3919
3920         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3921         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3922         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3923         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3924         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3925         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3926         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3927         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3928         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3929         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3930         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3931         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3932         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3933         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3934                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3935 }
3936
3937 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3938 {
3939         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3940
3941         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3942         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3943         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3944         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3945         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3946 }
3947
3948 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3949 {
3950         bool ret = false;
3951
3952         switch (adev->pdev->revision) {
3953         case 0xc2:
3954         case 0xc3:
3955                 ret = true;
3956                 break;
3957         default:
3958                 ret = false;
3959                 break;
3960         }
3961
3962         return ret ;
3963 }
3964
3965 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3966 {
3967         switch (adev->asic_type) {
3968         case CHIP_NAVI10:
3969                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3970                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3971                 break;
3972         default:
3973                 break;
3974         }
3975 }
3976
3977 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3978 {
3979         const char *chip_name;
3980         char fw_name[40];
3981         char *wks = "";
3982         int err;
3983         struct amdgpu_firmware_info *info = NULL;
3984         const struct common_firmware_header *header = NULL;
3985         const struct gfx_firmware_header_v1_0 *cp_hdr;
3986         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3987         unsigned int *tmp = NULL;
3988         unsigned int i = 0;
3989         uint16_t version_major;
3990         uint16_t version_minor;
3991
3992         DRM_DEBUG("\n");
3993
3994         switch (adev->asic_type) {
3995         case CHIP_NAVI10:
3996                 chip_name = "navi10";
3997                 break;
3998         case CHIP_NAVI14:
3999                 chip_name = "navi14";
4000                 if (!(adev->pdev->device == 0x7340 &&
4001                       adev->pdev->revision != 0x00))
4002                         wks = "_wks";
4003                 break;
4004         case CHIP_NAVI12:
4005                 chip_name = "navi12";
4006                 break;
4007         case CHIP_SIENNA_CICHLID:
4008                 chip_name = "sienna_cichlid";
4009                 break;
4010         case CHIP_NAVY_FLOUNDER:
4011                 chip_name = "navy_flounder";
4012                 break;
4013         case CHIP_VANGOGH:
4014                 chip_name = "vangogh";
4015                 break;
4016         case CHIP_DIMGREY_CAVEFISH:
4017                 chip_name = "dimgrey_cavefish";
4018                 break;
4019         case CHIP_BEIGE_GOBY:
4020                 chip_name = "beige_goby";
4021                 break;
4022         case CHIP_YELLOW_CARP:
4023                 chip_name = "yellow_carp";
4024                 break;
4025         default:
4026                 BUG();
4027         }
4028
4029         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4030         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4031         if (err)
4032                 goto out;
4033         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4034         if (err)
4035                 goto out;
4036         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4037         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4038         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4039
4040         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4041         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4042         if (err)
4043                 goto out;
4044         err = amdgpu_ucode_validate(adev->gfx.me_fw);
4045         if (err)
4046                 goto out;
4047         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4048         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4049         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4050
4051         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4052         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4053         if (err)
4054                 goto out;
4055         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4056         if (err)
4057                 goto out;
4058         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4059         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4060         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4061
4062         if (!amdgpu_sriov_vf(adev)) {
4063                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4064                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4065                 if (err)
4066                         goto out;
4067                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4068                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4069                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4070                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4071
4072                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4073                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4074                 adev->gfx.rlc.save_and_restore_offset =
4075                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
4076                 adev->gfx.rlc.clear_state_descriptor_offset =
4077                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4078                 adev->gfx.rlc.avail_scratch_ram_locations =
4079                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4080                 adev->gfx.rlc.reg_restore_list_size =
4081                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
4082                 adev->gfx.rlc.reg_list_format_start =
4083                         le32_to_cpu(rlc_hdr->reg_list_format_start);
4084                 adev->gfx.rlc.reg_list_format_separate_start =
4085                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4086                 adev->gfx.rlc.starting_offsets_start =
4087                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4088                 adev->gfx.rlc.reg_list_format_size_bytes =
4089                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4090                 adev->gfx.rlc.reg_list_size_bytes =
4091                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4092                 adev->gfx.rlc.register_list_format =
4093                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4094                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4095                 if (!adev->gfx.rlc.register_list_format) {
4096                         err = -ENOMEM;
4097                         goto out;
4098                 }
4099
4100                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4101                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4102                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4103                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4104
4105                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4106
4107                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4108                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4109                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4110                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4111
4112                 if (version_major == 2) {
4113                         if (version_minor >= 1)
4114                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4115                         if (version_minor == 2)
4116                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4117                 }
4118         }
4119
4120         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4121         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4122         if (err)
4123                 goto out;
4124         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4125         if (err)
4126                 goto out;
4127         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4128         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4129         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4130
4131         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4132         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4133         if (!err) {
4134                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4135                 if (err)
4136                         goto out;
4137                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4138                 adev->gfx.mec2_fw->data;
4139                 adev->gfx.mec2_fw_version =
4140                 le32_to_cpu(cp_hdr->header.ucode_version);
4141                 adev->gfx.mec2_feature_version =
4142                 le32_to_cpu(cp_hdr->ucode_feature_version);
4143         } else {
4144                 err = 0;
4145                 adev->gfx.mec2_fw = NULL;
4146         }
4147
4148         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4149                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4150                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4151                 info->fw = adev->gfx.pfp_fw;
4152                 header = (const struct common_firmware_header *)info->fw->data;
4153                 adev->firmware.fw_size +=
4154                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4155
4156                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4157                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4158                 info->fw = adev->gfx.me_fw;
4159                 header = (const struct common_firmware_header *)info->fw->data;
4160                 adev->firmware.fw_size +=
4161                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4162
4163                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4164                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4165                 info->fw = adev->gfx.ce_fw;
4166                 header = (const struct common_firmware_header *)info->fw->data;
4167                 adev->firmware.fw_size +=
4168                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4169
4170                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4171                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4172                 info->fw = adev->gfx.rlc_fw;
4173                 if (info->fw) {
4174                         header = (const struct common_firmware_header *)info->fw->data;
4175                         adev->firmware.fw_size +=
4176                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4177                 }
4178                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4179                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4180                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4181                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4182                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4183                         info->fw = adev->gfx.rlc_fw;
4184                         adev->firmware.fw_size +=
4185                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4186
4187                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4188                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4189                         info->fw = adev->gfx.rlc_fw;
4190                         adev->firmware.fw_size +=
4191                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4192
4193                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4194                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4195                         info->fw = adev->gfx.rlc_fw;
4196                         adev->firmware.fw_size +=
4197                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4198
4199                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4200                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4201                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4202                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4203                                 info->fw = adev->gfx.rlc_fw;
4204                                 adev->firmware.fw_size +=
4205                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4206
4207                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4208                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4209                                 info->fw = adev->gfx.rlc_fw;
4210                                 adev->firmware.fw_size +=
4211                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4212                         }
4213                 }
4214
4215                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4216                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4217                 info->fw = adev->gfx.mec_fw;
4218                 header = (const struct common_firmware_header *)info->fw->data;
4219                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4220                 adev->firmware.fw_size +=
4221                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4222                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4223
4224                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4225                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4226                 info->fw = adev->gfx.mec_fw;
4227                 adev->firmware.fw_size +=
4228                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4229
4230                 if (adev->gfx.mec2_fw) {
4231                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4232                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4233                         info->fw = adev->gfx.mec2_fw;
4234                         header = (const struct common_firmware_header *)info->fw->data;
4235                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4236                         adev->firmware.fw_size +=
4237                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4238                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4239                                       PAGE_SIZE);
4240                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4241                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4242                         info->fw = adev->gfx.mec2_fw;
4243                         adev->firmware.fw_size +=
4244                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4245                                       PAGE_SIZE);
4246                 }
4247         }
4248
4249         gfx_v10_0_check_fw_write_wait(adev);
4250 out:
4251         if (err) {
4252                 dev_err(adev->dev,
4253                         "gfx10: Failed to load firmware \"%s\"\n",
4254                         fw_name);
4255                 release_firmware(adev->gfx.pfp_fw);
4256                 adev->gfx.pfp_fw = NULL;
4257                 release_firmware(adev->gfx.me_fw);
4258                 adev->gfx.me_fw = NULL;
4259                 release_firmware(adev->gfx.ce_fw);
4260                 adev->gfx.ce_fw = NULL;
4261                 release_firmware(adev->gfx.rlc_fw);
4262                 adev->gfx.rlc_fw = NULL;
4263                 release_firmware(adev->gfx.mec_fw);
4264                 adev->gfx.mec_fw = NULL;
4265                 release_firmware(adev->gfx.mec2_fw);
4266                 adev->gfx.mec2_fw = NULL;
4267         }
4268
4269         gfx_v10_0_check_gfxoff_flag(adev);
4270
4271         return err;
4272 }
4273
4274 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4275 {
4276         u32 count = 0;
4277         const struct cs_section_def *sect = NULL;
4278         const struct cs_extent_def *ext = NULL;
4279
4280         /* begin clear state */
4281         count += 2;
4282         /* context control state */
4283         count += 3;
4284
4285         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4286                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4287                         if (sect->id == SECT_CONTEXT)
4288                                 count += 2 + ext->reg_count;
4289                         else
4290                                 return 0;
4291                 }
4292         }
4293
4294         /* set PA_SC_TILE_STEERING_OVERRIDE */
4295         count += 3;
4296         /* end clear state */
4297         count += 2;
4298         /* clear state */
4299         count += 2;
4300
4301         return count;
4302 }
4303
4304 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4305                                     volatile u32 *buffer)
4306 {
4307         u32 count = 0, i;
4308         const struct cs_section_def *sect = NULL;
4309         const struct cs_extent_def *ext = NULL;
4310         int ctx_reg_offset;
4311
4312         if (adev->gfx.rlc.cs_data == NULL)
4313                 return;
4314         if (buffer == NULL)
4315                 return;
4316
4317         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4318         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4319
4320         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4321         buffer[count++] = cpu_to_le32(0x80000000);
4322         buffer[count++] = cpu_to_le32(0x80000000);
4323
4324         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4325                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4326                         if (sect->id == SECT_CONTEXT) {
4327                                 buffer[count++] =
4328                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4329                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4330                                                 PACKET3_SET_CONTEXT_REG_START);
4331                                 for (i = 0; i < ext->reg_count; i++)
4332                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4333                         } else {
4334                                 return;
4335                         }
4336                 }
4337         }
4338
4339         ctx_reg_offset =
4340                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4341         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4342         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4343         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4344
4345         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4346         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4347
4348         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4349         buffer[count++] = cpu_to_le32(0);
4350 }
4351
4352 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4353 {
4354         /* clear state block */
4355         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4356                         &adev->gfx.rlc.clear_state_gpu_addr,
4357                         (void **)&adev->gfx.rlc.cs_ptr);
4358
4359         /* jump table block */
4360         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4361                         &adev->gfx.rlc.cp_table_gpu_addr,
4362                         (void **)&adev->gfx.rlc.cp_table_ptr);
4363 }
4364
4365 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4366 {
4367         const struct cs_section_def *cs_data;
4368         int r;
4369
4370         adev->gfx.rlc.cs_data = gfx10_cs_data;
4371
4372         cs_data = adev->gfx.rlc.cs_data;
4373
4374         if (cs_data) {
4375                 /* init clear state block */
4376                 r = amdgpu_gfx_rlc_init_csb(adev);
4377                 if (r)
4378                         return r;
4379         }
4380
4381         /* init spm vmid with 0xf */
4382         if (adev->gfx.rlc.funcs->update_spm_vmid)
4383                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4384
4385         return 0;
4386 }
4387
4388 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4389 {
4390         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4391         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4392 }
4393
4394 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4395 {
4396         int r;
4397
4398         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4399
4400         amdgpu_gfx_graphics_queue_acquire(adev);
4401
4402         r = gfx_v10_0_init_microcode(adev);
4403         if (r)
4404                 DRM_ERROR("Failed to load gfx firmware!\n");
4405
4406         return r;
4407 }
4408
4409 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4410 {
4411         int r;
4412         u32 *hpd;
4413         const __le32 *fw_data = NULL;
4414         unsigned fw_size;
4415         u32 *fw = NULL;
4416         size_t mec_hpd_size;
4417
4418         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4419
4420         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4421
4422         /* take ownership of the relevant compute queues */
4423         amdgpu_gfx_compute_queue_acquire(adev);
4424         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4425
4426         if (mec_hpd_size) {
4427                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4428                                               AMDGPU_GEM_DOMAIN_GTT,
4429                                               &adev->gfx.mec.hpd_eop_obj,
4430                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4431                                               (void **)&hpd);
4432                 if (r) {
4433                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4434                         gfx_v10_0_mec_fini(adev);
4435                         return r;
4436                 }
4437
4438                 memset(hpd, 0, mec_hpd_size);
4439
4440                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4441                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4442         }
4443
4444         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4445                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4446
4447                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4448                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4449                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4450
4451                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4452                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4453                                               &adev->gfx.mec.mec_fw_obj,
4454                                               &adev->gfx.mec.mec_fw_gpu_addr,
4455                                               (void **)&fw);
4456                 if (r) {
4457                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4458                         gfx_v10_0_mec_fini(adev);
4459                         return r;
4460                 }
4461
4462                 memcpy(fw, fw_data, fw_size);
4463
4464                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4465                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4466         }
4467
4468         return 0;
4469 }
4470
4471 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4472 {
4473         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4474                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4475                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4476         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4477 }
4478
4479 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4480                            uint32_t thread, uint32_t regno,
4481                            uint32_t num, uint32_t *out)
4482 {
4483         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4484                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4485                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4486                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4487                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4488         while (num--)
4489                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4490 }
4491
4492 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4493 {
4494         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4495          * field when performing a select_se_sh so it should be
4496          * zero here */
4497         WARN_ON(simd != 0);
4498
4499         /* type 2 wave data */
4500         dst[(*no_fields)++] = 2;
4501         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4502         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4503         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4504         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4505         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4506         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4507         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4508         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4509         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4510         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4511         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4512         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4513         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4514         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4515         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4516 }
4517
4518 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4519                                      uint32_t wave, uint32_t start,
4520                                      uint32_t size, uint32_t *dst)
4521 {
4522         WARN_ON(simd != 0);
4523
4524         wave_read_regs(
4525                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4526                 dst);
4527 }
4528
4529 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4530                                       uint32_t wave, uint32_t thread,
4531                                       uint32_t start, uint32_t size,
4532                                       uint32_t *dst)
4533 {
4534         wave_read_regs(
4535                 adev, wave, thread,
4536                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4537 }
4538
4539 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4540                                        u32 me, u32 pipe, u32 q, u32 vm)
4541 {
4542         nv_grbm_select(adev, me, pipe, q, vm);
4543 }
4544
4545 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4546                                           bool enable)
4547 {
4548         uint32_t data, def;
4549
4550         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4551
4552         if (enable)
4553                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4554         else
4555                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4556
4557         if (data != def)
4558                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4559 }
4560
4561 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4562         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4563         .select_se_sh = &gfx_v10_0_select_se_sh,
4564         .read_wave_data = &gfx_v10_0_read_wave_data,
4565         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4566         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4567         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4568         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4569         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4570 };
4571
4572 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4573 {
4574         u32 gb_addr_config;
4575
4576         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4577
4578         switch (adev->asic_type) {
4579         case CHIP_NAVI10:
4580         case CHIP_NAVI14:
4581         case CHIP_NAVI12:
4582                 adev->gfx.config.max_hw_contexts = 8;
4583                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4584                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4585                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4586                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4587                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4588                 break;
4589         case CHIP_SIENNA_CICHLID:
4590         case CHIP_NAVY_FLOUNDER:
4591         case CHIP_VANGOGH:
4592         case CHIP_DIMGREY_CAVEFISH:
4593         case CHIP_BEIGE_GOBY:
4594         case CHIP_YELLOW_CARP:
4595                 adev->gfx.config.max_hw_contexts = 8;
4596                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4597                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4598                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4599                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4600                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4601                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4602                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4603                 break;
4604         default:
4605                 BUG();
4606                 break;
4607         }
4608
4609         adev->gfx.config.gb_addr_config = gb_addr_config;
4610
4611         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4612                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4613                                       GB_ADDR_CONFIG, NUM_PIPES);
4614
4615         adev->gfx.config.max_tile_pipes =
4616                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4617
4618         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4619                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4620                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4621         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4622                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4623                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4624         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4625                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4626                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4627         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4628                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4629                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4630 }
4631
4632 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4633                                    int me, int pipe, int queue)
4634 {
4635         int r;
4636         struct amdgpu_ring *ring;
4637         unsigned int irq_type;
4638
4639         ring = &adev->gfx.gfx_ring[ring_id];
4640
4641         ring->me = me;
4642         ring->pipe = pipe;
4643         ring->queue = queue;
4644
4645         ring->ring_obj = NULL;
4646         ring->use_doorbell = true;
4647
4648         if (!ring_id)
4649                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4650         else
4651                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4652         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4653
4654         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4655         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4656                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4657         if (r)
4658                 return r;
4659         return 0;
4660 }
4661
4662 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4663                                        int mec, int pipe, int queue)
4664 {
4665         int r;
4666         unsigned irq_type;
4667         struct amdgpu_ring *ring;
4668         unsigned int hw_prio;
4669
4670         ring = &adev->gfx.compute_ring[ring_id];
4671
4672         /* mec0 is me1 */
4673         ring->me = mec + 1;
4674         ring->pipe = pipe;
4675         ring->queue = queue;
4676
4677         ring->ring_obj = NULL;
4678         ring->use_doorbell = true;
4679         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4680         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4681                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4682         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4683
4684         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4685                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4686                 + ring->pipe;
4687         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4688                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4689         /* type-2 packets are deprecated on MEC, use type-3 instead */
4690         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4691                              hw_prio, NULL);
4692         if (r)
4693                 return r;
4694
4695         return 0;
4696 }
4697
4698 static int gfx_v10_0_sw_init(void *handle)
4699 {
4700         int i, j, k, r, ring_id = 0;
4701         struct amdgpu_kiq *kiq;
4702         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4703
4704         switch (adev->asic_type) {
4705         case CHIP_NAVI10:
4706         case CHIP_NAVI14:
4707         case CHIP_NAVI12:
4708                 adev->gfx.me.num_me = 1;
4709                 adev->gfx.me.num_pipe_per_me = 1;
4710                 adev->gfx.me.num_queue_per_pipe = 1;
4711                 adev->gfx.mec.num_mec = 2;
4712                 adev->gfx.mec.num_pipe_per_mec = 4;
4713                 adev->gfx.mec.num_queue_per_pipe = 8;
4714                 break;
4715         case CHIP_SIENNA_CICHLID:
4716         case CHIP_NAVY_FLOUNDER:
4717         case CHIP_VANGOGH:
4718         case CHIP_DIMGREY_CAVEFISH:
4719         case CHIP_BEIGE_GOBY:
4720         case CHIP_YELLOW_CARP:
4721                 adev->gfx.me.num_me = 1;
4722                 adev->gfx.me.num_pipe_per_me = 1;
4723                 adev->gfx.me.num_queue_per_pipe = 1;
4724                 adev->gfx.mec.num_mec = 2;
4725                 adev->gfx.mec.num_pipe_per_mec = 4;
4726                 adev->gfx.mec.num_queue_per_pipe = 4;
4727                 break;
4728         default:
4729                 adev->gfx.me.num_me = 1;
4730                 adev->gfx.me.num_pipe_per_me = 1;
4731                 adev->gfx.me.num_queue_per_pipe = 1;
4732                 adev->gfx.mec.num_mec = 1;
4733                 adev->gfx.mec.num_pipe_per_mec = 4;
4734                 adev->gfx.mec.num_queue_per_pipe = 8;
4735                 break;
4736         }
4737
4738         /* KIQ event */
4739         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4740                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4741                               &adev->gfx.kiq.irq);
4742         if (r)
4743                 return r;
4744
4745         /* EOP Event */
4746         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4747                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4748                               &adev->gfx.eop_irq);
4749         if (r)
4750                 return r;
4751
4752         /* Privileged reg */
4753         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4754                               &adev->gfx.priv_reg_irq);
4755         if (r)
4756                 return r;
4757
4758         /* Privileged inst */
4759         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4760                               &adev->gfx.priv_inst_irq);
4761         if (r)
4762                 return r;
4763
4764         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4765
4766         gfx_v10_0_scratch_init(adev);
4767
4768         r = gfx_v10_0_me_init(adev);
4769         if (r)
4770                 return r;
4771
4772         r = gfx_v10_0_rlc_init(adev);
4773         if (r) {
4774                 DRM_ERROR("Failed to init rlc BOs!\n");
4775                 return r;
4776         }
4777
4778         r = gfx_v10_0_mec_init(adev);
4779         if (r) {
4780                 DRM_ERROR("Failed to init MEC BOs!\n");
4781                 return r;
4782         }
4783
4784         /* set up the gfx ring */
4785         for (i = 0; i < adev->gfx.me.num_me; i++) {
4786                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4787                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4788                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4789                                         continue;
4790
4791                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4792                                                             i, k, j);
4793                                 if (r)
4794                                         return r;
4795                                 ring_id++;
4796                         }
4797                 }
4798         }
4799
4800         ring_id = 0;
4801         /* set up the compute queues - allocate horizontally across pipes */
4802         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4803                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4804                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4805                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4806                                                                      j))
4807                                         continue;
4808
4809                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4810                                                                 i, k, j);
4811                                 if (r)
4812                                         return r;
4813
4814                                 ring_id++;
4815                         }
4816                 }
4817         }
4818
4819         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4820         if (r) {
4821                 DRM_ERROR("Failed to init KIQ BOs!\n");
4822                 return r;
4823         }
4824
4825         kiq = &adev->gfx.kiq;
4826         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4827         if (r)
4828                 return r;
4829
4830         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4831         if (r)
4832                 return r;
4833
4834         /* allocate visible FB for rlc auto-loading fw */
4835         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4836                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4837                 if (r)
4838                         return r;
4839         }
4840
4841         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4842
4843         gfx_v10_0_gpu_early_init(adev);
4844
4845         return 0;
4846 }
4847
4848 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4849 {
4850         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4851                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4852                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4853 }
4854
4855 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4856 {
4857         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4858                               &adev->gfx.ce.ce_fw_gpu_addr,
4859                               (void **)&adev->gfx.ce.ce_fw_ptr);
4860 }
4861
4862 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4863 {
4864         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4865                               &adev->gfx.me.me_fw_gpu_addr,
4866                               (void **)&adev->gfx.me.me_fw_ptr);
4867 }
4868
4869 static int gfx_v10_0_sw_fini(void *handle)
4870 {
4871         int i;
4872         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4873
4874         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4875                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4876         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4877                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4878
4879         amdgpu_gfx_mqd_sw_fini(adev);
4880         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4881         amdgpu_gfx_kiq_fini(adev);
4882
4883         gfx_v10_0_pfp_fini(adev);
4884         gfx_v10_0_ce_fini(adev);
4885         gfx_v10_0_me_fini(adev);
4886         gfx_v10_0_rlc_fini(adev);
4887         gfx_v10_0_mec_fini(adev);
4888
4889         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4890                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4891
4892         gfx_v10_0_free_microcode(adev);
4893
4894         return 0;
4895 }
4896
4897 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4898                                    u32 sh_num, u32 instance)
4899 {
4900         u32 data;
4901
4902         if (instance == 0xffffffff)
4903                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4904                                      INSTANCE_BROADCAST_WRITES, 1);
4905         else
4906                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4907                                      instance);
4908
4909         if (se_num == 0xffffffff)
4910                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4911                                      1);
4912         else
4913                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4914
4915         if (sh_num == 0xffffffff)
4916                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4917                                      1);
4918         else
4919                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4920
4921         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4922 }
4923
4924 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4925 {
4926         u32 data, mask;
4927
4928         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4929         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4930
4931         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4932         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4933
4934         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4935                                          adev->gfx.config.max_sh_per_se);
4936
4937         return (~data) & mask;
4938 }
4939
4940 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4941 {
4942         int i, j;
4943         u32 data;
4944         u32 active_rbs = 0;
4945         u32 bitmap;
4946         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4947                                         adev->gfx.config.max_sh_per_se;
4948
4949         mutex_lock(&adev->grbm_idx_mutex);
4950         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4951                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4952                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4953                         if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
4954                                 (adev->asic_type == CHIP_YELLOW_CARP)) &&
4955                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4956                                 continue;
4957                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4958                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4959                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4960                                                rb_bitmap_width_per_sh);
4961                 }
4962         }
4963         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4964         mutex_unlock(&adev->grbm_idx_mutex);
4965
4966         adev->gfx.config.backend_enable_mask = active_rbs;
4967         adev->gfx.config.num_rbs = hweight32(active_rbs);
4968 }
4969
4970 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4971 {
4972         uint32_t num_sc;
4973         uint32_t enabled_rb_per_sh;
4974         uint32_t active_rb_bitmap;
4975         uint32_t num_rb_per_sc;
4976         uint32_t num_packer_per_sc;
4977         uint32_t pa_sc_tile_steering_override;
4978
4979         /* for ASICs that integrates GFX v10.3
4980          * pa_sc_tile_steering_override should be set to 0 */
4981         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4982                 return 0;
4983
4984         /* init num_sc */
4985         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4986                         adev->gfx.config.num_sc_per_sh;
4987         /* init num_rb_per_sc */
4988         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4989         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4990         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4991         /* init num_packer_per_sc */
4992         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4993
4994         pa_sc_tile_steering_override = 0;
4995         pa_sc_tile_steering_override |=
4996                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4997                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4998         pa_sc_tile_steering_override |=
4999                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5000                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5001         pa_sc_tile_steering_override |=
5002                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5003                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5004
5005         return pa_sc_tile_steering_override;
5006 }
5007
5008 #define DEFAULT_SH_MEM_BASES    (0x6000)
5009
5010 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5011 {
5012         int i;
5013         uint32_t sh_mem_bases;
5014
5015         /*
5016          * Configure apertures:
5017          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5018          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5019          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5020          */
5021         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5022
5023         mutex_lock(&adev->srbm_mutex);
5024         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5025                 nv_grbm_select(adev, 0, 0, 0, i);
5026                 /* CP and shaders */
5027                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5028                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5029         }
5030         nv_grbm_select(adev, 0, 0, 0, 0);
5031         mutex_unlock(&adev->srbm_mutex);
5032
5033         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5034            acccess. These should be enabled by FW for target VMIDs. */
5035         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5036                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5037                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5038                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5039                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5040         }
5041 }
5042
5043 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5044 {
5045         int vmid;
5046
5047         /*
5048          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5049          * access. Compute VMIDs should be enabled by FW for target VMIDs,
5050          * the driver can enable them for graphics. VMID0 should maintain
5051          * access so that HWS firmware can save/restore entries.
5052          */
5053         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5054                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5055                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5056                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5057                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5058         }
5059 }
5060
5061
5062 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5063 {
5064         int i, j, k;
5065         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5066         u32 tmp, wgp_active_bitmap = 0;
5067         u32 gcrd_targets_disable_tcp = 0;
5068         u32 utcl_invreq_disable = 0;
5069         /*
5070          * GCRD_TARGETS_DISABLE field contains
5071          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5072          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5073          */
5074         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5075                 2 * max_wgp_per_sh + /* TCP */
5076                 max_wgp_per_sh + /* SQC */
5077                 4); /* GL1C */
5078         /*
5079          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5080          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5081          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5082          */
5083         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5084                 2 * max_wgp_per_sh + /* TCP */
5085                 2 * max_wgp_per_sh + /* SQC */
5086                 4 + /* RMI */
5087                 1); /* SQG */
5088
5089         mutex_lock(&adev->grbm_idx_mutex);
5090         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5091                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5092                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5093                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5094                         /*
5095                          * Set corresponding TCP bits for the inactive WGPs in
5096                          * GCRD_SA_TARGETS_DISABLE
5097                          */
5098                         gcrd_targets_disable_tcp = 0;
5099                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5100                         utcl_invreq_disable = 0;
5101
5102                         for (k = 0; k < max_wgp_per_sh; k++) {
5103                                 if (!(wgp_active_bitmap & (1 << k))) {
5104                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
5105                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5106                                         utcl_invreq_disable |= (3 << (2 * k)) |
5107                                                 (3 << (2 * (max_wgp_per_sh + k)));
5108                                 }
5109                         }
5110
5111                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5112                         /* only override TCP & SQC bits */
5113                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5114                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5115                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5116
5117                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5118                         /* only override TCP & SQC bits */
5119                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5120                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5121                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5122                 }
5123         }
5124
5125         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5126         mutex_unlock(&adev->grbm_idx_mutex);
5127 }
5128
5129 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5130 {
5131         /* TCCs are global (not instanced). */
5132         uint32_t tcc_disable;
5133
5134         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5135                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5136                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5137         } else {
5138                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5139                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5140         }
5141
5142         adev->gfx.config.tcc_disabled_mask =
5143                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5144                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5145 }
5146
5147 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5148 {
5149         u32 tmp;
5150         int i;
5151
5152         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5153
5154         gfx_v10_0_setup_rb(adev);
5155         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5156         gfx_v10_0_get_tcc_info(adev);
5157         adev->gfx.config.pa_sc_tile_steering_override =
5158                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5159
5160         /* XXX SH_MEM regs */
5161         /* where to put LDS, scratch, GPUVM in FSA64 space */
5162         mutex_lock(&adev->srbm_mutex);
5163         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5164                 nv_grbm_select(adev, 0, 0, 0, i);
5165                 /* CP and shaders */
5166                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5167                 if (i != 0) {
5168                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5169                                 (adev->gmc.private_aperture_start >> 48));
5170                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5171                                 (adev->gmc.shared_aperture_start >> 48));
5172                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5173                 }
5174         }
5175         nv_grbm_select(adev, 0, 0, 0, 0);
5176
5177         mutex_unlock(&adev->srbm_mutex);
5178
5179         gfx_v10_0_init_compute_vmid(adev);
5180         gfx_v10_0_init_gds_vmid(adev);
5181
5182 }
5183
5184 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5185                                                bool enable)
5186 {
5187         u32 tmp;
5188
5189         if (amdgpu_sriov_vf(adev))
5190                 return;
5191
5192         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5193
5194         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5195                             enable ? 1 : 0);
5196         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5197                             enable ? 1 : 0);
5198         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5199                             enable ? 1 : 0);
5200         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5201                             enable ? 1 : 0);
5202
5203         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5204 }
5205
5206 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5207 {
5208         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5209
5210         /* csib */
5211         if (adev->asic_type == CHIP_NAVI12) {
5212                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5213                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5214                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5215                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5216                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5217         } else {
5218                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5219                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5220                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5221                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5222                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5223         }
5224         return 0;
5225 }
5226
5227 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5228 {
5229         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5230
5231         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5232         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5233 }
5234
5235 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5236 {
5237         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5238         udelay(50);
5239         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5240         udelay(50);
5241 }
5242
5243 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5244                                              bool enable)
5245 {
5246         uint32_t rlc_pg_cntl;
5247
5248         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5249
5250         if (!enable) {
5251                 /* RLC_PG_CNTL[23] = 0 (default)
5252                  * RLC will wait for handshake acks with SMU
5253                  * GFXOFF will be enabled
5254                  * RLC_PG_CNTL[23] = 1
5255                  * RLC will not issue any message to SMU
5256                  * hence no handshake between SMU & RLC
5257                  * GFXOFF will be disabled
5258                  */
5259                 rlc_pg_cntl |= 0x800000;
5260         } else
5261                 rlc_pg_cntl &= ~0x800000;
5262         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5263 }
5264
5265 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5266 {
5267         /* TODO: enable rlc & smu handshake until smu
5268          * and gfxoff feature works as expected */
5269         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5270                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5271
5272         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5273         udelay(50);
5274 }
5275
5276 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5277 {
5278         uint32_t tmp;
5279
5280         /* enable Save Restore Machine */
5281         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5282         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5283         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5284         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5285 }
5286
5287 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5288 {
5289         const struct rlc_firmware_header_v2_0 *hdr;
5290         const __le32 *fw_data;
5291         unsigned i, fw_size;
5292
5293         if (!adev->gfx.rlc_fw)
5294                 return -EINVAL;
5295
5296         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5297         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5298
5299         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5300                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5301         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5302
5303         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5304                      RLCG_UCODE_LOADING_START_ADDRESS);
5305
5306         for (i = 0; i < fw_size; i++)
5307                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5308                              le32_to_cpup(fw_data++));
5309
5310         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5311
5312         return 0;
5313 }
5314
5315 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5316 {
5317         int r;
5318
5319         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5320
5321                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5322                 if (r)
5323                         return r;
5324
5325                 gfx_v10_0_init_csb(adev);
5326
5327                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5328                         gfx_v10_0_rlc_enable_srm(adev);
5329         } else {
5330                 if (amdgpu_sriov_vf(adev)) {
5331                         gfx_v10_0_init_csb(adev);
5332                         return 0;
5333                 }
5334
5335                 adev->gfx.rlc.funcs->stop(adev);
5336
5337                 /* disable CG */
5338                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5339
5340                 /* disable PG */
5341                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5342
5343                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5344                         /* legacy rlc firmware loading */
5345                         r = gfx_v10_0_rlc_load_microcode(adev);
5346                         if (r)
5347                                 return r;
5348                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5349                         /* rlc backdoor autoload firmware */
5350                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5351                         if (r)
5352                                 return r;
5353                 }
5354
5355                 gfx_v10_0_init_csb(adev);
5356
5357                 adev->gfx.rlc.funcs->start(adev);
5358
5359                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5360                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5361                         if (r)
5362                                 return r;
5363                 }
5364         }
5365         return 0;
5366 }
5367
5368 static struct {
5369         FIRMWARE_ID     id;
5370         unsigned int    offset;
5371         unsigned int    size;
5372 } rlc_autoload_info[FIRMWARE_ID_MAX];
5373
5374 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5375 {
5376         int ret;
5377         RLC_TABLE_OF_CONTENT *rlc_toc;
5378
5379         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5380                                         AMDGPU_GEM_DOMAIN_GTT,
5381                                         &adev->gfx.rlc.rlc_toc_bo,
5382                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5383                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5384         if (ret) {
5385                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5386                 return ret;
5387         }
5388
5389         /* Copy toc from psp sos fw to rlc toc buffer */
5390         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5391
5392         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5393         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5394                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5395                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5396                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5397                         /* Offset needs 4KB alignment */
5398                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5399                 }
5400
5401                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5402                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5403                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5404
5405                 rlc_toc++;
5406         }
5407
5408         return 0;
5409 }
5410
5411 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5412 {
5413         uint32_t total_size = 0;
5414         FIRMWARE_ID id;
5415         int ret;
5416
5417         ret = gfx_v10_0_parse_rlc_toc(adev);
5418         if (ret) {
5419                 dev_err(adev->dev, "failed to parse rlc toc\n");
5420                 return 0;
5421         }
5422
5423         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5424                 total_size += rlc_autoload_info[id].size;
5425
5426         /* In case the offset in rlc toc ucode is aligned */
5427         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5428                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5429                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5430
5431         return total_size;
5432 }
5433
5434 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5435 {
5436         int r;
5437         uint32_t total_size;
5438
5439         total_size = gfx_v10_0_calc_toc_total_size(adev);
5440
5441         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5442                                       AMDGPU_GEM_DOMAIN_GTT,
5443                                       &adev->gfx.rlc.rlc_autoload_bo,
5444                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5445                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5446         if (r) {
5447                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5448                 return r;
5449         }
5450
5451         return 0;
5452 }
5453
5454 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5455 {
5456         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5457                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5458                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5459         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5460                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5461                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5462 }
5463
5464 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5465                                                        FIRMWARE_ID id,
5466                                                        const void *fw_data,
5467                                                        uint32_t fw_size)
5468 {
5469         uint32_t toc_offset;
5470         uint32_t toc_fw_size;
5471         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5472
5473         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5474                 return;
5475
5476         toc_offset = rlc_autoload_info[id].offset;
5477         toc_fw_size = rlc_autoload_info[id].size;
5478
5479         if (fw_size == 0)
5480                 fw_size = toc_fw_size;
5481
5482         if (fw_size > toc_fw_size)
5483                 fw_size = toc_fw_size;
5484
5485         memcpy(ptr + toc_offset, fw_data, fw_size);
5486
5487         if (fw_size < toc_fw_size)
5488                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5489 }
5490
5491 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5492 {
5493         void *data;
5494         uint32_t size;
5495
5496         data = adev->gfx.rlc.rlc_toc_buf;
5497         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5498
5499         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5500                                                    FIRMWARE_ID_RLC_TOC,
5501                                                    data, size);
5502 }
5503
5504 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5505 {
5506         const __le32 *fw_data;
5507         uint32_t fw_size;
5508         const struct gfx_firmware_header_v1_0 *cp_hdr;
5509         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5510
5511         /* pfp ucode */
5512         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5513                 adev->gfx.pfp_fw->data;
5514         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5515                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5516         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5517         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5518                                                    FIRMWARE_ID_CP_PFP,
5519                                                    fw_data, fw_size);
5520
5521         /* ce ucode */
5522         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5523                 adev->gfx.ce_fw->data;
5524         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5525                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5526         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5527         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5528                                                    FIRMWARE_ID_CP_CE,
5529                                                    fw_data, fw_size);
5530
5531         /* me ucode */
5532         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5533                 adev->gfx.me_fw->data;
5534         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5535                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5536         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5537         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5538                                                    FIRMWARE_ID_CP_ME,
5539                                                    fw_data, fw_size);
5540
5541         /* rlc ucode */
5542         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5543                 adev->gfx.rlc_fw->data;
5544         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5545                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5546         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5547         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5548                                                    FIRMWARE_ID_RLC_G_UCODE,
5549                                                    fw_data, fw_size);
5550
5551         /* mec1 ucode */
5552         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5553                 adev->gfx.mec_fw->data;
5554         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5555                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5556         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5557                 cp_hdr->jt_size * 4;
5558         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5559                                                    FIRMWARE_ID_CP_MEC,
5560                                                    fw_data, fw_size);
5561         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5562 }
5563
5564 /* Temporarily put sdma part here */
5565 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5566 {
5567         const __le32 *fw_data;
5568         uint32_t fw_size;
5569         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5570         int i;
5571
5572         for (i = 0; i < adev->sdma.num_instances; i++) {
5573                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5574                         adev->sdma.instance[i].fw->data;
5575                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5576                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5577                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5578
5579                 if (i == 0) {
5580                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5581                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5582                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5583                                 FIRMWARE_ID_SDMA0_JT,
5584                                 (uint32_t *)fw_data +
5585                                 sdma_hdr->jt_offset,
5586                                 sdma_hdr->jt_size * 4);
5587                 } else if (i == 1) {
5588                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5589                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5590                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5591                                 FIRMWARE_ID_SDMA1_JT,
5592                                 (uint32_t *)fw_data +
5593                                 sdma_hdr->jt_offset,
5594                                 sdma_hdr->jt_size * 4);
5595                 }
5596         }
5597 }
5598
5599 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5600 {
5601         uint32_t rlc_g_offset, rlc_g_size, tmp;
5602         uint64_t gpu_addr;
5603
5604         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5605         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5606         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5607
5608         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5609         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5610         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5611
5612         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5613         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5614         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5615
5616         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5617         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5618                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5619                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5620                 return -EINVAL;
5621         }
5622
5623         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5624         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5625                 DRM_ERROR("RLC ROM should halt itself\n");
5626                 return -EINVAL;
5627         }
5628
5629         return 0;
5630 }
5631
5632 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5633 {
5634         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5635         uint32_t tmp;
5636         int i;
5637         uint64_t addr;
5638
5639         /* Trigger an invalidation of the L1 instruction caches */
5640         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5641         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5642         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5643
5644         /* Wait for invalidation complete */
5645         for (i = 0; i < usec_timeout; i++) {
5646                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5647                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5648                         INVALIDATE_CACHE_COMPLETE))
5649                         break;
5650                 udelay(1);
5651         }
5652
5653         if (i >= usec_timeout) {
5654                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5655                 return -EINVAL;
5656         }
5657
5658         /* Program me ucode address into intruction cache address register */
5659         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5660                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5661         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5662                         lower_32_bits(addr) & 0xFFFFF000);
5663         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5664                         upper_32_bits(addr));
5665
5666         return 0;
5667 }
5668
5669 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5670 {
5671         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5672         uint32_t tmp;
5673         int i;
5674         uint64_t addr;
5675
5676         /* Trigger an invalidation of the L1 instruction caches */
5677         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5678         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5679         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5680
5681         /* Wait for invalidation complete */
5682         for (i = 0; i < usec_timeout; i++) {
5683                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5684                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5685                         INVALIDATE_CACHE_COMPLETE))
5686                         break;
5687                 udelay(1);
5688         }
5689
5690         if (i >= usec_timeout) {
5691                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5692                 return -EINVAL;
5693         }
5694
5695         /* Program ce ucode address into intruction cache address register */
5696         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5697                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5698         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5699                         lower_32_bits(addr) & 0xFFFFF000);
5700         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5701                         upper_32_bits(addr));
5702
5703         return 0;
5704 }
5705
5706 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5707 {
5708         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5709         uint32_t tmp;
5710         int i;
5711         uint64_t addr;
5712
5713         /* Trigger an invalidation of the L1 instruction caches */
5714         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5715         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5716         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5717
5718         /* Wait for invalidation complete */
5719         for (i = 0; i < usec_timeout; i++) {
5720                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5721                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5722                         INVALIDATE_CACHE_COMPLETE))
5723                         break;
5724                 udelay(1);
5725         }
5726
5727         if (i >= usec_timeout) {
5728                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5729                 return -EINVAL;
5730         }
5731
5732         /* Program pfp ucode address into intruction cache address register */
5733         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5734                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5735         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5736                         lower_32_bits(addr) & 0xFFFFF000);
5737         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5738                         upper_32_bits(addr));
5739
5740         return 0;
5741 }
5742
5743 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5744 {
5745         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5746         uint32_t tmp;
5747         int i;
5748         uint64_t addr;
5749
5750         /* Trigger an invalidation of the L1 instruction caches */
5751         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5752         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5753         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5754
5755         /* Wait for invalidation complete */
5756         for (i = 0; i < usec_timeout; i++) {
5757                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5758                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5759                         INVALIDATE_CACHE_COMPLETE))
5760                         break;
5761                 udelay(1);
5762         }
5763
5764         if (i >= usec_timeout) {
5765                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5766                 return -EINVAL;
5767         }
5768
5769         /* Program mec1 ucode address into intruction cache address register */
5770         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5771                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5772         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5773                         lower_32_bits(addr) & 0xFFFFF000);
5774         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5775                         upper_32_bits(addr));
5776
5777         return 0;
5778 }
5779
5780 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5781 {
5782         uint32_t cp_status;
5783         uint32_t bootload_status;
5784         int i, r;
5785
5786         for (i = 0; i < adev->usec_timeout; i++) {
5787                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5788                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5789                 if ((cp_status == 0) &&
5790                     (REG_GET_FIELD(bootload_status,
5791                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5792                         break;
5793                 }
5794                 udelay(1);
5795         }
5796
5797         if (i >= adev->usec_timeout) {
5798                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5799                 return -ETIMEDOUT;
5800         }
5801
5802         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5803                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5804                 if (r)
5805                         return r;
5806
5807                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5808                 if (r)
5809                         return r;
5810
5811                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5812                 if (r)
5813                         return r;
5814
5815                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5816                 if (r)
5817                         return r;
5818         }
5819
5820         return 0;
5821 }
5822
5823 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5824 {
5825         int i;
5826         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5827
5828         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5829         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5830         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5831
5832         if (adev->asic_type == CHIP_NAVI12) {
5833                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5834         } else {
5835                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5836         }
5837
5838         for (i = 0; i < adev->usec_timeout; i++) {
5839                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5840                         break;
5841                 udelay(1);
5842         }
5843
5844         if (i >= adev->usec_timeout)
5845                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5846
5847         return 0;
5848 }
5849
5850 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5851 {
5852         int r;
5853         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5854         const __le32 *fw_data;
5855         unsigned i, fw_size;
5856         uint32_t tmp;
5857         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5858
5859         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5860                 adev->gfx.pfp_fw->data;
5861
5862         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5863
5864         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5865                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5866         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5867
5868         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5869                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5870                                       &adev->gfx.pfp.pfp_fw_obj,
5871                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5872                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5873         if (r) {
5874                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5875                 gfx_v10_0_pfp_fini(adev);
5876                 return r;
5877         }
5878
5879         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5880
5881         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5882         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5883
5884         /* Trigger an invalidation of the L1 instruction caches */
5885         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5886         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5887         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5888
5889         /* Wait for invalidation complete */
5890         for (i = 0; i < usec_timeout; i++) {
5891                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5892                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5893                         INVALIDATE_CACHE_COMPLETE))
5894                         break;
5895                 udelay(1);
5896         }
5897
5898         if (i >= usec_timeout) {
5899                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5900                 return -EINVAL;
5901         }
5902
5903         if (amdgpu_emu_mode == 1)
5904                 adev->hdp.funcs->flush_hdp(adev, NULL);
5905
5906         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5907         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5908         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5909         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5910         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5911         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5912         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5913                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5914         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5915                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5916
5917         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5918
5919         for (i = 0; i < pfp_hdr->jt_size; i++)
5920                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5921                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5922
5923         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5924
5925         return 0;
5926 }
5927
5928 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5929 {
5930         int r;
5931         const struct gfx_firmware_header_v1_0 *ce_hdr;
5932         const __le32 *fw_data;
5933         unsigned i, fw_size;
5934         uint32_t tmp;
5935         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5936
5937         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5938                 adev->gfx.ce_fw->data;
5939
5940         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5941
5942         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5943                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5944         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5945
5946         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5947                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5948                                       &adev->gfx.ce.ce_fw_obj,
5949                                       &adev->gfx.ce.ce_fw_gpu_addr,
5950                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5951         if (r) {
5952                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5953                 gfx_v10_0_ce_fini(adev);
5954                 return r;
5955         }
5956
5957         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5958
5959         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5960         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5961
5962         /* Trigger an invalidation of the L1 instruction caches */
5963         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5964         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5965         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5966
5967         /* Wait for invalidation complete */
5968         for (i = 0; i < usec_timeout; i++) {
5969                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5970                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5971                         INVALIDATE_CACHE_COMPLETE))
5972                         break;
5973                 udelay(1);
5974         }
5975
5976         if (i >= usec_timeout) {
5977                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5978                 return -EINVAL;
5979         }
5980
5981         if (amdgpu_emu_mode == 1)
5982                 adev->hdp.funcs->flush_hdp(adev, NULL);
5983
5984         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5985         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5986         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5987         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5988         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5989         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5990                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5991         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5992                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5993
5994         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5995
5996         for (i = 0; i < ce_hdr->jt_size; i++)
5997                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5998                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5999
6000         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6001
6002         return 0;
6003 }
6004
6005 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6006 {
6007         int r;
6008         const struct gfx_firmware_header_v1_0 *me_hdr;
6009         const __le32 *fw_data;
6010         unsigned i, fw_size;
6011         uint32_t tmp;
6012         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6013
6014         me_hdr = (const struct gfx_firmware_header_v1_0 *)
6015                 adev->gfx.me_fw->data;
6016
6017         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6018
6019         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6020                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6021         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6022
6023         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6024                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6025                                       &adev->gfx.me.me_fw_obj,
6026                                       &adev->gfx.me.me_fw_gpu_addr,
6027                                       (void **)&adev->gfx.me.me_fw_ptr);
6028         if (r) {
6029                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6030                 gfx_v10_0_me_fini(adev);
6031                 return r;
6032         }
6033
6034         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6035
6036         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6037         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6038
6039         /* Trigger an invalidation of the L1 instruction caches */
6040         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6041         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6042         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6043
6044         /* Wait for invalidation complete */
6045         for (i = 0; i < usec_timeout; i++) {
6046                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6047                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6048                         INVALIDATE_CACHE_COMPLETE))
6049                         break;
6050                 udelay(1);
6051         }
6052
6053         if (i >= usec_timeout) {
6054                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6055                 return -EINVAL;
6056         }
6057
6058         if (amdgpu_emu_mode == 1)
6059                 adev->hdp.funcs->flush_hdp(adev, NULL);
6060
6061         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6062         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6063         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6064         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6065         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6066         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6067                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6068         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6069                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6070
6071         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6072
6073         for (i = 0; i < me_hdr->jt_size; i++)
6074                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6075                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6076
6077         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6078
6079         return 0;
6080 }
6081
6082 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6083 {
6084         int r;
6085
6086         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6087                 return -EINVAL;
6088
6089         gfx_v10_0_cp_gfx_enable(adev, false);
6090
6091         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6092         if (r) {
6093                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6094                 return r;
6095         }
6096
6097         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6098         if (r) {
6099                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6100                 return r;
6101         }
6102
6103         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6104         if (r) {
6105                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6106                 return r;
6107         }
6108
6109         return 0;
6110 }
6111
6112 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6113 {
6114         struct amdgpu_ring *ring;
6115         const struct cs_section_def *sect = NULL;
6116         const struct cs_extent_def *ext = NULL;
6117         int r, i;
6118         int ctx_reg_offset;
6119
6120         /* init the CP */
6121         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6122                      adev->gfx.config.max_hw_contexts - 1);
6123         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6124
6125         gfx_v10_0_cp_gfx_enable(adev, true);
6126
6127         ring = &adev->gfx.gfx_ring[0];
6128         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6129         if (r) {
6130                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6131                 return r;
6132         }
6133
6134         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6135         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6136
6137         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6138         amdgpu_ring_write(ring, 0x80000000);
6139         amdgpu_ring_write(ring, 0x80000000);
6140
6141         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6142                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6143                         if (sect->id == SECT_CONTEXT) {
6144                                 amdgpu_ring_write(ring,
6145                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6146                                                           ext->reg_count));
6147                                 amdgpu_ring_write(ring, ext->reg_index -
6148                                                   PACKET3_SET_CONTEXT_REG_START);
6149                                 for (i = 0; i < ext->reg_count; i++)
6150                                         amdgpu_ring_write(ring, ext->extent[i]);
6151                         }
6152                 }
6153         }
6154
6155         ctx_reg_offset =
6156                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6157         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6158         amdgpu_ring_write(ring, ctx_reg_offset);
6159         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6160
6161         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6162         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6163
6164         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6165         amdgpu_ring_write(ring, 0);
6166
6167         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6168         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6169         amdgpu_ring_write(ring, 0x8000);
6170         amdgpu_ring_write(ring, 0x8000);
6171
6172         amdgpu_ring_commit(ring);
6173
6174         /* submit cs packet to copy state 0 to next available state */
6175         if (adev->gfx.num_gfx_rings > 1) {
6176                 /* maximum supported gfx ring is 2 */
6177                 ring = &adev->gfx.gfx_ring[1];
6178                 r = amdgpu_ring_alloc(ring, 2);
6179                 if (r) {
6180                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6181                         return r;
6182                 }
6183
6184                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6185                 amdgpu_ring_write(ring, 0);
6186
6187                 amdgpu_ring_commit(ring);
6188         }
6189         return 0;
6190 }
6191
6192 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6193                                          CP_PIPE_ID pipe)
6194 {
6195         u32 tmp;
6196
6197         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6198         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6199
6200         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6201 }
6202
6203 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6204                                           struct amdgpu_ring *ring)
6205 {
6206         u32 tmp;
6207
6208         if (!amdgpu_async_gfx_ring) {
6209                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6210                 if (ring->use_doorbell) {
6211                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6212                                                 DOORBELL_OFFSET, ring->doorbell_index);
6213                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6214                                                 DOORBELL_EN, 1);
6215                 } else {
6216                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6217                                                 DOORBELL_EN, 0);
6218                 }
6219                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6220         }
6221         switch (adev->asic_type) {
6222         case CHIP_SIENNA_CICHLID:
6223         case CHIP_NAVY_FLOUNDER:
6224         case CHIP_VANGOGH:
6225         case CHIP_DIMGREY_CAVEFISH:
6226         case CHIP_BEIGE_GOBY:
6227         case CHIP_YELLOW_CARP:
6228                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6229                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6230                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6231
6232                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6233                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6234                 break;
6235         default:
6236                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6237                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6238                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6239
6240                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6241                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6242                 break;
6243         }
6244 }
6245
6246 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6247 {
6248         struct amdgpu_ring *ring;
6249         u32 tmp;
6250         u32 rb_bufsz;
6251         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6252         u32 i;
6253
6254         /* Set the write pointer delay */
6255         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6256
6257         /* set the RB to use vmid 0 */
6258         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6259
6260         /* Init gfx ring 0 for pipe 0 */
6261         mutex_lock(&adev->srbm_mutex);
6262         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6263
6264         /* Set ring buffer size */
6265         ring = &adev->gfx.gfx_ring[0];
6266         rb_bufsz = order_base_2(ring->ring_size / 8);
6267         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6268         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6269 #ifdef __BIG_ENDIAN
6270         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6271 #endif
6272         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6273
6274         /* Initialize the ring buffer's write pointers */
6275         ring->wptr = 0;
6276         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6277         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6278
6279         /* set the wb address wether it's enabled or not */
6280         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6281         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6282         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6283                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6284
6285         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6286         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6287                      lower_32_bits(wptr_gpu_addr));
6288         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6289                      upper_32_bits(wptr_gpu_addr));
6290
6291         mdelay(1);
6292         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6293
6294         rb_addr = ring->gpu_addr >> 8;
6295         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6296         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6297
6298         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6299
6300         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6301         mutex_unlock(&adev->srbm_mutex);
6302
6303         /* Init gfx ring 1 for pipe 1 */
6304         if (adev->gfx.num_gfx_rings > 1) {
6305                 mutex_lock(&adev->srbm_mutex);
6306                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6307                 /* maximum supported gfx ring is 2 */
6308                 ring = &adev->gfx.gfx_ring[1];
6309                 rb_bufsz = order_base_2(ring->ring_size / 8);
6310                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6311                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6312                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6313                 /* Initialize the ring buffer's write pointers */
6314                 ring->wptr = 0;
6315                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6316                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6317                 /* Set the wb address wether it's enabled or not */
6318                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6319                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6320                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6321                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6322                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6323                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6324                              lower_32_bits(wptr_gpu_addr));
6325                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6326                              upper_32_bits(wptr_gpu_addr));
6327
6328                 mdelay(1);
6329                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6330
6331                 rb_addr = ring->gpu_addr >> 8;
6332                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6333                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6334                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6335
6336                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6337                 mutex_unlock(&adev->srbm_mutex);
6338         }
6339         /* Switch to pipe 0 */
6340         mutex_lock(&adev->srbm_mutex);
6341         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6342         mutex_unlock(&adev->srbm_mutex);
6343
6344         /* start the ring */
6345         gfx_v10_0_cp_gfx_start(adev);
6346
6347         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6348                 ring = &adev->gfx.gfx_ring[i];
6349                 ring->sched.ready = true;
6350         }
6351
6352         return 0;
6353 }
6354
6355 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6356 {
6357         if (enable) {
6358                 switch (adev->asic_type) {
6359                 case CHIP_SIENNA_CICHLID:
6360                 case CHIP_NAVY_FLOUNDER:
6361                 case CHIP_VANGOGH:
6362                 case CHIP_DIMGREY_CAVEFISH:
6363                 case CHIP_BEIGE_GOBY:
6364                 case CHIP_YELLOW_CARP:
6365                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6366                         break;
6367                 default:
6368                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6369                         break;
6370                 }
6371         } else {
6372                 switch (adev->asic_type) {
6373                 case CHIP_SIENNA_CICHLID:
6374                 case CHIP_NAVY_FLOUNDER:
6375                 case CHIP_VANGOGH:
6376                 case CHIP_DIMGREY_CAVEFISH:
6377                 case CHIP_BEIGE_GOBY:
6378                 case CHIP_YELLOW_CARP:
6379                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6380                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6381                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6382                         break;
6383                 default:
6384                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6385                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6386                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6387                         break;
6388                 }
6389                 adev->gfx.kiq.ring.sched.ready = false;
6390         }
6391         udelay(50);
6392 }
6393
6394 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6395 {
6396         const struct gfx_firmware_header_v1_0 *mec_hdr;
6397         const __le32 *fw_data;
6398         unsigned i;
6399         u32 tmp;
6400         u32 usec_timeout = 50000; /* Wait for 50 ms */
6401
6402         if (!adev->gfx.mec_fw)
6403                 return -EINVAL;
6404
6405         gfx_v10_0_cp_compute_enable(adev, false);
6406
6407         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6408         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6409
6410         fw_data = (const __le32 *)
6411                 (adev->gfx.mec_fw->data +
6412                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6413
6414         /* Trigger an invalidation of the L1 instruction caches */
6415         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6416         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6417         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6418
6419         /* Wait for invalidation complete */
6420         for (i = 0; i < usec_timeout; i++) {
6421                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6422                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6423                                        INVALIDATE_CACHE_COMPLETE))
6424                         break;
6425                 udelay(1);
6426         }
6427
6428         if (i >= usec_timeout) {
6429                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6430                 return -EINVAL;
6431         }
6432
6433         if (amdgpu_emu_mode == 1)
6434                 adev->hdp.funcs->flush_hdp(adev, NULL);
6435
6436         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6437         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6438         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6439         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6440         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6441
6442         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6443                      0xFFFFF000);
6444         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6445                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6446
6447         /* MEC1 */
6448         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6449
6450         for (i = 0; i < mec_hdr->jt_size; i++)
6451                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6452                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6453
6454         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6455
6456         /*
6457          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6458          * different microcode than MEC1.
6459          */
6460
6461         return 0;
6462 }
6463
6464 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6465 {
6466         uint32_t tmp;
6467         struct amdgpu_device *adev = ring->adev;
6468
6469         /* tell RLC which is KIQ queue */
6470         switch (adev->asic_type) {
6471         case CHIP_SIENNA_CICHLID:
6472         case CHIP_NAVY_FLOUNDER:
6473         case CHIP_VANGOGH:
6474         case CHIP_DIMGREY_CAVEFISH:
6475         case CHIP_BEIGE_GOBY:
6476         case CHIP_YELLOW_CARP:
6477                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6478                 tmp &= 0xffffff00;
6479                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6480                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6481                 tmp |= 0x80;
6482                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6483                 break;
6484         default:
6485                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6486                 tmp &= 0xffffff00;
6487                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6488                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6489                 tmp |= 0x80;
6490                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6491                 break;
6492         }
6493 }
6494
6495 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6496 {
6497         struct amdgpu_device *adev = ring->adev;
6498         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6499         uint64_t hqd_gpu_addr, wb_gpu_addr;
6500         uint32_t tmp;
6501         uint32_t rb_bufsz;
6502
6503         /* set up gfx hqd wptr */
6504         mqd->cp_gfx_hqd_wptr = 0;
6505         mqd->cp_gfx_hqd_wptr_hi = 0;
6506
6507         /* set the pointer to the MQD */
6508         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6509         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6510
6511         /* set up mqd control */
6512         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6513         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6514         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6515         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6516         mqd->cp_gfx_mqd_control = tmp;
6517
6518         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6519         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6520         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6521         mqd->cp_gfx_hqd_vmid = 0;
6522
6523         /* set up default queue priority level
6524          * 0x0 = low priority, 0x1 = high priority */
6525         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6526         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6527         mqd->cp_gfx_hqd_queue_priority = tmp;
6528
6529         /* set up time quantum */
6530         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6531         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6532         mqd->cp_gfx_hqd_quantum = tmp;
6533
6534         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6535         hqd_gpu_addr = ring->gpu_addr >> 8;
6536         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6537         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6538
6539         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6540         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6541         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6542         mqd->cp_gfx_hqd_rptr_addr_hi =
6543                 upper_32_bits(wb_gpu_addr) & 0xffff;
6544
6545         /* set up rb_wptr_poll addr */
6546         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6547         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6548         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6549
6550         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6551         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6552         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6553         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6554         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6555 #ifdef __BIG_ENDIAN
6556         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6557 #endif
6558         mqd->cp_gfx_hqd_cntl = tmp;
6559
6560         /* set up cp_doorbell_control */
6561         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6562         if (ring->use_doorbell) {
6563                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6564                                     DOORBELL_OFFSET, ring->doorbell_index);
6565                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6566                                     DOORBELL_EN, 1);
6567         } else
6568                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6569                                     DOORBELL_EN, 0);
6570         mqd->cp_rb_doorbell_control = tmp;
6571
6572         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6573          *otherwise the range of the second ring will override the first ring */
6574         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6575                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6576
6577         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6578         ring->wptr = 0;
6579         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6580
6581         /* active the queue */
6582         mqd->cp_gfx_hqd_active = 1;
6583
6584         return 0;
6585 }
6586
6587 #ifdef BRING_UP_DEBUG
6588 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6589 {
6590         struct amdgpu_device *adev = ring->adev;
6591         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6592
6593         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6594         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6595         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6596
6597         /* set GFX_MQD_BASE */
6598         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6599         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6600
6601         /* set GFX_MQD_CONTROL */
6602         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6603
6604         /* set GFX_HQD_VMID to 0 */
6605         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6606
6607         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6608                         mqd->cp_gfx_hqd_queue_priority);
6609         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6610
6611         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6612         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6613         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6614
6615         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6616         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6617         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6618
6619         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6620         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6621
6622         /* set RB_WPTR_POLL_ADDR */
6623         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6624         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6625
6626         /* set RB_DOORBELL_CONTROL */
6627         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6628
6629         /* active the queue */
6630         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6631
6632         return 0;
6633 }
6634 #endif
6635
6636 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6637 {
6638         struct amdgpu_device *adev = ring->adev;
6639         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6640         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6641
6642         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6643                 memset((void *)mqd, 0, sizeof(*mqd));
6644                 mutex_lock(&adev->srbm_mutex);
6645                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6646                 gfx_v10_0_gfx_mqd_init(ring);
6647 #ifdef BRING_UP_DEBUG
6648                 gfx_v10_0_gfx_queue_init_register(ring);
6649 #endif
6650                 nv_grbm_select(adev, 0, 0, 0, 0);
6651                 mutex_unlock(&adev->srbm_mutex);
6652                 if (adev->gfx.me.mqd_backup[mqd_idx])
6653                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6654         } else if (amdgpu_in_reset(adev)) {
6655                 /* reset mqd with the backup copy */
6656                 if (adev->gfx.me.mqd_backup[mqd_idx])
6657                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6658                 /* reset the ring */
6659                 ring->wptr = 0;
6660                 adev->wb.wb[ring->wptr_offs] = 0;
6661                 amdgpu_ring_clear_ring(ring);
6662 #ifdef BRING_UP_DEBUG
6663                 mutex_lock(&adev->srbm_mutex);
6664                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6665                 gfx_v10_0_gfx_queue_init_register(ring);
6666                 nv_grbm_select(adev, 0, 0, 0, 0);
6667                 mutex_unlock(&adev->srbm_mutex);
6668 #endif
6669         } else {
6670                 amdgpu_ring_clear_ring(ring);
6671         }
6672
6673         return 0;
6674 }
6675
6676 #ifndef BRING_UP_DEBUG
6677 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6678 {
6679         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6680         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6681         int r, i;
6682
6683         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6684                 return -EINVAL;
6685
6686         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6687                                         adev->gfx.num_gfx_rings);
6688         if (r) {
6689                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6690                 return r;
6691         }
6692
6693         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6694                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6695
6696         return amdgpu_ring_test_helper(kiq_ring);
6697 }
6698 #endif
6699
6700 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6701 {
6702         int r, i;
6703         struct amdgpu_ring *ring;
6704
6705         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6706                 ring = &adev->gfx.gfx_ring[i];
6707
6708                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6709                 if (unlikely(r != 0))
6710                         goto done;
6711
6712                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6713                 if (!r) {
6714                         r = gfx_v10_0_gfx_init_queue(ring);
6715                         amdgpu_bo_kunmap(ring->mqd_obj);
6716                         ring->mqd_ptr = NULL;
6717                 }
6718                 amdgpu_bo_unreserve(ring->mqd_obj);
6719                 if (r)
6720                         goto done;
6721         }
6722 #ifndef BRING_UP_DEBUG
6723         r = gfx_v10_0_kiq_enable_kgq(adev);
6724         if (r)
6725                 goto done;
6726 #endif
6727         r = gfx_v10_0_cp_gfx_start(adev);
6728         if (r)
6729                 goto done;
6730
6731         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6732                 ring = &adev->gfx.gfx_ring[i];
6733                 ring->sched.ready = true;
6734         }
6735 done:
6736         return r;
6737 }
6738
6739 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6740 {
6741         struct amdgpu_device *adev = ring->adev;
6742
6743         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6744                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6745                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6746                         mqd->cp_hqd_queue_priority =
6747                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6748                 }
6749         }
6750 }
6751
6752 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6753 {
6754         struct amdgpu_device *adev = ring->adev;
6755         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6756         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6757         uint32_t tmp;
6758
6759         mqd->header = 0xC0310800;
6760         mqd->compute_pipelinestat_enable = 0x00000001;
6761         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6762         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6763         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6764         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6765         mqd->compute_misc_reserved = 0x00000003;
6766
6767         eop_base_addr = ring->eop_gpu_addr >> 8;
6768         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6769         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6770
6771         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6772         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6773         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6774                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6775
6776         mqd->cp_hqd_eop_control = tmp;
6777
6778         /* enable doorbell? */
6779         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6780
6781         if (ring->use_doorbell) {
6782                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6783                                     DOORBELL_OFFSET, ring->doorbell_index);
6784                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6785                                     DOORBELL_EN, 1);
6786                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6787                                     DOORBELL_SOURCE, 0);
6788                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6789                                     DOORBELL_HIT, 0);
6790         } else {
6791                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6792                                     DOORBELL_EN, 0);
6793         }
6794
6795         mqd->cp_hqd_pq_doorbell_control = tmp;
6796
6797         /* disable the queue if it's active */
6798         ring->wptr = 0;
6799         mqd->cp_hqd_dequeue_request = 0;
6800         mqd->cp_hqd_pq_rptr = 0;
6801         mqd->cp_hqd_pq_wptr_lo = 0;
6802         mqd->cp_hqd_pq_wptr_hi = 0;
6803
6804         /* set the pointer to the MQD */
6805         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6806         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6807
6808         /* set MQD vmid to 0 */
6809         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6810         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6811         mqd->cp_mqd_control = tmp;
6812
6813         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6814         hqd_gpu_addr = ring->gpu_addr >> 8;
6815         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6816         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6817
6818         /* set up the HQD, this is similar to CP_RB0_CNTL */
6819         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6820         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6821                             (order_base_2(ring->ring_size / 4) - 1));
6822         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6823                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6824 #ifdef __BIG_ENDIAN
6825         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6826 #endif
6827         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6828         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6829         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6830         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6831         mqd->cp_hqd_pq_control = tmp;
6832
6833         /* set the wb address whether it's enabled or not */
6834         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6835         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6836         mqd->cp_hqd_pq_rptr_report_addr_hi =
6837                 upper_32_bits(wb_gpu_addr) & 0xffff;
6838
6839         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6840         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6841         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6842         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6843
6844         tmp = 0;
6845         /* enable the doorbell if requested */
6846         if (ring->use_doorbell) {
6847                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6848                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6849                                 DOORBELL_OFFSET, ring->doorbell_index);
6850
6851                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6852                                     DOORBELL_EN, 1);
6853                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6854                                     DOORBELL_SOURCE, 0);
6855                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6856                                     DOORBELL_HIT, 0);
6857         }
6858
6859         mqd->cp_hqd_pq_doorbell_control = tmp;
6860
6861         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6862         ring->wptr = 0;
6863         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6864
6865         /* set the vmid for the queue */
6866         mqd->cp_hqd_vmid = 0;
6867
6868         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6869         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6870         mqd->cp_hqd_persistent_state = tmp;
6871
6872         /* set MIN_IB_AVAIL_SIZE */
6873         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6874         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6875         mqd->cp_hqd_ib_control = tmp;
6876
6877         /* set static priority for a compute queue/ring */
6878         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6879
6880         /* map_queues packet doesn't need activate the queue,
6881          * so only kiq need set this field.
6882          */
6883         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6884                 mqd->cp_hqd_active = 1;
6885
6886         return 0;
6887 }
6888
6889 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6890 {
6891         struct amdgpu_device *adev = ring->adev;
6892         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6893         int j;
6894
6895         /* inactivate the queue */
6896         if (amdgpu_sriov_vf(adev))
6897                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6898
6899         /* disable wptr polling */
6900         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6901
6902         /* write the EOP addr */
6903         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6904                mqd->cp_hqd_eop_base_addr_lo);
6905         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6906                mqd->cp_hqd_eop_base_addr_hi);
6907
6908         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6909         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6910                mqd->cp_hqd_eop_control);
6911
6912         /* enable doorbell? */
6913         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6914                mqd->cp_hqd_pq_doorbell_control);
6915
6916         /* disable the queue if it's active */
6917         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6918                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6919                 for (j = 0; j < adev->usec_timeout; j++) {
6920                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6921                                 break;
6922                         udelay(1);
6923                 }
6924                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6925                        mqd->cp_hqd_dequeue_request);
6926                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6927                        mqd->cp_hqd_pq_rptr);
6928                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6929                        mqd->cp_hqd_pq_wptr_lo);
6930                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6931                        mqd->cp_hqd_pq_wptr_hi);
6932         }
6933
6934         /* set the pointer to the MQD */
6935         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6936                mqd->cp_mqd_base_addr_lo);
6937         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6938                mqd->cp_mqd_base_addr_hi);
6939
6940         /* set MQD vmid to 0 */
6941         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6942                mqd->cp_mqd_control);
6943
6944         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6945         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6946                mqd->cp_hqd_pq_base_lo);
6947         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6948                mqd->cp_hqd_pq_base_hi);
6949
6950         /* set up the HQD, this is similar to CP_RB0_CNTL */
6951         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6952                mqd->cp_hqd_pq_control);
6953
6954         /* set the wb address whether it's enabled or not */
6955         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6956                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6957         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6958                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6959
6960         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6961         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6962                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6963         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6964                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6965
6966         /* enable the doorbell if requested */
6967         if (ring->use_doorbell) {
6968                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6969                         (adev->doorbell_index.kiq * 2) << 2);
6970                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6971                         (adev->doorbell_index.userqueue_end * 2) << 2);
6972         }
6973
6974         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6975                mqd->cp_hqd_pq_doorbell_control);
6976
6977         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6978         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6979                mqd->cp_hqd_pq_wptr_lo);
6980         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6981                mqd->cp_hqd_pq_wptr_hi);
6982
6983         /* set the vmid for the queue */
6984         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6985
6986         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6987                mqd->cp_hqd_persistent_state);
6988
6989         /* activate the queue */
6990         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6991                mqd->cp_hqd_active);
6992
6993         if (ring->use_doorbell)
6994                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6995
6996         return 0;
6997 }
6998
6999 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7000 {
7001         struct amdgpu_device *adev = ring->adev;
7002         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7003         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7004
7005         gfx_v10_0_kiq_setting(ring);
7006
7007         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7008                 /* reset MQD to a clean status */
7009                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7010                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7011
7012                 /* reset ring buffer */
7013                 ring->wptr = 0;
7014                 amdgpu_ring_clear_ring(ring);
7015
7016                 mutex_lock(&adev->srbm_mutex);
7017                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7018                 gfx_v10_0_kiq_init_register(ring);
7019                 nv_grbm_select(adev, 0, 0, 0, 0);
7020                 mutex_unlock(&adev->srbm_mutex);
7021         } else {
7022                 memset((void *)mqd, 0, sizeof(*mqd));
7023                 mutex_lock(&adev->srbm_mutex);
7024                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7025                 gfx_v10_0_compute_mqd_init(ring);
7026                 gfx_v10_0_kiq_init_register(ring);
7027                 nv_grbm_select(adev, 0, 0, 0, 0);
7028                 mutex_unlock(&adev->srbm_mutex);
7029
7030                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7031                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7032         }
7033
7034         return 0;
7035 }
7036
7037 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7038 {
7039         struct amdgpu_device *adev = ring->adev;
7040         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7041         int mqd_idx = ring - &adev->gfx.compute_ring[0];
7042
7043         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7044                 memset((void *)mqd, 0, sizeof(*mqd));
7045                 mutex_lock(&adev->srbm_mutex);
7046                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7047                 gfx_v10_0_compute_mqd_init(ring);
7048                 nv_grbm_select(adev, 0, 0, 0, 0);
7049                 mutex_unlock(&adev->srbm_mutex);
7050
7051                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7052                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7053         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7054                 /* reset MQD to a clean status */
7055                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7056                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7057
7058                 /* reset ring buffer */
7059                 ring->wptr = 0;
7060                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
7061                 amdgpu_ring_clear_ring(ring);
7062         } else {
7063                 amdgpu_ring_clear_ring(ring);
7064         }
7065
7066         return 0;
7067 }
7068
7069 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7070 {
7071         struct amdgpu_ring *ring;
7072         int r;
7073
7074         ring = &adev->gfx.kiq.ring;
7075
7076         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7077         if (unlikely(r != 0))
7078                 return r;
7079
7080         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7081         if (unlikely(r != 0))
7082                 return r;
7083
7084         gfx_v10_0_kiq_init_queue(ring);
7085         amdgpu_bo_kunmap(ring->mqd_obj);
7086         ring->mqd_ptr = NULL;
7087         amdgpu_bo_unreserve(ring->mqd_obj);
7088         ring->sched.ready = true;
7089         return 0;
7090 }
7091
7092 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7093 {
7094         struct amdgpu_ring *ring = NULL;
7095         int r = 0, i;
7096
7097         gfx_v10_0_cp_compute_enable(adev, true);
7098
7099         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7100                 ring = &adev->gfx.compute_ring[i];
7101
7102                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7103                 if (unlikely(r != 0))
7104                         goto done;
7105                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7106                 if (!r) {
7107                         r = gfx_v10_0_kcq_init_queue(ring);
7108                         amdgpu_bo_kunmap(ring->mqd_obj);
7109                         ring->mqd_ptr = NULL;
7110                 }
7111                 amdgpu_bo_unreserve(ring->mqd_obj);
7112                 if (r)
7113                         goto done;
7114         }
7115
7116         r = amdgpu_gfx_enable_kcq(adev);
7117 done:
7118         return r;
7119 }
7120
7121 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7122 {
7123         int r, i;
7124         struct amdgpu_ring *ring;
7125
7126         if (!(adev->flags & AMD_IS_APU))
7127                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7128
7129         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7130                 /* legacy firmware loading */
7131                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7132                 if (r)
7133                         return r;
7134
7135                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7136                 if (r)
7137                         return r;
7138         }
7139
7140         r = gfx_v10_0_kiq_resume(adev);
7141         if (r)
7142                 return r;
7143
7144         r = gfx_v10_0_kcq_resume(adev);
7145         if (r)
7146                 return r;
7147
7148         if (!amdgpu_async_gfx_ring) {
7149                 r = gfx_v10_0_cp_gfx_resume(adev);
7150                 if (r)
7151                         return r;
7152         } else {
7153                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7154                 if (r)
7155                         return r;
7156         }
7157
7158         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7159                 ring = &adev->gfx.gfx_ring[i];
7160                 r = amdgpu_ring_test_helper(ring);
7161                 if (r)
7162                         return r;
7163         }
7164
7165         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7166                 ring = &adev->gfx.compute_ring[i];
7167                 r = amdgpu_ring_test_helper(ring);
7168                 if (r)
7169                         return r;
7170         }
7171
7172         return 0;
7173 }
7174
7175 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7176 {
7177         gfx_v10_0_cp_gfx_enable(adev, enable);
7178         gfx_v10_0_cp_compute_enable(adev, enable);
7179 }
7180
7181 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7182 {
7183         uint32_t data, pattern = 0xDEADBEEF;
7184
7185         /* check if mmVGT_ESGS_RING_SIZE_UMD
7186          * has been remapped to mmVGT_ESGS_RING_SIZE */
7187         switch (adev->asic_type) {
7188         case CHIP_SIENNA_CICHLID:
7189         case CHIP_NAVY_FLOUNDER:
7190         case CHIP_DIMGREY_CAVEFISH:
7191         case CHIP_BEIGE_GOBY:
7192                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7193                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7194                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7195
7196                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7197                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7198                         return true;
7199                 } else {
7200                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7201                         return false;
7202                 }
7203                 break;
7204         case CHIP_VANGOGH:
7205         case CHIP_YELLOW_CARP:
7206                 return true;
7207         default:
7208                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7209                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7210                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7211
7212                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7213                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7214                         return true;
7215                 } else {
7216                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7217                         return false;
7218                 }
7219                 break;
7220         }
7221 }
7222
7223 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7224 {
7225         uint32_t data;
7226
7227         if (amdgpu_sriov_vf(adev))
7228                 return;
7229
7230         /* initialize cam_index to 0
7231          * index will auto-inc after each data writting */
7232         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7233
7234         switch (adev->asic_type) {
7235         case CHIP_SIENNA_CICHLID:
7236         case CHIP_NAVY_FLOUNDER:
7237         case CHIP_VANGOGH:
7238         case CHIP_DIMGREY_CAVEFISH:
7239         case CHIP_BEIGE_GOBY:
7240         case CHIP_YELLOW_CARP:
7241                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7242                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7243                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7244                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7245                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7246                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7247                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7248
7249                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7250                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7251                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7252                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7253                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7254                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7255                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7256
7257                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7258                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7259                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7260                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7261                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7262                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7263                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7264
7265                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7266                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7267                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7268                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7269                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7270                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7271                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7272
7273                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7274                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7275                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7276                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7277                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7278                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7279                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7280
7281                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7282                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7283                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7284                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7285                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7286                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7287                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7288
7289                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7290                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7291                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7292                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7293                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7294                 break;
7295         default:
7296                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7297                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7298                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7299                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7300                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7301                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7302                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7303
7304                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7305                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7306                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7307                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7308                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7309                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7310                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7311
7312                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7313                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7314                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7315                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7316                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7317                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7318                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7319
7320                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7321                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7322                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7323                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7324                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7325                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7326                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7327
7328                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7329                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7330                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7331                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7332                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7333                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7334                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7335
7336                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7337                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7338                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7339                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7340                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7341                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7342                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7343
7344                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7345                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7346                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7347                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7348                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7349                 break;
7350         }
7351
7352         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7353         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7354 }
7355
7356 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7357 {
7358         uint32_t data;
7359         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7360         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7361         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7362
7363         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7364         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7365         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7366 }
7367
7368 static int gfx_v10_0_hw_init(void *handle)
7369 {
7370         int r;
7371         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7372
7373         if (!amdgpu_emu_mode)
7374                 gfx_v10_0_init_golden_registers(adev);
7375
7376         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7377                 /**
7378                  * For gfx 10, rlc firmware loading relies on smu firmware is
7379                  * loaded firstly, so in direct type, it has to load smc ucode
7380                  * here before rlc.
7381                  */
7382                 if (!(adev->flags & AMD_IS_APU)) {
7383                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7384                         if (r)
7385                                 return r;
7386                 }
7387                 gfx_v10_0_disable_gpa_mode(adev);
7388         }
7389
7390         /* if GRBM CAM not remapped, set up the remapping */
7391         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7392                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7393
7394         gfx_v10_0_constants_init(adev);
7395
7396         r = gfx_v10_0_rlc_resume(adev);
7397         if (r)
7398                 return r;
7399
7400         /*
7401          * init golden registers and rlc resume may override some registers,
7402          * reconfig them here
7403          */
7404         if (adev->asic_type == CHIP_NAVI10 ||
7405             adev->asic_type == CHIP_NAVI14 ||
7406             adev->asic_type == CHIP_NAVI12)
7407                 gfx_v10_0_tcp_harvest(adev);
7408
7409         r = gfx_v10_0_cp_resume(adev);
7410         if (r)
7411                 return r;
7412
7413         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7414                 gfx_v10_3_program_pbb_mode(adev);
7415
7416         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7417                 gfx_v10_3_set_power_brake_sequence(adev);
7418
7419         return r;
7420 }
7421
7422 #ifndef BRING_UP_DEBUG
7423 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7424 {
7425         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7426         struct amdgpu_ring *kiq_ring = &kiq->ring;
7427         int i;
7428
7429         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7430                 return -EINVAL;
7431
7432         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7433                                         adev->gfx.num_gfx_rings))
7434                 return -ENOMEM;
7435
7436         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7437                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7438                                            PREEMPT_QUEUES, 0, 0);
7439
7440         return amdgpu_ring_test_helper(kiq_ring);
7441 }
7442 #endif
7443
7444 static int gfx_v10_0_hw_fini(void *handle)
7445 {
7446         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7447         int r;
7448         uint32_t tmp;
7449
7450         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7451         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7452
7453         if (!adev->no_hw_access) {
7454 #ifndef BRING_UP_DEBUG
7455                 if (amdgpu_async_gfx_ring) {
7456                         r = gfx_v10_0_kiq_disable_kgq(adev);
7457                         if (r)
7458                                 DRM_ERROR("KGQ disable failed\n");
7459                 }
7460 #endif
7461                 if (amdgpu_gfx_disable_kcq(adev))
7462                         DRM_ERROR("KCQ disable failed\n");
7463         }
7464
7465         if (amdgpu_sriov_vf(adev)) {
7466                 gfx_v10_0_cp_gfx_enable(adev, false);
7467                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7468                 if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
7469                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7470                         tmp &= 0xffffff00;
7471                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7472                 } else {
7473                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7474                         tmp &= 0xffffff00;
7475                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7476                 }
7477
7478                 return 0;
7479         }
7480         gfx_v10_0_cp_enable(adev, false);
7481         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7482
7483         return 0;
7484 }
7485
7486 static int gfx_v10_0_suspend(void *handle)
7487 {
7488         return gfx_v10_0_hw_fini(handle);
7489 }
7490
7491 static int gfx_v10_0_resume(void *handle)
7492 {
7493         return gfx_v10_0_hw_init(handle);
7494 }
7495
7496 static bool gfx_v10_0_is_idle(void *handle)
7497 {
7498         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7499
7500         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7501                                 GRBM_STATUS, GUI_ACTIVE))
7502                 return false;
7503         else
7504                 return true;
7505 }
7506
7507 static int gfx_v10_0_wait_for_idle(void *handle)
7508 {
7509         unsigned i;
7510         u32 tmp;
7511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7512
7513         for (i = 0; i < adev->usec_timeout; i++) {
7514                 /* read MC_STATUS */
7515                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7516                         GRBM_STATUS__GUI_ACTIVE_MASK;
7517
7518                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7519                         return 0;
7520                 udelay(1);
7521         }
7522         return -ETIMEDOUT;
7523 }
7524
7525 static int gfx_v10_0_soft_reset(void *handle)
7526 {
7527         u32 grbm_soft_reset = 0;
7528         u32 tmp;
7529         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7530
7531         /* GRBM_STATUS */
7532         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7533         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7534                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7535                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7536                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7537                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7538                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7539                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7540                                                 1);
7541                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7542                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7543                                                 1);
7544         }
7545
7546         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7547                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7548                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7549                                                 1);
7550         }
7551
7552         /* GRBM_STATUS2 */
7553         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7554         switch (adev->asic_type) {
7555         case CHIP_SIENNA_CICHLID:
7556         case CHIP_NAVY_FLOUNDER:
7557         case CHIP_VANGOGH:
7558         case CHIP_DIMGREY_CAVEFISH:
7559         case CHIP_BEIGE_GOBY:
7560         case CHIP_YELLOW_CARP:
7561                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7562                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7563                                                         GRBM_SOFT_RESET,
7564                                                         SOFT_RESET_RLC,
7565                                                         1);
7566                 break;
7567         default:
7568                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7569                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7570                                                         GRBM_SOFT_RESET,
7571                                                         SOFT_RESET_RLC,
7572                                                         1);
7573                 break;
7574         }
7575
7576         if (grbm_soft_reset) {
7577                 /* stop the rlc */
7578                 gfx_v10_0_rlc_stop(adev);
7579
7580                 /* Disable GFX parsing/prefetching */
7581                 gfx_v10_0_cp_gfx_enable(adev, false);
7582
7583                 /* Disable MEC parsing/prefetching */
7584                 gfx_v10_0_cp_compute_enable(adev, false);
7585
7586                 if (grbm_soft_reset) {
7587                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7588                         tmp |= grbm_soft_reset;
7589                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7590                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7591                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7592
7593                         udelay(50);
7594
7595                         tmp &= ~grbm_soft_reset;
7596                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7597                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7598                 }
7599
7600                 /* Wait a little for things to settle down */
7601                 udelay(50);
7602         }
7603         return 0;
7604 }
7605
7606 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7607 {
7608         uint64_t clock;
7609
7610         amdgpu_gfx_off_ctrl(adev, false);
7611         mutex_lock(&adev->gfx.gpu_clock_mutex);
7612         switch (adev->asic_type) {
7613         case CHIP_VANGOGH:
7614         case CHIP_YELLOW_CARP:
7615                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7616                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7617                 break;
7618         default:
7619                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7620                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7621                 break;
7622         }
7623         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7624         amdgpu_gfx_off_ctrl(adev, true);
7625         return clock;
7626 }
7627
7628 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7629                                            uint32_t vmid,
7630                                            uint32_t gds_base, uint32_t gds_size,
7631                                            uint32_t gws_base, uint32_t gws_size,
7632                                            uint32_t oa_base, uint32_t oa_size)
7633 {
7634         struct amdgpu_device *adev = ring->adev;
7635
7636         /* GDS Base */
7637         gfx_v10_0_write_data_to_reg(ring, 0, false,
7638                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7639                                     gds_base);
7640
7641         /* GDS Size */
7642         gfx_v10_0_write_data_to_reg(ring, 0, false,
7643                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7644                                     gds_size);
7645
7646         /* GWS */
7647         gfx_v10_0_write_data_to_reg(ring, 0, false,
7648                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7649                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7650
7651         /* OA */
7652         gfx_v10_0_write_data_to_reg(ring, 0, false,
7653                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7654                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7655 }
7656
7657 static int gfx_v10_0_early_init(void *handle)
7658 {
7659         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7660
7661         switch (adev->asic_type) {
7662         case CHIP_NAVI10:
7663         case CHIP_NAVI14:
7664         case CHIP_NAVI12:
7665                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7666                 break;
7667         case CHIP_SIENNA_CICHLID:
7668         case CHIP_NAVY_FLOUNDER:
7669         case CHIP_VANGOGH:
7670         case CHIP_DIMGREY_CAVEFISH:
7671         case CHIP_BEIGE_GOBY:
7672         case CHIP_YELLOW_CARP:
7673                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7674                 break;
7675         default:
7676                 break;
7677         }
7678
7679         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7680                                           AMDGPU_MAX_COMPUTE_RINGS);
7681
7682         gfx_v10_0_set_kiq_pm4_funcs(adev);
7683         gfx_v10_0_set_ring_funcs(adev);
7684         gfx_v10_0_set_irq_funcs(adev);
7685         gfx_v10_0_set_gds_init(adev);
7686         gfx_v10_0_set_rlc_funcs(adev);
7687
7688         return 0;
7689 }
7690
7691 static int gfx_v10_0_late_init(void *handle)
7692 {
7693         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7694         int r;
7695
7696         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7697         if (r)
7698                 return r;
7699
7700         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7701         if (r)
7702                 return r;
7703
7704         return 0;
7705 }
7706
7707 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7708 {
7709         uint32_t rlc_cntl;
7710
7711         /* if RLC is not enabled, do nothing */
7712         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7713         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7714 }
7715
7716 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7717 {
7718         uint32_t data;
7719         unsigned i;
7720
7721         data = RLC_SAFE_MODE__CMD_MASK;
7722         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7723
7724         switch (adev->asic_type) {
7725         case CHIP_SIENNA_CICHLID:
7726         case CHIP_NAVY_FLOUNDER:
7727         case CHIP_VANGOGH:
7728         case CHIP_DIMGREY_CAVEFISH:
7729         case CHIP_BEIGE_GOBY:
7730         case CHIP_YELLOW_CARP:
7731                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7732
7733                 /* wait for RLC_SAFE_MODE */
7734                 for (i = 0; i < adev->usec_timeout; i++) {
7735                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7736                                            RLC_SAFE_MODE, CMD))
7737                                 break;
7738                         udelay(1);
7739                 }
7740                 break;
7741         default:
7742                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7743
7744                 /* wait for RLC_SAFE_MODE */
7745                 for (i = 0; i < adev->usec_timeout; i++) {
7746                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7747                                            RLC_SAFE_MODE, CMD))
7748                                 break;
7749                         udelay(1);
7750                 }
7751                 break;
7752         }
7753 }
7754
7755 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7756 {
7757         uint32_t data;
7758
7759         data = RLC_SAFE_MODE__CMD_MASK;
7760         switch (adev->asic_type) {
7761         case CHIP_SIENNA_CICHLID:
7762         case CHIP_NAVY_FLOUNDER:
7763         case CHIP_VANGOGH:
7764         case CHIP_DIMGREY_CAVEFISH:
7765         case CHIP_BEIGE_GOBY:
7766         case CHIP_YELLOW_CARP:
7767                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7768                 break;
7769         default:
7770                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7771                 break;
7772         }
7773 }
7774
7775 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7776                                                       bool enable)
7777 {
7778         uint32_t data, def;
7779
7780         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7781                 return;
7782
7783         /* It is disabled by HW by default */
7784         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7785                 /* 0 - Disable some blocks' MGCG */
7786                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7787                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7788                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7789                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7790
7791                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7792                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7793                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7794                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7795                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7796                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7797                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7798                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7799
7800                 if (def != data)
7801                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7802
7803                 /* MGLS is a global flag to control all MGLS in GFX */
7804                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7805                         /* 2 - RLC memory Light sleep */
7806                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7807                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7808                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7809                                 if (def != data)
7810                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7811                         }
7812                         /* 3 - CP memory Light sleep */
7813                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7814                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7815                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7816                                 if (def != data)
7817                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7818                         }
7819                 }
7820         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7821                 /* 1 - MGCG_OVERRIDE */
7822                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7823                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7824                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7825                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7826                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7827                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7828                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7829                 if (def != data)
7830                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7831
7832                 /* 2 - disable MGLS in CP */
7833                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7834                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7835                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7836                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7837                 }
7838
7839                 /* 3 - disable MGLS in RLC */
7840                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7841                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7842                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7843                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7844                 }
7845
7846         }
7847 }
7848
7849 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7850                                            bool enable)
7851 {
7852         uint32_t data, def;
7853
7854         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7855                 return;
7856
7857         /* Enable 3D CGCG/CGLS */
7858         if (enable) {
7859                 /* write cmd to clear cgcg/cgls ov */
7860                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7861
7862                 /* unset CGCG override */
7863                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7864                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7865
7866                 /* update CGCG and CGLS override bits */
7867                 if (def != data)
7868                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7869
7870                 /* enable 3Dcgcg FSM(0x0000363f) */
7871                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7872                 data = 0;
7873
7874                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7875                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7876                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7877
7878                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7879                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7880                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7881
7882                 if (def != data)
7883                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7884
7885                 /* set IDLE_POLL_COUNT(0x00900100) */
7886                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7887                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7888                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7889                 if (def != data)
7890                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7891         } else {
7892                 /* Disable CGCG/CGLS */
7893                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7894
7895                 /* disable cgcg, cgls should be disabled */
7896                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7897                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7898
7899                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7900                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7901
7902                 /* disable cgcg and cgls in FSM */
7903                 if (def != data)
7904                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7905         }
7906 }
7907
7908 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7909                                                       bool enable)
7910 {
7911         uint32_t def, data;
7912
7913         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7914                 return;
7915
7916         if (enable) {
7917                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7918
7919                 /* unset CGCG override */
7920                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7921                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7922
7923                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7924                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7925
7926                 /* update CGCG and CGLS override bits */
7927                 if (def != data)
7928                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7929
7930                 /* enable cgcg FSM(0x0000363F) */
7931                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7932                 data = 0;
7933
7934                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7935                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7936                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7937
7938                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7939                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7940                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7941
7942                 if (def != data)
7943                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7944
7945                 /* set IDLE_POLL_COUNT(0x00900100) */
7946                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7947                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7948                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7949                 if (def != data)
7950                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7951         } else {
7952                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7953
7954                 /* reset CGCG/CGLS bits */
7955                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7956                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7957
7958                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7959                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7960
7961                 /* disable cgcg and cgls in FSM */
7962                 if (def != data)
7963                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7964         }
7965 }
7966
7967 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7968                                                       bool enable)
7969 {
7970         uint32_t def, data;
7971
7972         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7973                 return;
7974
7975         if (enable) {
7976                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7977                 /* unset FGCG override */
7978                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7979                 /* update FGCG override bits */
7980                 if (def != data)
7981                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7982
7983                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7984                 /* unset RLC SRAM CLK GATER override */
7985                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7986                 /* update RLC SRAM CLK GATER override bits */
7987                 if (def != data)
7988                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7989         } else {
7990                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7991                 /* reset FGCG bits */
7992                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7993                 /* disable FGCG*/
7994                 if (def != data)
7995                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7996
7997                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7998                 /* reset RLC SRAM CLK GATER bits */
7999                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8000                 /* disable RLC SRAM CLK*/
8001                 if (def != data)
8002                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8003         }
8004 }
8005
8006 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8007 {
8008         uint32_t reg_data = 0;
8009         uint32_t reg_idx = 0;
8010         uint32_t i;
8011
8012         const uint32_t tcp_ctrl_regs[] = {
8013                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8014                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8015                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8016                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8017                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8018                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8019                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8020                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8021                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8022                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8023                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8024                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8025                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8026                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8027                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8028                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8029                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8030                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8031                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8032                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8033                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8034                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8035                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8036                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8037         };
8038
8039         const uint32_t tcp_ctrl_regs_nv12[] = {
8040                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8041                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8042                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8043                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8044                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8045                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8046                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8047                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8048                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8049                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8050                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8051                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8052                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8053                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8054                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8055                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8056                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8057                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8058                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8059                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8060         };
8061
8062         const uint32_t sm_ctlr_regs[] = {
8063                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8064                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8065                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8066                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8067         };
8068
8069         if (adev->asic_type == CHIP_NAVI12) {
8070                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8071                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8072                                   tcp_ctrl_regs_nv12[i];
8073                         reg_data = RREG32(reg_idx);
8074                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8075                         WREG32(reg_idx, reg_data);
8076                 }
8077         } else {
8078                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8079                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8080                                   tcp_ctrl_regs[i];
8081                         reg_data = RREG32(reg_idx);
8082                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8083                         WREG32(reg_idx, reg_data);
8084                 }
8085         }
8086
8087         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8088                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8089                           sm_ctlr_regs[i];
8090                 reg_data = RREG32(reg_idx);
8091                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8092                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8093                 WREG32(reg_idx, reg_data);
8094         }
8095 }
8096
8097 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8098                                             bool enable)
8099 {
8100         amdgpu_gfx_rlc_enter_safe_mode(adev);
8101
8102         if (enable) {
8103                 /* enable FGCG firstly*/
8104                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8105                 /* CGCG/CGLS should be enabled after MGCG/MGLS
8106                  * ===  MGCG + MGLS ===
8107                  */
8108                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8109                 /* ===  CGCG /CGLS for GFX 3D Only === */
8110                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8111                 /* ===  CGCG + CGLS === */
8112                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8113
8114                 if ((adev->asic_type >= CHIP_NAVI10) &&
8115                      (adev->asic_type <= CHIP_NAVI12))
8116                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8117         } else {
8118                 /* CGCG/CGLS should be disabled before MGCG/MGLS
8119                  * ===  CGCG + CGLS ===
8120                  */
8121                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8122                 /* ===  CGCG /CGLS for GFX 3D Only === */
8123                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8124                 /* ===  MGCG + MGLS === */
8125                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8126                 /* disable fgcg at last*/
8127                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8128         }
8129
8130         if (adev->cg_flags &
8131             (AMD_CG_SUPPORT_GFX_MGCG |
8132              AMD_CG_SUPPORT_GFX_CGLS |
8133              AMD_CG_SUPPORT_GFX_CGCG |
8134              AMD_CG_SUPPORT_GFX_3D_CGCG |
8135              AMD_CG_SUPPORT_GFX_3D_CGLS))
8136                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8137
8138         amdgpu_gfx_rlc_exit_safe_mode(adev);
8139
8140         return 0;
8141 }
8142
8143 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8144 {
8145         u32 reg, data;
8146         /* not for *_SOC15 */
8147         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8148         if (amdgpu_sriov_is_pp_one_vf(adev))
8149                 data = RREG32_NO_KIQ(reg);
8150         else
8151                 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8152
8153         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8154         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8155
8156         if (amdgpu_sriov_is_pp_one_vf(adev))
8157                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8158         else
8159                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8160 }
8161
8162 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8163                                         uint32_t offset,
8164                                         struct soc15_reg_rlcg *entries, int arr_size)
8165 {
8166         int i;
8167         uint32_t reg;
8168
8169         if (!entries)
8170                 return false;
8171
8172         for (i = 0; i < arr_size; i++) {
8173                 const struct soc15_reg_rlcg *entry;
8174
8175                 entry = &entries[i];
8176                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8177                 if (offset == reg)
8178                         return true;
8179         }
8180
8181         return false;
8182 }
8183
8184 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8185 {
8186         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8187 }
8188
8189 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8190 {
8191         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8192
8193         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8194                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8195         else
8196                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8197
8198         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8199
8200         /*
8201          * CGPG enablement required and the register to program the hysteresis value
8202          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8203          * in refclk count. Note that RLC FW is modified to take 16 bits from
8204          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8205          *
8206          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8207          * of CGPG enablement starting point.
8208          * Power/performance team will optimize it and might give a new value later.
8209          */
8210         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8211                 switch (adev->asic_type) {
8212                 case CHIP_VANGOGH:
8213                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8214                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8215                         break;
8216                 case CHIP_YELLOW_CARP:
8217                         data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8218                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8219                         break;
8220                 default:
8221                         break;
8222                 }
8223         }
8224 }
8225
8226 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8227 {
8228         amdgpu_gfx_rlc_enter_safe_mode(adev);
8229
8230         gfx_v10_cntl_power_gating(adev, enable);
8231
8232         amdgpu_gfx_rlc_exit_safe_mode(adev);
8233 }
8234
8235 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8236         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8237         .set_safe_mode = gfx_v10_0_set_safe_mode,
8238         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8239         .init = gfx_v10_0_rlc_init,
8240         .get_csb_size = gfx_v10_0_get_csb_size,
8241         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8242         .resume = gfx_v10_0_rlc_resume,
8243         .stop = gfx_v10_0_rlc_stop,
8244         .reset = gfx_v10_0_rlc_reset,
8245         .start = gfx_v10_0_rlc_start,
8246         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8247 };
8248
8249 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8250         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8251         .set_safe_mode = gfx_v10_0_set_safe_mode,
8252         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8253         .init = gfx_v10_0_rlc_init,
8254         .get_csb_size = gfx_v10_0_get_csb_size,
8255         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8256         .resume = gfx_v10_0_rlc_resume,
8257         .stop = gfx_v10_0_rlc_stop,
8258         .reset = gfx_v10_0_rlc_reset,
8259         .start = gfx_v10_0_rlc_start,
8260         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8261         .rlcg_wreg = gfx_v10_rlcg_wreg,
8262         .rlcg_rreg = gfx_v10_rlcg_rreg,
8263         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8264 };
8265
8266 static int gfx_v10_0_set_powergating_state(void *handle,
8267                                           enum amd_powergating_state state)
8268 {
8269         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8270         bool enable = (state == AMD_PG_STATE_GATE);
8271
8272         if (amdgpu_sriov_vf(adev))
8273                 return 0;
8274
8275         switch (adev->asic_type) {
8276         case CHIP_NAVI10:
8277         case CHIP_NAVI14:
8278         case CHIP_NAVI12:
8279         case CHIP_SIENNA_CICHLID:
8280         case CHIP_NAVY_FLOUNDER:
8281         case CHIP_DIMGREY_CAVEFISH:
8282         case CHIP_BEIGE_GOBY:
8283                 amdgpu_gfx_off_ctrl(adev, enable);
8284                 break;
8285         case CHIP_VANGOGH:
8286         case CHIP_YELLOW_CARP:
8287                 gfx_v10_cntl_pg(adev, enable);
8288                 amdgpu_gfx_off_ctrl(adev, enable);
8289                 break;
8290         default:
8291                 break;
8292         }
8293         return 0;
8294 }
8295
8296 static int gfx_v10_0_set_clockgating_state(void *handle,
8297                                           enum amd_clockgating_state state)
8298 {
8299         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8300
8301         if (amdgpu_sriov_vf(adev))
8302                 return 0;
8303
8304         switch (adev->asic_type) {
8305         case CHIP_NAVI10:
8306         case CHIP_NAVI14:
8307         case CHIP_NAVI12:
8308         case CHIP_SIENNA_CICHLID:
8309         case CHIP_NAVY_FLOUNDER:
8310         case CHIP_VANGOGH:
8311         case CHIP_DIMGREY_CAVEFISH:
8312         case CHIP_BEIGE_GOBY:
8313         case CHIP_YELLOW_CARP:
8314                 gfx_v10_0_update_gfx_clock_gating(adev,
8315                                                  state == AMD_CG_STATE_GATE);
8316                 break;
8317         default:
8318                 break;
8319         }
8320         return 0;
8321 }
8322
8323 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8324 {
8325         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8326         int data;
8327
8328         /* AMD_CG_SUPPORT_GFX_FGCG */
8329         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8330         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8331                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8332
8333         /* AMD_CG_SUPPORT_GFX_MGCG */
8334         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8335         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8336                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8337
8338         /* AMD_CG_SUPPORT_GFX_CGCG */
8339         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8340         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8341                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8342
8343         /* AMD_CG_SUPPORT_GFX_CGLS */
8344         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8345                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8346
8347         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8348         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8349         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8350                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8351
8352         /* AMD_CG_SUPPORT_GFX_CP_LS */
8353         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8354         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8355                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8356
8357         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8358         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8359         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8360                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8361
8362         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8363         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8364                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8365 }
8366
8367 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8368 {
8369         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8370 }
8371
8372 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8373 {
8374         struct amdgpu_device *adev = ring->adev;
8375         u64 wptr;
8376
8377         /* XXX check if swapping is necessary on BE */
8378         if (ring->use_doorbell) {
8379                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8380         } else {
8381                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8382                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8383         }
8384
8385         return wptr;
8386 }
8387
8388 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8389 {
8390         struct amdgpu_device *adev = ring->adev;
8391
8392         if (ring->use_doorbell) {
8393                 /* XXX check if swapping is necessary on BE */
8394                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8395                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8396         } else {
8397                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8398                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8399         }
8400 }
8401
8402 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8403 {
8404         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8405 }
8406
8407 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8408 {
8409         u64 wptr;
8410
8411         /* XXX check if swapping is necessary on BE */
8412         if (ring->use_doorbell)
8413                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8414         else
8415                 BUG();
8416         return wptr;
8417 }
8418
8419 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8420 {
8421         struct amdgpu_device *adev = ring->adev;
8422
8423         /* XXX check if swapping is necessary on BE */
8424         if (ring->use_doorbell) {
8425                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8426                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8427         } else {
8428                 BUG(); /* only DOORBELL method supported on gfx10 now */
8429         }
8430 }
8431
8432 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8433 {
8434         struct amdgpu_device *adev = ring->adev;
8435         u32 ref_and_mask, reg_mem_engine;
8436         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8437
8438         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8439                 switch (ring->me) {
8440                 case 1:
8441                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8442                         break;
8443                 case 2:
8444                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8445                         break;
8446                 default:
8447                         return;
8448                 }
8449                 reg_mem_engine = 0;
8450         } else {
8451                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8452                 reg_mem_engine = 1; /* pfp */
8453         }
8454
8455         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8456                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8457                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8458                                ref_and_mask, ref_and_mask, 0x20);
8459 }
8460
8461 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8462                                        struct amdgpu_job *job,
8463                                        struct amdgpu_ib *ib,
8464                                        uint32_t flags)
8465 {
8466         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8467         u32 header, control = 0;
8468
8469         if (ib->flags & AMDGPU_IB_FLAG_CE)
8470                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8471         else
8472                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8473
8474         control |= ib->length_dw | (vmid << 24);
8475
8476         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8477                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8478
8479                 if (flags & AMDGPU_IB_PREEMPTED)
8480                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8481
8482                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8483                         gfx_v10_0_ring_emit_de_meta(ring,
8484                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8485         }
8486
8487         amdgpu_ring_write(ring, header);
8488         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8489         amdgpu_ring_write(ring,
8490 #ifdef __BIG_ENDIAN
8491                 (2 << 0) |
8492 #endif
8493                 lower_32_bits(ib->gpu_addr));
8494         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8495         amdgpu_ring_write(ring, control);
8496 }
8497
8498 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8499                                            struct amdgpu_job *job,
8500                                            struct amdgpu_ib *ib,
8501                                            uint32_t flags)
8502 {
8503         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8504         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8505
8506         /* Currently, there is a high possibility to get wave ID mismatch
8507          * between ME and GDS, leading to a hw deadlock, because ME generates
8508          * different wave IDs than the GDS expects. This situation happens
8509          * randomly when at least 5 compute pipes use GDS ordered append.
8510          * The wave IDs generated by ME are also wrong after suspend/resume.
8511          * Those are probably bugs somewhere else in the kernel driver.
8512          *
8513          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8514          * GDS to 0 for this ring (me/pipe).
8515          */
8516         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8517                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8518                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8519                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8520         }
8521
8522         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8523         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8524         amdgpu_ring_write(ring,
8525 #ifdef __BIG_ENDIAN
8526                                 (2 << 0) |
8527 #endif
8528                                 lower_32_bits(ib->gpu_addr));
8529         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8530         amdgpu_ring_write(ring, control);
8531 }
8532
8533 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8534                                      u64 seq, unsigned flags)
8535 {
8536         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8537         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8538
8539         /* RELEASE_MEM - flush caches, send int */
8540         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8541         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8542                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8543                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8544                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8545                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8546                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8547                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8548         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8549                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8550
8551         /*
8552          * the address should be Qword aligned if 64bit write, Dword
8553          * aligned if only send 32bit data low (discard data high)
8554          */
8555         if (write64bit)
8556                 BUG_ON(addr & 0x7);
8557         else
8558                 BUG_ON(addr & 0x3);
8559         amdgpu_ring_write(ring, lower_32_bits(addr));
8560         amdgpu_ring_write(ring, upper_32_bits(addr));
8561         amdgpu_ring_write(ring, lower_32_bits(seq));
8562         amdgpu_ring_write(ring, upper_32_bits(seq));
8563         amdgpu_ring_write(ring, 0);
8564 }
8565
8566 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8567 {
8568         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8569         uint32_t seq = ring->fence_drv.sync_seq;
8570         uint64_t addr = ring->fence_drv.gpu_addr;
8571
8572         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8573                                upper_32_bits(addr), seq, 0xffffffff, 4);
8574 }
8575
8576 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8577                                          unsigned vmid, uint64_t pd_addr)
8578 {
8579         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8580
8581         /* compute doesn't have PFP */
8582         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8583                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8584                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8585                 amdgpu_ring_write(ring, 0x0);
8586         }
8587 }
8588
8589 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8590                                           u64 seq, unsigned int flags)
8591 {
8592         struct amdgpu_device *adev = ring->adev;
8593
8594         /* we only allocate 32bit for each seq wb address */
8595         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8596
8597         /* write fence seq to the "addr" */
8598         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8599         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8600                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8601         amdgpu_ring_write(ring, lower_32_bits(addr));
8602         amdgpu_ring_write(ring, upper_32_bits(addr));
8603         amdgpu_ring_write(ring, lower_32_bits(seq));
8604
8605         if (flags & AMDGPU_FENCE_FLAG_INT) {
8606                 /* set register to trigger INT */
8607                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8608                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8609                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8610                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8611                 amdgpu_ring_write(ring, 0);
8612                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8613         }
8614 }
8615
8616 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8617 {
8618         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8619         amdgpu_ring_write(ring, 0);
8620 }
8621
8622 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8623                                          uint32_t flags)
8624 {
8625         uint32_t dw2 = 0;
8626
8627         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8628                 gfx_v10_0_ring_emit_ce_meta(ring,
8629                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8630
8631         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8632         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8633                 /* set load_global_config & load_global_uconfig */
8634                 dw2 |= 0x8001;
8635                 /* set load_cs_sh_regs */
8636                 dw2 |= 0x01000000;
8637                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8638                 dw2 |= 0x10002;
8639
8640                 /* set load_ce_ram if preamble presented */
8641                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8642                         dw2 |= 0x10000000;
8643         } else {
8644                 /* still load_ce_ram if this is the first time preamble presented
8645                  * although there is no context switch happens.
8646                  */
8647                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8648                         dw2 |= 0x10000000;
8649         }
8650
8651         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8652         amdgpu_ring_write(ring, dw2);
8653         amdgpu_ring_write(ring, 0);
8654 }
8655
8656 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8657 {
8658         unsigned ret;
8659
8660         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8661         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8662         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8663         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8664         ret = ring->wptr & ring->buf_mask;
8665         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8666
8667         return ret;
8668 }
8669
8670 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8671 {
8672         unsigned cur;
8673         BUG_ON(offset > ring->buf_mask);
8674         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8675
8676         cur = (ring->wptr - 1) & ring->buf_mask;
8677         if (likely(cur > offset))
8678                 ring->ring[offset] = cur - offset;
8679         else
8680                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8681 }
8682
8683 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8684 {
8685         int i, r = 0;
8686         struct amdgpu_device *adev = ring->adev;
8687         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8688         struct amdgpu_ring *kiq_ring = &kiq->ring;
8689         unsigned long flags;
8690
8691         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8692                 return -EINVAL;
8693
8694         spin_lock_irqsave(&kiq->ring_lock, flags);
8695
8696         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8697                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8698                 return -ENOMEM;
8699         }
8700
8701         /* assert preemption condition */
8702         amdgpu_ring_set_preempt_cond_exec(ring, false);
8703
8704         /* assert IB preemption, emit the trailing fence */
8705         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8706                                    ring->trail_fence_gpu_addr,
8707                                    ++ring->trail_seq);
8708         amdgpu_ring_commit(kiq_ring);
8709
8710         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8711
8712         /* poll the trailing fence */
8713         for (i = 0; i < adev->usec_timeout; i++) {
8714                 if (ring->trail_seq ==
8715                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8716                         break;
8717                 udelay(1);
8718         }
8719
8720         if (i >= adev->usec_timeout) {
8721                 r = -EINVAL;
8722                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8723         }
8724
8725         /* deassert preemption condition */
8726         amdgpu_ring_set_preempt_cond_exec(ring, true);
8727         return r;
8728 }
8729
8730 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8731 {
8732         struct amdgpu_device *adev = ring->adev;
8733         struct v10_ce_ib_state ce_payload = {0};
8734         uint64_t csa_addr;
8735         int cnt;
8736
8737         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8738         csa_addr = amdgpu_csa_vaddr(ring->adev);
8739
8740         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8741         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8742                                  WRITE_DATA_DST_SEL(8) |
8743                                  WR_CONFIRM) |
8744                                  WRITE_DATA_CACHE_POLICY(0));
8745         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8746                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8747         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8748                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8749
8750         if (resume)
8751                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8752                                            offsetof(struct v10_gfx_meta_data,
8753                                                     ce_payload),
8754                                            sizeof(ce_payload) >> 2);
8755         else
8756                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8757                                            sizeof(ce_payload) >> 2);
8758 }
8759
8760 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8761 {
8762         struct amdgpu_device *adev = ring->adev;
8763         struct v10_de_ib_state de_payload = {0};
8764         uint64_t csa_addr, gds_addr;
8765         int cnt;
8766
8767         csa_addr = amdgpu_csa_vaddr(ring->adev);
8768         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8769                          PAGE_SIZE);
8770         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8771         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8772
8773         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8774         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8775         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8776                                  WRITE_DATA_DST_SEL(8) |
8777                                  WR_CONFIRM) |
8778                                  WRITE_DATA_CACHE_POLICY(0));
8779         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8780                               offsetof(struct v10_gfx_meta_data, de_payload)));
8781         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8782                               offsetof(struct v10_gfx_meta_data, de_payload)));
8783
8784         if (resume)
8785                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8786                                            offsetof(struct v10_gfx_meta_data,
8787                                                     de_payload),
8788                                            sizeof(de_payload) >> 2);
8789         else
8790                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8791                                            sizeof(de_payload) >> 2);
8792 }
8793
8794 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8795                                     bool secure)
8796 {
8797         uint32_t v = secure ? FRAME_TMZ : 0;
8798
8799         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8800         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8801 }
8802
8803 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8804                                      uint32_t reg_val_offs)
8805 {
8806         struct amdgpu_device *adev = ring->adev;
8807
8808         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8809         amdgpu_ring_write(ring, 0 |     /* src: register*/
8810                                 (5 << 8) |      /* dst: memory */
8811                                 (1 << 20));     /* write confirm */
8812         amdgpu_ring_write(ring, reg);
8813         amdgpu_ring_write(ring, 0);
8814         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8815                                 reg_val_offs * 4));
8816         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8817                                 reg_val_offs * 4));
8818 }
8819
8820 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8821                                    uint32_t val)
8822 {
8823         uint32_t cmd = 0;
8824
8825         switch (ring->funcs->type) {
8826         case AMDGPU_RING_TYPE_GFX:
8827                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8828                 break;
8829         case AMDGPU_RING_TYPE_KIQ:
8830                 cmd = (1 << 16); /* no inc addr */
8831                 break;
8832         default:
8833                 cmd = WR_CONFIRM;
8834                 break;
8835         }
8836         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8837         amdgpu_ring_write(ring, cmd);
8838         amdgpu_ring_write(ring, reg);
8839         amdgpu_ring_write(ring, 0);
8840         amdgpu_ring_write(ring, val);
8841 }
8842
8843 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8844                                         uint32_t val, uint32_t mask)
8845 {
8846         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8847 }
8848
8849 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8850                                                    uint32_t reg0, uint32_t reg1,
8851                                                    uint32_t ref, uint32_t mask)
8852 {
8853         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8854         struct amdgpu_device *adev = ring->adev;
8855         bool fw_version_ok = false;
8856
8857         fw_version_ok = adev->gfx.cp_fw_write_wait;
8858
8859         if (fw_version_ok)
8860                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8861                                        ref, mask, 0x20);
8862         else
8863                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8864                                                            ref, mask);
8865 }
8866
8867 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8868                                          unsigned vmid)
8869 {
8870         struct amdgpu_device *adev = ring->adev;
8871         uint32_t value = 0;
8872
8873         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8874         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8875         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8876         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8877         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8878 }
8879
8880 static void
8881 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8882                                       uint32_t me, uint32_t pipe,
8883                                       enum amdgpu_interrupt_state state)
8884 {
8885         uint32_t cp_int_cntl, cp_int_cntl_reg;
8886
8887         if (!me) {
8888                 switch (pipe) {
8889                 case 0:
8890                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8891                         break;
8892                 case 1:
8893                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8894                         break;
8895                 default:
8896                         DRM_DEBUG("invalid pipe %d\n", pipe);
8897                         return;
8898                 }
8899         } else {
8900                 DRM_DEBUG("invalid me %d\n", me);
8901                 return;
8902         }
8903
8904         switch (state) {
8905         case AMDGPU_IRQ_STATE_DISABLE:
8906                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8907                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8908                                             TIME_STAMP_INT_ENABLE, 0);
8909                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8910                 break;
8911         case AMDGPU_IRQ_STATE_ENABLE:
8912                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8913                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8914                                             TIME_STAMP_INT_ENABLE, 1);
8915                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8916                 break;
8917         default:
8918                 break;
8919         }
8920 }
8921
8922 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8923                                                      int me, int pipe,
8924                                                      enum amdgpu_interrupt_state state)
8925 {
8926         u32 mec_int_cntl, mec_int_cntl_reg;
8927
8928         /*
8929          * amdgpu controls only the first MEC. That's why this function only
8930          * handles the setting of interrupts for this specific MEC. All other
8931          * pipes' interrupts are set by amdkfd.
8932          */
8933
8934         if (me == 1) {
8935                 switch (pipe) {
8936                 case 0:
8937                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8938                         break;
8939                 case 1:
8940                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8941                         break;
8942                 case 2:
8943                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8944                         break;
8945                 case 3:
8946                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8947                         break;
8948                 default:
8949                         DRM_DEBUG("invalid pipe %d\n", pipe);
8950                         return;
8951                 }
8952         } else {
8953                 DRM_DEBUG("invalid me %d\n", me);
8954                 return;
8955         }
8956
8957         switch (state) {
8958         case AMDGPU_IRQ_STATE_DISABLE:
8959                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8960                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8961                                              TIME_STAMP_INT_ENABLE, 0);
8962                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8963                 break;
8964         case AMDGPU_IRQ_STATE_ENABLE:
8965                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8966                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8967                                              TIME_STAMP_INT_ENABLE, 1);
8968                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8969                 break;
8970         default:
8971                 break;
8972         }
8973 }
8974
8975 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8976                                             struct amdgpu_irq_src *src,
8977                                             unsigned type,
8978                                             enum amdgpu_interrupt_state state)
8979 {
8980         switch (type) {
8981         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8982                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8983                 break;
8984         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8985                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8986                 break;
8987         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8988                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8989                 break;
8990         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8991                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8992                 break;
8993         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8994                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8995                 break;
8996         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8997                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8998                 break;
8999         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9000                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9001                 break;
9002         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9003                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9004                 break;
9005         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9006                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9007                 break;
9008         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9009                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9010                 break;
9011         default:
9012                 break;
9013         }
9014         return 0;
9015 }
9016
9017 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9018                              struct amdgpu_irq_src *source,
9019                              struct amdgpu_iv_entry *entry)
9020 {
9021         int i;
9022         u8 me_id, pipe_id, queue_id;
9023         struct amdgpu_ring *ring;
9024
9025         DRM_DEBUG("IH: CP EOP\n");
9026         me_id = (entry->ring_id & 0x0c) >> 2;
9027         pipe_id = (entry->ring_id & 0x03) >> 0;
9028         queue_id = (entry->ring_id & 0x70) >> 4;
9029
9030         switch (me_id) {
9031         case 0:
9032                 if (pipe_id == 0)
9033                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9034                 else
9035                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9036                 break;
9037         case 1:
9038         case 2:
9039                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9040                         ring = &adev->gfx.compute_ring[i];
9041                         /* Per-queue interrupt is supported for MEC starting from VI.
9042                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
9043                           */
9044                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
9045                                 amdgpu_fence_process(ring);
9046                 }
9047                 break;
9048         }
9049         return 0;
9050 }
9051
9052 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9053                                               struct amdgpu_irq_src *source,
9054                                               unsigned type,
9055                                               enum amdgpu_interrupt_state state)
9056 {
9057         switch (state) {
9058         case AMDGPU_IRQ_STATE_DISABLE:
9059         case AMDGPU_IRQ_STATE_ENABLE:
9060                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9061                                PRIV_REG_INT_ENABLE,
9062                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9063                 break;
9064         default:
9065                 break;
9066         }
9067
9068         return 0;
9069 }
9070
9071 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9072                                                struct amdgpu_irq_src *source,
9073                                                unsigned type,
9074                                                enum amdgpu_interrupt_state state)
9075 {
9076         switch (state) {
9077         case AMDGPU_IRQ_STATE_DISABLE:
9078         case AMDGPU_IRQ_STATE_ENABLE:
9079                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9080                                PRIV_INSTR_INT_ENABLE,
9081                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9082                 break;
9083         default:
9084                 break;
9085         }
9086
9087         return 0;
9088 }
9089
9090 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9091                                         struct amdgpu_iv_entry *entry)
9092 {
9093         u8 me_id, pipe_id, queue_id;
9094         struct amdgpu_ring *ring;
9095         int i;
9096
9097         me_id = (entry->ring_id & 0x0c) >> 2;
9098         pipe_id = (entry->ring_id & 0x03) >> 0;
9099         queue_id = (entry->ring_id & 0x70) >> 4;
9100
9101         switch (me_id) {
9102         case 0:
9103                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9104                         ring = &adev->gfx.gfx_ring[i];
9105                         /* we only enabled 1 gfx queue per pipe for now */
9106                         if (ring->me == me_id && ring->pipe == pipe_id)
9107                                 drm_sched_fault(&ring->sched);
9108                 }
9109                 break;
9110         case 1:
9111         case 2:
9112                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9113                         ring = &adev->gfx.compute_ring[i];
9114                         if (ring->me == me_id && ring->pipe == pipe_id &&
9115                             ring->queue == queue_id)
9116                                 drm_sched_fault(&ring->sched);
9117                 }
9118                 break;
9119         default:
9120                 BUG();
9121         }
9122 }
9123
9124 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9125                                   struct amdgpu_irq_src *source,
9126                                   struct amdgpu_iv_entry *entry)
9127 {
9128         DRM_ERROR("Illegal register access in command stream\n");
9129         gfx_v10_0_handle_priv_fault(adev, entry);
9130         return 0;
9131 }
9132
9133 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9134                                    struct amdgpu_irq_src *source,
9135                                    struct amdgpu_iv_entry *entry)
9136 {
9137         DRM_ERROR("Illegal instruction in command stream\n");
9138         gfx_v10_0_handle_priv_fault(adev, entry);
9139         return 0;
9140 }
9141
9142 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9143                                              struct amdgpu_irq_src *src,
9144                                              unsigned int type,
9145                                              enum amdgpu_interrupt_state state)
9146 {
9147         uint32_t tmp, target;
9148         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9149
9150         if (ring->me == 1)
9151                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9152         else
9153                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9154         target += ring->pipe;
9155
9156         switch (type) {
9157         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9158                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9159                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9160                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9161                                             GENERIC2_INT_ENABLE, 0);
9162                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9163
9164                         tmp = RREG32_SOC15_IP(GC, target);
9165                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9166                                             GENERIC2_INT_ENABLE, 0);
9167                         WREG32_SOC15_IP(GC, target, tmp);
9168                 } else {
9169                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9170                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9171                                             GENERIC2_INT_ENABLE, 1);
9172                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9173
9174                         tmp = RREG32_SOC15_IP(GC, target);
9175                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9176                                             GENERIC2_INT_ENABLE, 1);
9177                         WREG32_SOC15_IP(GC, target, tmp);
9178                 }
9179                 break;
9180         default:
9181                 BUG(); /* kiq only support GENERIC2_INT now */
9182                 break;
9183         }
9184         return 0;
9185 }
9186
9187 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9188                              struct amdgpu_irq_src *source,
9189                              struct amdgpu_iv_entry *entry)
9190 {
9191         u8 me_id, pipe_id, queue_id;
9192         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9193
9194         me_id = (entry->ring_id & 0x0c) >> 2;
9195         pipe_id = (entry->ring_id & 0x03) >> 0;
9196         queue_id = (entry->ring_id & 0x70) >> 4;
9197         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9198                    me_id, pipe_id, queue_id);
9199
9200         amdgpu_fence_process(ring);
9201         return 0;
9202 }
9203
9204 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9205 {
9206         const unsigned int gcr_cntl =
9207                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9208                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9209                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9210                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9211                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9212                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9213                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9214                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9215
9216         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9217         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9218         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9219         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9220         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9221         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9222         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9223         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9224         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9225 }
9226
9227 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9228         .name = "gfx_v10_0",
9229         .early_init = gfx_v10_0_early_init,
9230         .late_init = gfx_v10_0_late_init,
9231         .sw_init = gfx_v10_0_sw_init,
9232         .sw_fini = gfx_v10_0_sw_fini,
9233         .hw_init = gfx_v10_0_hw_init,
9234         .hw_fini = gfx_v10_0_hw_fini,
9235         .suspend = gfx_v10_0_suspend,
9236         .resume = gfx_v10_0_resume,
9237         .is_idle = gfx_v10_0_is_idle,
9238         .wait_for_idle = gfx_v10_0_wait_for_idle,
9239         .soft_reset = gfx_v10_0_soft_reset,
9240         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9241         .set_powergating_state = gfx_v10_0_set_powergating_state,
9242         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9243 };
9244
9245 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9246         .type = AMDGPU_RING_TYPE_GFX,
9247         .align_mask = 0xff,
9248         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9249         .support_64bit_ptrs = true,
9250         .vmhub = AMDGPU_GFXHUB_0,
9251         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9252         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9253         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9254         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9255                 5 + /* COND_EXEC */
9256                 7 + /* PIPELINE_SYNC */
9257                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9258                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9259                 2 + /* VM_FLUSH */
9260                 8 + /* FENCE for VM_FLUSH */
9261                 20 + /* GDS switch */
9262                 4 + /* double SWITCH_BUFFER,
9263                      * the first COND_EXEC jump to the place
9264                      * just prior to this double SWITCH_BUFFER
9265                      */
9266                 5 + /* COND_EXEC */
9267                 7 + /* HDP_flush */
9268                 4 + /* VGT_flush */
9269                 14 + /* CE_META */
9270                 31 + /* DE_META */
9271                 3 + /* CNTX_CTRL */
9272                 5 + /* HDP_INVL */
9273                 8 + 8 + /* FENCE x2 */
9274                 2 + /* SWITCH_BUFFER */
9275                 8, /* gfx_v10_0_emit_mem_sync */
9276         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9277         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9278         .emit_fence = gfx_v10_0_ring_emit_fence,
9279         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9280         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9281         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9282         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9283         .test_ring = gfx_v10_0_ring_test_ring,
9284         .test_ib = gfx_v10_0_ring_test_ib,
9285         .insert_nop = amdgpu_ring_insert_nop,
9286         .pad_ib = amdgpu_ring_generic_pad_ib,
9287         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9288         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9289         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9290         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9291         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9292         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9293         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9294         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9295         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9296         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9297         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9298 };
9299
9300 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9301         .type = AMDGPU_RING_TYPE_COMPUTE,
9302         .align_mask = 0xff,
9303         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9304         .support_64bit_ptrs = true,
9305         .vmhub = AMDGPU_GFXHUB_0,
9306         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9307         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9308         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9309         .emit_frame_size =
9310                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9311                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9312                 5 + /* hdp invalidate */
9313                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9314                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9315                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9316                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9317                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9318                 8, /* gfx_v10_0_emit_mem_sync */
9319         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9320         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9321         .emit_fence = gfx_v10_0_ring_emit_fence,
9322         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9323         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9324         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9325         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9326         .test_ring = gfx_v10_0_ring_test_ring,
9327         .test_ib = gfx_v10_0_ring_test_ib,
9328         .insert_nop = amdgpu_ring_insert_nop,
9329         .pad_ib = amdgpu_ring_generic_pad_ib,
9330         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9331         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9332         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9333         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9334 };
9335
9336 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9337         .type = AMDGPU_RING_TYPE_KIQ,
9338         .align_mask = 0xff,
9339         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9340         .support_64bit_ptrs = true,
9341         .vmhub = AMDGPU_GFXHUB_0,
9342         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9343         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9344         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9345         .emit_frame_size =
9346                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9347                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9348                 5 + /*hdp invalidate */
9349                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9350                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9351                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9352                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9353                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9354         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9355         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9356         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9357         .test_ring = gfx_v10_0_ring_test_ring,
9358         .test_ib = gfx_v10_0_ring_test_ib,
9359         .insert_nop = amdgpu_ring_insert_nop,
9360         .pad_ib = amdgpu_ring_generic_pad_ib,
9361         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9362         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9363         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9364         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9365 };
9366
9367 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9368 {
9369         int i;
9370
9371         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9372
9373         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9374                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9375
9376         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9377                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9378 }
9379
9380 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9381         .set = gfx_v10_0_set_eop_interrupt_state,
9382         .process = gfx_v10_0_eop_irq,
9383 };
9384
9385 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9386         .set = gfx_v10_0_set_priv_reg_fault_state,
9387         .process = gfx_v10_0_priv_reg_irq,
9388 };
9389
9390 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9391         .set = gfx_v10_0_set_priv_inst_fault_state,
9392         .process = gfx_v10_0_priv_inst_irq,
9393 };
9394
9395 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9396         .set = gfx_v10_0_kiq_set_interrupt_state,
9397         .process = gfx_v10_0_kiq_irq,
9398 };
9399
9400 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9401 {
9402         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9403         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9404
9405         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9406         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9407
9408         adev->gfx.priv_reg_irq.num_types = 1;
9409         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9410
9411         adev->gfx.priv_inst_irq.num_types = 1;
9412         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9413 }
9414
9415 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9416 {
9417         switch (adev->asic_type) {
9418         case CHIP_NAVI10:
9419         case CHIP_NAVI14:
9420         case CHIP_NAVY_FLOUNDER:
9421         case CHIP_VANGOGH:
9422         case CHIP_DIMGREY_CAVEFISH:
9423         case CHIP_BEIGE_GOBY:
9424         case CHIP_YELLOW_CARP:
9425                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9426                 break;
9427         case CHIP_NAVI12:
9428         case CHIP_SIENNA_CICHLID:
9429                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9430                 break;
9431         default:
9432                 break;
9433         }
9434 }
9435
9436 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9437 {
9438         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9439                             adev->gfx.config.max_sh_per_se *
9440                             adev->gfx.config.max_shader_engines;
9441
9442         adev->gds.gds_size = 0x10000;
9443         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9444         adev->gds.gws_size = 64;
9445         adev->gds.oa_size = 16;
9446 }
9447
9448 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9449                                                           u32 bitmap)
9450 {
9451         u32 data;
9452
9453         if (!bitmap)
9454                 return;
9455
9456         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9457         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9458
9459         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9460 }
9461
9462 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9463 {
9464         u32 disabled_mask =
9465                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9466         u32 efuse_setting = 0;
9467         u32 vbios_setting = 0;
9468
9469         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9470         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9471         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9472
9473         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9474         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9475         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9476
9477         disabled_mask |= efuse_setting | vbios_setting;
9478
9479         return (~disabled_mask);
9480 }
9481
9482 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9483 {
9484         u32 wgp_idx, wgp_active_bitmap;
9485         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9486
9487         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9488         cu_active_bitmap = 0;
9489
9490         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9491                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9492                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9493                 if (wgp_active_bitmap & (1 << wgp_idx))
9494                         cu_active_bitmap |= cu_bitmap_per_wgp;
9495         }
9496
9497         return cu_active_bitmap;
9498 }
9499
9500 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9501                                  struct amdgpu_cu_info *cu_info)
9502 {
9503         int i, j, k, counter, active_cu_number = 0;
9504         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9505         unsigned disable_masks[4 * 2];
9506
9507         if (!adev || !cu_info)
9508                 return -EINVAL;
9509
9510         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9511
9512         mutex_lock(&adev->grbm_idx_mutex);
9513         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9514                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9515                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9516                         if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
9517                                 (adev->asic_type == CHIP_YELLOW_CARP)) &&
9518                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9519                                 continue;
9520                         mask = 1;
9521                         ao_bitmap = 0;
9522                         counter = 0;
9523                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9524                         if (i < 4 && j < 2)
9525                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9526                                         adev, disable_masks[i * 2 + j]);
9527                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9528                         cu_info->bitmap[i][j] = bitmap;
9529
9530                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9531                                 if (bitmap & mask) {
9532                                         if (counter < adev->gfx.config.max_cu_per_sh)
9533                                                 ao_bitmap |= mask;
9534                                         counter++;
9535                                 }
9536                                 mask <<= 1;
9537                         }
9538                         active_cu_number += counter;
9539                         if (i < 2 && j < 2)
9540                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9541                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9542                 }
9543         }
9544         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9545         mutex_unlock(&adev->grbm_idx_mutex);
9546
9547         cu_info->number = active_cu_number;
9548         cu_info->ao_cu_mask = ao_cu_mask;
9549         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9550
9551         return 0;
9552 }
9553
9554 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9555 {
9556         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9557
9558         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9559         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9560         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9561
9562         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9563         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9564         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9565
9566         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9567                                                 adev->gfx.config.max_shader_engines);
9568         disabled_sa = efuse_setting | vbios_setting;
9569         disabled_sa &= max_sa_mask;
9570
9571         return disabled_sa;
9572 }
9573
9574 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9575 {
9576         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9577         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9578
9579         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9580
9581         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9582         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9583         max_shader_engines = adev->gfx.config.max_shader_engines;
9584
9585         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9586                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9587                 disabled_sa_per_se &= max_sa_per_se_mask;
9588                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9589                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9590                         break;
9591                 }
9592         }
9593 }
9594
9595 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9596 {
9597         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9598                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9599                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9600                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9601
9602         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9603         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9604                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9605                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9606                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9607                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9608
9609         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9610                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9611                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9612                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9613
9614         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9615
9616         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9617                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9618 }
9619
9620 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9621 {
9622         .type = AMD_IP_BLOCK_TYPE_GFX,
9623         .major = 10,
9624         .minor = 0,
9625         .rev = 0,
9626         .funcs = &gfx_v10_0_ip_funcs,
9627 };