drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "navi10_enum.h"
  39 #include "hdp/hdp_5_0_0_offset.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15_common.h"
  44 #include "clearstate_gfx10.h"
  45 #include "v10_structs.h"
  46 #include "gfx_v10_0.h"
  47 #include "nbio_v2_3.h"
  48
  49 /**
  50  * Navi10 has two graphic rings to share each graphic pipe.
  51  * 1. Primary ring
  52  * 2. Async ring
  53  *
  54  * In bring-up phase, it just used primary ring so set gfx ring number as 1 at
  55  * first.
  56  */
  57 #define GFX10_NUM_GFX_RINGS     2
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65
  66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
  67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
  68 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
  69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
  70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
  71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
  72
  73 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
  74 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
  75 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
  76 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
  77 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
  78 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
  79
  80 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
  81 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
  82 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
  83 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
  84 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
  85 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
  86
  87 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
  88 {
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
 126 };
 127
 128 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 129 {
 130         /* Pending on emulation bring up */
 131 };
 132
 133 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
 134 {
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
 170 };
 171
 172 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
 173 {
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
 214 };
 215
 216 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
 217 {
 218         /* Pending on emulation bring up */
 219 };
 220
 221 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
 222 {
 223         /* Pending on emulation bring up */
 224 };
 225
 226 #define DEFAULT_SH_MEM_CONFIG \
 227         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 228          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 229          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
 230          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 231
 232
 233 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
 234 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 235 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
 236 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
 237 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
 238                                  struct amdgpu_cu_info *cu_info);
 239 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 240 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 241                                    u32 sh_num, u32 instance);
 242 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 243
 244 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
 245 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
 246 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
 247 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 248 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
 249 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 250 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
 251
 252 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 253 {
 254         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 255         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 256                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 257         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 258         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 259         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 260         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 261         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 262         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 263 }
 264
 265 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 266                                  struct amdgpu_ring *ring)
 267 {
 268         struct amdgpu_device *adev = kiq_ring->adev;
 269         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 270         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 271         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 272
 273         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 274         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 275         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 276                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 277                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 278                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 279                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 280                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
 281                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 282                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 283                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 284                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 285         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 286         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 287         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 288         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 289         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 290 }
 291
 292 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 293                                    struct amdgpu_ring *ring,
 294                                    enum amdgpu_unmap_queues_action action,
 295                                    u64 gpu_addr, u64 seq)
 296 {
 297         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 298
 299         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 300         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 301                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 302                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 303                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 304                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 305         amdgpu_ring_write(kiq_ring,
 306                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 307
 308         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 309                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 310                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 311                 amdgpu_ring_write(kiq_ring, seq);
 312         } else {
 313                 amdgpu_ring_write(kiq_ring, 0);
 314                 amdgpu_ring_write(kiq_ring, 0);
 315                 amdgpu_ring_write(kiq_ring, 0);
 316         }
 317 }
 318
 319 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
 320                                    struct amdgpu_ring *ring,
 321                                    u64 addr,
 322                                    u64 seq)
 323 {
 324         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 325
 326         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 327         amdgpu_ring_write(kiq_ring,
 328                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 329                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 330                           PACKET3_QUERY_STATUS_COMMAND(2));
 331         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 332                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 333                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 334         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 335         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 336         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 337         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 338 }
 339
 340 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
 341         .kiq_set_resources = gfx10_kiq_set_resources,
 342         .kiq_map_queues = gfx10_kiq_map_queues,
 343         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
 344         .kiq_query_status = gfx10_kiq_query_status,
 345         .set_resources_size = 8,
 346         .map_queues_size = 7,
 347         .unmap_queues_size = 6,
 348         .query_status_size = 7,
 349 };
 350
 351 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 352 {
 353         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
 354 }
 355
 356 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 357 {
 358         switch (adev->asic_type) {
 359         case CHIP_NAVI10:
 360                 soc15_program_register_sequence(adev,
 361                                                 golden_settings_gc_10_1,
 362                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
 363                 soc15_program_register_sequence(adev,
 364                                                 golden_settings_gc_10_0_nv10,
 365                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
 366                 break;
 367         case CHIP_NAVI14:
 368                 soc15_program_register_sequence(adev,
 369                                                 golden_settings_gc_10_1_1,
 370                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
 371                 soc15_program_register_sequence(adev,
 372                                                 golden_settings_gc_10_1_nv14,
 373                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
 374                 break;
 375         case CHIP_NAVI12:
 376                 soc15_program_register_sequence(adev,
 377                                                 golden_settings_gc_10_1_2,
 378                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
 379                 soc15_program_register_sequence(adev,
 380                                                 golden_settings_gc_10_1_2_nv12,
 381                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
 382                 break;
 383         default:
 384                 break;
 385         }
 386 }
 387
 388 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
 389 {
 390         adev->gfx.scratch.num_reg = 8;
 391         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 392         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 393 }
 394
 395 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 396                                        bool wc, uint32_t reg, uint32_t val)
 397 {
 398         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 399         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 400                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 401         amdgpu_ring_write(ring, reg);
 402         amdgpu_ring_write(ring, 0);
 403         amdgpu_ring_write(ring, val);
 404 }
 405
 406 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 407                                   int mem_space, int opt, uint32_t addr0,
 408                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 409                                   uint32_t inv)
 410 {
 411         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 412         amdgpu_ring_write(ring,
 413                           /* memory (1) or register (0) */
 414                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 415                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 416                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 417                            WAIT_REG_MEM_ENGINE(eng_sel)));
 418
 419         if (mem_space)
 420                 BUG_ON(addr0 & 0x3); /* Dword align */
 421         amdgpu_ring_write(ring, addr0);
 422         amdgpu_ring_write(ring, addr1);
 423         amdgpu_ring_write(ring, ref);
 424         amdgpu_ring_write(ring, mask);
 425         amdgpu_ring_write(ring, inv); /* poll interval */
 426 }
 427
 428 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 429 {
 430         struct amdgpu_device *adev = ring->adev;
 431         uint32_t scratch;
 432         uint32_t tmp = 0;
 433         unsigned i;
 434         int r;
 435
 436         r = amdgpu_gfx_scratch_get(adev, &scratch);
 437         if (r) {
 438                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 439                 return r;
 440         }
 441
 442         WREG32(scratch, 0xCAFEDEAD);
 443
 444         r = amdgpu_ring_alloc(ring, 3);
 445         if (r) {
 446                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 447                           ring->idx, r);
 448                 amdgpu_gfx_scratch_free(adev, scratch);
 449                 return r;
 450         }
 451
 452         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 453         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 454         amdgpu_ring_write(ring, 0xDEADBEEF);
 455         amdgpu_ring_commit(ring);
 456
 457         for (i = 0; i < adev->usec_timeout; i++) {
 458                 tmp = RREG32(scratch);
 459                 if (tmp == 0xDEADBEEF)
 460                         break;
 461                 if (amdgpu_emu_mode == 1)
 462                         msleep(1);
 463                 else
 464                         udelay(1);
 465         }
 466         if (i < adev->usec_timeout) {
 467                 if (amdgpu_emu_mode == 1)
 468                         DRM_INFO("ring test on %d succeeded in %d msecs\n",
 469                                  ring->idx, i);
 470                 else
 471                         DRM_INFO("ring test on %d succeeded in %d usecs\n",
 472                                  ring->idx, i);
 473         } else {
 474                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 475                           ring->idx, scratch, tmp);
 476                 r = -EINVAL;
 477         }
 478         amdgpu_gfx_scratch_free(adev, scratch);
 479
 480         return r;
 481 }
 482
 483 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 484 {
 485         struct amdgpu_device *adev = ring->adev;
 486         struct amdgpu_ib ib;
 487         struct dma_fence *f = NULL;
 488         uint32_t scratch;
 489         uint32_t tmp = 0;
 490         long r;
 491
 492         r = amdgpu_gfx_scratch_get(adev, &scratch);
 493         if (r) {
 494                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
 495                 return r;
 496         }
 497
 498         WREG32(scratch, 0xCAFEDEAD);
 499
 500         memset(&ib, 0, sizeof(ib));
 501         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 502         if (r) {
 503                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 504                 goto err1;
 505         }
 506
 507         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 508         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 509         ib.ptr[2] = 0xDEADBEEF;
 510         ib.length_dw = 3;
 511
 512         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 513         if (r)
 514                 goto err2;
 515
 516         r = dma_fence_wait_timeout(f, false, timeout);
 517         if (r == 0) {
 518                 DRM_ERROR("amdgpu: IB test timed out.\n");
 519                 r = -ETIMEDOUT;
 520                 goto err2;
 521         } else if (r < 0) {
 522                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 523                 goto err2;
 524         }
 525
 526         tmp = RREG32(scratch);
 527         if (tmp == 0xDEADBEEF) {
 528                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 529                 r = 0;
 530         } else {
 531                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 532                           scratch, tmp);
 533                 r = -EINVAL;
 534         }
 535 err2:
 536         amdgpu_ib_free(adev, &ib, NULL);
 537         dma_fence_put(f);
 538 err1:
 539         amdgpu_gfx_scratch_free(adev, scratch);
 540
 541         return r;
 542 }
 543
 544 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
 545 {
 546         release_firmware(adev->gfx.pfp_fw);
 547         adev->gfx.pfp_fw = NULL;
 548         release_firmware(adev->gfx.me_fw);
 549         adev->gfx.me_fw = NULL;
 550         release_firmware(adev->gfx.ce_fw);
 551         adev->gfx.ce_fw = NULL;
 552         release_firmware(adev->gfx.rlc_fw);
 553         adev->gfx.rlc_fw = NULL;
 554         release_firmware(adev->gfx.mec_fw);
 555         adev->gfx.mec_fw = NULL;
 556         release_firmware(adev->gfx.mec2_fw);
 557         adev->gfx.mec2_fw = NULL;
 558
 559         kfree(adev->gfx.rlc.register_list_format);
 560 }
 561
 562 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 563 {
 564         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 565
 566         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 567         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 568         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 569         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 570         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 571         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 572         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 573         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 574         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 575         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 576         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 577         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 578         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 579         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 580                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 581 }
 582
 583 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
 584 {
 585         switch (adev->asic_type) {
 586         case CHIP_NAVI10:
 587                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 588                 break;
 589         default:
 590                 break;
 591         }
 592 }
 593
 594 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 595 {
 596         const char *chip_name;
 597         char fw_name[30];
 598         int err;
 599         struct amdgpu_firmware_info *info = NULL;
 600         const struct common_firmware_header *header = NULL;
 601         const struct gfx_firmware_header_v1_0 *cp_hdr;
 602         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 603         unsigned int *tmp = NULL;
 604         unsigned int i = 0;
 605         uint16_t version_major;
 606         uint16_t version_minor;
 607
 608         DRM_DEBUG("\n");
 609
 610         switch (adev->asic_type) {
 611         case CHIP_NAVI10:
 612                 chip_name = "navi10";
 613                 break;
 614         case CHIP_NAVI14:
 615                 chip_name = "navi14";
 616                 break;
 617         case CHIP_NAVI12:
 618                 chip_name = "navi12";
 619                 break;
 620         default:
 621                 BUG();
 622         }
 623
 624         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 625         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 626         if (err)
 627                 goto out;
 628         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 629         if (err)
 630                 goto out;
 631         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 632         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 633         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 634
 635         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 636         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 637         if (err)
 638                 goto out;
 639         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 640         if (err)
 641                 goto out;
 642         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 643         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 644         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 645
 646         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 647         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 648         if (err)
 649                 goto out;
 650         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 651         if (err)
 652                 goto out;
 653         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 654         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 655         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 656
 657         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 658         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 659         if (err)
 660                 goto out;
 661         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 662         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 663         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 664         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 665         if (version_major == 2 && version_minor == 1)
 666                 adev->gfx.rlc.is_rlc_v2_1 = true;
 667
 668         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 669         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 670         adev->gfx.rlc.save_and_restore_offset =
 671                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 672         adev->gfx.rlc.clear_state_descriptor_offset =
 673                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 674         adev->gfx.rlc.avail_scratch_ram_locations =
 675                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 676         adev->gfx.rlc.reg_restore_list_size =
 677                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 678         adev->gfx.rlc.reg_list_format_start =
 679                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 680         adev->gfx.rlc.reg_list_format_separate_start =
 681                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 682         adev->gfx.rlc.starting_offsets_start =
 683                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 684         adev->gfx.rlc.reg_list_format_size_bytes =
 685                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 686         adev->gfx.rlc.reg_list_size_bytes =
 687                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 688         adev->gfx.rlc.register_list_format =
 689                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 690                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 691         if (!adev->gfx.rlc.register_list_format) {
 692                 err = -ENOMEM;
 693                 goto out;
 694         }
 695
 696         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 697                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 698         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 699                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 700
 701         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 702
 703         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 704                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 705         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 706                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 707
 708         if (adev->gfx.rlc.is_rlc_v2_1)
 709                 gfx_v10_0_init_rlc_ext_microcode(adev);
 710
 711         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 712         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 713         if (err)
 714                 goto out;
 715         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 716         if (err)
 717                 goto out;
 718         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 719         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 720         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 721
 722         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 723         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 724         if (!err) {
 725                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 726                 if (err)
 727                         goto out;
 728                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 729                 adev->gfx.mec2_fw->data;
 730                 adev->gfx.mec2_fw_version =
 731                 le32_to_cpu(cp_hdr->header.ucode_version);
 732                 adev->gfx.mec2_feature_version =
 733                 le32_to_cpu(cp_hdr->ucode_feature_version);
 734         } else {
 735                 err = 0;
 736                 adev->gfx.mec2_fw = NULL;
 737         }
 738
 739         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 740                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 741                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 742                 info->fw = adev->gfx.pfp_fw;
 743                 header = (const struct common_firmware_header *)info->fw->data;
 744                 adev->firmware.fw_size +=
 745                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 746
 747                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 748                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 749                 info->fw = adev->gfx.me_fw;
 750                 header = (const struct common_firmware_header *)info->fw->data;
 751                 adev->firmware.fw_size +=
 752                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 753
 754                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 755                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 756                 info->fw = adev->gfx.ce_fw;
 757                 header = (const struct common_firmware_header *)info->fw->data;
 758                 adev->firmware.fw_size +=
 759                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 760
 761                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 762                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 763                 info->fw = adev->gfx.rlc_fw;
 764                 header = (const struct common_firmware_header *)info->fw->data;
 765                 adev->firmware.fw_size +=
 766                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 767
 768                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 769                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 770                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 771                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 772                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 773                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 774                         info->fw = adev->gfx.rlc_fw;
 775                         adev->firmware.fw_size +=
 776                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 777
 778                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 779                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 780                         info->fw = adev->gfx.rlc_fw;
 781                         adev->firmware.fw_size +=
 782                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 783
 784                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 785                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 786                         info->fw = adev->gfx.rlc_fw;
 787                         adev->firmware.fw_size +=
 788                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 789                 }
 790
 791                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 792                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 793                 info->fw = adev->gfx.mec_fw;
 794                 header = (const struct common_firmware_header *)info->fw->data;
 795                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 796                 adev->firmware.fw_size +=
 797                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 798                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 799
 800                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 801                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 802                 info->fw = adev->gfx.mec_fw;
 803                 adev->firmware.fw_size +=
 804                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 805
 806                 if (adev->gfx.mec2_fw) {
 807                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 808                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 809                         info->fw = adev->gfx.mec2_fw;
 810                         header = (const struct common_firmware_header *)info->fw->data;
 811                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 812                         adev->firmware.fw_size +=
 813                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
 814                                       le32_to_cpu(cp_hdr->jt_size) * 4,
 815                                       PAGE_SIZE);
 816                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 817                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 818                         info->fw = adev->gfx.mec2_fw;
 819                         adev->firmware.fw_size +=
 820                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
 821                                       PAGE_SIZE);
 822                 }
 823         }
 824
 825 out:
 826         if (err) {
 827                 dev_err(adev->dev,
 828                         "gfx10: Failed to load firmware \"%s\"\n",
 829                         fw_name);
 830                 release_firmware(adev->gfx.pfp_fw);
 831                 adev->gfx.pfp_fw = NULL;
 832                 release_firmware(adev->gfx.me_fw);
 833                 adev->gfx.me_fw = NULL;
 834                 release_firmware(adev->gfx.ce_fw);
 835                 adev->gfx.ce_fw = NULL;
 836                 release_firmware(adev->gfx.rlc_fw);
 837                 adev->gfx.rlc_fw = NULL;
 838                 release_firmware(adev->gfx.mec_fw);
 839                 adev->gfx.mec_fw = NULL;
 840                 release_firmware(adev->gfx.mec2_fw);
 841                 adev->gfx.mec2_fw = NULL;
 842         }
 843
 844         gfx_v10_0_check_gfxoff_flag(adev);
 845
 846         return err;
 847 }
 848
 849 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
 850 {
 851         u32 count = 0;
 852         const struct cs_section_def *sect = NULL;
 853         const struct cs_extent_def *ext = NULL;
 854
 855         /* begin clear state */
 856         count += 2;
 857         /* context control state */
 858         count += 3;
 859
 860         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
 861                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 862                         if (sect->id == SECT_CONTEXT)
 863                                 count += 2 + ext->reg_count;
 864                         else
 865                                 return 0;
 866                 }
 867         }
 868
 869         /* set PA_SC_TILE_STEERING_OVERRIDE */
 870         count += 3;
 871         /* end clear state */
 872         count += 2;
 873         /* clear state */
 874         count += 2;
 875
 876         return count;
 877 }
 878
 879 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
 880                                     volatile u32 *buffer)
 881 {
 882         u32 count = 0, i;
 883         const struct cs_section_def *sect = NULL;
 884         const struct cs_extent_def *ext = NULL;
 885         int ctx_reg_offset;
 886
 887         if (adev->gfx.rlc.cs_data == NULL)
 888                 return;
 889         if (buffer == NULL)
 890                 return;
 891
 892         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 893         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 894
 895         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 896         buffer[count++] = cpu_to_le32(0x80000000);
 897         buffer[count++] = cpu_to_le32(0x80000000);
 898
 899         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 900                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 901                         if (sect->id == SECT_CONTEXT) {
 902                                 buffer[count++] =
 903                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 904                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 905                                                 PACKET3_SET_CONTEXT_REG_START);
 906                                 for (i = 0; i < ext->reg_count; i++)
 907                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 908                         } else {
 909                                 return;
 910                         }
 911                 }
 912         }
 913
 914         ctx_reg_offset =
 915                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 916         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 917         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 918         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 919
 920         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 921         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 922
 923         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 924         buffer[count++] = cpu_to_le32(0);
 925 }
 926
 927 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
 928 {
 929         /* clear state block */
 930         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 931                         &adev->gfx.rlc.clear_state_gpu_addr,
 932                         (void **)&adev->gfx.rlc.cs_ptr);
 933
 934         /* jump table block */
 935         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 936                         &adev->gfx.rlc.cp_table_gpu_addr,
 937                         (void **)&adev->gfx.rlc.cp_table_ptr);
 938 }
 939
 940 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
 941 {
 942         const struct cs_section_def *cs_data;
 943         int r;
 944
 945         adev->gfx.rlc.cs_data = gfx10_cs_data;
 946
 947         cs_data = adev->gfx.rlc.cs_data;
 948
 949         if (cs_data) {
 950                 /* init clear state block */
 951                 r = amdgpu_gfx_rlc_init_csb(adev);
 952                 if (r)
 953                         return r;
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
 960 {
 961         int r;
 962
 963         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
 964         if (unlikely(r != 0))
 965                 return r;
 966
 967         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
 968                         AMDGPU_GEM_DOMAIN_VRAM);
 969         if (!r)
 970                 adev->gfx.rlc.clear_state_gpu_addr =
 971                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
 972
 973         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 974
 975         return r;
 976 }
 977
 978 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
 979 {
 980         int r;
 981
 982         if (!adev->gfx.rlc.clear_state_obj)
 983                 return;
 984
 985         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
 986         if (likely(r == 0)) {
 987                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
 988                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 989         }
 990 }
 991
 992 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
 993 {
 994         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 995         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 996 }
 997
 998 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
 999 {
1000         int r;
1001
1002         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1003
1004         amdgpu_gfx_graphics_queue_acquire(adev);
1005
1006         r = gfx_v10_0_init_microcode(adev);
1007         if (r)
1008                 DRM_ERROR("Failed to load gfx firmware!\n");
1009
1010         return r;
1011 }
1012
1013 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1014 {
1015         int r;
1016         u32 *hpd;
1017         const __le32 *fw_data = NULL;
1018         unsigned fw_size;
1019         u32 *fw = NULL;
1020         size_t mec_hpd_size;
1021
1022         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1023
1024         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1025
1026         /* take ownership of the relevant compute queues */
1027         amdgpu_gfx_compute_queue_acquire(adev);
1028         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1029
1030         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1031                                       AMDGPU_GEM_DOMAIN_GTT,
1032                                       &adev->gfx.mec.hpd_eop_obj,
1033                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1034                                       (void **)&hpd);
1035         if (r) {
1036                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1037                 gfx_v10_0_mec_fini(adev);
1038                 return r;
1039         }
1040
1041         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1042
1043         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1044         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1045
1046         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1047                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1048
1049                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1050                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1051                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1052
1053                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1054                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1055                                               &adev->gfx.mec.mec_fw_obj,
1056                                               &adev->gfx.mec.mec_fw_gpu_addr,
1057                                               (void **)&fw);
1058                 if (r) {
1059                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1060                         gfx_v10_0_mec_fini(adev);
1061                         return r;
1062                 }
1063
1064                 memcpy(fw, fw_data, fw_size);
1065
1066                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1067                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1068         }
1069
1070         return 0;
1071 }
1072
1073 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1074 {
1075         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1076                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1077                 (address << SQ_IND_INDEX__INDEX__SHIFT));
1078         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1079 }
1080
1081 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1082                            uint32_t thread, uint32_t regno,
1083                            uint32_t num, uint32_t *out)
1084 {
1085         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1086                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1087                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1088                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1089                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1090         while (num--)
1091                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1092 }
1093
1094 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1095 {
1096         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1097          * field when performing a select_se_sh so it should be
1098          * zero here */
1099         WARN_ON(simd != 0);
1100
1101         /* type 2 wave data */
1102         dst[(*no_fields)++] = 2;
1103         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1104         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1105         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1106         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1107         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1108         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1109         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1110         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1111         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1112         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1113         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1114         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1115         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1116         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1117         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1118 }
1119
1120 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1121                                      uint32_t wave, uint32_t start,
1122                                      uint32_t size, uint32_t *dst)
1123 {
1124         WARN_ON(simd != 0);
1125
1126         wave_read_regs(
1127                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1128                 dst);
1129 }
1130
1131 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1132                                       uint32_t wave, uint32_t thread,
1133                                       uint32_t start, uint32_t size,
1134                                       uint32_t *dst)
1135 {
1136         wave_read_regs(
1137                 adev, wave, thread,
1138                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1139 }
1140
1141 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1142                                                                           u32 me, u32 pipe, u32 q, u32 vm)
1143  {
1144        nv_grbm_select(adev, me, pipe, q, vm);
1145  }
1146
1147
1148 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1149         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1150         .select_se_sh = &gfx_v10_0_select_se_sh,
1151         .read_wave_data = &gfx_v10_0_read_wave_data,
1152         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1153         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1154         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1155 };
1156
1157 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1158 {
1159         u32 gb_addr_config;
1160
1161         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1162
1163         switch (adev->asic_type) {
1164         case CHIP_NAVI10:
1165         case CHIP_NAVI14:
1166         case CHIP_NAVI12:
1167                 adev->gfx.config.max_hw_contexts = 8;
1168                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1169                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1170                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1171                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1172                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1173                 break;
1174         default:
1175                 BUG();
1176                 break;
1177         }
1178
1179         adev->gfx.config.gb_addr_config = gb_addr_config;
1180
1181         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1182                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1183                                       GB_ADDR_CONFIG, NUM_PIPES);
1184
1185         adev->gfx.config.max_tile_pipes =
1186                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1187
1188         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1189                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1190                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1191         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1192                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1193                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
1194         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1195                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1196                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1197         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1198                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1199                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1200 }
1201
1202 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1203                                    int me, int pipe, int queue)
1204 {
1205         int r;
1206         struct amdgpu_ring *ring;
1207         unsigned int irq_type;
1208
1209         ring = &adev->gfx.gfx_ring[ring_id];
1210
1211         ring->me = me;
1212         ring->pipe = pipe;
1213         ring->queue = queue;
1214
1215         ring->ring_obj = NULL;
1216         ring->use_doorbell = true;
1217
1218         if (!ring_id)
1219                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1220         else
1221                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1222         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1223
1224         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1225         r = amdgpu_ring_init(adev, ring, 1024,
1226                              &adev->gfx.eop_irq, irq_type);
1227         if (r)
1228                 return r;
1229         return 0;
1230 }
1231
1232 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1233                                        int mec, int pipe, int queue)
1234 {
1235         int r;
1236         unsigned irq_type;
1237         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1238
1239         ring = &adev->gfx.compute_ring[ring_id];
1240
1241         /* mec0 is me1 */
1242         ring->me = mec + 1;
1243         ring->pipe = pipe;
1244         ring->queue = queue;
1245
1246         ring->ring_obj = NULL;
1247         ring->use_doorbell = true;
1248         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1249         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1250                                 + (ring_id * GFX10_MEC_HPD_SIZE);
1251         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1252
1253         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1254                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1255                 + ring->pipe;
1256
1257         /* type-2 packets are deprecated on MEC, use type-3 instead */
1258         r = amdgpu_ring_init(adev, ring, 1024,
1259                              &adev->gfx.eop_irq, irq_type);
1260         if (r)
1261                 return r;
1262
1263         return 0;
1264 }
1265
1266 static int gfx_v10_0_sw_init(void *handle)
1267 {
1268         int i, j, k, r, ring_id = 0;
1269         struct amdgpu_kiq *kiq;
1270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
1272         switch (adev->asic_type) {
1273         case CHIP_NAVI10:
1274         case CHIP_NAVI14:
1275         case CHIP_NAVI12:
1276                 adev->gfx.me.num_me = 1;
1277                 adev->gfx.me.num_pipe_per_me = 2;
1278                 adev->gfx.me.num_queue_per_pipe = 1;
1279                 adev->gfx.mec.num_mec = 2;
1280                 adev->gfx.mec.num_pipe_per_mec = 4;
1281                 adev->gfx.mec.num_queue_per_pipe = 8;
1282                 break;
1283         default:
1284                 adev->gfx.me.num_me = 1;
1285                 adev->gfx.me.num_pipe_per_me = 1;
1286                 adev->gfx.me.num_queue_per_pipe = 1;
1287                 adev->gfx.mec.num_mec = 1;
1288                 adev->gfx.mec.num_pipe_per_mec = 4;
1289                 adev->gfx.mec.num_queue_per_pipe = 8;
1290                 break;
1291         }
1292
1293         /* KIQ event */
1294         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1295                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1296                               &adev->gfx.kiq.irq);
1297         if (r)
1298                 return r;
1299
1300         /* EOP Event */
1301         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1302                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1303                               &adev->gfx.eop_irq);
1304         if (r)
1305                 return r;
1306
1307         /* Privileged reg */
1308         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1309                               &adev->gfx.priv_reg_irq);
1310         if (r)
1311                 return r;
1312
1313         /* Privileged inst */
1314         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1315                               &adev->gfx.priv_inst_irq);
1316         if (r)
1317                 return r;
1318
1319         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1320
1321         gfx_v10_0_scratch_init(adev);
1322
1323         r = gfx_v10_0_me_init(adev);
1324         if (r)
1325                 return r;
1326
1327         r = gfx_v10_0_rlc_init(adev);
1328         if (r) {
1329                 DRM_ERROR("Failed to init rlc BOs!\n");
1330                 return r;
1331         }
1332
1333         r = gfx_v10_0_mec_init(adev);
1334         if (r) {
1335                 DRM_ERROR("Failed to init MEC BOs!\n");
1336                 return r;
1337         }
1338
1339         /* set up the gfx ring */
1340         for (i = 0; i < adev->gfx.me.num_me; i++) {
1341                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1342                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1343                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1344                                         continue;
1345
1346                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1347                                                             i, k, j);
1348                                 if (r)
1349                                         return r;
1350                                 ring_id++;
1351                         }
1352                 }
1353         }
1354
1355         ring_id = 0;
1356         /* set up the compute queues - allocate horizontally across pipes */
1357         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1358                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1359                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1360                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1361                                                                      j))
1362                                         continue;
1363
1364                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
1365                                                                 i, k, j);
1366                                 if (r)
1367                                         return r;
1368
1369                                 ring_id++;
1370                         }
1371                 }
1372         }
1373
1374         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1375         if (r) {
1376                 DRM_ERROR("Failed to init KIQ BOs!\n");
1377                 return r;
1378         }
1379
1380         kiq = &adev->gfx.kiq;
1381         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1382         if (r)
1383                 return r;
1384
1385         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1386         if (r)
1387                 return r;
1388
1389         /* allocate visible FB for rlc auto-loading fw */
1390         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1391                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1392                 if (r)
1393                         return r;
1394         }
1395
1396         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1397
1398         gfx_v10_0_gpu_early_init(adev);
1399
1400         return 0;
1401 }
1402
1403 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1404 {
1405         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1406                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1407                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1408 }
1409
1410 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1411 {
1412         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1413                               &adev->gfx.ce.ce_fw_gpu_addr,
1414                               (void **)&adev->gfx.ce.ce_fw_ptr);
1415 }
1416
1417 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1418 {
1419         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1420                               &adev->gfx.me.me_fw_gpu_addr,
1421                               (void **)&adev->gfx.me.me_fw_ptr);
1422 }
1423
1424 static int gfx_v10_0_sw_fini(void *handle)
1425 {
1426         int i;
1427         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1428
1429         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1430                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1431         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1432                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1433
1434         amdgpu_gfx_mqd_sw_fini(adev);
1435         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1436         amdgpu_gfx_kiq_fini(adev);
1437
1438         gfx_v10_0_pfp_fini(adev);
1439         gfx_v10_0_ce_fini(adev);
1440         gfx_v10_0_me_fini(adev);
1441         gfx_v10_0_rlc_fini(adev);
1442         gfx_v10_0_mec_fini(adev);
1443
1444         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1445                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1446
1447         gfx_v10_0_free_microcode(adev);
1448
1449         return 0;
1450 }
1451
1452
1453 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1454 {
1455         /* TODO */
1456 }
1457
1458 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1459                                    u32 sh_num, u32 instance)
1460 {
1461         u32 data;
1462
1463         if (instance == 0xffffffff)
1464                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1465                                      INSTANCE_BROADCAST_WRITES, 1);
1466         else
1467                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1468                                      instance);
1469
1470         if (se_num == 0xffffffff)
1471                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1472                                      1);
1473         else
1474                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1475
1476         if (sh_num == 0xffffffff)
1477                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1478                                      1);
1479         else
1480                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1481
1482         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1483 }
1484
1485 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1486 {
1487         u32 data, mask;
1488
1489         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1490         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1491
1492         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1493         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1494
1495         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1496                                          adev->gfx.config.max_sh_per_se);
1497
1498         return (~data) & mask;
1499 }
1500
1501 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1502 {
1503         int i, j;
1504         u32 data;
1505         u32 active_rbs = 0;
1506         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1507                                         adev->gfx.config.max_sh_per_se;
1508
1509         mutex_lock(&adev->grbm_idx_mutex);
1510         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1511                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1512                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1513                         data = gfx_v10_0_get_rb_active_bitmap(adev);
1514                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1515                                                rb_bitmap_width_per_sh);
1516                 }
1517         }
1518         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1519         mutex_unlock(&adev->grbm_idx_mutex);
1520
1521         adev->gfx.config.backend_enable_mask = active_rbs;
1522         adev->gfx.config.num_rbs = hweight32(active_rbs);
1523 }
1524
1525 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1526 {
1527         uint32_t num_sc;
1528         uint32_t enabled_rb_per_sh;
1529         uint32_t active_rb_bitmap;
1530         uint32_t num_rb_per_sc;
1531         uint32_t num_packer_per_sc;
1532         uint32_t pa_sc_tile_steering_override;
1533
1534         /* init num_sc */
1535         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1536                         adev->gfx.config.num_sc_per_sh;
1537         /* init num_rb_per_sc */
1538         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1539         enabled_rb_per_sh = hweight32(active_rb_bitmap);
1540         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1541         /* init num_packer_per_sc */
1542         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1543
1544         pa_sc_tile_steering_override = 0;
1545         pa_sc_tile_steering_override |=
1546                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1547                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1548         pa_sc_tile_steering_override |=
1549                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1550                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1551         pa_sc_tile_steering_override |=
1552                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1553                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1554
1555         return pa_sc_tile_steering_override;
1556 }
1557
1558 #define DEFAULT_SH_MEM_BASES    (0x6000)
1559 #define FIRST_COMPUTE_VMID      (8)
1560 #define LAST_COMPUTE_VMID       (16)
1561
1562 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1563 {
1564         int i;
1565         uint32_t sh_mem_bases;
1566
1567         /*
1568          * Configure apertures:
1569          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1570          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1571          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1572          */
1573         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1574
1575         mutex_lock(&adev->srbm_mutex);
1576         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1577                 nv_grbm_select(adev, 0, 0, 0, i);
1578                 /* CP and shaders */
1579                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1580                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1581         }
1582         nv_grbm_select(adev, 0, 0, 0, 0);
1583         mutex_unlock(&adev->srbm_mutex);
1584 }
1585
1586 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1587 {
1588         int vmid;
1589
1590         /*
1591          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1592          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1593          * the driver can enable them for graphics. VMID0 should maintain
1594          * access so that HWS firmware can save/restore entries.
1595          */
1596         for (vmid = 1; vmid < 16; vmid++) {
1597                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1598                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1599                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1600                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1601         }
1602 }
1603
1604
1605 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1606 {
1607         int i, j, k;
1608         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1609         u32 tmp, wgp_active_bitmap = 0;
1610         u32 gcrd_targets_disable_tcp = 0;
1611         u32 utcl_invreq_disable = 0;
1612         /*
1613          * GCRD_TARGETS_DISABLE field contains
1614          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1615          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1616          */
1617         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1618                 2 * max_wgp_per_sh + /* TCP */
1619                 max_wgp_per_sh + /* SQC */
1620                 4); /* GL1C */
1621         /*
1622          * UTCL1_UTCL0_INVREQ_DISABLE field contains
1623          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1624          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1625          */
1626         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1627                 2 * max_wgp_per_sh + /* TCP */
1628                 2 * max_wgp_per_sh + /* SQC */
1629                 4 + /* RMI */
1630                 1); /* SQG */
1631
1632         if (adev->asic_type == CHIP_NAVI10 ||
1633             adev->asic_type == CHIP_NAVI14 ||
1634             adev->asic_type == CHIP_NAVI12) {
1635                 mutex_lock(&adev->grbm_idx_mutex);
1636                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1637                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1638                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1639                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1640                                 /*
1641                                  * Set corresponding TCP bits for the inactive WGPs in
1642                                  * GCRD_SA_TARGETS_DISABLE
1643                                  */
1644                                 gcrd_targets_disable_tcp = 0;
1645                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1646                                 utcl_invreq_disable = 0;
1647
1648                                 for (k = 0; k < max_wgp_per_sh; k++) {
1649                                         if (!(wgp_active_bitmap & (1 << k))) {
1650                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
1651                                                 utcl_invreq_disable |= (3 << (2 * k)) |
1652                                                         (3 << (2 * (max_wgp_per_sh + k)));
1653                                         }
1654                                 }
1655
1656                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1657                                 /* only override TCP & SQC bits */
1658                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1659                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1660                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1661
1662                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1663                                 /* only override TCP bits */
1664                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1665                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1666                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1667                         }
1668                 }
1669
1670                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1671                 mutex_unlock(&adev->grbm_idx_mutex);
1672         }
1673 }
1674
1675 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1676 {
1677         u32 tmp;
1678         int i;
1679
1680         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1681
1682         gfx_v10_0_tiling_mode_table_init(adev);
1683
1684         gfx_v10_0_setup_rb(adev);
1685         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1686         adev->gfx.config.pa_sc_tile_steering_override =
1687                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1688
1689         /* XXX SH_MEM regs */
1690         /* where to put LDS, scratch, GPUVM in FSA64 space */
1691         mutex_lock(&adev->srbm_mutex);
1692         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1693                 nv_grbm_select(adev, 0, 0, 0, i);
1694                 /* CP and shaders */
1695                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1696                 if (i != 0) {
1697                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1698                                 (adev->gmc.private_aperture_start >> 48));
1699                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1700                                 (adev->gmc.shared_aperture_start >> 48));
1701                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1702                 }
1703         }
1704         nv_grbm_select(adev, 0, 0, 0, 0);
1705
1706         mutex_unlock(&adev->srbm_mutex);
1707
1708         gfx_v10_0_init_compute_vmid(adev);
1709         gfx_v10_0_init_gds_vmid(adev);
1710
1711 }
1712
1713 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1714                                                bool enable)
1715 {
1716         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1717
1718         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1719                             enable ? 1 : 0);
1720         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1721                             enable ? 1 : 0);
1722         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1723                             enable ? 1 : 0);
1724         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1725                             enable ? 1 : 0);
1726
1727         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1728 }
1729
1730 static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
1731 {
1732         /* csib */
1733         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1734                      adev->gfx.rlc.clear_state_gpu_addr >> 32);
1735         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1736                      adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1737         WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1738 }
1739
1740 static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
1741 {
1742         gfx_v10_0_init_csb(adev);
1743
1744         amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
1745
1746         /* TODO: init power gating */
1747         return;
1748 }
1749
1750 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1751 {
1752         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1753
1754         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1755         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1756 }
1757
1758 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1759 {
1760         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1761         udelay(50);
1762         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1763         udelay(50);
1764 }
1765
1766 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1767                                              bool enable)
1768 {
1769         uint32_t rlc_pg_cntl;
1770
1771         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1772
1773         if (!enable) {
1774                 /* RLC_PG_CNTL[23] = 0 (default)
1775                  * RLC will wait for handshake acks with SMU
1776                  * GFXOFF will be enabled
1777                  * RLC_PG_CNTL[23] = 1
1778                  * RLC will not issue any message to SMU
1779                  * hence no handshake between SMU & RLC
1780                  * GFXOFF will be disabled
1781                  */
1782                 rlc_pg_cntl |= 0x800000;
1783         } else
1784                 rlc_pg_cntl &= ~0x800000;
1785         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1786 }
1787
1788 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1789 {
1790         /* TODO: enable rlc & smu handshake until smu
1791          * and gfxoff feature works as expected */
1792         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1793                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1794
1795         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1796         udelay(50);
1797 }
1798
1799 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1800 {
1801         uint32_t tmp;
1802
1803         /* enable Save Restore Machine */
1804         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1805         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1806         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1807         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1808 }
1809
1810 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1811 {
1812         const struct rlc_firmware_header_v2_0 *hdr;
1813         const __le32 *fw_data;
1814         unsigned i, fw_size;
1815
1816         if (!adev->gfx.rlc_fw)
1817                 return -EINVAL;
1818
1819         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1820         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1821
1822         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1823                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1824         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1825
1826         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1827                      RLCG_UCODE_LOADING_START_ADDRESS);
1828
1829         for (i = 0; i < fw_size; i++)
1830                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1831                              le32_to_cpup(fw_data++));
1832
1833         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1834
1835         return 0;
1836 }
1837
1838 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1839 {
1840         int r;
1841
1842         if (amdgpu_sriov_vf(adev))
1843                 return 0;
1844
1845         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1846                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1847                 if (r)
1848                         return r;
1849                 gfx_v10_0_init_pg(adev);
1850
1851                 /* enable RLC SRM */
1852                 gfx_v10_0_rlc_enable_srm(adev);
1853
1854         } else {
1855                 adev->gfx.rlc.funcs->stop(adev);
1856
1857                 /* disable CG */
1858                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1859
1860                 /* disable PG */
1861                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1862
1863                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1864                         /* legacy rlc firmware loading */
1865                         r = gfx_v10_0_rlc_load_microcode(adev);
1866                         if (r)
1867                                 return r;
1868                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1869                         /* rlc backdoor autoload firmware */
1870                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1871                         if (r)
1872                                 return r;
1873                 }
1874
1875                 gfx_v10_0_init_pg(adev);
1876                 adev->gfx.rlc.funcs->start(adev);
1877
1878                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1879                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1880                         if (r)
1881                                 return r;
1882                 }
1883         }
1884         return 0;
1885 }
1886
1887 static struct {
1888         FIRMWARE_ID     id;
1889         unsigned int    offset;
1890         unsigned int    size;
1891 } rlc_autoload_info[FIRMWARE_ID_MAX];
1892
1893 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1894 {
1895         int ret;
1896         RLC_TABLE_OF_CONTENT *rlc_toc;
1897
1898         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1899                                         AMDGPU_GEM_DOMAIN_GTT,
1900                                         &adev->gfx.rlc.rlc_toc_bo,
1901                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
1902                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
1903         if (ret) {
1904                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1905                 return ret;
1906         }
1907
1908         /* Copy toc from psp sos fw to rlc toc buffer */
1909         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1910
1911         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1912         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1913                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
1914                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1915                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1916                         /* Offset needs 4KB alignment */
1917                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1918                 }
1919
1920                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1921                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1922                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1923
1924                 rlc_toc++;
1925         };
1926
1927         return 0;
1928 }
1929
1930 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1931 {
1932         uint32_t total_size = 0;
1933         FIRMWARE_ID id;
1934         int ret;
1935
1936         ret = gfx_v10_0_parse_rlc_toc(adev);
1937         if (ret) {
1938                 dev_err(adev->dev, "failed to parse rlc toc\n");
1939                 return 0;
1940         }
1941
1942         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1943                 total_size += rlc_autoload_info[id].size;
1944
1945         /* In case the offset in rlc toc ucode is aligned */
1946         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1947                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1948                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1949
1950         return total_size;
1951 }
1952
1953 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
1954 {
1955         int r;
1956         uint32_t total_size;
1957
1958         total_size = gfx_v10_0_calc_toc_total_size(adev);
1959
1960         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
1961                                       AMDGPU_GEM_DOMAIN_GTT,
1962                                       &adev->gfx.rlc.rlc_autoload_bo,
1963                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
1964                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1965         if (r) {
1966                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1967                 return r;
1968         }
1969
1970         return 0;
1971 }
1972
1973 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
1974 {
1975         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
1976                               &adev->gfx.rlc.rlc_toc_gpu_addr,
1977                               (void **)&adev->gfx.rlc.rlc_toc_buf);
1978         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1979                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
1980                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1981 }
1982
1983 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1984                                                        FIRMWARE_ID id,
1985                                                        const void *fw_data,
1986                                                        uint32_t fw_size)
1987 {
1988         uint32_t toc_offset;
1989         uint32_t toc_fw_size;
1990         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1991
1992         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
1993                 return;
1994
1995         toc_offset = rlc_autoload_info[id].offset;
1996         toc_fw_size = rlc_autoload_info[id].size;
1997
1998         if (fw_size == 0)
1999                 fw_size = toc_fw_size;
2000
2001         if (fw_size > toc_fw_size)
2002                 fw_size = toc_fw_size;
2003
2004         memcpy(ptr + toc_offset, fw_data, fw_size);
2005
2006         if (fw_size < toc_fw_size)
2007                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2008 }
2009
2010 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2011 {
2012         void *data;
2013         uint32_t size;
2014
2015         data = adev->gfx.rlc.rlc_toc_buf;
2016         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2017
2018         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2019                                                    FIRMWARE_ID_RLC_TOC,
2020                                                    data, size);
2021 }
2022
2023 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2024 {
2025         const __le32 *fw_data;
2026         uint32_t fw_size;
2027         const struct gfx_firmware_header_v1_0 *cp_hdr;
2028         const struct rlc_firmware_header_v2_0 *rlc_hdr;
2029
2030         /* pfp ucode */
2031         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2032                 adev->gfx.pfp_fw->data;
2033         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2034                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2035         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2036         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2037                                                    FIRMWARE_ID_CP_PFP,
2038                                                    fw_data, fw_size);
2039
2040         /* ce ucode */
2041         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2042                 adev->gfx.ce_fw->data;
2043         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2044                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2045         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2046         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2047                                                    FIRMWARE_ID_CP_CE,
2048                                                    fw_data, fw_size);
2049
2050         /* me ucode */
2051         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2052                 adev->gfx.me_fw->data;
2053         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2054                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2055         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2056         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2057                                                    FIRMWARE_ID_CP_ME,
2058                                                    fw_data, fw_size);
2059
2060         /* rlc ucode */
2061         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2062                 adev->gfx.rlc_fw->data;
2063         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2064                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2065         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2066         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2067                                                    FIRMWARE_ID_RLC_G_UCODE,
2068                                                    fw_data, fw_size);
2069
2070         /* mec1 ucode */
2071         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2072                 adev->gfx.mec_fw->data;
2073         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2074                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2075         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2076                 cp_hdr->jt_size * 4;
2077         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2078                                                    FIRMWARE_ID_CP_MEC,
2079                                                    fw_data, fw_size);
2080         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2081 }
2082
2083 /* Temporarily put sdma part here */
2084 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2085 {
2086         const __le32 *fw_data;
2087         uint32_t fw_size;
2088         const struct sdma_firmware_header_v1_0 *sdma_hdr;
2089         int i;
2090
2091         for (i = 0; i < adev->sdma.num_instances; i++) {
2092                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2093                         adev->sdma.instance[i].fw->data;
2094                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2095                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2096                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2097
2098                 if (i == 0) {
2099                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2100                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2101                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2102                                 FIRMWARE_ID_SDMA0_JT,
2103                                 (uint32_t *)fw_data +
2104                                 sdma_hdr->jt_offset,
2105                                 sdma_hdr->jt_size * 4);
2106                 } else if (i == 1) {
2107                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2108                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2109                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2110                                 FIRMWARE_ID_SDMA1_JT,
2111                                 (uint32_t *)fw_data +
2112                                 sdma_hdr->jt_offset,
2113                                 sdma_hdr->jt_size * 4);
2114                 }
2115         }
2116 }
2117
2118 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2119 {
2120         uint32_t rlc_g_offset, rlc_g_size, tmp;
2121         uint64_t gpu_addr;
2122
2123         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2124         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2125         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2126
2127         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2128         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2129         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2130
2131         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2132         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2133         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2134
2135         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2136         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2137                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2138                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2139                 return -EINVAL;
2140         }
2141
2142         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2143         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2144                 DRM_ERROR("RLC ROM should halt itself\n");
2145                 return -EINVAL;
2146         }
2147
2148         return 0;
2149 }
2150
2151 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2152 {
2153         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2154         uint32_t tmp;
2155         int i;
2156         uint64_t addr;
2157
2158         /* Trigger an invalidation of the L1 instruction caches */
2159         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2160         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2161         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2162
2163         /* Wait for invalidation complete */
2164         for (i = 0; i < usec_timeout; i++) {
2165                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2166                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2167                         INVALIDATE_CACHE_COMPLETE))
2168                         break;
2169                 udelay(1);
2170         }
2171
2172         if (i >= usec_timeout) {
2173                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2174                 return -EINVAL;
2175         }
2176
2177         /* Program me ucode address into intruction cache address register */
2178         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2179                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2180         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2181                         lower_32_bits(addr) & 0xFFFFF000);
2182         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2183                         upper_32_bits(addr));
2184
2185         return 0;
2186 }
2187
2188 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2189 {
2190         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2191         uint32_t tmp;
2192         int i;
2193         uint64_t addr;
2194
2195         /* Trigger an invalidation of the L1 instruction caches */
2196         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2197         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2198         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2199
2200         /* Wait for invalidation complete */
2201         for (i = 0; i < usec_timeout; i++) {
2202                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2203                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2204                         INVALIDATE_CACHE_COMPLETE))
2205                         break;
2206                 udelay(1);
2207         }
2208
2209         if (i >= usec_timeout) {
2210                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2211                 return -EINVAL;
2212         }
2213
2214         /* Program ce ucode address into intruction cache address register */
2215         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2216                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2217         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2218                         lower_32_bits(addr) & 0xFFFFF000);
2219         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2220                         upper_32_bits(addr));
2221
2222         return 0;
2223 }
2224
2225 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2226 {
2227         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2228         uint32_t tmp;
2229         int i;
2230         uint64_t addr;
2231
2232         /* Trigger an invalidation of the L1 instruction caches */
2233         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2234         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2235         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2236
2237         /* Wait for invalidation complete */
2238         for (i = 0; i < usec_timeout; i++) {
2239                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2240                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2241                         INVALIDATE_CACHE_COMPLETE))
2242                         break;
2243                 udelay(1);
2244         }
2245
2246         if (i >= usec_timeout) {
2247                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2248                 return -EINVAL;
2249         }
2250
2251         /* Program pfp ucode address into intruction cache address register */
2252         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2253                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2254         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2255                         lower_32_bits(addr) & 0xFFFFF000);
2256         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2257                         upper_32_bits(addr));
2258
2259         return 0;
2260 }
2261
2262 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2263 {
2264         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2265         uint32_t tmp;
2266         int i;
2267         uint64_t addr;
2268
2269         /* Trigger an invalidation of the L1 instruction caches */
2270         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2271         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2272         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2273
2274         /* Wait for invalidation complete */
2275         for (i = 0; i < usec_timeout; i++) {
2276                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2277                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2278                         INVALIDATE_CACHE_COMPLETE))
2279                         break;
2280                 udelay(1);
2281         }
2282
2283         if (i >= usec_timeout) {
2284                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2285                 return -EINVAL;
2286         }
2287
2288         /* Program mec1 ucode address into intruction cache address register */
2289         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2290                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2291         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2292                         lower_32_bits(addr) & 0xFFFFF000);
2293         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2294                         upper_32_bits(addr));
2295
2296         return 0;
2297 }
2298
2299 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2300 {
2301         uint32_t cp_status;
2302         uint32_t bootload_status;
2303         int i, r;
2304
2305         for (i = 0; i < adev->usec_timeout; i++) {
2306                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2307                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2308                 if ((cp_status == 0) &&
2309                     (REG_GET_FIELD(bootload_status,
2310                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2311                         break;
2312                 }
2313                 udelay(1);
2314         }
2315
2316         if (i >= adev->usec_timeout) {
2317                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2318                 return -ETIMEDOUT;
2319         }
2320
2321         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2322                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2323                 if (r)
2324                         return r;
2325
2326                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2327                 if (r)
2328                         return r;
2329
2330                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2331                 if (r)
2332                         return r;
2333
2334                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2335                 if (r)
2336                         return r;
2337         }
2338
2339         return 0;
2340 }
2341
2342 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2343 {
2344         int i;
2345         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2346
2347         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2348         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2349         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2350         if (!enable) {
2351                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2352                         adev->gfx.gfx_ring[i].sched.ready = false;
2353         }
2354         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2355         udelay(50);
2356 }
2357
2358 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2359 {
2360         int r;
2361         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2362         const __le32 *fw_data;
2363         unsigned i, fw_size;
2364         uint32_t tmp;
2365         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2366
2367         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2368                 adev->gfx.pfp_fw->data;
2369
2370         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2371
2372         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2373                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2374         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2375
2376         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2377                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2378                                       &adev->gfx.pfp.pfp_fw_obj,
2379                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2380                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2381         if (r) {
2382                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2383                 gfx_v10_0_pfp_fini(adev);
2384                 return r;
2385         }
2386
2387         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2388
2389         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2390         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2391
2392         /* Trigger an invalidation of the L1 instruction caches */
2393         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2394         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2395         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2396
2397         /* Wait for invalidation complete */
2398         for (i = 0; i < usec_timeout; i++) {
2399                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2400                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2401                         INVALIDATE_CACHE_COMPLETE))
2402                         break;
2403                 udelay(1);
2404         }
2405
2406         if (i >= usec_timeout) {
2407                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2408                 return -EINVAL;
2409         }
2410
2411         if (amdgpu_emu_mode == 1)
2412                 adev->nbio_funcs->hdp_flush(adev, NULL);
2413
2414         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2415         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2416         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2417         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2418         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2419         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2420         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2421                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2422         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2423                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2424
2425         return 0;
2426 }
2427
2428 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2429 {
2430         int r;
2431         const struct gfx_firmware_header_v1_0 *ce_hdr;
2432         const __le32 *fw_data;
2433         unsigned i, fw_size;
2434         uint32_t tmp;
2435         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2436
2437         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2438                 adev->gfx.ce_fw->data;
2439
2440         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2441
2442         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2443                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2444         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2445
2446         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2447                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2448                                       &adev->gfx.ce.ce_fw_obj,
2449                                       &adev->gfx.ce.ce_fw_gpu_addr,
2450                                       (void **)&adev->gfx.ce.ce_fw_ptr);
2451         if (r) {
2452                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2453                 gfx_v10_0_ce_fini(adev);
2454                 return r;
2455         }
2456
2457         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2458
2459         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2460         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2461
2462         /* Trigger an invalidation of the L1 instruction caches */
2463         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2464         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2465         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2466
2467         /* Wait for invalidation complete */
2468         for (i = 0; i < usec_timeout; i++) {
2469                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2470                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2471                         INVALIDATE_CACHE_COMPLETE))
2472                         break;
2473                 udelay(1);
2474         }
2475
2476         if (i >= usec_timeout) {
2477                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2478                 return -EINVAL;
2479         }
2480
2481         if (amdgpu_emu_mode == 1)
2482                 adev->nbio_funcs->hdp_flush(adev, NULL);
2483
2484         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2485         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2486         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2487         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2488         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2489         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2490                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2491         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2492                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2493
2494         return 0;
2495 }
2496
2497 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2498 {
2499         int r;
2500         const struct gfx_firmware_header_v1_0 *me_hdr;
2501         const __le32 *fw_data;
2502         unsigned i, fw_size;
2503         uint32_t tmp;
2504         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2505
2506         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2507                 adev->gfx.me_fw->data;
2508
2509         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2510
2511         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2512                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2513         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2514
2515         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2516                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2517                                       &adev->gfx.me.me_fw_obj,
2518                                       &adev->gfx.me.me_fw_gpu_addr,
2519                                       (void **)&adev->gfx.me.me_fw_ptr);
2520         if (r) {
2521                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2522                 gfx_v10_0_me_fini(adev);
2523                 return r;
2524         }
2525
2526         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2527
2528         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2529         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2530
2531         /* Trigger an invalidation of the L1 instruction caches */
2532         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2533         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2534         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2535
2536         /* Wait for invalidation complete */
2537         for (i = 0; i < usec_timeout; i++) {
2538                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2539                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2540                         INVALIDATE_CACHE_COMPLETE))
2541                         break;
2542                 udelay(1);
2543         }
2544
2545         if (i >= usec_timeout) {
2546                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2547                 return -EINVAL;
2548         }
2549
2550         if (amdgpu_emu_mode == 1)
2551                 adev->nbio_funcs->hdp_flush(adev, NULL);
2552
2553         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2554         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2555         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2556         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2557         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2558         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2559                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2560         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2561                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2562
2563         return 0;
2564 }
2565
2566 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2567 {
2568         int r;
2569
2570         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2571                 return -EINVAL;
2572
2573         gfx_v10_0_cp_gfx_enable(adev, false);
2574
2575         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2576         if (r) {
2577                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2578                 return r;
2579         }
2580
2581         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2582         if (r) {
2583                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2584                 return r;
2585         }
2586
2587         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2588         if (r) {
2589                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2590                 return r;
2591         }
2592
2593         return 0;
2594 }
2595
2596 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2597 {
2598         struct amdgpu_ring *ring;
2599         const struct cs_section_def *sect = NULL;
2600         const struct cs_extent_def *ext = NULL;
2601         int r, i;
2602         int ctx_reg_offset;
2603
2604         /* init the CP */
2605         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2606                      adev->gfx.config.max_hw_contexts - 1);
2607         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2608
2609         gfx_v10_0_cp_gfx_enable(adev, true);
2610
2611         ring = &adev->gfx.gfx_ring[0];
2612         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2613         if (r) {
2614                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2615                 return r;
2616         }
2617
2618         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2619         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2620
2621         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2622         amdgpu_ring_write(ring, 0x80000000);
2623         amdgpu_ring_write(ring, 0x80000000);
2624
2625         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2626                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2627                         if (sect->id == SECT_CONTEXT) {
2628                                 amdgpu_ring_write(ring,
2629                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
2630                                                           ext->reg_count));
2631                                 amdgpu_ring_write(ring, ext->reg_index -
2632                                                   PACKET3_SET_CONTEXT_REG_START);
2633                                 for (i = 0; i < ext->reg_count; i++)
2634                                         amdgpu_ring_write(ring, ext->extent[i]);
2635                         }
2636                 }
2637         }
2638
2639         ctx_reg_offset =
2640                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2641         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2642         amdgpu_ring_write(ring, ctx_reg_offset);
2643         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2644
2645         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2646         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2647
2648         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2649         amdgpu_ring_write(ring, 0);
2650
2651         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2652         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2653         amdgpu_ring_write(ring, 0x8000);
2654         amdgpu_ring_write(ring, 0x8000);
2655
2656         amdgpu_ring_commit(ring);
2657
2658         /* submit cs packet to copy state 0 to next available state */
2659         ring = &adev->gfx.gfx_ring[1];
2660         r = amdgpu_ring_alloc(ring, 2);
2661         if (r) {
2662                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2663                 return r;
2664         }
2665
2666         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2667         amdgpu_ring_write(ring, 0);
2668
2669         amdgpu_ring_commit(ring);
2670
2671         return 0;
2672 }
2673
2674 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2675                                          CP_PIPE_ID pipe)
2676 {
2677         u32 tmp;
2678
2679         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2680         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2681
2682         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2683 }
2684
2685 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2686                                           struct amdgpu_ring *ring)
2687 {
2688         u32 tmp;
2689
2690         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2691         if (ring->use_doorbell) {
2692                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2693                                     DOORBELL_OFFSET, ring->doorbell_index);
2694                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2695                                     DOORBELL_EN, 1);
2696         } else {
2697                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2698                                     DOORBELL_EN, 0);
2699         }
2700         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2701         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2702                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
2703         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2704
2705         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2706                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2707 }
2708
2709 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2710 {
2711         struct amdgpu_ring *ring;
2712         u32 tmp;
2713         u32 rb_bufsz;
2714         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2715         u32 i;
2716
2717         /* Set the write pointer delay */
2718         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2719
2720         /* set the RB to use vmid 0 */
2721         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2722
2723         /* Init gfx ring 0 for pipe 0 */
2724         mutex_lock(&adev->srbm_mutex);
2725         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2726         mutex_unlock(&adev->srbm_mutex);
2727         /* Set ring buffer size */
2728         ring = &adev->gfx.gfx_ring[0];
2729         rb_bufsz = order_base_2(ring->ring_size / 8);
2730         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2731         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2732 #ifdef __BIG_ENDIAN
2733         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2734 #endif
2735         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2736
2737         /* Initialize the ring buffer's write pointers */
2738         ring->wptr = 0;
2739         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2740         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2741
2742         /* set the wb address wether it's enabled or not */
2743         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2744         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2745         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2746                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2747
2748         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2749         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2750                      lower_32_bits(wptr_gpu_addr));
2751         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2752                      upper_32_bits(wptr_gpu_addr));
2753
2754         mdelay(1);
2755         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2756
2757         rb_addr = ring->gpu_addr >> 8;
2758         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2759         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2760
2761         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2762
2763         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2764
2765         /* Init gfx ring 1 for pipe 1 */
2766         mutex_lock(&adev->srbm_mutex);
2767         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2768         mutex_unlock(&adev->srbm_mutex);
2769         ring = &adev->gfx.gfx_ring[1];
2770         rb_bufsz = order_base_2(ring->ring_size / 8);
2771         tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2772         tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2773         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2774         /* Initialize the ring buffer's write pointers */
2775         ring->wptr = 0;
2776         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2777         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2778         /* Set the wb address wether it's enabled or not */
2779         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2780         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2781         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2782                 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2783         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2784         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2785                 lower_32_bits(wptr_gpu_addr));
2786         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2787                 upper_32_bits(wptr_gpu_addr));
2788
2789         mdelay(1);
2790         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2791
2792         rb_addr = ring->gpu_addr >> 8;
2793         WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2794         WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2795         WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2796
2797         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2798
2799         /* Switch to pipe 0 */
2800         mutex_lock(&adev->srbm_mutex);
2801         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2802         mutex_unlock(&adev->srbm_mutex);
2803
2804         /* start the ring */
2805         gfx_v10_0_cp_gfx_start(adev);
2806
2807         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2808                 ring = &adev->gfx.gfx_ring[i];
2809                 ring->sched.ready = true;
2810         }
2811
2812         return 0;
2813 }
2814
2815 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2816 {
2817         int i;
2818
2819         if (enable) {
2820                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2821         } else {
2822                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2823                              (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2824                               CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2825                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2826                         adev->gfx.compute_ring[i].sched.ready = false;
2827                 adev->gfx.kiq.ring.sched.ready = false;
2828         }
2829         udelay(50);
2830 }
2831
2832 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2833 {
2834         const struct gfx_firmware_header_v1_0 *mec_hdr;
2835         const __le32 *fw_data;
2836         unsigned i;
2837         u32 tmp;
2838         u32 usec_timeout = 50000; /* Wait for 50 ms */
2839
2840         if (!adev->gfx.mec_fw)
2841                 return -EINVAL;
2842
2843         gfx_v10_0_cp_compute_enable(adev, false);
2844
2845         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2846         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2847
2848         fw_data = (const __le32 *)
2849                 (adev->gfx.mec_fw->data +
2850                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2851
2852         /* Trigger an invalidation of the L1 instruction caches */
2853         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2854         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2855         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2856
2857         /* Wait for invalidation complete */
2858         for (i = 0; i < usec_timeout; i++) {
2859                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2860                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2861                                        INVALIDATE_CACHE_COMPLETE))
2862                         break;
2863                 udelay(1);
2864         }
2865
2866         if (i >= usec_timeout) {
2867                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2868                 return -EINVAL;
2869         }
2870
2871         if (amdgpu_emu_mode == 1)
2872                 adev->nbio_funcs->hdp_flush(adev, NULL);
2873
2874         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2875         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2876         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2877         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2878         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2879
2880         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2881                      0xFFFFF000);
2882         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2883                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2884
2885         /* MEC1 */
2886         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2887
2888         for (i = 0; i < mec_hdr->jt_size; i++)
2889                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2890                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2891
2892         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2893
2894         /*
2895          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2896          * different microcode than MEC1.
2897          */
2898
2899         return 0;
2900 }
2901
2902 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2903 {
2904         uint32_t tmp;
2905         struct amdgpu_device *adev = ring->adev;
2906
2907         /* tell RLC which is KIQ queue */
2908         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2909         tmp &= 0xffffff00;
2910         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2911         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2912         tmp |= 0x80;
2913         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2914 }
2915
2916 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2917 {
2918         struct amdgpu_device *adev = ring->adev;
2919         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2920         uint64_t hqd_gpu_addr, wb_gpu_addr;
2921         uint32_t tmp;
2922         uint32_t rb_bufsz;
2923
2924         /* set up gfx hqd wptr */
2925         mqd->cp_gfx_hqd_wptr = 0;
2926         mqd->cp_gfx_hqd_wptr_hi = 0;
2927
2928         /* set the pointer to the MQD */
2929         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2930         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2931
2932         /* set up mqd control */
2933         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2934         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2935         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2936         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2937         mqd->cp_gfx_mqd_control = tmp;
2938
2939         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2940         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
2941         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2942         mqd->cp_gfx_hqd_vmid = 0;
2943
2944         /* set up default queue priority level
2945          * 0x0 = low priority, 0x1 = high priority */
2946         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
2947         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2948         mqd->cp_gfx_hqd_queue_priority = tmp;
2949
2950         /* set up time quantum */
2951         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
2952         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
2953         mqd->cp_gfx_hqd_quantum = tmp;
2954
2955         /* set up gfx hqd base. this is similar as CP_RB_BASE */
2956         hqd_gpu_addr = ring->gpu_addr >> 8;
2957         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
2958         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
2959
2960         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
2961         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2962         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
2963         mqd->cp_gfx_hqd_rptr_addr_hi =
2964                 upper_32_bits(wb_gpu_addr) & 0xffff;
2965
2966         /* set up rb_wptr_poll addr */
2967         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2968         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2969         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2970
2971         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
2972         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
2973         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
2974         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
2975         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
2976 #ifdef __BIG_ENDIAN
2977         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
2978 #endif
2979         mqd->cp_gfx_hqd_cntl = tmp;
2980
2981         /* set up cp_doorbell_control */
2982         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2983         if (ring->use_doorbell) {
2984                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2985                                     DOORBELL_OFFSET, ring->doorbell_index);
2986                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2987                                     DOORBELL_EN, 1);
2988         } else
2989                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2990                                     DOORBELL_EN, 0);
2991         mqd->cp_rb_doorbell_control = tmp;
2992
2993         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2994         ring->wptr = 0;
2995         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
2996
2997         /* active the queue */
2998         mqd->cp_gfx_hqd_active = 1;
2999
3000         return 0;
3001 }
3002
3003 #ifdef BRING_UP_DEBUG
3004 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3005 {
3006         struct amdgpu_device *adev = ring->adev;
3007         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3008
3009         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3010         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3011         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3012
3013         /* set GFX_MQD_BASE */
3014         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3015         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3016
3017         /* set GFX_MQD_CONTROL */
3018         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3019
3020         /* set GFX_HQD_VMID to 0 */
3021         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3022
3023         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3024                         mqd->cp_gfx_hqd_queue_priority);
3025         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3026
3027         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
3028         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3029         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3030
3031         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3032         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3033         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3034
3035         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3036         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3037
3038         /* set RB_WPTR_POLL_ADDR */
3039         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3040         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3041
3042         /* set RB_DOORBELL_CONTROL */
3043         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3044
3045         /* active the queue */
3046         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3047
3048         return 0;
3049 }
3050 #endif
3051
3052 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3053 {
3054         struct amdgpu_device *adev = ring->adev;
3055         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3056
3057         if (!adev->in_gpu_reset && !adev->in_suspend) {
3058                 memset((void *)mqd, 0, sizeof(*mqd));
3059                 mutex_lock(&adev->srbm_mutex);
3060                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3061                 gfx_v10_0_gfx_mqd_init(ring);
3062 #ifdef BRING_UP_DEBUG
3063                 gfx_v10_0_gfx_queue_init_register(ring);
3064 #endif
3065                 nv_grbm_select(adev, 0, 0, 0, 0);
3066                 mutex_unlock(&adev->srbm_mutex);
3067                 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3068                         memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd));
3069         } else if (adev->in_gpu_reset) {
3070                 /* reset mqd with the backup copy */
3071                 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
3072                         memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
3073                 /* reset the ring */
3074                 ring->wptr = 0;
3075                 amdgpu_ring_clear_ring(ring);
3076 #ifdef BRING_UP_DEBUG
3077                 mutex_lock(&adev->srbm_mutex);
3078                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3079                 gfx_v10_0_gfx_queue_init_register(ring);
3080                 nv_grbm_select(adev, 0, 0, 0, 0);
3081                 mutex_unlock(&adev->srbm_mutex);
3082 #endif
3083         } else {
3084                 amdgpu_ring_clear_ring(ring);
3085         }
3086
3087         return 0;
3088 }
3089
3090 #ifndef BRING_UP_DEBUG
3091 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3092 {
3093         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3094         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3095         int r, i;
3096
3097         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3098                 return -EINVAL;
3099
3100         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3101                                         adev->gfx.num_gfx_rings);
3102         if (r) {
3103                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3104                 return r;
3105         }
3106
3107         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3108                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3109
3110         r = amdgpu_ring_test_ring(kiq_ring);
3111         if (r) {
3112                 DRM_ERROR("kfq enable failed\n");
3113                 kiq_ring->sched.ready = false;
3114         }
3115         return r;
3116 }
3117 #endif
3118
3119 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3120 {
3121         int r, i;
3122         struct amdgpu_ring *ring;
3123
3124         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3125                 ring = &adev->gfx.gfx_ring[i];
3126
3127                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3128                 if (unlikely(r != 0))
3129                         goto done;
3130
3131                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3132                 if (!r) {
3133                         r = gfx_v10_0_gfx_init_queue(ring);
3134                         amdgpu_bo_kunmap(ring->mqd_obj);
3135                         ring->mqd_ptr = NULL;
3136                 }
3137                 amdgpu_bo_unreserve(ring->mqd_obj);
3138                 if (r)
3139                         goto done;
3140         }
3141 #ifndef BRING_UP_DEBUG
3142         r = gfx_v10_0_kiq_enable_kgq(adev);
3143         if (r)
3144                 goto done;
3145 #endif
3146         r = gfx_v10_0_cp_gfx_start(adev);
3147         if (r)
3148                 goto done;
3149
3150         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3151                 ring = &adev->gfx.gfx_ring[i];
3152                 ring->sched.ready = true;
3153         }
3154 done:
3155         return r;
3156 }
3157
3158 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3159 {
3160         struct amdgpu_device *adev = ring->adev;
3161         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3162         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3163         uint32_t tmp;
3164
3165         mqd->header = 0xC0310800;
3166         mqd->compute_pipelinestat_enable = 0x00000001;
3167         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3168         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3169         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3170         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3171         mqd->compute_misc_reserved = 0x00000003;
3172
3173         eop_base_addr = ring->eop_gpu_addr >> 8;
3174         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3175         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3176
3177         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3178         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3179         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3180                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3181
3182         mqd->cp_hqd_eop_control = tmp;
3183
3184         /* enable doorbell? */
3185         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3186
3187         if (ring->use_doorbell) {
3188                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3189                                     DOORBELL_OFFSET, ring->doorbell_index);
3190                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3191                                     DOORBELL_EN, 1);
3192                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3193                                     DOORBELL_SOURCE, 0);
3194                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3195                                     DOORBELL_HIT, 0);
3196         } else {
3197                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3198                                     DOORBELL_EN, 0);
3199         }
3200
3201         mqd->cp_hqd_pq_doorbell_control = tmp;
3202
3203         /* disable the queue if it's active */
3204         ring->wptr = 0;
3205         mqd->cp_hqd_dequeue_request = 0;
3206         mqd->cp_hqd_pq_rptr = 0;
3207         mqd->cp_hqd_pq_wptr_lo = 0;
3208         mqd->cp_hqd_pq_wptr_hi = 0;
3209
3210         /* set the pointer to the MQD */
3211         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3212         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3213
3214         /* set MQD vmid to 0 */
3215         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3216         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3217         mqd->cp_mqd_control = tmp;
3218
3219         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3220         hqd_gpu_addr = ring->gpu_addr >> 8;
3221         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3222         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3223
3224         /* set up the HQD, this is similar to CP_RB0_CNTL */
3225         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3226         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3227                             (order_base_2(ring->ring_size / 4) - 1));
3228         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3229                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3230 #ifdef __BIG_ENDIAN
3231         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3232 #endif
3233         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3234         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3235         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3236         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3237         mqd->cp_hqd_pq_control = tmp;
3238
3239         /* set the wb address whether it's enabled or not */
3240         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3241         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3242         mqd->cp_hqd_pq_rptr_report_addr_hi =
3243                 upper_32_bits(wb_gpu_addr) & 0xffff;
3244
3245         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3246         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3247         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3248         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3249
3250         tmp = 0;
3251         /* enable the doorbell if requested */
3252         if (ring->use_doorbell) {
3253                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3254                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3255                                 DOORBELL_OFFSET, ring->doorbell_index);
3256
3257                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3258                                     DOORBELL_EN, 1);
3259                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3260                                     DOORBELL_SOURCE, 0);
3261                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3262                                     DOORBELL_HIT, 0);
3263         }
3264
3265         mqd->cp_hqd_pq_doorbell_control = tmp;
3266
3267         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3268         ring->wptr = 0;
3269         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3270
3271         /* set the vmid for the queue */
3272         mqd->cp_hqd_vmid = 0;
3273
3274         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3275         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3276         mqd->cp_hqd_persistent_state = tmp;
3277
3278         /* set MIN_IB_AVAIL_SIZE */
3279         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3280         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3281         mqd->cp_hqd_ib_control = tmp;
3282
3283         /* activate the queue */
3284         mqd->cp_hqd_active = 1;
3285
3286         return 0;
3287 }
3288
3289 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3290 {
3291         struct amdgpu_device *adev = ring->adev;
3292         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3293         int j;
3294
3295         /* disable wptr polling */
3296         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3297
3298         /* write the EOP addr */
3299         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3300                mqd->cp_hqd_eop_base_addr_lo);
3301         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3302                mqd->cp_hqd_eop_base_addr_hi);
3303
3304         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3305         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3306                mqd->cp_hqd_eop_control);
3307
3308         /* enable doorbell? */
3309         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3310                mqd->cp_hqd_pq_doorbell_control);
3311
3312         /* disable the queue if it's active */
3313         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3314                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3315                 for (j = 0; j < adev->usec_timeout; j++) {
3316                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3317                                 break;
3318                         udelay(1);
3319                 }
3320                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3321                        mqd->cp_hqd_dequeue_request);
3322                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3323                        mqd->cp_hqd_pq_rptr);
3324                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3325                        mqd->cp_hqd_pq_wptr_lo);
3326                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3327                        mqd->cp_hqd_pq_wptr_hi);
3328         }
3329
3330         /* set the pointer to the MQD */
3331         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3332                mqd->cp_mqd_base_addr_lo);
3333         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3334                mqd->cp_mqd_base_addr_hi);
3335
3336         /* set MQD vmid to 0 */
3337         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3338                mqd->cp_mqd_control);
3339
3340         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3341         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3342                mqd->cp_hqd_pq_base_lo);
3343         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3344                mqd->cp_hqd_pq_base_hi);
3345
3346         /* set up the HQD, this is similar to CP_RB0_CNTL */
3347         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3348                mqd->cp_hqd_pq_control);
3349
3350         /* set the wb address whether it's enabled or not */
3351         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3352                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3353         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3354                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3355
3356         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3357         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3358                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3359         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3360                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3361
3362         /* enable the doorbell if requested */
3363         if (ring->use_doorbell) {
3364                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3365                         (adev->doorbell_index.kiq * 2) << 2);
3366                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3367                         (adev->doorbell_index.userqueue_end * 2) << 2);
3368         }
3369
3370         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3371                mqd->cp_hqd_pq_doorbell_control);
3372
3373         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3374         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3375                mqd->cp_hqd_pq_wptr_lo);
3376         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3377                mqd->cp_hqd_pq_wptr_hi);
3378
3379         /* set the vmid for the queue */
3380         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3381
3382         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3383                mqd->cp_hqd_persistent_state);
3384
3385         /* activate the queue */
3386         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3387                mqd->cp_hqd_active);
3388
3389         if (ring->use_doorbell)
3390                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3391
3392         return 0;
3393 }
3394
3395 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3396 {
3397         struct amdgpu_device *adev = ring->adev;
3398         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3399         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3400
3401         gfx_v10_0_kiq_setting(ring);
3402
3403         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3404                 /* reset MQD to a clean status */
3405                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3406                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3407
3408                 /* reset ring buffer */
3409                 ring->wptr = 0;
3410                 amdgpu_ring_clear_ring(ring);
3411
3412                 mutex_lock(&adev->srbm_mutex);
3413                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3414                 gfx_v10_0_kiq_init_register(ring);
3415                 nv_grbm_select(adev, 0, 0, 0, 0);
3416                 mutex_unlock(&adev->srbm_mutex);
3417         } else {
3418                 memset((void *)mqd, 0, sizeof(*mqd));
3419                 mutex_lock(&adev->srbm_mutex);
3420                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3421                 gfx_v10_0_compute_mqd_init(ring);
3422                 gfx_v10_0_kiq_init_register(ring);
3423                 nv_grbm_select(adev, 0, 0, 0, 0);
3424                 mutex_unlock(&adev->srbm_mutex);
3425
3426                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3427                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3428         }
3429
3430         return 0;
3431 }
3432
3433 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3434 {
3435         struct amdgpu_device *adev = ring->adev;
3436         struct v10_compute_mqd *mqd = ring->mqd_ptr;
3437         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3438
3439         if (!adev->in_gpu_reset && !adev->in_suspend) {
3440                 memset((void *)mqd, 0, sizeof(*mqd));
3441                 mutex_lock(&adev->srbm_mutex);
3442                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3443                 gfx_v10_0_compute_mqd_init(ring);
3444                 nv_grbm_select(adev, 0, 0, 0, 0);
3445                 mutex_unlock(&adev->srbm_mutex);
3446
3447                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3448                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3449         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3450                 /* reset MQD to a clean status */
3451                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3452                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3453
3454                 /* reset ring buffer */
3455                 ring->wptr = 0;
3456                 amdgpu_ring_clear_ring(ring);
3457         } else {
3458                 amdgpu_ring_clear_ring(ring);
3459         }
3460
3461         return 0;
3462 }
3463
3464 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3465 {
3466         struct amdgpu_ring *ring;
3467         int r;
3468
3469         ring = &adev->gfx.kiq.ring;
3470
3471         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3472         if (unlikely(r != 0))
3473                 return r;
3474
3475         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3476         if (unlikely(r != 0))
3477                 return r;
3478
3479         gfx_v10_0_kiq_init_queue(ring);
3480         amdgpu_bo_kunmap(ring->mqd_obj);
3481         ring->mqd_ptr = NULL;
3482         amdgpu_bo_unreserve(ring->mqd_obj);
3483         ring->sched.ready = true;
3484         return 0;
3485 }
3486
3487 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3488 {
3489         struct amdgpu_ring *ring = NULL;
3490         int r = 0, i;
3491
3492         gfx_v10_0_cp_compute_enable(adev, true);
3493
3494         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3495                 ring = &adev->gfx.compute_ring[i];
3496
3497                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3498                 if (unlikely(r != 0))
3499                         goto done;
3500                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3501                 if (!r) {
3502                         r = gfx_v10_0_kcq_init_queue(ring);
3503                         amdgpu_bo_kunmap(ring->mqd_obj);
3504                         ring->mqd_ptr = NULL;
3505                 }
3506                 amdgpu_bo_unreserve(ring->mqd_obj);
3507                 if (r)
3508                         goto done;
3509         }
3510
3511         r = amdgpu_gfx_enable_kcq(adev);
3512 done:
3513         return r;
3514 }
3515
3516 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3517 {
3518         int r, i;
3519         struct amdgpu_ring *ring;
3520
3521         if (!(adev->flags & AMD_IS_APU))
3522                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3523
3524         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3525                 /* legacy firmware loading */
3526                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
3527                 if (r)
3528                         return r;
3529
3530                 r = gfx_v10_0_cp_compute_load_microcode(adev);
3531                 if (r)
3532                         return r;
3533         }
3534
3535         r = gfx_v10_0_kiq_resume(adev);
3536         if (r)
3537                 return r;
3538
3539         r = gfx_v10_0_kcq_resume(adev);
3540         if (r)
3541                 return r;
3542
3543         if (!amdgpu_async_gfx_ring) {
3544                 r = gfx_v10_0_cp_gfx_resume(adev);
3545                 if (r)
3546                         return r;
3547         } else {
3548                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3549                 if (r)
3550                         return r;
3551         }
3552
3553         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3554                 ring = &adev->gfx.gfx_ring[i];
3555                 DRM_INFO("gfx %d ring me %d pipe %d q %d\n",
3556                          i, ring->me, ring->pipe, ring->queue);
3557                 r = amdgpu_ring_test_ring(ring);
3558                 if (r) {
3559                         ring->sched.ready = false;
3560                         return r;
3561                 }
3562         }
3563
3564         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3565                 ring = &adev->gfx.compute_ring[i];
3566                 ring->sched.ready = true;
3567                 DRM_INFO("compute ring %d mec %d pipe %d q %d\n",
3568                          i, ring->me, ring->pipe, ring->queue);
3569                 r = amdgpu_ring_test_ring(ring);
3570                 if (r)
3571                         ring->sched.ready = false;
3572         }
3573
3574         return 0;
3575 }
3576
3577 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3578 {
3579         gfx_v10_0_cp_gfx_enable(adev, enable);
3580         gfx_v10_0_cp_compute_enable(adev, enable);
3581 }
3582
3583 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3584 {
3585         uint32_t data, pattern = 0xDEADBEEF;
3586
3587         /* check if mmVGT_ESGS_RING_SIZE_UMD
3588          * has been remapped to mmVGT_ESGS_RING_SIZE */
3589         data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3590
3591         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3592
3593         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3594
3595         if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3596                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3597                 return true;
3598         } else {
3599                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3600                 return false;
3601         }
3602 }
3603
3604 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3605 {
3606         uint32_t data;
3607
3608         /* initialize cam_index to 0
3609          * index will auto-inc after each data writting */
3610         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3611
3612         /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
3613         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3614                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3615                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3616                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3617         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3618         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3619
3620         /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
3621         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3622                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3623                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3624                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3625         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3626         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3627
3628         /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
3629         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3630                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3631                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3632                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3633         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3634         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3635
3636         /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
3637         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3638                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3639                (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3640                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3641         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3642         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3643
3644         /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
3645         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3646                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3647                (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3648                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3649         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3650         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3651
3652         /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
3653         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3654                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3655                (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3656                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3657         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3658         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3659
3660         /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3661         data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3662                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3663                (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3664                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3665         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3666         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3667 }
3668
3669 static int gfx_v10_0_hw_init(void *handle)
3670 {
3671         int r;
3672         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3673
3674         r = gfx_v10_0_csb_vram_pin(adev);
3675         if (r)
3676                 return r;
3677
3678         if (!amdgpu_emu_mode)
3679                 gfx_v10_0_init_golden_registers(adev);
3680
3681         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3682                 /**
3683                  * For gfx 10, rlc firmware loading relies on smu firmware is
3684                  * loaded firstly, so in direct type, it has to load smc ucode
3685                  * here before rlc.
3686                  */
3687                 r = smu_load_microcode(&adev->smu);
3688                 if (r)
3689                         return r;
3690
3691                 r = smu_check_fw_status(&adev->smu);
3692                 if (r) {
3693                         pr_err("SMC firmware status is not correct\n");
3694                         return r;
3695                 }
3696         }
3697
3698         /* if GRBM CAM not remapped, set up the remapping */
3699         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3700                 gfx_v10_0_setup_grbm_cam_remapping(adev);
3701
3702         gfx_v10_0_constants_init(adev);
3703
3704         r = gfx_v10_0_rlc_resume(adev);
3705         if (r)
3706                 return r;
3707
3708         /*
3709          * init golden registers and rlc resume may override some registers,
3710          * reconfig them here
3711          */
3712         gfx_v10_0_tcp_harvest(adev);
3713
3714         r = gfx_v10_0_cp_resume(adev);
3715         if (r)
3716                 return r;
3717
3718         return r;
3719 }
3720
3721 #ifndef BRING_UP_DEBUG
3722 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3723 {
3724         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3725         struct amdgpu_ring *kiq_ring = &kiq->ring;
3726         int i;
3727
3728         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3729                 return -EINVAL;
3730
3731         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3732                                         adev->gfx.num_gfx_rings))
3733                 return -ENOMEM;
3734
3735         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3736                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3737                                            PREEMPT_QUEUES, 0, 0);
3738
3739         return amdgpu_ring_test_ring(kiq_ring);
3740 }
3741 #endif
3742
3743 static int gfx_v10_0_hw_fini(void *handle)
3744 {
3745         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3746         int r;
3747
3748         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3749         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3750 #ifndef BRING_UP_DEBUG
3751         if (amdgpu_async_gfx_ring) {
3752                 r = gfx_v10_0_kiq_disable_kgq(adev);
3753                 if (r)
3754                         DRM_ERROR("KGQ disable failed\n");
3755         }
3756 #endif
3757         if (amdgpu_gfx_disable_kcq(adev))
3758                 DRM_ERROR("KCQ disable failed\n");
3759         if (amdgpu_sriov_vf(adev)) {
3760                 pr_debug("For SRIOV client, shouldn't do anything.\n");
3761                 return 0;
3762         }
3763         gfx_v10_0_cp_enable(adev, false);
3764         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3765         gfx_v10_0_csb_vram_unpin(adev);
3766
3767         return 0;
3768 }
3769
3770 static int gfx_v10_0_suspend(void *handle)
3771 {
3772         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3773
3774         adev->in_suspend = true;
3775         return gfx_v10_0_hw_fini(adev);
3776 }
3777
3778 static int gfx_v10_0_resume(void *handle)
3779 {
3780         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3781         int r;
3782
3783         r = gfx_v10_0_hw_init(adev);
3784         adev->in_suspend = false;
3785         return r;
3786 }
3787
3788 static bool gfx_v10_0_is_idle(void *handle)
3789 {
3790         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3791
3792         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3793                                 GRBM_STATUS, GUI_ACTIVE))
3794                 return false;
3795         else
3796                 return true;
3797 }
3798
3799 static int gfx_v10_0_wait_for_idle(void *handle)
3800 {
3801         unsigned i;
3802         u32 tmp;
3803         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3804
3805         for (i = 0; i < adev->usec_timeout; i++) {
3806                 /* read MC_STATUS */
3807                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3808                         GRBM_STATUS__GUI_ACTIVE_MASK;
3809
3810                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3811                         return 0;
3812                 udelay(1);
3813         }
3814         return -ETIMEDOUT;
3815 }
3816
3817 static int gfx_v10_0_soft_reset(void *handle)
3818 {
3819         u32 grbm_soft_reset = 0;
3820         u32 tmp;
3821         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3822
3823         /* GRBM_STATUS */
3824         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3825         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3826                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3827                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3828                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3829                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3830                    | GRBM_STATUS__BCI_BUSY_MASK)) {
3831                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3832                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3833                                                 1);
3834                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3835                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
3836                                                 1);
3837         }
3838
3839         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3840                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3841                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
3842                                                 1);
3843         }
3844
3845         /* GRBM_STATUS2 */
3846         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3847         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3848                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3849                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC,
3850                                                 1);
3851
3852         if (grbm_soft_reset) {
3853                 /* stop the rlc */
3854                 gfx_v10_0_rlc_stop(adev);
3855
3856                 /* Disable GFX parsing/prefetching */
3857                 gfx_v10_0_cp_gfx_enable(adev, false);
3858
3859                 /* Disable MEC parsing/prefetching */
3860                 gfx_v10_0_cp_compute_enable(adev, false);
3861
3862                 if (grbm_soft_reset) {
3863                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3864                         tmp |= grbm_soft_reset;
3865                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3866                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3867                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3868
3869                         udelay(50);
3870
3871                         tmp &= ~grbm_soft_reset;
3872                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3873                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3874                 }
3875
3876                 /* Wait a little for things to settle down */
3877                 udelay(50);
3878         }
3879         return 0;
3880 }
3881
3882 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3883 {
3884         uint64_t clock;
3885
3886         mutex_lock(&adev->gfx.gpu_clock_mutex);
3887         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3888         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3889                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3890         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3891         return clock;
3892 }
3893
3894 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3895                                            uint32_t vmid,
3896                                            uint32_t gds_base, uint32_t gds_size,
3897                                            uint32_t gws_base, uint32_t gws_size,
3898                                            uint32_t oa_base, uint32_t oa_size)
3899 {
3900         struct amdgpu_device *adev = ring->adev;
3901
3902         /* GDS Base */
3903         gfx_v10_0_write_data_to_reg(ring, 0, false,
3904                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3905                                     gds_base);
3906
3907         /* GDS Size */
3908         gfx_v10_0_write_data_to_reg(ring, 0, false,
3909                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3910                                     gds_size);
3911
3912         /* GWS */
3913         gfx_v10_0_write_data_to_reg(ring, 0, false,
3914                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3915                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3916
3917         /* OA */
3918         gfx_v10_0_write_data_to_reg(ring, 0, false,
3919                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3920                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
3921 }
3922
3923 static int gfx_v10_0_early_init(void *handle)
3924 {
3925         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3926
3927         adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;
3928         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3929
3930         gfx_v10_0_set_kiq_pm4_funcs(adev);
3931         gfx_v10_0_set_ring_funcs(adev);
3932         gfx_v10_0_set_irq_funcs(adev);
3933         gfx_v10_0_set_gds_init(adev);
3934         gfx_v10_0_set_rlc_funcs(adev);
3935
3936         return 0;
3937 }
3938
3939 static int gfx_v10_0_late_init(void *handle)
3940 {
3941         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3942         int r;
3943
3944         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3945         if (r)
3946                 return r;
3947
3948         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3949         if (r)
3950                 return r;
3951
3952         return 0;
3953 }
3954
3955 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
3956 {
3957         uint32_t rlc_cntl;
3958
3959         /* if RLC is not enabled, do nothing */
3960         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3961         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3962 }
3963
3964 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
3965 {
3966         uint32_t data;
3967         unsigned i;
3968
3969         data = RLC_SAFE_MODE__CMD_MASK;
3970         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3971         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3972
3973         /* wait for RLC_SAFE_MODE */
3974         for (i = 0; i < adev->usec_timeout; i++) {
3975                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3976                         break;
3977                 udelay(1);
3978         }
3979 }
3980
3981 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
3982 {
3983         uint32_t data;
3984
3985         data = RLC_SAFE_MODE__CMD_MASK;
3986         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3987 }
3988
3989 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3990                                                       bool enable)
3991 {
3992         uint32_t data, def;
3993
3994         /* It is disabled by HW by default */
3995         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3996                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3997                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3998                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3999                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4000                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4001
4002                 /* only for Vega10 & Raven1 */
4003                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4004
4005                 if (def != data)
4006                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4007
4008                 /* MGLS is a global flag to control all MGLS in GFX */
4009                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4010                         /* 2 - RLC memory Light sleep */
4011                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4012                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4013                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4014                                 if (def != data)
4015                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4016                         }
4017                         /* 3 - CP memory Light sleep */
4018                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4019                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4020                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4021                                 if (def != data)
4022                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4023                         }
4024                 }
4025         } else {
4026                 /* 1 - MGCG_OVERRIDE */
4027                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4028                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4029                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4030                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4031                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4032                 if (def != data)
4033                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4034
4035                 /* 2 - disable MGLS in RLC */
4036                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4037                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4038                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4039                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4040                 }
4041
4042                 /* 3 - disable MGLS in CP */
4043                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4044                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4045                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4046                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4047                 }
4048         }
4049 }
4050
4051 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4052                                            bool enable)
4053 {
4054         uint32_t data, def;
4055
4056         /* Enable 3D CGCG/CGLS */
4057         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4058                 /* write cmd to clear cgcg/cgls ov */
4059                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4060                 /* unset CGCG override */
4061                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4062                 /* update CGCG and CGLS override bits */
4063                 if (def != data)
4064                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4065                 /* enable 3Dcgcg FSM(0x0000363f) */
4066                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4067                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4068                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4069                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4070                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4071                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4072                 if (def != data)
4073                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4074
4075                 /* set IDLE_POLL_COUNT(0x00900100) */
4076                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4077                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4078                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4079                 if (def != data)
4080                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4081         } else {
4082                 /* Disable CGCG/CGLS */
4083                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4084                 /* disable cgcg, cgls should be disabled */
4085                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4086                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4087                 /* disable cgcg and cgls in FSM */
4088                 if (def != data)
4089                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4090         }
4091 }
4092
4093 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4094                                                       bool enable)
4095 {
4096         uint32_t def, data;
4097
4098         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4099                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4100                 /* unset CGCG override */
4101                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4102                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4103                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4104                 else
4105                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4106                 /* update CGCG and CGLS override bits */
4107                 if (def != data)
4108                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4109
4110                 /* enable cgcg FSM(0x0000363F) */
4111                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4112                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4113                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4114                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4115                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4116                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4117                 if (def != data)
4118                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4119
4120                 /* set IDLE_POLL_COUNT(0x00900100) */
4121                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4122                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4123                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4124                 if (def != data)
4125                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4126         } else {
4127                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4128                 /* reset CGCG/CGLS bits */
4129                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4130                 /* disable cgcg and cgls in FSM */
4131                 if (def != data)
4132                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4133         }
4134 }
4135
4136 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4137                                             bool enable)
4138 {
4139         amdgpu_gfx_rlc_enter_safe_mode(adev);
4140
4141         if (enable) {
4142                 /* CGCG/CGLS should be enabled after MGCG/MGLS
4143                  * ===  MGCG + MGLS ===
4144                  */
4145                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4146                 /* ===  CGCG /CGLS for GFX 3D Only === */
4147                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4148                 /* ===  CGCG + CGLS === */
4149                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4150         } else {
4151                 /* CGCG/CGLS should be disabled before MGCG/MGLS
4152                  * ===  CGCG + CGLS ===
4153                  */
4154                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4155                 /* ===  CGCG /CGLS for GFX 3D Only === */
4156                 gfx_v10_0_update_3d_clock_gating(adev, enable);
4157                 /* ===  MGCG + MGLS === */
4158                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4159         }
4160
4161         if (adev->cg_flags &
4162             (AMD_CG_SUPPORT_GFX_MGCG |
4163              AMD_CG_SUPPORT_GFX_CGLS |
4164              AMD_CG_SUPPORT_GFX_CGCG |
4165              AMD_CG_SUPPORT_GFX_CGLS |
4166              AMD_CG_SUPPORT_GFX_3D_CGCG |
4167              AMD_CG_SUPPORT_GFX_3D_CGLS))
4168                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4169
4170         amdgpu_gfx_rlc_exit_safe_mode(adev);
4171
4172         return 0;
4173 }
4174
4175 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4176         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4177         .set_safe_mode = gfx_v10_0_set_safe_mode,
4178         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
4179         .init = gfx_v10_0_rlc_init,
4180         .get_csb_size = gfx_v10_0_get_csb_size,
4181         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
4182         .resume = gfx_v10_0_rlc_resume,
4183         .stop = gfx_v10_0_rlc_stop,
4184         .reset = gfx_v10_0_rlc_reset,
4185         .start = gfx_v10_0_rlc_start
4186 };
4187
4188 static int gfx_v10_0_set_powergating_state(void *handle,
4189                                           enum amd_powergating_state state)
4190 {
4191         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4192         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
4193         switch (adev->asic_type) {
4194         case CHIP_NAVI10:
4195         case CHIP_NAVI14:
4196                 if (!enable) {
4197                         amdgpu_gfx_off_ctrl(adev, false);
4198                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4199                 } else
4200                         amdgpu_gfx_off_ctrl(adev, true);
4201                 break;
4202         default:
4203                 break;
4204         }
4205         return 0;
4206 }
4207
4208 static int gfx_v10_0_set_clockgating_state(void *handle,
4209                                           enum amd_clockgating_state state)
4210 {
4211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4212
4213         switch (adev->asic_type) {
4214         case CHIP_NAVI10:
4215         case CHIP_NAVI14:
4216         case CHIP_NAVI12:
4217                 gfx_v10_0_update_gfx_clock_gating(adev,
4218                                                  state == AMD_CG_STATE_GATE ? true : false);
4219                 break;
4220         default:
4221                 break;
4222         }
4223         return 0;
4224 }
4225
4226 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4227 {
4228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4229         int data;
4230
4231         /* AMD_CG_SUPPORT_GFX_MGCG */
4232         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4233         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4234                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4235
4236         /* AMD_CG_SUPPORT_GFX_CGCG */
4237         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4238         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4239                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4240
4241         /* AMD_CG_SUPPORT_GFX_CGLS */
4242         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4243                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4244
4245         /* AMD_CG_SUPPORT_GFX_RLC_LS */
4246         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4247         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4248                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4249
4250         /* AMD_CG_SUPPORT_GFX_CP_LS */
4251         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4252         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4253                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4254
4255         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4256         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4257         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4258                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4259
4260         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4261         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4262                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4263 }
4264
4265 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4266 {
4267         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
4268 }
4269
4270 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4271 {
4272         struct amdgpu_device *adev = ring->adev;
4273         u64 wptr;
4274
4275         /* XXX check if swapping is necessary on BE */
4276         if (ring->use_doorbell) {
4277                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4278         } else {
4279                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4280                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4281         }
4282
4283         return wptr;
4284 }
4285
4286 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4287 {
4288         struct amdgpu_device *adev = ring->adev;
4289
4290         if (ring->use_doorbell) {
4291                 /* XXX check if swapping is necessary on BE */
4292                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4293                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4294         } else {
4295                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4296                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4297         }
4298 }
4299
4300 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4301 {
4302         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
4303 }
4304
4305 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4306 {
4307         u64 wptr;
4308
4309         /* XXX check if swapping is necessary on BE */
4310         if (ring->use_doorbell)
4311                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4312         else
4313                 BUG();
4314         return wptr;
4315 }
4316
4317 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4318 {
4319         struct amdgpu_device *adev = ring->adev;
4320
4321         /* XXX check if swapping is necessary on BE */
4322         if (ring->use_doorbell) {
4323                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4324                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4325         } else {
4326                 BUG(); /* only DOORBELL method supported on gfx10 now */
4327         }
4328 }
4329
4330 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4331 {
4332         struct amdgpu_device *adev = ring->adev;
4333         u32 ref_and_mask, reg_mem_engine;
4334         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
4335
4336         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4337                 switch (ring->me) {
4338                 case 1:
4339                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4340                         break;
4341                 case 2:
4342                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4343                         break;
4344                 default:
4345                         return;
4346                 }
4347                 reg_mem_engine = 0;
4348         } else {
4349                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4350                 reg_mem_engine = 1; /* pfp */
4351         }
4352
4353         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4354                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
4355                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
4356                                ref_and_mask, ref_and_mask, 0x20);
4357 }
4358
4359 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4360                                        struct amdgpu_job *job,
4361                                        struct amdgpu_ib *ib,
4362                                        uint32_t flags)
4363 {
4364         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4365         u32 header, control = 0;
4366
4367         /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
4368          * This resets the wave ID counters. (needed by transform feedback)
4369          * TODO: This might only be needed on a VMID switch when we change
4370          *       the GDS OA mapping, not sure.
4371          */
4372         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4373         amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
4374         amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
4375
4376         if (ib->flags & AMDGPU_IB_FLAG_CE)
4377                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4378         else
4379                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4380
4381         control |= ib->length_dw | (vmid << 24);
4382
4383         if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4384                 control |= INDIRECT_BUFFER_PRE_ENB(1);
4385
4386                 if (flags & AMDGPU_IB_PREEMPTED)
4387                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
4388
4389                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4390                         gfx_v10_0_ring_emit_de_meta(ring,
4391                                     flags & AMDGPU_IB_PREEMPTED ? true : false);
4392         }
4393
4394         amdgpu_ring_write(ring, header);
4395         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4396         amdgpu_ring_write(ring,
4397 #ifdef __BIG_ENDIAN
4398                 (2 << 0) |
4399 #endif
4400                 lower_32_bits(ib->gpu_addr));
4401         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4402         amdgpu_ring_write(ring, control);
4403 }
4404
4405 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4406                                            struct amdgpu_job *job,
4407                                            struct amdgpu_ib *ib,
4408                                            uint32_t flags)
4409 {
4410         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4411         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4412
4413         /* Currently, there is a high possibility to get wave ID mismatch
4414          * between ME and GDS, leading to a hw deadlock, because ME generates
4415          * different wave IDs than the GDS expects. This situation happens
4416          * randomly when at least 5 compute pipes use GDS ordered append.
4417          * The wave IDs generated by ME are also wrong after suspend/resume.
4418          * Those are probably bugs somewhere else in the kernel driver.
4419          *
4420          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4421          * GDS to 0 for this ring (me/pipe).
4422          */
4423         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4424                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4425                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4426                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4427         }
4428
4429         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4430         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4431         amdgpu_ring_write(ring,
4432 #ifdef __BIG_ENDIAN
4433                                 (2 << 0) |
4434 #endif
4435                                 lower_32_bits(ib->gpu_addr));
4436         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4437         amdgpu_ring_write(ring, control);
4438 }
4439
4440 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4441                                      u64 seq, unsigned flags)
4442 {
4443         struct amdgpu_device *adev = ring->adev;
4444         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4445         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4446
4447         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
4448         if (adev->pdev->device == 0x50)
4449                 int_sel = false;
4450
4451         /* RELEASE_MEM - flush caches, send int */
4452         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4453         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4454                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
4455                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4456                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
4457                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4458                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4459                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4460         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4461                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4462
4463         /*
4464          * the address should be Qword aligned if 64bit write, Dword
4465          * aligned if only send 32bit data low (discard data high)
4466          */
4467         if (write64bit)
4468                 BUG_ON(addr & 0x7);
4469         else
4470                 BUG_ON(addr & 0x3);
4471         amdgpu_ring_write(ring, lower_32_bits(addr));
4472         amdgpu_ring_write(ring, upper_32_bits(addr));
4473         amdgpu_ring_write(ring, lower_32_bits(seq));
4474         amdgpu_ring_write(ring, upper_32_bits(seq));
4475         amdgpu_ring_write(ring, 0);
4476 }
4477
4478 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4479 {
4480         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4481         uint32_t seq = ring->fence_drv.sync_seq;
4482         uint64_t addr = ring->fence_drv.gpu_addr;
4483
4484         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4485                                upper_32_bits(addr), seq, 0xffffffff, 4);
4486 }
4487
4488 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4489                                          unsigned vmid, uint64_t pd_addr)
4490 {
4491         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4492
4493         /* compute doesn't have PFP */
4494         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4495                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4496                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4497                 amdgpu_ring_write(ring, 0x0);
4498         }
4499 }
4500
4501 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4502                                           u64 seq, unsigned int flags)
4503 {
4504         struct amdgpu_device *adev = ring->adev;
4505
4506         /* we only allocate 32bit for each seq wb address */
4507         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4508
4509         /* write fence seq to the "addr" */
4510         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4511         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4512                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4513         amdgpu_ring_write(ring, lower_32_bits(addr));
4514         amdgpu_ring_write(ring, upper_32_bits(addr));
4515         amdgpu_ring_write(ring, lower_32_bits(seq));
4516
4517         if (flags & AMDGPU_FENCE_FLAG_INT) {
4518                 /* set register to trigger INT */
4519                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4520                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4521                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4522                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4523                 amdgpu_ring_write(ring, 0);
4524                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4525         }
4526 }
4527
4528 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4529 {
4530         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4531         amdgpu_ring_write(ring, 0);
4532 }
4533
4534 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4535 {
4536         uint32_t dw2 = 0;
4537
4538         if (amdgpu_mcbp)
4539                 gfx_v10_0_ring_emit_ce_meta(ring,
4540                                     flags & AMDGPU_IB_PREEMPTED ? true : false);
4541
4542         gfx_v10_0_ring_emit_tmz(ring, true);
4543
4544         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4545         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4546                 /* set load_global_config & load_global_uconfig */
4547                 dw2 |= 0x8001;
4548                 /* set load_cs_sh_regs */
4549                 dw2 |= 0x01000000;
4550                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4551                 dw2 |= 0x10002;
4552
4553                 /* set load_ce_ram if preamble presented */
4554                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4555                         dw2 |= 0x10000000;
4556         } else {
4557                 /* still load_ce_ram if this is the first time preamble presented
4558                  * although there is no context switch happens.
4559                  */
4560                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4561                         dw2 |= 0x10000000;
4562         }
4563
4564         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4565         amdgpu_ring_write(ring, dw2);
4566         amdgpu_ring_write(ring, 0);
4567 }
4568
4569 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4570 {
4571         unsigned ret;
4572
4573         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4574         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4575         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4576         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4577         ret = ring->wptr & ring->buf_mask;
4578         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4579
4580         return ret;
4581 }
4582
4583 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4584 {
4585         unsigned cur;
4586         BUG_ON(offset > ring->buf_mask);
4587         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4588
4589         cur = (ring->wptr - 1) & ring->buf_mask;
4590         if (likely(cur > offset))
4591                 ring->ring[offset] = cur - offset;
4592         else
4593                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4594 }
4595
4596 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4597 {
4598         int i, r = 0;
4599         struct amdgpu_device *adev = ring->adev;
4600         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4601         struct amdgpu_ring *kiq_ring = &kiq->ring;
4602
4603         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4604                 return -EINVAL;
4605
4606         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4607                 return -ENOMEM;
4608
4609         /* assert preemption condition */
4610         amdgpu_ring_set_preempt_cond_exec(ring, false);
4611
4612         /* assert IB preemption, emit the trailing fence */
4613         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4614                                    ring->trail_fence_gpu_addr,
4615                                    ++ring->trail_seq);
4616         amdgpu_ring_commit(kiq_ring);
4617
4618         /* poll the trailing fence */
4619         for (i = 0; i < adev->usec_timeout; i++) {
4620                 if (ring->trail_seq ==
4621                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4622                         break;
4623                 udelay(1);
4624         }
4625
4626         if (i >= adev->usec_timeout) {
4627                 r = -EINVAL;
4628                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4629         }
4630
4631         /* deassert preemption condition */
4632         amdgpu_ring_set_preempt_cond_exec(ring, true);
4633         return r;
4634 }
4635
4636 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4637 {
4638         struct amdgpu_device *adev = ring->adev;
4639         struct v10_ce_ib_state ce_payload = {0};
4640         uint64_t csa_addr;
4641         int cnt;
4642
4643         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4644         csa_addr = amdgpu_csa_vaddr(ring->adev);
4645
4646         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4647         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4648                                  WRITE_DATA_DST_SEL(8) |
4649                                  WR_CONFIRM) |
4650                                  WRITE_DATA_CACHE_POLICY(0));
4651         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4652                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4653         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4654                               offsetof(struct v10_gfx_meta_data, ce_payload)));
4655
4656         if (resume)
4657                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4658                                            offsetof(struct v10_gfx_meta_data,
4659                                                     ce_payload),
4660                                            sizeof(ce_payload) >> 2);
4661         else
4662                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4663                                            sizeof(ce_payload) >> 2);
4664 }
4665
4666 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4667 {
4668         struct amdgpu_device *adev = ring->adev;
4669         struct v10_de_ib_state de_payload = {0};
4670         uint64_t csa_addr, gds_addr;
4671         int cnt;
4672
4673         csa_addr = amdgpu_csa_vaddr(ring->adev);
4674         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4675                          PAGE_SIZE);
4676         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4677         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4678
4679         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4680         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4681         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4682                                  WRITE_DATA_DST_SEL(8) |
4683                                  WR_CONFIRM) |
4684                                  WRITE_DATA_CACHE_POLICY(0));
4685         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4686                               offsetof(struct v10_gfx_meta_data, de_payload)));
4687         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4688                               offsetof(struct v10_gfx_meta_data, de_payload)));
4689
4690         if (resume)
4691                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4692                                            offsetof(struct v10_gfx_meta_data,
4693                                                     de_payload),
4694                                            sizeof(de_payload) >> 2);
4695         else
4696                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4697                                            sizeof(de_payload) >> 2);
4698 }
4699
4700 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4701 {
4702         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4703         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4704 }
4705
4706 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4707 {
4708         struct amdgpu_device *adev = ring->adev;
4709
4710         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4711         amdgpu_ring_write(ring, 0 |     /* src: register*/
4712                                 (5 << 8) |      /* dst: memory */
4713                                 (1 << 20));     /* write confirm */
4714         amdgpu_ring_write(ring, reg);
4715         amdgpu_ring_write(ring, 0);
4716         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4717                                 adev->virt.reg_val_offs * 4));
4718         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4719                                 adev->virt.reg_val_offs * 4));
4720 }
4721
4722 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4723                                    uint32_t val)
4724 {
4725         uint32_t cmd = 0;
4726
4727         switch (ring->funcs->type) {
4728         case AMDGPU_RING_TYPE_GFX:
4729                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4730                 break;
4731         case AMDGPU_RING_TYPE_KIQ:
4732                 cmd = (1 << 16); /* no inc addr */
4733                 break;
4734         default:
4735                 cmd = WR_CONFIRM;
4736                 break;
4737         }
4738         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4739         amdgpu_ring_write(ring, cmd);
4740         amdgpu_ring_write(ring, reg);
4741         amdgpu_ring_write(ring, 0);
4742         amdgpu_ring_write(ring, val);
4743 }
4744
4745 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4746                                         uint32_t val, uint32_t mask)
4747 {
4748         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4749 }
4750
4751 static void
4752 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4753                                       uint32_t me, uint32_t pipe,
4754                                       enum amdgpu_interrupt_state state)
4755 {
4756         uint32_t cp_int_cntl, cp_int_cntl_reg;
4757
4758         if (!me) {
4759                 switch (pipe) {
4760                 case 0:
4761                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4762                         break;
4763                 case 1:
4764                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4765                         break;
4766                 default:
4767                         DRM_DEBUG("invalid pipe %d\n", pipe);
4768                         return;
4769                 }
4770         } else {
4771                 DRM_DEBUG("invalid me %d\n", me);
4772                 return;
4773         }
4774
4775         switch (state) {
4776         case AMDGPU_IRQ_STATE_DISABLE:
4777                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4778                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4779                                             TIME_STAMP_INT_ENABLE, 0);
4780                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4781         case AMDGPU_IRQ_STATE_ENABLE:
4782                 cp_int_cntl = RREG32(cp_int_cntl_reg);
4783                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4784                                             TIME_STAMP_INT_ENABLE, 1);
4785                 WREG32(cp_int_cntl_reg, cp_int_cntl);
4786                 break;
4787         default:
4788                 break;
4789         }
4790 }
4791
4792 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4793                                                      int me, int pipe,
4794                                                      enum amdgpu_interrupt_state state)
4795 {
4796         u32 mec_int_cntl, mec_int_cntl_reg;
4797
4798         /*
4799          * amdgpu controls only the first MEC. That's why this function only
4800          * handles the setting of interrupts for this specific MEC. All other
4801          * pipes' interrupts are set by amdkfd.
4802          */
4803
4804         if (me == 1) {
4805                 switch (pipe) {
4806                 case 0:
4807                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4808                         break;
4809                 case 1:
4810                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4811                         break;
4812                 case 2:
4813                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4814                         break;
4815                 case 3:
4816                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4817                         break;
4818                 default:
4819                         DRM_DEBUG("invalid pipe %d\n", pipe);
4820                         return;
4821                 }
4822         } else {
4823                 DRM_DEBUG("invalid me %d\n", me);
4824                 return;
4825         }
4826
4827         switch (state) {
4828         case AMDGPU_IRQ_STATE_DISABLE:
4829                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4830                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4831                                              TIME_STAMP_INT_ENABLE, 0);
4832                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4833                 break;
4834         case AMDGPU_IRQ_STATE_ENABLE:
4835                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4836                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4837                                              TIME_STAMP_INT_ENABLE, 1);
4838                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4839                 break;
4840         default:
4841                 break;
4842         }
4843 }
4844
4845 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4846                                             struct amdgpu_irq_src *src,
4847                                             unsigned type,
4848                                             enum amdgpu_interrupt_state state)
4849 {
4850         switch (type) {
4851         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4852                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4853                 break;
4854         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4855                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4856                 break;
4857         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4858                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4859                 break;
4860         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4861                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4862                 break;
4863         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4864                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4865                 break;
4866         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4867                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4868                 break;
4869         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4870                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4871                 break;
4872         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4873                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4874                 break;
4875         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4876                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4877                 break;
4878         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4879                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4880                 break;
4881         default:
4882                 break;
4883         }
4884         return 0;
4885 }
4886
4887 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4888                              struct amdgpu_irq_src *source,
4889                              struct amdgpu_iv_entry *entry)
4890 {
4891         int i;
4892         u8 me_id, pipe_id, queue_id;
4893         struct amdgpu_ring *ring;
4894
4895         DRM_DEBUG("IH: CP EOP\n");
4896         me_id = (entry->ring_id & 0x0c) >> 2;
4897         pipe_id = (entry->ring_id & 0x03) >> 0;
4898         queue_id = (entry->ring_id & 0x70) >> 4;
4899
4900         switch (me_id) {
4901         case 0:
4902                 if (pipe_id == 0)
4903                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4904                 else
4905                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4906                 break;
4907         case 1:
4908         case 2:
4909                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4910                         ring = &adev->gfx.compute_ring[i];
4911                         /* Per-queue interrupt is supported for MEC starting from VI.
4912                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4913                           */
4914                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4915                                 amdgpu_fence_process(ring);
4916                 }
4917                 break;
4918         }
4919         return 0;
4920 }
4921
4922 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4923                                               struct amdgpu_irq_src *source,
4924                                               unsigned type,
4925                                               enum amdgpu_interrupt_state state)
4926 {
4927         switch (state) {
4928         case AMDGPU_IRQ_STATE_DISABLE:
4929         case AMDGPU_IRQ_STATE_ENABLE:
4930                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4931                                PRIV_REG_INT_ENABLE,
4932                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4933                 break;
4934         default:
4935                 break;
4936         }
4937
4938         return 0;
4939 }
4940
4941 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4942                                                struct amdgpu_irq_src *source,
4943                                                unsigned type,
4944                                                enum amdgpu_interrupt_state state)
4945 {
4946         switch (state) {
4947         case AMDGPU_IRQ_STATE_DISABLE:
4948         case AMDGPU_IRQ_STATE_ENABLE:
4949                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4950                                PRIV_INSTR_INT_ENABLE,
4951                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4952         default:
4953                 break;
4954         }
4955
4956         return 0;
4957 }
4958
4959 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
4960                                         struct amdgpu_iv_entry *entry)
4961 {
4962         u8 me_id, pipe_id, queue_id;
4963         struct amdgpu_ring *ring;
4964         int i;
4965
4966         me_id = (entry->ring_id & 0x0c) >> 2;
4967         pipe_id = (entry->ring_id & 0x03) >> 0;
4968         queue_id = (entry->ring_id & 0x70) >> 4;
4969
4970         switch (me_id) {
4971         case 0:
4972                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4973                         ring = &adev->gfx.gfx_ring[i];
4974                         /* we only enabled 1 gfx queue per pipe for now */
4975                         if (ring->me == me_id && ring->pipe == pipe_id)
4976                                 drm_sched_fault(&ring->sched);
4977                 }
4978                 break;
4979         case 1:
4980         case 2:
4981                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4982                         ring = &adev->gfx.compute_ring[i];
4983                         if (ring->me == me_id && ring->pipe == pipe_id &&
4984                             ring->queue == queue_id)
4985                                 drm_sched_fault(&ring->sched);
4986                 }
4987                 break;
4988         default:
4989                 BUG();
4990         }
4991 }
4992
4993 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
4994                                   struct amdgpu_irq_src *source,
4995                                   struct amdgpu_iv_entry *entry)
4996 {
4997         DRM_ERROR("Illegal register access in command stream\n");
4998         gfx_v10_0_handle_priv_fault(adev, entry);
4999         return 0;
5000 }
5001
5002 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
5003                                    struct amdgpu_irq_src *source,
5004                                    struct amdgpu_iv_entry *entry)
5005 {
5006         DRM_ERROR("Illegal instruction in command stream\n");
5007         gfx_v10_0_handle_priv_fault(adev, entry);
5008         return 0;
5009 }
5010
5011 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5012                                              struct amdgpu_irq_src *src,
5013                                              unsigned int type,
5014                                              enum amdgpu_interrupt_state state)
5015 {
5016         uint32_t tmp, target;
5017         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5018
5019         if (ring->me == 1)
5020                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5021         else
5022                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5023         target += ring->pipe;
5024
5025         switch (type) {
5026         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5027                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5028                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5029                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5030                                             GENERIC2_INT_ENABLE, 0);
5031                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5032
5033                         tmp = RREG32(target);
5034                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5035                                             GENERIC2_INT_ENABLE, 0);
5036                         WREG32(target, tmp);
5037                 } else {
5038                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5039                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5040                                             GENERIC2_INT_ENABLE, 1);
5041                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5042
5043                         tmp = RREG32(target);
5044                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5045                                             GENERIC2_INT_ENABLE, 1);
5046                         WREG32(target, tmp);
5047                 }
5048                 break;
5049         default:
5050                 BUG(); /* kiq only support GENERIC2_INT now */
5051                 break;
5052         }
5053         return 0;
5054 }
5055
5056 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5057                              struct amdgpu_irq_src *source,
5058                              struct amdgpu_iv_entry *entry)
5059 {
5060         u8 me_id, pipe_id, queue_id;
5061         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5062
5063         me_id = (entry->ring_id & 0x0c) >> 2;
5064         pipe_id = (entry->ring_id & 0x03) >> 0;
5065         queue_id = (entry->ring_id & 0x70) >> 4;
5066         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5067                    me_id, pipe_id, queue_id);
5068
5069         amdgpu_fence_process(ring);
5070         return 0;
5071 }
5072
5073 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5074         .name = "gfx_v10_0",
5075         .early_init = gfx_v10_0_early_init,
5076         .late_init = gfx_v10_0_late_init,
5077         .sw_init = gfx_v10_0_sw_init,
5078         .sw_fini = gfx_v10_0_sw_fini,
5079         .hw_init = gfx_v10_0_hw_init,
5080         .hw_fini = gfx_v10_0_hw_fini,
5081         .suspend = gfx_v10_0_suspend,
5082         .resume = gfx_v10_0_resume,
5083         .is_idle = gfx_v10_0_is_idle,
5084         .wait_for_idle = gfx_v10_0_wait_for_idle,
5085         .soft_reset = gfx_v10_0_soft_reset,
5086         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
5087         .set_powergating_state = gfx_v10_0_set_powergating_state,
5088         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
5089 };
5090
5091 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5092         .type = AMDGPU_RING_TYPE_GFX,
5093         .align_mask = 0xff,
5094         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5095         .support_64bit_ptrs = true,
5096         .vmhub = AMDGPU_GFXHUB_0,
5097         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5098         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5099         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5100         .emit_frame_size = /* totally 242 maximum if 16 IBs */
5101                 5 + /* COND_EXEC */
5102                 7 + /* PIPELINE_SYNC */
5103                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5104                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5105                 2 + /* VM_FLUSH */
5106                 8 + /* FENCE for VM_FLUSH */
5107                 20 + /* GDS switch */
5108                 4 + /* double SWITCH_BUFFER,
5109                      * the first COND_EXEC jump to the place
5110                      * just prior to this double SWITCH_BUFFER
5111                      */
5112                 5 + /* COND_EXEC */
5113                 7 + /* HDP_flush */
5114                 4 + /* VGT_flush */
5115                 14 + /* CE_META */
5116                 31 + /* DE_META */
5117                 3 + /* CNTX_CTRL */
5118                 5 + /* HDP_INVL */
5119                 8 + 8 + /* FENCE x2 */
5120                 2, /* SWITCH_BUFFER */
5121         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */
5122         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5123         .emit_fence = gfx_v10_0_ring_emit_fence,
5124         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5125         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5126         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5127         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5128         .test_ring = gfx_v10_0_ring_test_ring,
5129         .test_ib = gfx_v10_0_ring_test_ib,
5130         .insert_nop = amdgpu_ring_insert_nop,
5131         .pad_ib = amdgpu_ring_generic_pad_ib,
5132         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5133         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5134         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5135         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5136         .preempt_ib = gfx_v10_0_ring_preempt_ib,
5137         .emit_tmz = gfx_v10_0_ring_emit_tmz,
5138         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5139         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5140 };
5141
5142 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5143         .type = AMDGPU_RING_TYPE_COMPUTE,
5144         .align_mask = 0xff,
5145         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5146         .support_64bit_ptrs = true,
5147         .vmhub = AMDGPU_GFXHUB_0,
5148         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5149         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5150         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5151         .emit_frame_size =
5152                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5153                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5154                 5 + /* hdp invalidate */
5155                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5156                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5157                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5158                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5159                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
5160         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5161         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5162         .emit_fence = gfx_v10_0_ring_emit_fence,
5163         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5164         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5165         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5166         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5167         .test_ring = gfx_v10_0_ring_test_ring,
5168         .test_ib = gfx_v10_0_ring_test_ib,
5169         .insert_nop = amdgpu_ring_insert_nop,
5170         .pad_ib = amdgpu_ring_generic_pad_ib,
5171         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5172         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5173 };
5174
5175 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5176         .type = AMDGPU_RING_TYPE_KIQ,
5177         .align_mask = 0xff,
5178         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5179         .support_64bit_ptrs = true,
5180         .vmhub = AMDGPU_GFXHUB_0,
5181         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5182         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5183         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5184         .emit_frame_size =
5185                 20 + /* gfx_v10_0_ring_emit_gds_switch */
5186                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
5187                 5 + /*hdp invalidate */
5188                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5189                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5190                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5191                 2 + /* gfx_v10_0_ring_emit_vm_flush */
5192                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5193         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
5194         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5195         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5196         .test_ring = gfx_v10_0_ring_test_ring,
5197         .test_ib = gfx_v10_0_ring_test_ib,
5198         .insert_nop = amdgpu_ring_insert_nop,
5199         .pad_ib = amdgpu_ring_generic_pad_ib,
5200         .emit_rreg = gfx_v10_0_ring_emit_rreg,
5201         .emit_wreg = gfx_v10_0_ring_emit_wreg,
5202         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5203 };
5204
5205 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5206 {
5207         int i;
5208
5209         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5210
5211         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5212                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5213
5214         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5215                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5216 }
5217
5218 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5219         .set = gfx_v10_0_set_eop_interrupt_state,
5220         .process = gfx_v10_0_eop_irq,
5221 };
5222
5223 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5224         .set = gfx_v10_0_set_priv_reg_fault_state,
5225         .process = gfx_v10_0_priv_reg_irq,
5226 };
5227
5228 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5229         .set = gfx_v10_0_set_priv_inst_fault_state,
5230         .process = gfx_v10_0_priv_inst_irq,
5231 };
5232
5233 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5234         .set = gfx_v10_0_kiq_set_interrupt_state,
5235         .process = gfx_v10_0_kiq_irq,
5236 };
5237
5238 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5239 {
5240         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5241         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5242
5243         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5244         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5245
5246         adev->gfx.priv_reg_irq.num_types = 1;
5247         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5248
5249         adev->gfx.priv_inst_irq.num_types = 1;
5250         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5251 }
5252
5253 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5254 {
5255         switch (adev->asic_type) {
5256         case CHIP_NAVI10:
5257         case CHIP_NAVI14:
5258         case CHIP_NAVI12:
5259                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5260                 break;
5261         default:
5262                 break;
5263         }
5264 }
5265
5266 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5267 {
5268         /* init asic gds info */
5269         switch (adev->asic_type) {
5270         case CHIP_NAVI10:
5271         default:
5272                 adev->gds.gds_size = 0x10000;
5273                 adev->gds.gds_compute_max_wave_id = 0x4ff;
5274                 adev->gds.vgt_gs_max_wave_id = 0x3ff;
5275                 break;
5276         }
5277
5278         adev->gds.gws_size = 64;
5279         adev->gds.oa_size = 16;
5280 }
5281
5282 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5283                                                           u32 bitmap)
5284 {
5285         u32 data;
5286
5287         if (!bitmap)
5288                 return;
5289
5290         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5291         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5292
5293         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5294 }
5295
5296 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5297 {
5298         u32 data, wgp_bitmask;
5299         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5300         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5301
5302         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5303         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5304
5305         wgp_bitmask =
5306                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5307
5308         return (~data) & wgp_bitmask;
5309 }
5310
5311 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5312 {
5313         u32 wgp_idx, wgp_active_bitmap;
5314         u32 cu_bitmap_per_wgp, cu_active_bitmap;
5315
5316         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5317         cu_active_bitmap = 0;
5318
5319         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5320                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5321                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5322                 if (wgp_active_bitmap & (1 << wgp_idx))
5323                         cu_active_bitmap |= cu_bitmap_per_wgp;
5324         }
5325
5326         return cu_active_bitmap;
5327 }
5328
5329 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5330                                  struct amdgpu_cu_info *cu_info)
5331 {
5332         int i, j, k, counter, active_cu_number = 0;
5333         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5334         unsigned disable_masks[4 * 2];
5335
5336         if (!adev || !cu_info)
5337                 return -EINVAL;
5338
5339         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5340
5341         mutex_lock(&adev->grbm_idx_mutex);
5342         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5343                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5344                         mask = 1;
5345                         ao_bitmap = 0;
5346                         counter = 0;
5347                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5348                         if (i < 4 && j < 2)
5349                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5350                                         adev, disable_masks[i * 2 + j]);
5351                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5352                         cu_info->bitmap[i][j] = bitmap;
5353
5354                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5355                                 if (bitmap & mask) {
5356                                         if (counter < adev->gfx.config.max_cu_per_sh)
5357                                                 ao_bitmap |= mask;
5358                                         counter++;
5359                                 }
5360                                 mask <<= 1;
5361                         }
5362                         active_cu_number += counter;
5363                         if (i < 2 && j < 2)
5364                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5365                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5366                 }
5367         }
5368         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5369         mutex_unlock(&adev->grbm_idx_mutex);
5370
5371         cu_info->number = active_cu_number;
5372         cu_info->ao_cu_mask = ao_cu_mask;
5373         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5374
5375         return 0;
5376 }
5377
5378 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5379 {
5380         .type = AMD_IP_BLOCK_TYPE_GFX,
5381         .major = 10,
5382         .minor = 0,
5383         .rev = 0,
5384         .funcs = &gfx_v10_0_ip_funcs,
5385 };