drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 //CC_GC_SA_UNIT_DISABLE
 116 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 117 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 118 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 119 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 120 //GC_USER_SA_UNIT_DISABLE
 121 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 122 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 123 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 124 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 125 //PA_SC_ENHANCE_3
 126 #define mmPA_SC_ENHANCE_3                       0x1085
 127 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 128 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 129 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 130
 131 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 132 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 133 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 134 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 135 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 136 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 137
 138 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 139 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 140 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 141 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 142 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 143 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 144 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 145 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 146 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 147 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 148 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 149
 150 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 151 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 152 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 153 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 154 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 155 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 156
 157 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 158 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 159 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 160 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 161 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 162 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 163
 164 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 165 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 166 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 167 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 168 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 169 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 170
 171 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 172 {
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 213 };
 214
 215 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 216 {
 217         /* Pending on emulation bring up */
 218 };
 219
 220 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 221 {
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1274 };
1275
1276 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1277 {
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1316 };
1317
1318 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1319 {
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1360 };
1361
1362 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1363 {
1364         static void *scratch_reg0;
1365         static void *scratch_reg1;
1366         static void *scratch_reg2;
1367         static void *scratch_reg3;
1368         static void *spare_int;
1369         static uint32_t grbm_cntl;
1370         static uint32_t grbm_idx;
1371         uint32_t i = 0;
1372         uint32_t retries = 50000;
1373
1374         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1375         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1376         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1377         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1378         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1379
1380         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1381         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1382
1383         if (amdgpu_sriov_runtime(adev)) {
1384                 pr_err("shouldn't call rlcg write register during runtime\n");
1385                 return;
1386         }
1387
1388         writel(v, scratch_reg0);
1389         writel(offset | 0x80000000, scratch_reg1);
1390         writel(1, spare_int);
1391         for (i = 0; i < retries; i++) {
1392                 u32 tmp;
1393
1394                 tmp = readl(scratch_reg1);
1395                 if (!(tmp & 0x80000000))
1396                         break;
1397
1398                 udelay(10);
1399         }
1400
1401         if (i >= retries)
1402                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1403 }
1404
1405 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1406 {
1407         /* Pending on emulation bring up */
1408 };
1409
1410 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1411 {
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2032 };
2033
2034 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2035 {
2036         /* Pending on emulation bring up */
2037 };
2038
2039 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2040 {
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3093 };
3094
3095 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3096 {
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3134 };
3135
3136 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3137 {
3138         /* Pending on emulation bring up */
3139 };
3140
3141 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3142 {
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3181 };
3182
3183 #define DEFAULT_SH_MEM_CONFIG \
3184         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3185          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3186          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3187          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3188
3189
3190 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3191 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3192 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3193 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3194 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3195                                  struct amdgpu_cu_info *cu_info);
3196 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3197 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3198                                    u32 sh_num, u32 instance);
3199 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3200
3201 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3202 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3203 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3204 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3205 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3206 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3207 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3208 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3209 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3210
3211 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3212 {
3213         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3214         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3215                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3216         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3217         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3218         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3219         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3220         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3221         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3222 }
3223
3224 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3225                                  struct amdgpu_ring *ring)
3226 {
3227         struct amdgpu_device *adev = kiq_ring->adev;
3228         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3229         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3230         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3231
3232         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3233         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3234         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3235                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3236                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3237                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3238                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3239                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3240                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3241                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3242                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3243                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3244         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3245         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3246         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3247         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3248         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3249 }
3250
3251 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3252                                    struct amdgpu_ring *ring,
3253                                    enum amdgpu_unmap_queues_action action,
3254                                    u64 gpu_addr, u64 seq)
3255 {
3256         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3257
3258         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3259         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3260                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3261                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3262                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3263                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3264         amdgpu_ring_write(kiq_ring,
3265                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3266
3267         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3268                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3269                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3270                 amdgpu_ring_write(kiq_ring, seq);
3271         } else {
3272                 amdgpu_ring_write(kiq_ring, 0);
3273                 amdgpu_ring_write(kiq_ring, 0);
3274                 amdgpu_ring_write(kiq_ring, 0);
3275         }
3276 }
3277
3278 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3279                                    struct amdgpu_ring *ring,
3280                                    u64 addr,
3281                                    u64 seq)
3282 {
3283         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3284
3285         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3286         amdgpu_ring_write(kiq_ring,
3287                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3288                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3289                           PACKET3_QUERY_STATUS_COMMAND(2));
3290         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3291                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3292                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3293         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3294         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3295         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3296         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3297 }
3298
3299 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3300                                 uint16_t pasid, uint32_t flush_type,
3301                                 bool all_hub)
3302 {
3303         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3304         amdgpu_ring_write(kiq_ring,
3305                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3306                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3307                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3308                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3309 }
3310
3311 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3312         .kiq_set_resources = gfx10_kiq_set_resources,
3313         .kiq_map_queues = gfx10_kiq_map_queues,
3314         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3315         .kiq_query_status = gfx10_kiq_query_status,
3316         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3317         .set_resources_size = 8,
3318         .map_queues_size = 7,
3319         .unmap_queues_size = 6,
3320         .query_status_size = 7,
3321         .invalidate_tlbs_size = 2,
3322 };
3323
3324 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3325 {
3326         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3327 }
3328
3329 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3330 {
3331         switch (adev->asic_type) {
3332         case CHIP_NAVI10:
3333                 soc15_program_register_sequence(adev,
3334                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3335                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3336                 break;
3337         case CHIP_NAVI14:
3338                 soc15_program_register_sequence(adev,
3339                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3340                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3341                 break;
3342         case CHIP_NAVI12:
3343                 soc15_program_register_sequence(adev,
3344                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3345                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3346                 break;
3347         default:
3348                 break;
3349         }
3350 }
3351
3352 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3353 {
3354         switch (adev->asic_type) {
3355         case CHIP_NAVI10:
3356                 soc15_program_register_sequence(adev,
3357                                                 golden_settings_gc_10_1,
3358                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3359                 soc15_program_register_sequence(adev,
3360                                                 golden_settings_gc_10_0_nv10,
3361                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3362                 break;
3363         case CHIP_NAVI14:
3364                 soc15_program_register_sequence(adev,
3365                                                 golden_settings_gc_10_1_1,
3366                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3367                 soc15_program_register_sequence(adev,
3368                                                 golden_settings_gc_10_1_nv14,
3369                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3370                 break;
3371         case CHIP_NAVI12:
3372                 soc15_program_register_sequence(adev,
3373                                                 golden_settings_gc_10_1_2,
3374                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3375                 soc15_program_register_sequence(adev,
3376                                                 golden_settings_gc_10_1_2_nv12,
3377                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3378                 break;
3379         case CHIP_SIENNA_CICHLID:
3380                 soc15_program_register_sequence(adev,
3381                                                 golden_settings_gc_10_3,
3382                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3383                 soc15_program_register_sequence(adev,
3384                                                 golden_settings_gc_10_3_sienna_cichlid,
3385                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3386                 break;
3387         case CHIP_NAVY_FLOUNDER:
3388                 soc15_program_register_sequence(adev,
3389                                                 golden_settings_gc_10_3_2,
3390                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3391                 break;
3392
3393         default:
3394                 break;
3395         }
3396         gfx_v10_0_init_spm_golden_registers(adev);
3397 }
3398
3399 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3400 {
3401         adev->gfx.scratch.num_reg = 8;
3402         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3403         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3404 }
3405
3406 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3407                                        bool wc, uint32_t reg, uint32_t val)
3408 {
3409         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3410         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3411                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3412         amdgpu_ring_write(ring, reg);
3413         amdgpu_ring_write(ring, 0);
3414         amdgpu_ring_write(ring, val);
3415 }
3416
3417 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3418                                   int mem_space, int opt, uint32_t addr0,
3419                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3420                                   uint32_t inv)
3421 {
3422         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3423         amdgpu_ring_write(ring,
3424                           /* memory (1) or register (0) */
3425                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3426                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3427                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3428                            WAIT_REG_MEM_ENGINE(eng_sel)));
3429
3430         if (mem_space)
3431                 BUG_ON(addr0 & 0x3); /* Dword align */
3432         amdgpu_ring_write(ring, addr0);
3433         amdgpu_ring_write(ring, addr1);
3434         amdgpu_ring_write(ring, ref);
3435         amdgpu_ring_write(ring, mask);
3436         amdgpu_ring_write(ring, inv); /* poll interval */
3437 }
3438
3439 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3440 {
3441         struct amdgpu_device *adev = ring->adev;
3442         uint32_t scratch;
3443         uint32_t tmp = 0;
3444         unsigned i;
3445         int r;
3446
3447         r = amdgpu_gfx_scratch_get(adev, &scratch);
3448         if (r) {
3449                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3450                 return r;
3451         }
3452
3453         WREG32(scratch, 0xCAFEDEAD);
3454
3455         r = amdgpu_ring_alloc(ring, 3);
3456         if (r) {
3457                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3458                           ring->idx, r);
3459                 amdgpu_gfx_scratch_free(adev, scratch);
3460                 return r;
3461         }
3462
3463         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3464         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3465         amdgpu_ring_write(ring, 0xDEADBEEF);
3466         amdgpu_ring_commit(ring);
3467
3468         for (i = 0; i < adev->usec_timeout; i++) {
3469                 tmp = RREG32(scratch);
3470                 if (tmp == 0xDEADBEEF)
3471                         break;
3472                 if (amdgpu_emu_mode == 1)
3473                         msleep(1);
3474                 else
3475                         udelay(1);
3476         }
3477
3478         if (i >= adev->usec_timeout)
3479                 r = -ETIMEDOUT;
3480
3481         amdgpu_gfx_scratch_free(adev, scratch);
3482
3483         return r;
3484 }
3485
3486 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3487 {
3488         struct amdgpu_device *adev = ring->adev;
3489         struct amdgpu_ib ib;
3490         struct dma_fence *f = NULL;
3491         unsigned index;
3492         uint64_t gpu_addr;
3493         uint32_t tmp;
3494         long r;
3495
3496         r = amdgpu_device_wb_get(adev, &index);
3497         if (r)
3498                 return r;
3499
3500         gpu_addr = adev->wb.gpu_addr + (index * 4);
3501         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3502         memset(&ib, 0, sizeof(ib));
3503         r = amdgpu_ib_get(adev, NULL, 16,
3504                                         AMDGPU_IB_POOL_DIRECT, &ib);
3505         if (r)
3506                 goto err1;
3507
3508         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3509         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3510         ib.ptr[2] = lower_32_bits(gpu_addr);
3511         ib.ptr[3] = upper_32_bits(gpu_addr);
3512         ib.ptr[4] = 0xDEADBEEF;
3513         ib.length_dw = 5;
3514
3515         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3516         if (r)
3517                 goto err2;
3518
3519         r = dma_fence_wait_timeout(f, false, timeout);
3520         if (r == 0) {
3521                 r = -ETIMEDOUT;
3522                 goto err2;
3523         } else if (r < 0) {
3524                 goto err2;
3525         }
3526
3527         tmp = adev->wb.wb[index];
3528         if (tmp == 0xDEADBEEF)
3529                 r = 0;
3530         else
3531                 r = -EINVAL;
3532 err2:
3533         amdgpu_ib_free(adev, &ib, NULL);
3534         dma_fence_put(f);
3535 err1:
3536         amdgpu_device_wb_free(adev, index);
3537         return r;
3538 }
3539
3540 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3541 {
3542         release_firmware(adev->gfx.pfp_fw);
3543         adev->gfx.pfp_fw = NULL;
3544         release_firmware(adev->gfx.me_fw);
3545         adev->gfx.me_fw = NULL;
3546         release_firmware(adev->gfx.ce_fw);
3547         adev->gfx.ce_fw = NULL;
3548         release_firmware(adev->gfx.rlc_fw);
3549         adev->gfx.rlc_fw = NULL;
3550         release_firmware(adev->gfx.mec_fw);
3551         adev->gfx.mec_fw = NULL;
3552         release_firmware(adev->gfx.mec2_fw);
3553         adev->gfx.mec2_fw = NULL;
3554
3555         kfree(adev->gfx.rlc.register_list_format);
3556 }
3557
3558 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3559 {
3560         adev->gfx.cp_fw_write_wait = false;
3561
3562         switch (adev->asic_type) {
3563         case CHIP_NAVI10:
3564         case CHIP_NAVI12:
3565         case CHIP_NAVI14:
3566                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3567                     (adev->gfx.me_feature_version >= 27) &&
3568                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3569                     (adev->gfx.pfp_feature_version >= 27) &&
3570                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3571                     (adev->gfx.mec_feature_version >= 27))
3572                         adev->gfx.cp_fw_write_wait = true;
3573                 break;
3574         case CHIP_SIENNA_CICHLID:
3575         case CHIP_NAVY_FLOUNDER:
3576                 adev->gfx.cp_fw_write_wait = true;
3577                 break;
3578         default:
3579                 break;
3580         }
3581
3582         if (!adev->gfx.cp_fw_write_wait)
3583                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3584 }
3585
3586
3587 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3588 {
3589         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3590
3591         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3592         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3593         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3594         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3595         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3596         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3597         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3598         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3599         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3600         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3601         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3602         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3603         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3604         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3605                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3606 }
3607
3608 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3609 {
3610         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3611
3612         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3613         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3614         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3615         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3616         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3617 }
3618
3619 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3620 {
3621         bool ret = false;
3622
3623         switch (adev->pdev->revision) {
3624         case 0xc2:
3625         case 0xc3:
3626                 ret = true;
3627                 break;
3628         default:
3629                 ret = false;
3630                 break;
3631         }
3632
3633         return ret ;
3634 }
3635
3636 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3637 {
3638         switch (adev->asic_type) {
3639         case CHIP_NAVI10:
3640                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3641                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3642                 break;
3643         case CHIP_NAVY_FLOUNDER:
3644                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3645                 break;
3646         default:
3647                 break;
3648         }
3649 }
3650
3651 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3652 {
3653         const char *chip_name;
3654         char fw_name[40];
3655         char wks[10];
3656         int err;
3657         struct amdgpu_firmware_info *info = NULL;
3658         const struct common_firmware_header *header = NULL;
3659         const struct gfx_firmware_header_v1_0 *cp_hdr;
3660         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3661         unsigned int *tmp = NULL;
3662         unsigned int i = 0;
3663         uint16_t version_major;
3664         uint16_t version_minor;
3665
3666         DRM_DEBUG("\n");
3667
3668         memset(wks, 0, sizeof(wks));
3669         switch (adev->asic_type) {
3670         case CHIP_NAVI10:
3671                 chip_name = "navi10";
3672                 break;
3673         case CHIP_NAVI14:
3674                 chip_name = "navi14";
3675                 if (!(adev->pdev->device == 0x7340 &&
3676                       adev->pdev->revision != 0x00))
3677                         snprintf(wks, sizeof(wks), "_wks");
3678                 break;
3679         case CHIP_NAVI12:
3680                 chip_name = "navi12";
3681                 break;
3682         case CHIP_SIENNA_CICHLID:
3683                 chip_name = "sienna_cichlid";
3684                 break;
3685         case CHIP_NAVY_FLOUNDER:
3686                 chip_name = "navy_flounder";
3687                 break;
3688         default:
3689                 BUG();
3690         }
3691
3692         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3693         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3694         if (err)
3695                 goto out;
3696         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3697         if (err)
3698                 goto out;
3699         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3700         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3701         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3702
3703         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3704         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3705         if (err)
3706                 goto out;
3707         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3708         if (err)
3709                 goto out;
3710         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3711         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3712         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3713
3714         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3715         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3716         if (err)
3717                 goto out;
3718         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3719         if (err)
3720                 goto out;
3721         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3722         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3723         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3724
3725         if (!amdgpu_sriov_vf(adev)) {
3726                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3727                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3728                 if (err)
3729                         goto out;
3730                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3731                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3732                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3733                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3734
3735                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3736                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3737                 adev->gfx.rlc.save_and_restore_offset =
3738                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3739                 adev->gfx.rlc.clear_state_descriptor_offset =
3740                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3741                 adev->gfx.rlc.avail_scratch_ram_locations =
3742                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3743                 adev->gfx.rlc.reg_restore_list_size =
3744                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3745                 adev->gfx.rlc.reg_list_format_start =
3746                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3747                 adev->gfx.rlc.reg_list_format_separate_start =
3748                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3749                 adev->gfx.rlc.starting_offsets_start =
3750                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3751                 adev->gfx.rlc.reg_list_format_size_bytes =
3752                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3753                 adev->gfx.rlc.reg_list_size_bytes =
3754                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3755                 adev->gfx.rlc.register_list_format =
3756                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3757                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3758                 if (!adev->gfx.rlc.register_list_format) {
3759                         err = -ENOMEM;
3760                         goto out;
3761                 }
3762
3763                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3764                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3765                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3766                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3767
3768                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3769
3770                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3771                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3772                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3773                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3774
3775                 if (version_major == 2) {
3776                         if (version_minor >= 1)
3777                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3778                         if (version_minor == 2)
3779                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3780                 }
3781         }
3782
3783         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3784         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3785         if (err)
3786                 goto out;
3787         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3788         if (err)
3789                 goto out;
3790         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3791         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3792         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3793
3794         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3795         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3796         if (!err) {
3797                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3798                 if (err)
3799                         goto out;
3800                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3801                 adev->gfx.mec2_fw->data;
3802                 adev->gfx.mec2_fw_version =
3803                 le32_to_cpu(cp_hdr->header.ucode_version);
3804                 adev->gfx.mec2_feature_version =
3805                 le32_to_cpu(cp_hdr->ucode_feature_version);
3806         } else {
3807                 err = 0;
3808                 adev->gfx.mec2_fw = NULL;
3809         }
3810
3811         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3812                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3813                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3814                 info->fw = adev->gfx.pfp_fw;
3815                 header = (const struct common_firmware_header *)info->fw->data;
3816                 adev->firmware.fw_size +=
3817                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3818
3819                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3820                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3821                 info->fw = adev->gfx.me_fw;
3822                 header = (const struct common_firmware_header *)info->fw->data;
3823                 adev->firmware.fw_size +=
3824                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3825
3826                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3827                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3828                 info->fw = adev->gfx.ce_fw;
3829                 header = (const struct common_firmware_header *)info->fw->data;
3830                 adev->firmware.fw_size +=
3831                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3832
3833                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3834                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3835                 info->fw = adev->gfx.rlc_fw;
3836                 if (info->fw) {
3837                         header = (const struct common_firmware_header *)info->fw->data;
3838                         adev->firmware.fw_size +=
3839                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3840                 }
3841                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3842                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3843                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3844                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3845                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3846                         info->fw = adev->gfx.rlc_fw;
3847                         adev->firmware.fw_size +=
3848                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3849
3850                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3851                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3852                         info->fw = adev->gfx.rlc_fw;
3853                         adev->firmware.fw_size +=
3854                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3855
3856                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3857                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3858                         info->fw = adev->gfx.rlc_fw;
3859                         adev->firmware.fw_size +=
3860                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3861
3862                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
3863                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
3864                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
3865                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
3866                                 info->fw = adev->gfx.rlc_fw;
3867                                 adev->firmware.fw_size +=
3868                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
3869
3870                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
3871                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
3872                                 info->fw = adev->gfx.rlc_fw;
3873                                 adev->firmware.fw_size +=
3874                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
3875                         }
3876                 }
3877
3878                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3879                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3880                 info->fw = adev->gfx.mec_fw;
3881                 header = (const struct common_firmware_header *)info->fw->data;
3882                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3883                 adev->firmware.fw_size +=
3884                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3885                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3886
3887                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3888                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3889                 info->fw = adev->gfx.mec_fw;
3890                 adev->firmware.fw_size +=
3891                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3892
3893                 if (adev->gfx.mec2_fw) {
3894                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3895                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3896                         info->fw = adev->gfx.mec2_fw;
3897                         header = (const struct common_firmware_header *)info->fw->data;
3898                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3899                         adev->firmware.fw_size +=
3900                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3901                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3902                                       PAGE_SIZE);
3903                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3904                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3905                         info->fw = adev->gfx.mec2_fw;
3906                         adev->firmware.fw_size +=
3907                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3908                                       PAGE_SIZE);
3909                 }
3910         }
3911
3912         gfx_v10_0_check_fw_write_wait(adev);
3913 out:
3914         if (err) {
3915                 dev_err(adev->dev,
3916                         "gfx10: Failed to load firmware \"%s\"\n",
3917                         fw_name);
3918                 release_firmware(adev->gfx.pfp_fw);
3919                 adev->gfx.pfp_fw = NULL;
3920                 release_firmware(adev->gfx.me_fw);
3921                 adev->gfx.me_fw = NULL;
3922                 release_firmware(adev->gfx.ce_fw);
3923                 adev->gfx.ce_fw = NULL;
3924                 release_firmware(adev->gfx.rlc_fw);
3925                 adev->gfx.rlc_fw = NULL;
3926                 release_firmware(adev->gfx.mec_fw);
3927                 adev->gfx.mec_fw = NULL;
3928                 release_firmware(adev->gfx.mec2_fw);
3929                 adev->gfx.mec2_fw = NULL;
3930         }
3931
3932         gfx_v10_0_check_gfxoff_flag(adev);
3933
3934         return err;
3935 }
3936
3937 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3938 {
3939         u32 count = 0;
3940         const struct cs_section_def *sect = NULL;
3941         const struct cs_extent_def *ext = NULL;
3942
3943         /* begin clear state */
3944         count += 2;
3945         /* context control state */
3946         count += 3;
3947
3948         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3949                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3950                         if (sect->id == SECT_CONTEXT)
3951                                 count += 2 + ext->reg_count;
3952                         else
3953                                 return 0;
3954                 }
3955         }
3956
3957         /* set PA_SC_TILE_STEERING_OVERRIDE */
3958         count += 3;
3959         /* end clear state */
3960         count += 2;
3961         /* clear state */
3962         count += 2;
3963
3964         return count;
3965 }
3966
3967 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3968                                     volatile u32 *buffer)
3969 {
3970         u32 count = 0, i;
3971         const struct cs_section_def *sect = NULL;
3972         const struct cs_extent_def *ext = NULL;
3973         int ctx_reg_offset;
3974
3975         if (adev->gfx.rlc.cs_data == NULL)
3976                 return;
3977         if (buffer == NULL)
3978                 return;
3979
3980         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3981         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3982
3983         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3984         buffer[count++] = cpu_to_le32(0x80000000);
3985         buffer[count++] = cpu_to_le32(0x80000000);
3986
3987         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3988                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3989                         if (sect->id == SECT_CONTEXT) {
3990                                 buffer[count++] =
3991                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3992                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3993                                                 PACKET3_SET_CONTEXT_REG_START);
3994                                 for (i = 0; i < ext->reg_count; i++)
3995                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3996                         } else {
3997                                 return;
3998                         }
3999                 }
4000         }
4001
4002         ctx_reg_offset =
4003                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4004         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4005         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4006         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4007
4008         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4009         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4010
4011         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4012         buffer[count++] = cpu_to_le32(0);
4013 }
4014
4015 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4016 {
4017         /* clear state block */
4018         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4019                         &adev->gfx.rlc.clear_state_gpu_addr,
4020                         (void **)&adev->gfx.rlc.cs_ptr);
4021
4022         /* jump table block */
4023         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4024                         &adev->gfx.rlc.cp_table_gpu_addr,
4025                         (void **)&adev->gfx.rlc.cp_table_ptr);
4026 }
4027
4028 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4029 {
4030         const struct cs_section_def *cs_data;
4031         int r;
4032
4033         adev->gfx.rlc.cs_data = gfx10_cs_data;
4034
4035         cs_data = adev->gfx.rlc.cs_data;
4036
4037         if (cs_data) {
4038                 /* init clear state block */
4039                 r = amdgpu_gfx_rlc_init_csb(adev);
4040                 if (r)
4041                         return r;
4042         }
4043
4044         /* init spm vmid with 0xf */
4045         if (adev->gfx.rlc.funcs->update_spm_vmid)
4046                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4047
4048         return 0;
4049 }
4050
4051 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4052 {
4053         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4054         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4055 }
4056
4057 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4058 {
4059         int r;
4060
4061         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4062
4063         amdgpu_gfx_graphics_queue_acquire(adev);
4064
4065         r = gfx_v10_0_init_microcode(adev);
4066         if (r)
4067                 DRM_ERROR("Failed to load gfx firmware!\n");
4068
4069         return r;
4070 }
4071
4072 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4073 {
4074         int r;
4075         u32 *hpd;
4076         const __le32 *fw_data = NULL;
4077         unsigned fw_size;
4078         u32 *fw = NULL;
4079         size_t mec_hpd_size;
4080
4081         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4082
4083         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4084
4085         /* take ownership of the relevant compute queues */
4086         amdgpu_gfx_compute_queue_acquire(adev);
4087         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4088
4089         if (mec_hpd_size) {
4090                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4091                                               AMDGPU_GEM_DOMAIN_GTT,
4092                                               &adev->gfx.mec.hpd_eop_obj,
4093                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4094                                               (void **)&hpd);
4095                 if (r) {
4096                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4097                         gfx_v10_0_mec_fini(adev);
4098                         return r;
4099                 }
4100
4101                 memset(hpd, 0, mec_hpd_size);
4102
4103                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4104                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4105         }
4106
4107         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4108                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4109
4110                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4111                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4112                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4113
4114                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4115                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4116                                               &adev->gfx.mec.mec_fw_obj,
4117                                               &adev->gfx.mec.mec_fw_gpu_addr,
4118                                               (void **)&fw);
4119                 if (r) {
4120                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4121                         gfx_v10_0_mec_fini(adev);
4122                         return r;
4123                 }
4124
4125                 memcpy(fw, fw_data, fw_size);
4126
4127                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4128                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4129         }
4130
4131         return 0;
4132 }
4133
4134 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4135 {
4136         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4137                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4138                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4139         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4140 }
4141
4142 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4143                            uint32_t thread, uint32_t regno,
4144                            uint32_t num, uint32_t *out)
4145 {
4146         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4147                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4148                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4149                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4150                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4151         while (num--)
4152                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4153 }
4154
4155 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4156 {
4157         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4158          * field when performing a select_se_sh so it should be
4159          * zero here */
4160         WARN_ON(simd != 0);
4161
4162         /* type 2 wave data */
4163         dst[(*no_fields)++] = 2;
4164         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4165         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4166         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4167         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4168         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4169         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4170         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4171         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4172         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4173         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4174         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4175         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4176         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4177         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4178         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4179 }
4180
4181 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4182                                      uint32_t wave, uint32_t start,
4183                                      uint32_t size, uint32_t *dst)
4184 {
4185         WARN_ON(simd != 0);
4186
4187         wave_read_regs(
4188                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4189                 dst);
4190 }
4191
4192 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4193                                       uint32_t wave, uint32_t thread,
4194                                       uint32_t start, uint32_t size,
4195                                       uint32_t *dst)
4196 {
4197         wave_read_regs(
4198                 adev, wave, thread,
4199                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4200 }
4201
4202 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4203                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4204  {
4205        nv_grbm_select(adev, me, pipe, q, vm);
4206  }
4207
4208
4209 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4210         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4211         .select_se_sh = &gfx_v10_0_select_se_sh,
4212         .read_wave_data = &gfx_v10_0_read_wave_data,
4213         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4214         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4215         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4216         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4217 };
4218
4219 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4220 {
4221         u32 gb_addr_config;
4222
4223         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4224
4225         switch (adev->asic_type) {
4226         case CHIP_NAVI10:
4227         case CHIP_NAVI14:
4228         case CHIP_NAVI12:
4229                 adev->gfx.config.max_hw_contexts = 8;
4230                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4231                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4232                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4233                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4234                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4235                 break;
4236         case CHIP_SIENNA_CICHLID:
4237         case CHIP_NAVY_FLOUNDER:
4238                 adev->gfx.config.max_hw_contexts = 8;
4239                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4240                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4241                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4242                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4243                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4244                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4245                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4246                 break;
4247         default:
4248                 BUG();
4249                 break;
4250         }
4251
4252         adev->gfx.config.gb_addr_config = gb_addr_config;
4253
4254         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4255                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4256                                       GB_ADDR_CONFIG, NUM_PIPES);
4257
4258         adev->gfx.config.max_tile_pipes =
4259                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4260
4261         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4262                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4263                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4264         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4265                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4266                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4267         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4268                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4269                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4270         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4271                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4272                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4273 }
4274
4275 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4276                                    int me, int pipe, int queue)
4277 {
4278         int r;
4279         struct amdgpu_ring *ring;
4280         unsigned int irq_type;
4281
4282         ring = &adev->gfx.gfx_ring[ring_id];
4283
4284         ring->me = me;
4285         ring->pipe = pipe;
4286         ring->queue = queue;
4287
4288         ring->ring_obj = NULL;
4289         ring->use_doorbell = true;
4290
4291         if (!ring_id)
4292                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4293         else
4294                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4295         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4296
4297         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4298         r = amdgpu_ring_init(adev, ring, 1024,
4299                              &adev->gfx.eop_irq, irq_type,
4300                              AMDGPU_RING_PRIO_DEFAULT);
4301         if (r)
4302                 return r;
4303         return 0;
4304 }
4305
4306 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4307                                        int mec, int pipe, int queue)
4308 {
4309         int r;
4310         unsigned irq_type;
4311         struct amdgpu_ring *ring;
4312         unsigned int hw_prio;
4313
4314         ring = &adev->gfx.compute_ring[ring_id];
4315
4316         /* mec0 is me1 */
4317         ring->me = mec + 1;
4318         ring->pipe = pipe;
4319         ring->queue = queue;
4320
4321         ring->ring_obj = NULL;
4322         ring->use_doorbell = true;
4323         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4324         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4325                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4326         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4327
4328         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4329                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4330                 + ring->pipe;
4331         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4332                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4333         /* type-2 packets are deprecated on MEC, use type-3 instead */
4334         r = amdgpu_ring_init(adev, ring, 1024,
4335                              &adev->gfx.eop_irq, irq_type, hw_prio);
4336         if (r)
4337                 return r;
4338
4339         return 0;
4340 }
4341
4342 static int gfx_v10_0_sw_init(void *handle)
4343 {
4344         int i, j, k, r, ring_id = 0;
4345         struct amdgpu_kiq *kiq;
4346         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4347
4348         switch (adev->asic_type) {
4349         case CHIP_NAVI10:
4350         case CHIP_NAVI14:
4351         case CHIP_NAVI12:
4352                 adev->gfx.me.num_me = 1;
4353                 adev->gfx.me.num_pipe_per_me = 1;
4354                 adev->gfx.me.num_queue_per_pipe = 1;
4355                 adev->gfx.mec.num_mec = 2;
4356                 adev->gfx.mec.num_pipe_per_mec = 4;
4357                 adev->gfx.mec.num_queue_per_pipe = 8;
4358                 break;
4359         case CHIP_SIENNA_CICHLID:
4360         case CHIP_NAVY_FLOUNDER:
4361                 adev->gfx.me.num_me = 1;
4362                 adev->gfx.me.num_pipe_per_me = 1;
4363                 adev->gfx.me.num_queue_per_pipe = 1;
4364                 adev->gfx.mec.num_mec = 2;
4365                 adev->gfx.mec.num_pipe_per_mec = 4;
4366                 adev->gfx.mec.num_queue_per_pipe = 4;
4367                 break;
4368         default:
4369                 adev->gfx.me.num_me = 1;
4370                 adev->gfx.me.num_pipe_per_me = 1;
4371                 adev->gfx.me.num_queue_per_pipe = 1;
4372                 adev->gfx.mec.num_mec = 1;
4373                 adev->gfx.mec.num_pipe_per_mec = 4;
4374                 adev->gfx.mec.num_queue_per_pipe = 8;
4375                 break;
4376         }
4377
4378         /* KIQ event */
4379         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4380                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4381                               &adev->gfx.kiq.irq);
4382         if (r)
4383                 return r;
4384
4385         /* EOP Event */
4386         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4387                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4388                               &adev->gfx.eop_irq);
4389         if (r)
4390                 return r;
4391
4392         /* Privileged reg */
4393         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4394                               &adev->gfx.priv_reg_irq);
4395         if (r)
4396                 return r;
4397
4398         /* Privileged inst */
4399         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4400                               &adev->gfx.priv_inst_irq);
4401         if (r)
4402                 return r;
4403
4404         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4405
4406         gfx_v10_0_scratch_init(adev);
4407
4408         r = gfx_v10_0_me_init(adev);
4409         if (r)
4410                 return r;
4411
4412         r = gfx_v10_0_rlc_init(adev);
4413         if (r) {
4414                 DRM_ERROR("Failed to init rlc BOs!\n");
4415                 return r;
4416         }
4417
4418         r = gfx_v10_0_mec_init(adev);
4419         if (r) {
4420                 DRM_ERROR("Failed to init MEC BOs!\n");
4421                 return r;
4422         }
4423
4424         /* set up the gfx ring */
4425         for (i = 0; i < adev->gfx.me.num_me; i++) {
4426                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4427                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4428                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4429                                         continue;
4430
4431                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4432                                                             i, k, j);
4433                                 if (r)
4434                                         return r;
4435                                 ring_id++;
4436                         }
4437                 }
4438         }
4439
4440         ring_id = 0;
4441         /* set up the compute queues - allocate horizontally across pipes */
4442         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4443                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4444                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4445                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4446                                                                      j))
4447                                         continue;
4448
4449                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4450                                                                 i, k, j);
4451                                 if (r)
4452                                         return r;
4453
4454                                 ring_id++;
4455                         }
4456                 }
4457         }
4458
4459         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4460         if (r) {
4461                 DRM_ERROR("Failed to init KIQ BOs!\n");
4462                 return r;
4463         }
4464
4465         kiq = &adev->gfx.kiq;
4466         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4467         if (r)
4468                 return r;
4469
4470         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4471         if (r)
4472                 return r;
4473
4474         /* allocate visible FB for rlc auto-loading fw */
4475         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4476                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4477                 if (r)
4478                         return r;
4479         }
4480
4481         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4482
4483         gfx_v10_0_gpu_early_init(adev);
4484
4485         return 0;
4486 }
4487
4488 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4489 {
4490         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4491                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4492                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4493 }
4494
4495 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4496 {
4497         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4498                               &adev->gfx.ce.ce_fw_gpu_addr,
4499                               (void **)&adev->gfx.ce.ce_fw_ptr);
4500 }
4501
4502 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4503 {
4504         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4505                               &adev->gfx.me.me_fw_gpu_addr,
4506                               (void **)&adev->gfx.me.me_fw_ptr);
4507 }
4508
4509 static int gfx_v10_0_sw_fini(void *handle)
4510 {
4511         int i;
4512         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4513
4514         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4515                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4516         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4517                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4518
4519         amdgpu_gfx_mqd_sw_fini(adev);
4520         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4521         amdgpu_gfx_kiq_fini(adev);
4522
4523         gfx_v10_0_pfp_fini(adev);
4524         gfx_v10_0_ce_fini(adev);
4525         gfx_v10_0_me_fini(adev);
4526         gfx_v10_0_rlc_fini(adev);
4527         gfx_v10_0_mec_fini(adev);
4528
4529         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4530                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4531
4532         gfx_v10_0_free_microcode(adev);
4533
4534         return 0;
4535 }
4536
4537 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4538                                    u32 sh_num, u32 instance)
4539 {
4540         u32 data;
4541
4542         if (instance == 0xffffffff)
4543                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4544                                      INSTANCE_BROADCAST_WRITES, 1);
4545         else
4546                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4547                                      instance);
4548
4549         if (se_num == 0xffffffff)
4550                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4551                                      1);
4552         else
4553                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4554
4555         if (sh_num == 0xffffffff)
4556                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4557                                      1);
4558         else
4559                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4560
4561         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4562 }
4563
4564 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4565 {
4566         u32 data, mask;
4567
4568         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4569         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4570
4571         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4572         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4573
4574         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4575                                          adev->gfx.config.max_sh_per_se);
4576
4577         return (~data) & mask;
4578 }
4579
4580 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4581 {
4582         int i, j;
4583         u32 data;
4584         u32 active_rbs = 0;
4585         u32 bitmap;
4586         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4587                                         adev->gfx.config.max_sh_per_se;
4588
4589         mutex_lock(&adev->grbm_idx_mutex);
4590         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4591                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4592                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4593                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4594                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4595                                 continue;
4596                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4597                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4598                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4599                                                rb_bitmap_width_per_sh);
4600                 }
4601         }
4602         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4603         mutex_unlock(&adev->grbm_idx_mutex);
4604
4605         adev->gfx.config.backend_enable_mask = active_rbs;
4606         adev->gfx.config.num_rbs = hweight32(active_rbs);
4607 }
4608
4609 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4610 {
4611         uint32_t num_sc;
4612         uint32_t enabled_rb_per_sh;
4613         uint32_t active_rb_bitmap;
4614         uint32_t num_rb_per_sc;
4615         uint32_t num_packer_per_sc;
4616         uint32_t pa_sc_tile_steering_override;
4617
4618         /* for ASICs that integrates GFX v10.3
4619          * pa_sc_tile_steering_override should be set to 0 */
4620         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4621             adev->asic_type == CHIP_NAVY_FLOUNDER)
4622                 return 0;
4623
4624         /* init num_sc */
4625         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4626                         adev->gfx.config.num_sc_per_sh;
4627         /* init num_rb_per_sc */
4628         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4629         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4630         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4631         /* init num_packer_per_sc */
4632         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4633
4634         pa_sc_tile_steering_override = 0;
4635         pa_sc_tile_steering_override |=
4636                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4637                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4638         pa_sc_tile_steering_override |=
4639                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4640                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4641         pa_sc_tile_steering_override |=
4642                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4643                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4644
4645         return pa_sc_tile_steering_override;
4646 }
4647
4648 #define DEFAULT_SH_MEM_BASES    (0x6000)
4649
4650 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4651 {
4652         int i;
4653         uint32_t sh_mem_bases;
4654
4655         /*
4656          * Configure apertures:
4657          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4658          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4659          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4660          */
4661         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4662
4663         mutex_lock(&adev->srbm_mutex);
4664         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4665                 nv_grbm_select(adev, 0, 0, 0, i);
4666                 /* CP and shaders */
4667                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4668                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4669         }
4670         nv_grbm_select(adev, 0, 0, 0, 0);
4671         mutex_unlock(&adev->srbm_mutex);
4672
4673         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4674            acccess. These should be enabled by FW for target VMIDs. */
4675         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4676                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4677                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4678                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4679                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4680         }
4681 }
4682
4683 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4684 {
4685         int vmid;
4686
4687         /*
4688          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4689          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4690          * the driver can enable them for graphics. VMID0 should maintain
4691          * access so that HWS firmware can save/restore entries.
4692          */
4693         for (vmid = 1; vmid < 16; vmid++) {
4694                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4695                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4696                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4697                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4698         }
4699 }
4700
4701
4702 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4703 {
4704         int i, j, k;
4705         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4706         u32 tmp, wgp_active_bitmap = 0;
4707         u32 gcrd_targets_disable_tcp = 0;
4708         u32 utcl_invreq_disable = 0;
4709         /*
4710          * GCRD_TARGETS_DISABLE field contains
4711          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4712          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4713          */
4714         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4715                 2 * max_wgp_per_sh + /* TCP */
4716                 max_wgp_per_sh + /* SQC */
4717                 4); /* GL1C */
4718         /*
4719          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4720          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4721          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4722          */
4723         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4724                 2 * max_wgp_per_sh + /* TCP */
4725                 2 * max_wgp_per_sh + /* SQC */
4726                 4 + /* RMI */
4727                 1); /* SQG */
4728
4729         if (adev->asic_type == CHIP_NAVI10 ||
4730             adev->asic_type == CHIP_NAVI14 ||
4731             adev->asic_type == CHIP_NAVI12) {
4732                 mutex_lock(&adev->grbm_idx_mutex);
4733                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4734                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4735                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4736                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4737                                 /*
4738                                  * Set corresponding TCP bits for the inactive WGPs in
4739                                  * GCRD_SA_TARGETS_DISABLE
4740                                  */
4741                                 gcrd_targets_disable_tcp = 0;
4742                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4743                                 utcl_invreq_disable = 0;
4744
4745                                 for (k = 0; k < max_wgp_per_sh; k++) {
4746                                         if (!(wgp_active_bitmap & (1 << k))) {
4747                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4748                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4749                                                         (3 << (2 * (max_wgp_per_sh + k)));
4750                                         }
4751                                 }
4752
4753                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4754                                 /* only override TCP & SQC bits */
4755                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4756                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4757                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4758
4759                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4760                                 /* only override TCP bits */
4761                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4762                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4763                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4764                         }
4765                 }
4766
4767                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4768                 mutex_unlock(&adev->grbm_idx_mutex);
4769         }
4770 }
4771
4772 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4773 {
4774         /* TCCs are global (not instanced). */
4775         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4776                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4777
4778         adev->gfx.config.tcc_disabled_mask =
4779                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4780                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4781 }
4782
4783 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4784 {
4785         u32 tmp;
4786         int i;
4787
4788         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4789
4790         gfx_v10_0_setup_rb(adev);
4791         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4792         gfx_v10_0_get_tcc_info(adev);
4793         adev->gfx.config.pa_sc_tile_steering_override =
4794                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4795
4796         /* XXX SH_MEM regs */
4797         /* where to put LDS, scratch, GPUVM in FSA64 space */
4798         mutex_lock(&adev->srbm_mutex);
4799         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4800                 nv_grbm_select(adev, 0, 0, 0, i);
4801                 /* CP and shaders */
4802                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4803                 if (i != 0) {
4804                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4805                                 (adev->gmc.private_aperture_start >> 48));
4806                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4807                                 (adev->gmc.shared_aperture_start >> 48));
4808                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4809                 }
4810         }
4811         nv_grbm_select(adev, 0, 0, 0, 0);
4812
4813         mutex_unlock(&adev->srbm_mutex);
4814
4815         gfx_v10_0_init_compute_vmid(adev);
4816         gfx_v10_0_init_gds_vmid(adev);
4817
4818 }
4819
4820 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4821                                                bool enable)
4822 {
4823         u32 tmp;
4824
4825         if (amdgpu_sriov_vf(adev))
4826                 return;
4827
4828         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4829
4830         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4831                             enable ? 1 : 0);
4832         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4833                             enable ? 1 : 0);
4834         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4835                             enable ? 1 : 0);
4836         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4837                             enable ? 1 : 0);
4838
4839         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4840 }
4841
4842 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4843 {
4844         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4845
4846         /* csib */
4847         if (adev->asic_type == CHIP_NAVI12) {
4848                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4849                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4850                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4851                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4852                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4853         } else {
4854                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4855                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4856                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4857                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4858                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4859         }
4860         return 0;
4861 }
4862
4863 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4864 {
4865         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4866
4867         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4868         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4869 }
4870
4871 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4872 {
4873         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4874         udelay(50);
4875         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4876         udelay(50);
4877 }
4878
4879 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4880                                              bool enable)
4881 {
4882         uint32_t rlc_pg_cntl;
4883
4884         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4885
4886         if (!enable) {
4887                 /* RLC_PG_CNTL[23] = 0 (default)
4888                  * RLC will wait for handshake acks with SMU
4889                  * GFXOFF will be enabled
4890                  * RLC_PG_CNTL[23] = 1
4891                  * RLC will not issue any message to SMU
4892                  * hence no handshake between SMU & RLC
4893                  * GFXOFF will be disabled
4894                  */
4895                 rlc_pg_cntl |= 0x800000;
4896         } else
4897                 rlc_pg_cntl &= ~0x800000;
4898         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4899 }
4900
4901 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4902 {
4903         /* TODO: enable rlc & smu handshake until smu
4904          * and gfxoff feature works as expected */
4905         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4906                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4907
4908         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4909         udelay(50);
4910 }
4911
4912 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4913 {
4914         uint32_t tmp;
4915
4916         /* enable Save Restore Machine */
4917         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4918         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4919         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4920         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4921 }
4922
4923 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4924 {
4925         const struct rlc_firmware_header_v2_0 *hdr;
4926         const __le32 *fw_data;
4927         unsigned i, fw_size;
4928
4929         if (!adev->gfx.rlc_fw)
4930                 return -EINVAL;
4931
4932         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4933         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4934
4935         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4936                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4937         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4938
4939         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4940                      RLCG_UCODE_LOADING_START_ADDRESS);
4941
4942         for (i = 0; i < fw_size; i++)
4943                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4944                              le32_to_cpup(fw_data++));
4945
4946         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4947
4948         return 0;
4949 }
4950
4951 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4952 {
4953         int r;
4954
4955         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4956
4957                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4958                 if (r)
4959                         return r;
4960
4961                 gfx_v10_0_init_csb(adev);
4962
4963                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4964                         gfx_v10_0_rlc_enable_srm(adev);
4965         } else {
4966                 if (amdgpu_sriov_vf(adev)) {
4967                         gfx_v10_0_init_csb(adev);
4968                         return 0;
4969                 }
4970
4971                 adev->gfx.rlc.funcs->stop(adev);
4972
4973                 /* disable CG */
4974                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4975
4976                 /* disable PG */
4977                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4978
4979                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4980                         /* legacy rlc firmware loading */
4981                         r = gfx_v10_0_rlc_load_microcode(adev);
4982                         if (r)
4983                                 return r;
4984                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4985                         /* rlc backdoor autoload firmware */
4986                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4987                         if (r)
4988                                 return r;
4989                 }
4990
4991                 gfx_v10_0_init_csb(adev);
4992
4993                 adev->gfx.rlc.funcs->start(adev);
4994
4995                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4996                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4997                         if (r)
4998                                 return r;
4999                 }
5000         }
5001         return 0;
5002 }
5003
5004 static struct {
5005         FIRMWARE_ID     id;
5006         unsigned int    offset;
5007         unsigned int    size;
5008 } rlc_autoload_info[FIRMWARE_ID_MAX];
5009
5010 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5011 {
5012         int ret;
5013         RLC_TABLE_OF_CONTENT *rlc_toc;
5014
5015         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5016                                         AMDGPU_GEM_DOMAIN_GTT,
5017                                         &adev->gfx.rlc.rlc_toc_bo,
5018                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5019                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5020         if (ret) {
5021                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5022                 return ret;
5023         }
5024
5025         /* Copy toc from psp sos fw to rlc toc buffer */
5026         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5027
5028         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5029         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5030                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5031                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5032                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5033                         /* Offset needs 4KB alignment */
5034                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5035                 }
5036
5037                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5038                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5039                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5040
5041                 rlc_toc++;
5042         }
5043
5044         return 0;
5045 }
5046
5047 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5048 {
5049         uint32_t total_size = 0;
5050         FIRMWARE_ID id;
5051         int ret;
5052
5053         ret = gfx_v10_0_parse_rlc_toc(adev);
5054         if (ret) {
5055                 dev_err(adev->dev, "failed to parse rlc toc\n");
5056                 return 0;
5057         }
5058
5059         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5060                 total_size += rlc_autoload_info[id].size;
5061
5062         /* In case the offset in rlc toc ucode is aligned */
5063         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5064                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5065                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5066
5067         return total_size;
5068 }
5069
5070 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5071 {
5072         int r;
5073         uint32_t total_size;
5074
5075         total_size = gfx_v10_0_calc_toc_total_size(adev);
5076
5077         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5078                                       AMDGPU_GEM_DOMAIN_GTT,
5079                                       &adev->gfx.rlc.rlc_autoload_bo,
5080                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5081                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5082         if (r) {
5083                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5084                 return r;
5085         }
5086
5087         return 0;
5088 }
5089
5090 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5091 {
5092         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5093                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5094                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5095         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5096                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5097                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5098 }
5099
5100 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5101                                                        FIRMWARE_ID id,
5102                                                        const void *fw_data,
5103                                                        uint32_t fw_size)
5104 {
5105         uint32_t toc_offset;
5106         uint32_t toc_fw_size;
5107         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5108
5109         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5110                 return;
5111
5112         toc_offset = rlc_autoload_info[id].offset;
5113         toc_fw_size = rlc_autoload_info[id].size;
5114
5115         if (fw_size == 0)
5116                 fw_size = toc_fw_size;
5117
5118         if (fw_size > toc_fw_size)
5119                 fw_size = toc_fw_size;
5120
5121         memcpy(ptr + toc_offset, fw_data, fw_size);
5122
5123         if (fw_size < toc_fw_size)
5124                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5125 }
5126
5127 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5128 {
5129         void *data;
5130         uint32_t size;
5131
5132         data = adev->gfx.rlc.rlc_toc_buf;
5133         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5134
5135         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5136                                                    FIRMWARE_ID_RLC_TOC,
5137                                                    data, size);
5138 }
5139
5140 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5141 {
5142         const __le32 *fw_data;
5143         uint32_t fw_size;
5144         const struct gfx_firmware_header_v1_0 *cp_hdr;
5145         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5146
5147         /* pfp ucode */
5148         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5149                 adev->gfx.pfp_fw->data;
5150         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5151                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5152         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5153         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5154                                                    FIRMWARE_ID_CP_PFP,
5155                                                    fw_data, fw_size);
5156
5157         /* ce ucode */
5158         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5159                 adev->gfx.ce_fw->data;
5160         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5161                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5162         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5163         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5164                                                    FIRMWARE_ID_CP_CE,
5165                                                    fw_data, fw_size);
5166
5167         /* me ucode */
5168         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5169                 adev->gfx.me_fw->data;
5170         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5171                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5172         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5173         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5174                                                    FIRMWARE_ID_CP_ME,
5175                                                    fw_data, fw_size);
5176
5177         /* rlc ucode */
5178         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5179                 adev->gfx.rlc_fw->data;
5180         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5181                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5182         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5183         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5184                                                    FIRMWARE_ID_RLC_G_UCODE,
5185                                                    fw_data, fw_size);
5186
5187         /* mec1 ucode */
5188         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5189                 adev->gfx.mec_fw->data;
5190         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5191                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5192         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5193                 cp_hdr->jt_size * 4;
5194         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5195                                                    FIRMWARE_ID_CP_MEC,
5196                                                    fw_data, fw_size);
5197         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5198 }
5199
5200 /* Temporarily put sdma part here */
5201 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5202 {
5203         const __le32 *fw_data;
5204         uint32_t fw_size;
5205         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5206         int i;
5207
5208         for (i = 0; i < adev->sdma.num_instances; i++) {
5209                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5210                         adev->sdma.instance[i].fw->data;
5211                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5212                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5213                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5214
5215                 if (i == 0) {
5216                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5217                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5218                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5219                                 FIRMWARE_ID_SDMA0_JT,
5220                                 (uint32_t *)fw_data +
5221                                 sdma_hdr->jt_offset,
5222                                 sdma_hdr->jt_size * 4);
5223                 } else if (i == 1) {
5224                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5225                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5226                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5227                                 FIRMWARE_ID_SDMA1_JT,
5228                                 (uint32_t *)fw_data +
5229                                 sdma_hdr->jt_offset,
5230                                 sdma_hdr->jt_size * 4);
5231                 }
5232         }
5233 }
5234
5235 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5236 {
5237         uint32_t rlc_g_offset, rlc_g_size, tmp;
5238         uint64_t gpu_addr;
5239
5240         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5241         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5242         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5243
5244         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5245         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5246         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5247
5248         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5249         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5250         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5251
5252         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5253         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5254                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5255                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5256                 return -EINVAL;
5257         }
5258
5259         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5260         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5261                 DRM_ERROR("RLC ROM should halt itself\n");
5262                 return -EINVAL;
5263         }
5264
5265         return 0;
5266 }
5267
5268 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5269 {
5270         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5271         uint32_t tmp;
5272         int i;
5273         uint64_t addr;
5274
5275         /* Trigger an invalidation of the L1 instruction caches */
5276         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5277         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5278         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5279
5280         /* Wait for invalidation complete */
5281         for (i = 0; i < usec_timeout; i++) {
5282                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5283                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5284                         INVALIDATE_CACHE_COMPLETE))
5285                         break;
5286                 udelay(1);
5287         }
5288
5289         if (i >= usec_timeout) {
5290                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5291                 return -EINVAL;
5292         }
5293
5294         /* Program me ucode address into intruction cache address register */
5295         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5296                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5297         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5298                         lower_32_bits(addr) & 0xFFFFF000);
5299         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5300                         upper_32_bits(addr));
5301
5302         return 0;
5303 }
5304
5305 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5306 {
5307         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5308         uint32_t tmp;
5309         int i;
5310         uint64_t addr;
5311
5312         /* Trigger an invalidation of the L1 instruction caches */
5313         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5314         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5315         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5316
5317         /* Wait for invalidation complete */
5318         for (i = 0; i < usec_timeout; i++) {
5319                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5320                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5321                         INVALIDATE_CACHE_COMPLETE))
5322                         break;
5323                 udelay(1);
5324         }
5325
5326         if (i >= usec_timeout) {
5327                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5328                 return -EINVAL;
5329         }
5330
5331         /* Program ce ucode address into intruction cache address register */
5332         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5333                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5334         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5335                         lower_32_bits(addr) & 0xFFFFF000);
5336         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5337                         upper_32_bits(addr));
5338
5339         return 0;
5340 }
5341
5342 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5343 {
5344         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5345         uint32_t tmp;
5346         int i;
5347         uint64_t addr;
5348
5349         /* Trigger an invalidation of the L1 instruction caches */
5350         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5351         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5352         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5353
5354         /* Wait for invalidation complete */
5355         for (i = 0; i < usec_timeout; i++) {
5356                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5357                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5358                         INVALIDATE_CACHE_COMPLETE))
5359                         break;
5360                 udelay(1);
5361         }
5362
5363         if (i >= usec_timeout) {
5364                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5365                 return -EINVAL;
5366         }
5367
5368         /* Program pfp ucode address into intruction cache address register */
5369         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5370                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5371         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5372                         lower_32_bits(addr) & 0xFFFFF000);
5373         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5374                         upper_32_bits(addr));
5375
5376         return 0;
5377 }
5378
5379 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5380 {
5381         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5382         uint32_t tmp;
5383         int i;
5384         uint64_t addr;
5385
5386         /* Trigger an invalidation of the L1 instruction caches */
5387         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5388         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5389         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5390
5391         /* Wait for invalidation complete */
5392         for (i = 0; i < usec_timeout; i++) {
5393                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5394                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5395                         INVALIDATE_CACHE_COMPLETE))
5396                         break;
5397                 udelay(1);
5398         }
5399
5400         if (i >= usec_timeout) {
5401                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5402                 return -EINVAL;
5403         }
5404
5405         /* Program mec1 ucode address into intruction cache address register */
5406         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5407                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5408         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5409                         lower_32_bits(addr) & 0xFFFFF000);
5410         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5411                         upper_32_bits(addr));
5412
5413         return 0;
5414 }
5415
5416 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5417 {
5418         uint32_t cp_status;
5419         uint32_t bootload_status;
5420         int i, r;
5421
5422         for (i = 0; i < adev->usec_timeout; i++) {
5423                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5424                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5425                 if ((cp_status == 0) &&
5426                     (REG_GET_FIELD(bootload_status,
5427                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5428                         break;
5429                 }
5430                 udelay(1);
5431         }
5432
5433         if (i >= adev->usec_timeout) {
5434                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5435                 return -ETIMEDOUT;
5436         }
5437
5438         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5439                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5440                 if (r)
5441                         return r;
5442
5443                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5444                 if (r)
5445                         return r;
5446
5447                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5448                 if (r)
5449                         return r;
5450
5451                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5452                 if (r)
5453                         return r;
5454         }
5455
5456         return 0;
5457 }
5458
5459 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5460 {
5461         int i;
5462         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5463
5464         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5465         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5466         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5467
5468         if (adev->asic_type == CHIP_NAVI12) {
5469                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5470         } else {
5471                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5472         }
5473
5474         for (i = 0; i < adev->usec_timeout; i++) {
5475                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5476                         break;
5477                 udelay(1);
5478         }
5479
5480         if (i >= adev->usec_timeout)
5481                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5482
5483         return 0;
5484 }
5485
5486 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5487 {
5488         int r;
5489         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5490         const __le32 *fw_data;
5491         unsigned i, fw_size;
5492         uint32_t tmp;
5493         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5494
5495         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5496                 adev->gfx.pfp_fw->data;
5497
5498         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5499
5500         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5501                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5502         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5503
5504         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5505                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5506                                       &adev->gfx.pfp.pfp_fw_obj,
5507                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5508                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5509         if (r) {
5510                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5511                 gfx_v10_0_pfp_fini(adev);
5512                 return r;
5513         }
5514
5515         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5516
5517         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5518         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5519
5520         /* Trigger an invalidation of the L1 instruction caches */
5521         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5522         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5523         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5524
5525         /* Wait for invalidation complete */
5526         for (i = 0; i < usec_timeout; i++) {
5527                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5528                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5529                         INVALIDATE_CACHE_COMPLETE))
5530                         break;
5531                 udelay(1);
5532         }
5533
5534         if (i >= usec_timeout) {
5535                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5536                 return -EINVAL;
5537         }
5538
5539         if (amdgpu_emu_mode == 1)
5540                 adev->nbio.funcs->hdp_flush(adev, NULL);
5541
5542         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5543         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5544         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5545         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5546         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5547         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5548         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5549                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5550         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5551                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5552
5553         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5554
5555         for (i = 0; i < pfp_hdr->jt_size; i++)
5556                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5557                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5558
5559         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5560
5561         return 0;
5562 }
5563
5564 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5565 {
5566         int r;
5567         const struct gfx_firmware_header_v1_0 *ce_hdr;
5568         const __le32 *fw_data;
5569         unsigned i, fw_size;
5570         uint32_t tmp;
5571         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5572
5573         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5574                 adev->gfx.ce_fw->data;
5575
5576         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5577
5578         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5579                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5580         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5581
5582         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5583                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5584                                       &adev->gfx.ce.ce_fw_obj,
5585                                       &adev->gfx.ce.ce_fw_gpu_addr,
5586                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5587         if (r) {
5588                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5589                 gfx_v10_0_ce_fini(adev);
5590                 return r;
5591         }
5592
5593         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5594
5595         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5596         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5597
5598         /* Trigger an invalidation of the L1 instruction caches */
5599         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5600         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5601         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5602
5603         /* Wait for invalidation complete */
5604         for (i = 0; i < usec_timeout; i++) {
5605                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5606                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5607                         INVALIDATE_CACHE_COMPLETE))
5608                         break;
5609                 udelay(1);
5610         }
5611
5612         if (i >= usec_timeout) {
5613                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5614                 return -EINVAL;
5615         }
5616
5617         if (amdgpu_emu_mode == 1)
5618                 adev->nbio.funcs->hdp_flush(adev, NULL);
5619
5620         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5621         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5622         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5623         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5624         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5625         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5626                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5627         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5628                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5629
5630         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5631
5632         for (i = 0; i < ce_hdr->jt_size; i++)
5633                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5634                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5635
5636         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5637
5638         return 0;
5639 }
5640
5641 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5642 {
5643         int r;
5644         const struct gfx_firmware_header_v1_0 *me_hdr;
5645         const __le32 *fw_data;
5646         unsigned i, fw_size;
5647         uint32_t tmp;
5648         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5649
5650         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5651                 adev->gfx.me_fw->data;
5652
5653         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5654
5655         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5656                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5657         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5658
5659         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5660                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5661                                       &adev->gfx.me.me_fw_obj,
5662                                       &adev->gfx.me.me_fw_gpu_addr,
5663                                       (void **)&adev->gfx.me.me_fw_ptr);
5664         if (r) {
5665                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5666                 gfx_v10_0_me_fini(adev);
5667                 return r;
5668         }
5669
5670         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5671
5672         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5673         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5674
5675         /* Trigger an invalidation of the L1 instruction caches */
5676         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5677         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5678         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5679
5680         /* Wait for invalidation complete */
5681         for (i = 0; i < usec_timeout; i++) {
5682                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5683                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5684                         INVALIDATE_CACHE_COMPLETE))
5685                         break;
5686                 udelay(1);
5687         }
5688
5689         if (i >= usec_timeout) {
5690                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5691                 return -EINVAL;
5692         }
5693
5694         if (amdgpu_emu_mode == 1)
5695                 adev->nbio.funcs->hdp_flush(adev, NULL);
5696
5697         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5698         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5699         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5700         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5701         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5702         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5703                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5704         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5705                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5706
5707         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5708
5709         for (i = 0; i < me_hdr->jt_size; i++)
5710                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5711                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5712
5713         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5714
5715         return 0;
5716 }
5717
5718 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5719 {
5720         int r;
5721
5722         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5723                 return -EINVAL;
5724
5725         gfx_v10_0_cp_gfx_enable(adev, false);
5726
5727         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5728         if (r) {
5729                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5730                 return r;
5731         }
5732
5733         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5734         if (r) {
5735                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5736                 return r;
5737         }
5738
5739         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5740         if (r) {
5741                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5742                 return r;
5743         }
5744
5745         return 0;
5746 }
5747
5748 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5749 {
5750         struct amdgpu_ring *ring;
5751         const struct cs_section_def *sect = NULL;
5752         const struct cs_extent_def *ext = NULL;
5753         int r, i;
5754         int ctx_reg_offset;
5755
5756         /* init the CP */
5757         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5758                      adev->gfx.config.max_hw_contexts - 1);
5759         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5760
5761         gfx_v10_0_cp_gfx_enable(adev, true);
5762
5763         ring = &adev->gfx.gfx_ring[0];
5764         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5765         if (r) {
5766                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5767                 return r;
5768         }
5769
5770         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5771         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5772
5773         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5774         amdgpu_ring_write(ring, 0x80000000);
5775         amdgpu_ring_write(ring, 0x80000000);
5776
5777         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5778                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5779                         if (sect->id == SECT_CONTEXT) {
5780                                 amdgpu_ring_write(ring,
5781                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5782                                                           ext->reg_count));
5783                                 amdgpu_ring_write(ring, ext->reg_index -
5784                                                   PACKET3_SET_CONTEXT_REG_START);
5785                                 for (i = 0; i < ext->reg_count; i++)
5786                                         amdgpu_ring_write(ring, ext->extent[i]);
5787                         }
5788                 }
5789         }
5790
5791         ctx_reg_offset =
5792                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5793         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5794         amdgpu_ring_write(ring, ctx_reg_offset);
5795         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5796
5797         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5798         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5799
5800         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5801         amdgpu_ring_write(ring, 0);
5802
5803         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5804         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5805         amdgpu_ring_write(ring, 0x8000);
5806         amdgpu_ring_write(ring, 0x8000);
5807
5808         amdgpu_ring_commit(ring);
5809
5810         /* submit cs packet to copy state 0 to next available state */
5811         if (adev->gfx.num_gfx_rings > 1) {
5812                 /* maximum supported gfx ring is 2 */
5813                 ring = &adev->gfx.gfx_ring[1];
5814                 r = amdgpu_ring_alloc(ring, 2);
5815                 if (r) {
5816                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5817                         return r;
5818                 }
5819
5820                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5821                 amdgpu_ring_write(ring, 0);
5822
5823                 amdgpu_ring_commit(ring);
5824         }
5825         return 0;
5826 }
5827
5828 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5829                                          CP_PIPE_ID pipe)
5830 {
5831         u32 tmp;
5832
5833         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5834         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5835
5836         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5837 }
5838
5839 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5840                                           struct amdgpu_ring *ring)
5841 {
5842         u32 tmp;
5843
5844         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5845         if (ring->use_doorbell) {
5846                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5847                                     DOORBELL_OFFSET, ring->doorbell_index);
5848                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5849                                     DOORBELL_EN, 1);
5850         } else {
5851                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5852                                     DOORBELL_EN, 0);
5853         }
5854         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5855         switch (adev->asic_type) {
5856         case CHIP_SIENNA_CICHLID:
5857         case CHIP_NAVY_FLOUNDER:
5858                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5859                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5860                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5861
5862                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5863                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5864                 break;
5865         default:
5866                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5867                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5868                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5869
5870                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5871                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5872                 break;
5873         }
5874 }
5875
5876 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5877 {
5878         struct amdgpu_ring *ring;
5879         u32 tmp;
5880         u32 rb_bufsz;
5881         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5882         u32 i;
5883
5884         /* Set the write pointer delay */
5885         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5886
5887         /* set the RB to use vmid 0 */
5888         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5889
5890         /* Init gfx ring 0 for pipe 0 */
5891         mutex_lock(&adev->srbm_mutex);
5892         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5893
5894         /* Set ring buffer size */
5895         ring = &adev->gfx.gfx_ring[0];
5896         rb_bufsz = order_base_2(ring->ring_size / 8);
5897         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5898         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5899 #ifdef __BIG_ENDIAN
5900         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5901 #endif
5902         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5903
5904         /* Initialize the ring buffer's write pointers */
5905         ring->wptr = 0;
5906         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5907         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5908
5909         /* set the wb address wether it's enabled or not */
5910         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5911         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5912         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5913                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5914
5915         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5916         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5917                      lower_32_bits(wptr_gpu_addr));
5918         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5919                      upper_32_bits(wptr_gpu_addr));
5920
5921         mdelay(1);
5922         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5923
5924         rb_addr = ring->gpu_addr >> 8;
5925         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5926         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5927
5928         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5929
5930         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5931         mutex_unlock(&adev->srbm_mutex);
5932
5933         /* Init gfx ring 1 for pipe 1 */
5934         if (adev->gfx.num_gfx_rings > 1) {
5935                 mutex_lock(&adev->srbm_mutex);
5936                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5937                 /* maximum supported gfx ring is 2 */
5938                 ring = &adev->gfx.gfx_ring[1];
5939                 rb_bufsz = order_base_2(ring->ring_size / 8);
5940                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5941                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5942                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5943                 /* Initialize the ring buffer's write pointers */
5944                 ring->wptr = 0;
5945                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5946                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5947                 /* Set the wb address wether it's enabled or not */
5948                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5949                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5950                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5951                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5952                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5953                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5954                              lower_32_bits(wptr_gpu_addr));
5955                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5956                              upper_32_bits(wptr_gpu_addr));
5957
5958                 mdelay(1);
5959                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5960
5961                 rb_addr = ring->gpu_addr >> 8;
5962                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5963                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5964                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5965
5966                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5967                 mutex_unlock(&adev->srbm_mutex);
5968         }
5969         /* Switch to pipe 0 */
5970         mutex_lock(&adev->srbm_mutex);
5971         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5972         mutex_unlock(&adev->srbm_mutex);
5973
5974         /* start the ring */
5975         gfx_v10_0_cp_gfx_start(adev);
5976
5977         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5978                 ring = &adev->gfx.gfx_ring[i];
5979                 ring->sched.ready = true;
5980         }
5981
5982         return 0;
5983 }
5984
5985 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5986 {
5987         if (enable) {
5988                 switch (adev->asic_type) {
5989                 case CHIP_SIENNA_CICHLID:
5990                 case CHIP_NAVY_FLOUNDER:
5991                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5992                         break;
5993                 default:
5994                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5995                         break;
5996                 }
5997         } else {
5998                 switch (adev->asic_type) {
5999                 case CHIP_SIENNA_CICHLID:
6000                 case CHIP_NAVY_FLOUNDER:
6001                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6002                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6003                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6004                         break;
6005                 default:
6006                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6007                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6008                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6009                         break;
6010                 }
6011                 adev->gfx.kiq.ring.sched.ready = false;
6012         }
6013         udelay(50);
6014 }
6015
6016 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6017 {
6018         const struct gfx_firmware_header_v1_0 *mec_hdr;
6019         const __le32 *fw_data;
6020         unsigned i;
6021         u32 tmp;
6022         u32 usec_timeout = 50000; /* Wait for 50 ms */
6023
6024         if (!adev->gfx.mec_fw)
6025                 return -EINVAL;
6026
6027         gfx_v10_0_cp_compute_enable(adev, false);
6028
6029         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6030         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6031
6032         fw_data = (const __le32 *)
6033                 (adev->gfx.mec_fw->data +
6034                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6035
6036         /* Trigger an invalidation of the L1 instruction caches */
6037         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6038         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6039         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6040
6041         /* Wait for invalidation complete */
6042         for (i = 0; i < usec_timeout; i++) {
6043                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6044                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6045                                        INVALIDATE_CACHE_COMPLETE))
6046                         break;
6047                 udelay(1);
6048         }
6049
6050         if (i >= usec_timeout) {
6051                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6052                 return -EINVAL;
6053         }
6054
6055         if (amdgpu_emu_mode == 1)
6056                 adev->nbio.funcs->hdp_flush(adev, NULL);
6057
6058         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6059         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6060         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6061         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6062         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6063
6064         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6065                      0xFFFFF000);
6066         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6067                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6068
6069         /* MEC1 */
6070         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6071
6072         for (i = 0; i < mec_hdr->jt_size; i++)
6073                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6074                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6075
6076         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6077
6078         /*
6079          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6080          * different microcode than MEC1.
6081          */
6082
6083         return 0;
6084 }
6085
6086 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6087 {
6088         uint32_t tmp;
6089         struct amdgpu_device *adev = ring->adev;
6090
6091         /* tell RLC which is KIQ queue */
6092         switch (adev->asic_type) {
6093         case CHIP_SIENNA_CICHLID:
6094         case CHIP_NAVY_FLOUNDER:
6095                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6096                 tmp &= 0xffffff00;
6097                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6098                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6099                 tmp |= 0x80;
6100                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6101                 break;
6102         default:
6103                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6104                 tmp &= 0xffffff00;
6105                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6106                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6107                 tmp |= 0x80;
6108                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6109                 break;
6110         }
6111 }
6112
6113 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6114 {
6115         struct amdgpu_device *adev = ring->adev;
6116         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6117         uint64_t hqd_gpu_addr, wb_gpu_addr;
6118         uint32_t tmp;
6119         uint32_t rb_bufsz;
6120
6121         /* set up gfx hqd wptr */
6122         mqd->cp_gfx_hqd_wptr = 0;
6123         mqd->cp_gfx_hqd_wptr_hi = 0;
6124
6125         /* set the pointer to the MQD */
6126         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6127         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6128
6129         /* set up mqd control */
6130         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6131         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6132         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6133         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6134         mqd->cp_gfx_mqd_control = tmp;
6135
6136         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6137         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6138         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6139         mqd->cp_gfx_hqd_vmid = 0;
6140
6141         /* set up default queue priority level
6142          * 0x0 = low priority, 0x1 = high priority */
6143         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6144         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6145         mqd->cp_gfx_hqd_queue_priority = tmp;
6146
6147         /* set up time quantum */
6148         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6149         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6150         mqd->cp_gfx_hqd_quantum = tmp;
6151
6152         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6153         hqd_gpu_addr = ring->gpu_addr >> 8;
6154         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6155         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6156
6157         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6158         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6159         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6160         mqd->cp_gfx_hqd_rptr_addr_hi =
6161                 upper_32_bits(wb_gpu_addr) & 0xffff;
6162
6163         /* set up rb_wptr_poll addr */
6164         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6165         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6166         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6167
6168         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6169         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6170         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6171         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6172         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6173 #ifdef __BIG_ENDIAN
6174         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6175 #endif
6176         mqd->cp_gfx_hqd_cntl = tmp;
6177
6178         /* set up cp_doorbell_control */
6179         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6180         if (ring->use_doorbell) {
6181                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6182                                     DOORBELL_OFFSET, ring->doorbell_index);
6183                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6184                                     DOORBELL_EN, 1);
6185         } else
6186                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6187                                     DOORBELL_EN, 0);
6188         mqd->cp_rb_doorbell_control = tmp;
6189
6190         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6191         ring->wptr = 0;
6192         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6193
6194         /* active the queue */
6195         mqd->cp_gfx_hqd_active = 1;
6196
6197         return 0;
6198 }
6199
6200 #ifdef BRING_UP_DEBUG
6201 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6202 {
6203         struct amdgpu_device *adev = ring->adev;
6204         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6205
6206         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6207         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6208         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6209
6210         /* set GFX_MQD_BASE */
6211         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6212         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6213
6214         /* set GFX_MQD_CONTROL */
6215         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6216
6217         /* set GFX_HQD_VMID to 0 */
6218         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6219
6220         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6221                         mqd->cp_gfx_hqd_queue_priority);
6222         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6223
6224         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6225         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6226         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6227
6228         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6229         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6230         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6231
6232         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6233         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6234
6235         /* set RB_WPTR_POLL_ADDR */
6236         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6237         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6238
6239         /* set RB_DOORBELL_CONTROL */
6240         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6241
6242         /* active the queue */
6243         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6244
6245         return 0;
6246 }
6247 #endif
6248
6249 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6250 {
6251         struct amdgpu_device *adev = ring->adev;
6252         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6253         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6254
6255         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6256                 memset((void *)mqd, 0, sizeof(*mqd));
6257                 mutex_lock(&adev->srbm_mutex);
6258                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6259                 gfx_v10_0_gfx_mqd_init(ring);
6260 #ifdef BRING_UP_DEBUG
6261                 gfx_v10_0_gfx_queue_init_register(ring);
6262 #endif
6263                 nv_grbm_select(adev, 0, 0, 0, 0);
6264                 mutex_unlock(&adev->srbm_mutex);
6265                 if (adev->gfx.me.mqd_backup[mqd_idx])
6266                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6267         } else if (amdgpu_in_reset(adev)) {
6268                 /* reset mqd with the backup copy */
6269                 if (adev->gfx.me.mqd_backup[mqd_idx])
6270                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6271                 /* reset the ring */
6272                 ring->wptr = 0;
6273                 adev->wb.wb[ring->wptr_offs] = 0;
6274                 amdgpu_ring_clear_ring(ring);
6275 #ifdef BRING_UP_DEBUG
6276                 mutex_lock(&adev->srbm_mutex);
6277                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6278                 gfx_v10_0_gfx_queue_init_register(ring);
6279                 nv_grbm_select(adev, 0, 0, 0, 0);
6280                 mutex_unlock(&adev->srbm_mutex);
6281 #endif
6282         } else {
6283                 amdgpu_ring_clear_ring(ring);
6284         }
6285
6286         return 0;
6287 }
6288
6289 #ifndef BRING_UP_DEBUG
6290 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6291 {
6292         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6293         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6294         int r, i;
6295
6296         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6297                 return -EINVAL;
6298
6299         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6300                                         adev->gfx.num_gfx_rings);
6301         if (r) {
6302                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6303                 return r;
6304         }
6305
6306         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6307                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6308
6309         return amdgpu_ring_test_helper(kiq_ring);
6310 }
6311 #endif
6312
6313 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6314 {
6315         int r, i;
6316         struct amdgpu_ring *ring;
6317
6318         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6319                 ring = &adev->gfx.gfx_ring[i];
6320
6321                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6322                 if (unlikely(r != 0))
6323                         goto done;
6324
6325                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6326                 if (!r) {
6327                         r = gfx_v10_0_gfx_init_queue(ring);
6328                         amdgpu_bo_kunmap(ring->mqd_obj);
6329                         ring->mqd_ptr = NULL;
6330                 }
6331                 amdgpu_bo_unreserve(ring->mqd_obj);
6332                 if (r)
6333                         goto done;
6334         }
6335 #ifndef BRING_UP_DEBUG
6336         r = gfx_v10_0_kiq_enable_kgq(adev);
6337         if (r)
6338                 goto done;
6339 #endif
6340         r = gfx_v10_0_cp_gfx_start(adev);
6341         if (r)
6342                 goto done;
6343
6344         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6345                 ring = &adev->gfx.gfx_ring[i];
6346                 ring->sched.ready = true;
6347         }
6348 done:
6349         return r;
6350 }
6351
6352 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6353 {
6354         struct amdgpu_device *adev = ring->adev;
6355
6356         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6357                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6358                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6359                         mqd->cp_hqd_queue_priority =
6360                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6361                 }
6362         }
6363 }
6364
6365 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6366 {
6367         struct amdgpu_device *adev = ring->adev;
6368         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6369         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6370         uint32_t tmp;
6371
6372         mqd->header = 0xC0310800;
6373         mqd->compute_pipelinestat_enable = 0x00000001;
6374         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6375         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6376         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6377         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6378         mqd->compute_misc_reserved = 0x00000003;
6379
6380         eop_base_addr = ring->eop_gpu_addr >> 8;
6381         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6382         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6383
6384         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6385         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6386         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6387                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6388
6389         mqd->cp_hqd_eop_control = tmp;
6390
6391         /* enable doorbell? */
6392         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6393
6394         if (ring->use_doorbell) {
6395                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6396                                     DOORBELL_OFFSET, ring->doorbell_index);
6397                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6398                                     DOORBELL_EN, 1);
6399                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6400                                     DOORBELL_SOURCE, 0);
6401                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6402                                     DOORBELL_HIT, 0);
6403         } else {
6404                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6405                                     DOORBELL_EN, 0);
6406         }
6407
6408         mqd->cp_hqd_pq_doorbell_control = tmp;
6409
6410         /* disable the queue if it's active */
6411         ring->wptr = 0;
6412         mqd->cp_hqd_dequeue_request = 0;
6413         mqd->cp_hqd_pq_rptr = 0;
6414         mqd->cp_hqd_pq_wptr_lo = 0;
6415         mqd->cp_hqd_pq_wptr_hi = 0;
6416
6417         /* set the pointer to the MQD */
6418         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6419         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6420
6421         /* set MQD vmid to 0 */
6422         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6423         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6424         mqd->cp_mqd_control = tmp;
6425
6426         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6427         hqd_gpu_addr = ring->gpu_addr >> 8;
6428         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6429         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6430
6431         /* set up the HQD, this is similar to CP_RB0_CNTL */
6432         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6433         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6434                             (order_base_2(ring->ring_size / 4) - 1));
6435         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6436                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6437 #ifdef __BIG_ENDIAN
6438         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6439 #endif
6440         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6441         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6442         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6443         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6444         mqd->cp_hqd_pq_control = tmp;
6445
6446         /* set the wb address whether it's enabled or not */
6447         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6448         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6449         mqd->cp_hqd_pq_rptr_report_addr_hi =
6450                 upper_32_bits(wb_gpu_addr) & 0xffff;
6451
6452         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6453         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6454         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6455         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6456
6457         tmp = 0;
6458         /* enable the doorbell if requested */
6459         if (ring->use_doorbell) {
6460                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6461                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6462                                 DOORBELL_OFFSET, ring->doorbell_index);
6463
6464                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6465                                     DOORBELL_EN, 1);
6466                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6467                                     DOORBELL_SOURCE, 0);
6468                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6469                                     DOORBELL_HIT, 0);
6470         }
6471
6472         mqd->cp_hqd_pq_doorbell_control = tmp;
6473
6474         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6475         ring->wptr = 0;
6476         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6477
6478         /* set the vmid for the queue */
6479         mqd->cp_hqd_vmid = 0;
6480
6481         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6482         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6483         mqd->cp_hqd_persistent_state = tmp;
6484
6485         /* set MIN_IB_AVAIL_SIZE */
6486         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6487         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6488         mqd->cp_hqd_ib_control = tmp;
6489
6490         /* set static priority for a compute queue/ring */
6491         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6492
6493         /* map_queues packet doesn't need activate the queue,
6494          * so only kiq need set this field.
6495          */
6496         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6497                 mqd->cp_hqd_active = 1;
6498
6499         return 0;
6500 }
6501
6502 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6503 {
6504         struct amdgpu_device *adev = ring->adev;
6505         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6506         int j;
6507
6508         /* inactivate the queue */
6509         if (amdgpu_sriov_vf(adev))
6510                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6511
6512         /* disable wptr polling */
6513         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6514
6515         /* write the EOP addr */
6516         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6517                mqd->cp_hqd_eop_base_addr_lo);
6518         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6519                mqd->cp_hqd_eop_base_addr_hi);
6520
6521         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6522         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6523                mqd->cp_hqd_eop_control);
6524
6525         /* enable doorbell? */
6526         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6527                mqd->cp_hqd_pq_doorbell_control);
6528
6529         /* disable the queue if it's active */
6530         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6531                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6532                 for (j = 0; j < adev->usec_timeout; j++) {
6533                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6534                                 break;
6535                         udelay(1);
6536                 }
6537                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6538                        mqd->cp_hqd_dequeue_request);
6539                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6540                        mqd->cp_hqd_pq_rptr);
6541                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6542                        mqd->cp_hqd_pq_wptr_lo);
6543                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6544                        mqd->cp_hqd_pq_wptr_hi);
6545         }
6546
6547         /* set the pointer to the MQD */
6548         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6549                mqd->cp_mqd_base_addr_lo);
6550         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6551                mqd->cp_mqd_base_addr_hi);
6552
6553         /* set MQD vmid to 0 */
6554         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6555                mqd->cp_mqd_control);
6556
6557         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6558         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6559                mqd->cp_hqd_pq_base_lo);
6560         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6561                mqd->cp_hqd_pq_base_hi);
6562
6563         /* set up the HQD, this is similar to CP_RB0_CNTL */
6564         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6565                mqd->cp_hqd_pq_control);
6566
6567         /* set the wb address whether it's enabled or not */
6568         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6569                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6570         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6571                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6572
6573         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6574         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6575                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6576         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6577                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6578
6579         /* enable the doorbell if requested */
6580         if (ring->use_doorbell) {
6581                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6582                         (adev->doorbell_index.kiq * 2) << 2);
6583                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6584                         (adev->doorbell_index.userqueue_end * 2) << 2);
6585         }
6586
6587         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6588                mqd->cp_hqd_pq_doorbell_control);
6589
6590         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6591         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6592                mqd->cp_hqd_pq_wptr_lo);
6593         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6594                mqd->cp_hqd_pq_wptr_hi);
6595
6596         /* set the vmid for the queue */
6597         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6598
6599         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6600                mqd->cp_hqd_persistent_state);
6601
6602         /* activate the queue */
6603         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6604                mqd->cp_hqd_active);
6605
6606         if (ring->use_doorbell)
6607                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6608
6609         return 0;
6610 }
6611
6612 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6613 {
6614         struct amdgpu_device *adev = ring->adev;
6615         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6616         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6617
6618         gfx_v10_0_kiq_setting(ring);
6619
6620         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6621                 /* reset MQD to a clean status */
6622                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6623                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6624
6625                 /* reset ring buffer */
6626                 ring->wptr = 0;
6627                 amdgpu_ring_clear_ring(ring);
6628
6629                 mutex_lock(&adev->srbm_mutex);
6630                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6631                 gfx_v10_0_kiq_init_register(ring);
6632                 nv_grbm_select(adev, 0, 0, 0, 0);
6633                 mutex_unlock(&adev->srbm_mutex);
6634         } else {
6635                 memset((void *)mqd, 0, sizeof(*mqd));
6636                 mutex_lock(&adev->srbm_mutex);
6637                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6638                 gfx_v10_0_compute_mqd_init(ring);
6639                 gfx_v10_0_kiq_init_register(ring);
6640                 nv_grbm_select(adev, 0, 0, 0, 0);
6641                 mutex_unlock(&adev->srbm_mutex);
6642
6643                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6644                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6645         }
6646
6647         return 0;
6648 }
6649
6650 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6651 {
6652         struct amdgpu_device *adev = ring->adev;
6653         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6654         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6655
6656         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6657                 memset((void *)mqd, 0, sizeof(*mqd));
6658                 mutex_lock(&adev->srbm_mutex);
6659                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6660                 gfx_v10_0_compute_mqd_init(ring);
6661                 nv_grbm_select(adev, 0, 0, 0, 0);
6662                 mutex_unlock(&adev->srbm_mutex);
6663
6664                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6665                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6666         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6667                 /* reset MQD to a clean status */
6668                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6669                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6670
6671                 /* reset ring buffer */
6672                 ring->wptr = 0;
6673                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6674                 amdgpu_ring_clear_ring(ring);
6675         } else {
6676                 amdgpu_ring_clear_ring(ring);
6677         }
6678
6679         return 0;
6680 }
6681
6682 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6683 {
6684         struct amdgpu_ring *ring;
6685         int r;
6686
6687         ring = &adev->gfx.kiq.ring;
6688
6689         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6690         if (unlikely(r != 0))
6691                 return r;
6692
6693         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6694         if (unlikely(r != 0))
6695                 return r;
6696
6697         gfx_v10_0_kiq_init_queue(ring);
6698         amdgpu_bo_kunmap(ring->mqd_obj);
6699         ring->mqd_ptr = NULL;
6700         amdgpu_bo_unreserve(ring->mqd_obj);
6701         ring->sched.ready = true;
6702         return 0;
6703 }
6704
6705 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6706 {
6707         struct amdgpu_ring *ring = NULL;
6708         int r = 0, i;
6709
6710         gfx_v10_0_cp_compute_enable(adev, true);
6711
6712         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6713                 ring = &adev->gfx.compute_ring[i];
6714
6715                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6716                 if (unlikely(r != 0))
6717                         goto done;
6718                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6719                 if (!r) {
6720                         r = gfx_v10_0_kcq_init_queue(ring);
6721                         amdgpu_bo_kunmap(ring->mqd_obj);
6722                         ring->mqd_ptr = NULL;
6723                 }
6724                 amdgpu_bo_unreserve(ring->mqd_obj);
6725                 if (r)
6726                         goto done;
6727         }
6728
6729         r = amdgpu_gfx_enable_kcq(adev);
6730 done:
6731         return r;
6732 }
6733
6734 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6735 {
6736         int r, i;
6737         struct amdgpu_ring *ring;
6738
6739         if (!(adev->flags & AMD_IS_APU))
6740                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6741
6742         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6743                 /* legacy firmware loading */
6744                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6745                 if (r)
6746                         return r;
6747
6748                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6749                 if (r)
6750                         return r;
6751         }
6752
6753         r = gfx_v10_0_kiq_resume(adev);
6754         if (r)
6755                 return r;
6756
6757         r = gfx_v10_0_kcq_resume(adev);
6758         if (r)
6759                 return r;
6760
6761         if (!amdgpu_async_gfx_ring) {
6762                 r = gfx_v10_0_cp_gfx_resume(adev);
6763                 if (r)
6764                         return r;
6765         } else {
6766                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6767                 if (r)
6768                         return r;
6769         }
6770
6771         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6772                 ring = &adev->gfx.gfx_ring[i];
6773                 r = amdgpu_ring_test_helper(ring);
6774                 if (r)
6775                         return r;
6776         }
6777
6778         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6779                 ring = &adev->gfx.compute_ring[i];
6780                 r = amdgpu_ring_test_helper(ring);
6781                 if (r)
6782                         return r;
6783         }
6784
6785         return 0;
6786 }
6787
6788 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6789 {
6790         gfx_v10_0_cp_gfx_enable(adev, enable);
6791         gfx_v10_0_cp_compute_enable(adev, enable);
6792 }
6793
6794 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6795 {
6796         uint32_t data, pattern = 0xDEADBEEF;
6797
6798         /* check if mmVGT_ESGS_RING_SIZE_UMD
6799          * has been remapped to mmVGT_ESGS_RING_SIZE */
6800         switch (adev->asic_type) {
6801         case CHIP_SIENNA_CICHLID:
6802         case CHIP_NAVY_FLOUNDER:
6803                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6804                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6805                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6806
6807                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6808                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6809                         return true;
6810                 } else {
6811                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6812                         return false;
6813                 }
6814                 break;
6815         default:
6816                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6817                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6818                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6819
6820                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6821                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6822                         return true;
6823                 } else {
6824                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6825                         return false;
6826                 }
6827                 break;
6828         }
6829 }
6830
6831 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6832 {
6833         uint32_t data;
6834
6835         /* initialize cam_index to 0
6836          * index will auto-inc after each data writting */
6837         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6838
6839         switch (adev->asic_type) {
6840         case CHIP_SIENNA_CICHLID:
6841         case CHIP_NAVY_FLOUNDER:
6842                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6843                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6844                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6845                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6846                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6847                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6848                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6849
6850                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6851                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6852                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6853                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6854                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6855                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6856                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6857
6858                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6859                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6860                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6861                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6862                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6863                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6864                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6865
6866                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6867                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6868                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6869                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6870                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6871                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6872                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6873
6874                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6875                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6876                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6877                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6878                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6879                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6880                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6881
6882                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6883                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6884                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6885                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6886                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6887                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6888                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6889
6890                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6891                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6892                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6893                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6894                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6895                 break;
6896         default:
6897                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6898                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6899                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6900                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6901                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6902                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6903                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6904
6905                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6906                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6907                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6908                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6909                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6910                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6911                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6912
6913                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6914                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6915                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6916                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6917                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6918                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6919                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6920
6921                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6922                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6923                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6924                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6925                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6926                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6927                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6928
6929                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6930                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6931                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6932                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6933                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6934                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6935                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6936
6937                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6938                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6939                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6940                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6941                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6942                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6943                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6944
6945                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6946                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6947                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6948                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6949                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6950                 break;
6951         }
6952
6953         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6954         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6955 }
6956
6957 static int gfx_v10_0_hw_init(void *handle)
6958 {
6959         int r;
6960         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6961
6962         if (!amdgpu_emu_mode)
6963                 gfx_v10_0_init_golden_registers(adev);
6964
6965         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6966                 /**
6967                  * For gfx 10, rlc firmware loading relies on smu firmware is
6968                  * loaded firstly, so in direct type, it has to load smc ucode
6969                  * here before rlc.
6970                  */
6971                 if (adev->smu.ppt_funcs != NULL) {
6972                         r = smu_load_microcode(&adev->smu);
6973                         if (r)
6974                                 return r;
6975
6976                         r = smu_check_fw_status(&adev->smu);
6977                         if (r) {
6978                                 pr_err("SMC firmware status is not correct\n");
6979                                 return r;
6980                         }
6981                 }
6982         }
6983
6984         /* if GRBM CAM not remapped, set up the remapping */
6985         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6986                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6987
6988         gfx_v10_0_constants_init(adev);
6989
6990         r = gfx_v10_0_rlc_resume(adev);
6991         if (r)
6992                 return r;
6993
6994         /*
6995          * init golden registers and rlc resume may override some registers,
6996          * reconfig them here
6997          */
6998         gfx_v10_0_tcp_harvest(adev);
6999
7000         r = gfx_v10_0_cp_resume(adev);
7001         if (r)
7002                 return r;
7003
7004         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7005                 gfx_v10_3_program_pbb_mode(adev);
7006
7007         return r;
7008 }
7009
7010 #ifndef BRING_UP_DEBUG
7011 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7012 {
7013         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7014         struct amdgpu_ring *kiq_ring = &kiq->ring;
7015         int i;
7016
7017         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7018                 return -EINVAL;
7019
7020         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7021                                         adev->gfx.num_gfx_rings))
7022                 return -ENOMEM;
7023
7024         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7025                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7026                                            PREEMPT_QUEUES, 0, 0);
7027
7028         return amdgpu_ring_test_helper(kiq_ring);
7029 }
7030 #endif
7031
7032 static int gfx_v10_0_hw_fini(void *handle)
7033 {
7034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7035         int r;
7036         uint32_t tmp;
7037
7038         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7039         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7040
7041         if (!adev->in_pci_err_recovery) {
7042 #ifndef BRING_UP_DEBUG
7043                 if (amdgpu_async_gfx_ring) {
7044                         r = gfx_v10_0_kiq_disable_kgq(adev);
7045                         if (r)
7046                                 DRM_ERROR("KGQ disable failed\n");
7047                 }
7048 #endif
7049                 if (amdgpu_gfx_disable_kcq(adev))
7050                         DRM_ERROR("KCQ disable failed\n");
7051         }
7052
7053         if (amdgpu_sriov_vf(adev)) {
7054                 gfx_v10_0_cp_gfx_enable(adev, false);
7055                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7056                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7057                 tmp &= 0xffffff00;
7058                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7059
7060                 return 0;
7061         }
7062         gfx_v10_0_cp_enable(adev, false);
7063         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7064
7065         return 0;
7066 }
7067
7068 static int gfx_v10_0_suspend(void *handle)
7069 {
7070         return gfx_v10_0_hw_fini(handle);
7071 }
7072
7073 static int gfx_v10_0_resume(void *handle)
7074 {
7075         return gfx_v10_0_hw_init(handle);
7076 }
7077
7078 static bool gfx_v10_0_is_idle(void *handle)
7079 {
7080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7081
7082         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7083                                 GRBM_STATUS, GUI_ACTIVE))
7084                 return false;
7085         else
7086                 return true;
7087 }
7088
7089 static int gfx_v10_0_wait_for_idle(void *handle)
7090 {
7091         unsigned i;
7092         u32 tmp;
7093         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7094
7095         for (i = 0; i < adev->usec_timeout; i++) {
7096                 /* read MC_STATUS */
7097                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7098                         GRBM_STATUS__GUI_ACTIVE_MASK;
7099
7100                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7101                         return 0;
7102                 udelay(1);
7103         }
7104         return -ETIMEDOUT;
7105 }
7106
7107 static int gfx_v10_0_soft_reset(void *handle)
7108 {
7109         u32 grbm_soft_reset = 0;
7110         u32 tmp;
7111         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7112
7113         /* GRBM_STATUS */
7114         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7115         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7116                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7117                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7118                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7119                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7120                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7121                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7122                                                 1);
7123                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7124                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7125                                                 1);
7126         }
7127
7128         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7129                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7130                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7131                                                 1);
7132         }
7133
7134         /* GRBM_STATUS2 */
7135         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7136         switch (adev->asic_type) {
7137         case CHIP_SIENNA_CICHLID:
7138         case CHIP_NAVY_FLOUNDER:
7139                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7140                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7141                                                         GRBM_SOFT_RESET,
7142                                                         SOFT_RESET_RLC,
7143                                                         1);
7144                 break;
7145         default:
7146                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7147                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7148                                                         GRBM_SOFT_RESET,
7149                                                         SOFT_RESET_RLC,
7150                                                         1);
7151                 break;
7152         }
7153
7154         if (grbm_soft_reset) {
7155                 /* stop the rlc */
7156                 gfx_v10_0_rlc_stop(adev);
7157
7158                 /* Disable GFX parsing/prefetching */
7159                 gfx_v10_0_cp_gfx_enable(adev, false);
7160
7161                 /* Disable MEC parsing/prefetching */
7162                 gfx_v10_0_cp_compute_enable(adev, false);
7163
7164                 if (grbm_soft_reset) {
7165                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7166                         tmp |= grbm_soft_reset;
7167                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7168                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7169                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7170
7171                         udelay(50);
7172
7173                         tmp &= ~grbm_soft_reset;
7174                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7175                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7176                 }
7177
7178                 /* Wait a little for things to settle down */
7179                 udelay(50);
7180         }
7181         return 0;
7182 }
7183
7184 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7185 {
7186         uint64_t clock;
7187
7188         amdgpu_gfx_off_ctrl(adev, false);
7189         mutex_lock(&adev->gfx.gpu_clock_mutex);
7190         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7191                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7192         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7193         amdgpu_gfx_off_ctrl(adev, true);
7194         return clock;
7195 }
7196
7197 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7198                                            uint32_t vmid,
7199                                            uint32_t gds_base, uint32_t gds_size,
7200                                            uint32_t gws_base, uint32_t gws_size,
7201                                            uint32_t oa_base, uint32_t oa_size)
7202 {
7203         struct amdgpu_device *adev = ring->adev;
7204
7205         /* GDS Base */
7206         gfx_v10_0_write_data_to_reg(ring, 0, false,
7207                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7208                                     gds_base);
7209
7210         /* GDS Size */
7211         gfx_v10_0_write_data_to_reg(ring, 0, false,
7212                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7213                                     gds_size);
7214
7215         /* GWS */
7216         gfx_v10_0_write_data_to_reg(ring, 0, false,
7217                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7218                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7219
7220         /* OA */
7221         gfx_v10_0_write_data_to_reg(ring, 0, false,
7222                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7223                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7224 }
7225
7226 static int gfx_v10_0_early_init(void *handle)
7227 {
7228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7229
7230         switch (adev->asic_type) {
7231         case CHIP_NAVI10:
7232         case CHIP_NAVI14:
7233         case CHIP_NAVI12:
7234                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7235                 break;
7236         case CHIP_SIENNA_CICHLID:
7237         case CHIP_NAVY_FLOUNDER:
7238                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7239                 break;
7240         default:
7241                 break;
7242         }
7243
7244         adev->gfx.num_compute_rings = amdgpu_num_kcq;
7245
7246         gfx_v10_0_set_kiq_pm4_funcs(adev);
7247         gfx_v10_0_set_ring_funcs(adev);
7248         gfx_v10_0_set_irq_funcs(adev);
7249         gfx_v10_0_set_gds_init(adev);
7250         gfx_v10_0_set_rlc_funcs(adev);
7251
7252         return 0;
7253 }
7254
7255 static int gfx_v10_0_late_init(void *handle)
7256 {
7257         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7258         int r;
7259
7260         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7261         if (r)
7262                 return r;
7263
7264         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7265         if (r)
7266                 return r;
7267
7268         return 0;
7269 }
7270
7271 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7272 {
7273         uint32_t rlc_cntl;
7274
7275         /* if RLC is not enabled, do nothing */
7276         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7277         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7278 }
7279
7280 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7281 {
7282         uint32_t data;
7283         unsigned i;
7284
7285         data = RLC_SAFE_MODE__CMD_MASK;
7286         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7287
7288         switch (adev->asic_type) {
7289         case CHIP_SIENNA_CICHLID:
7290         case CHIP_NAVY_FLOUNDER:
7291                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7292
7293                 /* wait for RLC_SAFE_MODE */
7294                 for (i = 0; i < adev->usec_timeout; i++) {
7295                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7296                                            RLC_SAFE_MODE, CMD))
7297                                 break;
7298                         udelay(1);
7299                 }
7300                 break;
7301         default:
7302                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7303
7304                 /* wait for RLC_SAFE_MODE */
7305                 for (i = 0; i < adev->usec_timeout; i++) {
7306                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7307                                            RLC_SAFE_MODE, CMD))
7308                                 break;
7309                         udelay(1);
7310                 }
7311                 break;
7312         }
7313 }
7314
7315 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7316 {
7317         uint32_t data;
7318
7319         data = RLC_SAFE_MODE__CMD_MASK;
7320         switch (adev->asic_type) {
7321         case CHIP_SIENNA_CICHLID:
7322         case CHIP_NAVY_FLOUNDER:
7323                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7324                 break;
7325         default:
7326                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7327                 break;
7328         }
7329 }
7330
7331 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7332                                                       bool enable)
7333 {
7334         uint32_t data, def;
7335
7336         /* It is disabled by HW by default */
7337         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7338                 /* 0 - Disable some blocks' MGCG */
7339                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7340                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7341                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7342                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7343
7344                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7345                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7346                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7347                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7348                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7349                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7350
7351                 if (def != data)
7352                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7353
7354                 /* MGLS is a global flag to control all MGLS in GFX */
7355                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7356                         /* 2 - RLC memory Light sleep */
7357                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7358                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7359                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7360                                 if (def != data)
7361                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7362                         }
7363                         /* 3 - CP memory Light sleep */
7364                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7365                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7366                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7367                                 if (def != data)
7368                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7369                         }
7370                 }
7371         } else {
7372                 /* 1 - MGCG_OVERRIDE */
7373                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7374                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7375                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7376                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7377                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7378                 if (def != data)
7379                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7380
7381                 /* 2 - disable MGLS in CP */
7382                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7383                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7384                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7385                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7386                 }
7387
7388                 /* 3 - disable MGLS in RLC */
7389                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7390                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7391                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7392                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7393                 }
7394
7395         }
7396 }
7397
7398 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7399                                            bool enable)
7400 {
7401         uint32_t data, def;
7402
7403         /* Enable 3D CGCG/CGLS */
7404         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7405                 /* write cmd to clear cgcg/cgls ov */
7406                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7407                 /* unset CGCG override */
7408                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7409                 /* update CGCG and CGLS override bits */
7410                 if (def != data)
7411                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7412                 /* enable 3Dcgcg FSM(0x0000363f) */
7413                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7414                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7415                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7416                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7417                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7418                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7419                 if (def != data)
7420                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7421
7422                 /* set IDLE_POLL_COUNT(0x00900100) */
7423                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7424                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7425                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7426                 if (def != data)
7427                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7428         } else {
7429                 /* Disable CGCG/CGLS */
7430                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7431                 /* disable cgcg, cgls should be disabled */
7432                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7433                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7434                 /* disable cgcg and cgls in FSM */
7435                 if (def != data)
7436                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7437         }
7438 }
7439
7440 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7441                                                       bool enable)
7442 {
7443         uint32_t def, data;
7444
7445         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7446                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7447                 /* unset CGCG override */
7448                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7449                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7450                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7451                 else
7452                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7453                 /* update CGCG and CGLS override bits */
7454                 if (def != data)
7455                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7456
7457                 /* enable cgcg FSM(0x0000363F) */
7458                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7459                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7460                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7461                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7462                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7463                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7464                 if (def != data)
7465                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7466
7467                 /* set IDLE_POLL_COUNT(0x00900100) */
7468                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7469                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7470                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7471                 if (def != data)
7472                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7473         } else {
7474                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7475                 /* reset CGCG/CGLS bits */
7476                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7477                 /* disable cgcg and cgls in FSM */
7478                 if (def != data)
7479                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7480         }
7481 }
7482
7483 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7484                                             bool enable)
7485 {
7486         amdgpu_gfx_rlc_enter_safe_mode(adev);
7487
7488         if (enable) {
7489                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7490                  * ===  MGCG + MGLS ===
7491                  */
7492                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7493                 /* ===  CGCG /CGLS for GFX 3D Only === */
7494                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7495                 /* ===  CGCG + CGLS === */
7496                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7497         } else {
7498                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7499                  * ===  CGCG + CGLS ===
7500                  */
7501                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7502                 /* ===  CGCG /CGLS for GFX 3D Only === */
7503                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7504                 /* ===  MGCG + MGLS === */
7505                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7506         }
7507
7508         if (adev->cg_flags &
7509             (AMD_CG_SUPPORT_GFX_MGCG |
7510              AMD_CG_SUPPORT_GFX_CGLS |
7511              AMD_CG_SUPPORT_GFX_CGCG |
7512              AMD_CG_SUPPORT_GFX_3D_CGCG |
7513              AMD_CG_SUPPORT_GFX_3D_CGLS))
7514                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7515
7516         amdgpu_gfx_rlc_exit_safe_mode(adev);
7517
7518         return 0;
7519 }
7520
7521 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7522 {
7523         u32 reg, data;
7524
7525         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7526         if (amdgpu_sriov_is_pp_one_vf(adev))
7527                 data = RREG32_NO_KIQ(reg);
7528         else
7529                 data = RREG32(reg);
7530
7531         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7532         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7533
7534         if (amdgpu_sriov_is_pp_one_vf(adev))
7535                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7536         else
7537                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7538 }
7539
7540 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7541                                         uint32_t offset,
7542                                         struct soc15_reg_rlcg *entries, int arr_size)
7543 {
7544         int i;
7545         uint32_t reg;
7546
7547         if (!entries)
7548                 return false;
7549
7550         for (i = 0; i < arr_size; i++) {
7551                 const struct soc15_reg_rlcg *entry;
7552
7553                 entry = &entries[i];
7554                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7555                 if (offset == reg)
7556                         return true;
7557         }
7558
7559         return false;
7560 }
7561
7562 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7563 {
7564         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7565 }
7566
7567 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7568         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7569         .set_safe_mode = gfx_v10_0_set_safe_mode,
7570         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7571         .init = gfx_v10_0_rlc_init,
7572         .get_csb_size = gfx_v10_0_get_csb_size,
7573         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7574         .resume = gfx_v10_0_rlc_resume,
7575         .stop = gfx_v10_0_rlc_stop,
7576         .reset = gfx_v10_0_rlc_reset,
7577         .start = gfx_v10_0_rlc_start,
7578         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7579 };
7580
7581 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7582         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7583         .set_safe_mode = gfx_v10_0_set_safe_mode,
7584         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7585         .init = gfx_v10_0_rlc_init,
7586         .get_csb_size = gfx_v10_0_get_csb_size,
7587         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7588         .resume = gfx_v10_0_rlc_resume,
7589         .stop = gfx_v10_0_rlc_stop,
7590         .reset = gfx_v10_0_rlc_reset,
7591         .start = gfx_v10_0_rlc_start,
7592         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7593         .rlcg_wreg = gfx_v10_rlcg_wreg,
7594         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7595 };
7596
7597 static int gfx_v10_0_set_powergating_state(void *handle,
7598                                           enum amd_powergating_state state)
7599 {
7600         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7601         bool enable = (state == AMD_PG_STATE_GATE);
7602
7603         if (amdgpu_sriov_vf(adev))
7604                 return 0;
7605
7606         switch (adev->asic_type) {
7607         case CHIP_NAVI10:
7608         case CHIP_NAVI14:
7609         case CHIP_NAVI12:
7610         case CHIP_SIENNA_CICHLID:
7611         case CHIP_NAVY_FLOUNDER:
7612                 amdgpu_gfx_off_ctrl(adev, enable);
7613                 break;
7614         default:
7615                 break;
7616         }
7617         return 0;
7618 }
7619
7620 static int gfx_v10_0_set_clockgating_state(void *handle,
7621                                           enum amd_clockgating_state state)
7622 {
7623         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7624
7625         if (amdgpu_sriov_vf(adev))
7626                 return 0;
7627
7628         switch (adev->asic_type) {
7629         case CHIP_NAVI10:
7630         case CHIP_NAVI14:
7631         case CHIP_NAVI12:
7632         case CHIP_SIENNA_CICHLID:
7633         case CHIP_NAVY_FLOUNDER:
7634                 gfx_v10_0_update_gfx_clock_gating(adev,
7635                                                  state == AMD_CG_STATE_GATE);
7636                 break;
7637         default:
7638                 break;
7639         }
7640         return 0;
7641 }
7642
7643 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7644 {
7645         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7646         int data;
7647
7648         /* AMD_CG_SUPPORT_GFX_MGCG */
7649         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7650         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7651                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7652
7653         /* AMD_CG_SUPPORT_GFX_CGCG */
7654         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7655         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7656                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7657
7658         /* AMD_CG_SUPPORT_GFX_CGLS */
7659         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7660                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7661
7662         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7663         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7664         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7665                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7666
7667         /* AMD_CG_SUPPORT_GFX_CP_LS */
7668         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7669         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7670                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7671
7672         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7673         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7674         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7675                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7676
7677         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7678         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7679                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7680 }
7681
7682 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7683 {
7684         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7685 }
7686
7687 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7688 {
7689         struct amdgpu_device *adev = ring->adev;
7690         u64 wptr;
7691
7692         /* XXX check if swapping is necessary on BE */
7693         if (ring->use_doorbell) {
7694                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7695         } else {
7696                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7697                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7698         }
7699
7700         return wptr;
7701 }
7702
7703 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7704 {
7705         struct amdgpu_device *adev = ring->adev;
7706
7707         if (ring->use_doorbell) {
7708                 /* XXX check if swapping is necessary on BE */
7709                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7710                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7711         } else {
7712                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7713                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7714         }
7715 }
7716
7717 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7718 {
7719         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7720 }
7721
7722 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7723 {
7724         u64 wptr;
7725
7726         /* XXX check if swapping is necessary on BE */
7727         if (ring->use_doorbell)
7728                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7729         else
7730                 BUG();
7731         return wptr;
7732 }
7733
7734 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7735 {
7736         struct amdgpu_device *adev = ring->adev;
7737
7738         /* XXX check if swapping is necessary on BE */
7739         if (ring->use_doorbell) {
7740                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7741                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7742         } else {
7743                 BUG(); /* only DOORBELL method supported on gfx10 now */
7744         }
7745 }
7746
7747 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7748 {
7749         struct amdgpu_device *adev = ring->adev;
7750         u32 ref_and_mask, reg_mem_engine;
7751         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7752
7753         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7754                 switch (ring->me) {
7755                 case 1:
7756                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7757                         break;
7758                 case 2:
7759                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7760                         break;
7761                 default:
7762                         return;
7763                 }
7764                 reg_mem_engine = 0;
7765         } else {
7766                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7767                 reg_mem_engine = 1; /* pfp */
7768         }
7769
7770         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7771                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7772                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7773                                ref_and_mask, ref_and_mask, 0x20);
7774 }
7775
7776 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7777                                        struct amdgpu_job *job,
7778                                        struct amdgpu_ib *ib,
7779                                        uint32_t flags)
7780 {
7781         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7782         u32 header, control = 0;
7783
7784         if (ib->flags & AMDGPU_IB_FLAG_CE)
7785                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7786         else
7787                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7788
7789         control |= ib->length_dw | (vmid << 24);
7790
7791         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7792                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7793
7794                 if (flags & AMDGPU_IB_PREEMPTED)
7795                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7796
7797                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7798                         gfx_v10_0_ring_emit_de_meta(ring,
7799                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7800         }
7801
7802         amdgpu_ring_write(ring, header);
7803         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7804         amdgpu_ring_write(ring,
7805 #ifdef __BIG_ENDIAN
7806                 (2 << 0) |
7807 #endif
7808                 lower_32_bits(ib->gpu_addr));
7809         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7810         amdgpu_ring_write(ring, control);
7811 }
7812
7813 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7814                                            struct amdgpu_job *job,
7815                                            struct amdgpu_ib *ib,
7816                                            uint32_t flags)
7817 {
7818         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7819         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7820
7821         /* Currently, there is a high possibility to get wave ID mismatch
7822          * between ME and GDS, leading to a hw deadlock, because ME generates
7823          * different wave IDs than the GDS expects. This situation happens
7824          * randomly when at least 5 compute pipes use GDS ordered append.
7825          * The wave IDs generated by ME are also wrong after suspend/resume.
7826          * Those are probably bugs somewhere else in the kernel driver.
7827          *
7828          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7829          * GDS to 0 for this ring (me/pipe).
7830          */
7831         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7832                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7833                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7834                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7835         }
7836
7837         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7838         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7839         amdgpu_ring_write(ring,
7840 #ifdef __BIG_ENDIAN
7841                                 (2 << 0) |
7842 #endif
7843                                 lower_32_bits(ib->gpu_addr));
7844         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7845         amdgpu_ring_write(ring, control);
7846 }
7847
7848 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7849                                      u64 seq, unsigned flags)
7850 {
7851         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7852         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7853
7854         /* RELEASE_MEM - flush caches, send int */
7855         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7856         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7857                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7858                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7859                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7860                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7861                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7862                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7863         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7864                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7865
7866         /*
7867          * the address should be Qword aligned if 64bit write, Dword
7868          * aligned if only send 32bit data low (discard data high)
7869          */
7870         if (write64bit)
7871                 BUG_ON(addr & 0x7);
7872         else
7873                 BUG_ON(addr & 0x3);
7874         amdgpu_ring_write(ring, lower_32_bits(addr));
7875         amdgpu_ring_write(ring, upper_32_bits(addr));
7876         amdgpu_ring_write(ring, lower_32_bits(seq));
7877         amdgpu_ring_write(ring, upper_32_bits(seq));
7878         amdgpu_ring_write(ring, 0);
7879 }
7880
7881 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7882 {
7883         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7884         uint32_t seq = ring->fence_drv.sync_seq;
7885         uint64_t addr = ring->fence_drv.gpu_addr;
7886
7887         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7888                                upper_32_bits(addr), seq, 0xffffffff, 4);
7889 }
7890
7891 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7892                                          unsigned vmid, uint64_t pd_addr)
7893 {
7894         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7895
7896         /* compute doesn't have PFP */
7897         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7898                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7899                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7900                 amdgpu_ring_write(ring, 0x0);
7901         }
7902 }
7903
7904 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7905                                           u64 seq, unsigned int flags)
7906 {
7907         struct amdgpu_device *adev = ring->adev;
7908
7909         /* we only allocate 32bit for each seq wb address */
7910         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7911
7912         /* write fence seq to the "addr" */
7913         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7914         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7915                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7916         amdgpu_ring_write(ring, lower_32_bits(addr));
7917         amdgpu_ring_write(ring, upper_32_bits(addr));
7918         amdgpu_ring_write(ring, lower_32_bits(seq));
7919
7920         if (flags & AMDGPU_FENCE_FLAG_INT) {
7921                 /* set register to trigger INT */
7922                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7923                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7924                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7925                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7926                 amdgpu_ring_write(ring, 0);
7927                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7928         }
7929 }
7930
7931 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7932 {
7933         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7934         amdgpu_ring_write(ring, 0);
7935 }
7936
7937 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7938                                          uint32_t flags)
7939 {
7940         uint32_t dw2 = 0;
7941
7942         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7943                 gfx_v10_0_ring_emit_ce_meta(ring,
7944                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7945
7946         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7947         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7948                 /* set load_global_config & load_global_uconfig */
7949                 dw2 |= 0x8001;
7950                 /* set load_cs_sh_regs */
7951                 dw2 |= 0x01000000;
7952                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7953                 dw2 |= 0x10002;
7954
7955                 /* set load_ce_ram if preamble presented */
7956                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7957                         dw2 |= 0x10000000;
7958         } else {
7959                 /* still load_ce_ram if this is the first time preamble presented
7960                  * although there is no context switch happens.
7961                  */
7962                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7963                         dw2 |= 0x10000000;
7964         }
7965
7966         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7967         amdgpu_ring_write(ring, dw2);
7968         amdgpu_ring_write(ring, 0);
7969 }
7970
7971 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7972 {
7973         unsigned ret;
7974
7975         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7976         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7977         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7978         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7979         ret = ring->wptr & ring->buf_mask;
7980         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7981
7982         return ret;
7983 }
7984
7985 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7986 {
7987         unsigned cur;
7988         BUG_ON(offset > ring->buf_mask);
7989         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7990
7991         cur = (ring->wptr - 1) & ring->buf_mask;
7992         if (likely(cur > offset))
7993                 ring->ring[offset] = cur - offset;
7994         else
7995                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7996 }
7997
7998 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7999 {
8000         int i, r = 0;
8001         struct amdgpu_device *adev = ring->adev;
8002         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8003         struct amdgpu_ring *kiq_ring = &kiq->ring;
8004         unsigned long flags;
8005
8006         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8007                 return -EINVAL;
8008
8009         spin_lock_irqsave(&kiq->ring_lock, flags);
8010
8011         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8012                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8013                 return -ENOMEM;
8014         }
8015
8016         /* assert preemption condition */
8017         amdgpu_ring_set_preempt_cond_exec(ring, false);
8018
8019         /* assert IB preemption, emit the trailing fence */
8020         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8021                                    ring->trail_fence_gpu_addr,
8022                                    ++ring->trail_seq);
8023         amdgpu_ring_commit(kiq_ring);
8024
8025         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8026
8027         /* poll the trailing fence */
8028         for (i = 0; i < adev->usec_timeout; i++) {
8029                 if (ring->trail_seq ==
8030                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8031                         break;
8032                 udelay(1);
8033         }
8034
8035         if (i >= adev->usec_timeout) {
8036                 r = -EINVAL;
8037                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8038         }
8039
8040         /* deassert preemption condition */
8041         amdgpu_ring_set_preempt_cond_exec(ring, true);
8042         return r;
8043 }
8044
8045 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8046 {
8047         struct amdgpu_device *adev = ring->adev;
8048         struct v10_ce_ib_state ce_payload = {0};
8049         uint64_t csa_addr;
8050         int cnt;
8051
8052         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8053         csa_addr = amdgpu_csa_vaddr(ring->adev);
8054
8055         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8056         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8057                                  WRITE_DATA_DST_SEL(8) |
8058                                  WR_CONFIRM) |
8059                                  WRITE_DATA_CACHE_POLICY(0));
8060         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8061                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8062         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8063                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8064
8065         if (resume)
8066                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8067                                            offsetof(struct v10_gfx_meta_data,
8068                                                     ce_payload),
8069                                            sizeof(ce_payload) >> 2);
8070         else
8071                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8072                                            sizeof(ce_payload) >> 2);
8073 }
8074
8075 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8076 {
8077         struct amdgpu_device *adev = ring->adev;
8078         struct v10_de_ib_state de_payload = {0};
8079         uint64_t csa_addr, gds_addr;
8080         int cnt;
8081
8082         csa_addr = amdgpu_csa_vaddr(ring->adev);
8083         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8084                          PAGE_SIZE);
8085         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8086         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8087
8088         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8089         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8090         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8091                                  WRITE_DATA_DST_SEL(8) |
8092                                  WR_CONFIRM) |
8093                                  WRITE_DATA_CACHE_POLICY(0));
8094         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8095                               offsetof(struct v10_gfx_meta_data, de_payload)));
8096         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8097                               offsetof(struct v10_gfx_meta_data, de_payload)));
8098
8099         if (resume)
8100                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8101                                            offsetof(struct v10_gfx_meta_data,
8102                                                     de_payload),
8103                                            sizeof(de_payload) >> 2);
8104         else
8105                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8106                                            sizeof(de_payload) >> 2);
8107 }
8108
8109 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8110                                     bool secure)
8111 {
8112         uint32_t v = secure ? FRAME_TMZ : 0;
8113
8114         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8115         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8116 }
8117
8118 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8119                                      uint32_t reg_val_offs)
8120 {
8121         struct amdgpu_device *adev = ring->adev;
8122
8123         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8124         amdgpu_ring_write(ring, 0 |     /* src: register*/
8125                                 (5 << 8) |      /* dst: memory */
8126                                 (1 << 20));     /* write confirm */
8127         amdgpu_ring_write(ring, reg);
8128         amdgpu_ring_write(ring, 0);
8129         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8130                                 reg_val_offs * 4));
8131         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8132                                 reg_val_offs * 4));
8133 }
8134
8135 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8136                                    uint32_t val)
8137 {
8138         uint32_t cmd = 0;
8139
8140         switch (ring->funcs->type) {
8141         case AMDGPU_RING_TYPE_GFX:
8142                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8143                 break;
8144         case AMDGPU_RING_TYPE_KIQ:
8145                 cmd = (1 << 16); /* no inc addr */
8146                 break;
8147         default:
8148                 cmd = WR_CONFIRM;
8149                 break;
8150         }
8151         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8152         amdgpu_ring_write(ring, cmd);
8153         amdgpu_ring_write(ring, reg);
8154         amdgpu_ring_write(ring, 0);
8155         amdgpu_ring_write(ring, val);
8156 }
8157
8158 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8159                                         uint32_t val, uint32_t mask)
8160 {
8161         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8162 }
8163
8164 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8165                                                    uint32_t reg0, uint32_t reg1,
8166                                                    uint32_t ref, uint32_t mask)
8167 {
8168         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8169         struct amdgpu_device *adev = ring->adev;
8170         bool fw_version_ok = false;
8171
8172         fw_version_ok = adev->gfx.cp_fw_write_wait;
8173
8174         if (fw_version_ok)
8175                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8176                                        ref, mask, 0x20);
8177         else
8178                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8179                                                            ref, mask);
8180 }
8181
8182 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8183                                          unsigned vmid)
8184 {
8185         struct amdgpu_device *adev = ring->adev;
8186         uint32_t value = 0;
8187
8188         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8189         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8190         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8191         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8192         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8193 }
8194
8195 static void
8196 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8197                                       uint32_t me, uint32_t pipe,
8198                                       enum amdgpu_interrupt_state state)
8199 {
8200         uint32_t cp_int_cntl, cp_int_cntl_reg;
8201
8202         if (!me) {
8203                 switch (pipe) {
8204                 case 0:
8205                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8206                         break;
8207                 case 1:
8208                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8209                         break;
8210                 default:
8211                         DRM_DEBUG("invalid pipe %d\n", pipe);
8212                         return;
8213                 }
8214         } else {
8215                 DRM_DEBUG("invalid me %d\n", me);
8216                 return;
8217         }
8218
8219         switch (state) {
8220         case AMDGPU_IRQ_STATE_DISABLE:
8221                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8222                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8223                                             TIME_STAMP_INT_ENABLE, 0);
8224                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8225                 break;
8226         case AMDGPU_IRQ_STATE_ENABLE:
8227                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8228                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8229                                             TIME_STAMP_INT_ENABLE, 1);
8230                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8231                 break;
8232         default:
8233                 break;
8234         }
8235 }
8236
8237 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8238                                                      int me, int pipe,
8239                                                      enum amdgpu_interrupt_state state)
8240 {
8241         u32 mec_int_cntl, mec_int_cntl_reg;
8242
8243         /*
8244          * amdgpu controls only the first MEC. That's why this function only
8245          * handles the setting of interrupts for this specific MEC. All other
8246          * pipes' interrupts are set by amdkfd.
8247          */
8248
8249         if (me == 1) {
8250                 switch (pipe) {
8251                 case 0:
8252                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8253                         break;
8254                 case 1:
8255                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8256                         break;
8257                 case 2:
8258                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8259                         break;
8260                 case 3:
8261                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8262                         break;
8263                 default:
8264                         DRM_DEBUG("invalid pipe %d\n", pipe);
8265                         return;
8266                 }
8267         } else {
8268                 DRM_DEBUG("invalid me %d\n", me);
8269                 return;
8270         }
8271
8272         switch (state) {
8273         case AMDGPU_IRQ_STATE_DISABLE:
8274                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8275                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8276                                              TIME_STAMP_INT_ENABLE, 0);
8277                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8278                 break;
8279         case AMDGPU_IRQ_STATE_ENABLE:
8280                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8281                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8282                                              TIME_STAMP_INT_ENABLE, 1);
8283                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8284                 break;
8285         default:
8286                 break;
8287         }
8288 }
8289
8290 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8291                                             struct amdgpu_irq_src *src,
8292                                             unsigned type,
8293                                             enum amdgpu_interrupt_state state)
8294 {
8295         switch (type) {
8296         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8297                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8298                 break;
8299         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8300                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8301                 break;
8302         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8303                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8304                 break;
8305         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8306                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8307                 break;
8308         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8309                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8310                 break;
8311         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8312                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8313                 break;
8314         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8315                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8316                 break;
8317         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8318                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8319                 break;
8320         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8321                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8322                 break;
8323         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8324                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8325                 break;
8326         default:
8327                 break;
8328         }
8329         return 0;
8330 }
8331
8332 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8333                              struct amdgpu_irq_src *source,
8334                              struct amdgpu_iv_entry *entry)
8335 {
8336         int i;
8337         u8 me_id, pipe_id, queue_id;
8338         struct amdgpu_ring *ring;
8339
8340         DRM_DEBUG("IH: CP EOP\n");
8341         me_id = (entry->ring_id & 0x0c) >> 2;
8342         pipe_id = (entry->ring_id & 0x03) >> 0;
8343         queue_id = (entry->ring_id & 0x70) >> 4;
8344
8345         switch (me_id) {
8346         case 0:
8347                 if (pipe_id == 0)
8348                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8349                 else
8350                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8351                 break;
8352         case 1:
8353         case 2:
8354                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8355                         ring = &adev->gfx.compute_ring[i];
8356                         /* Per-queue interrupt is supported for MEC starting from VI.
8357                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8358                           */
8359                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8360                                 amdgpu_fence_process(ring);
8361                 }
8362                 break;
8363         }
8364         return 0;
8365 }
8366
8367 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8368                                               struct amdgpu_irq_src *source,
8369                                               unsigned type,
8370                                               enum amdgpu_interrupt_state state)
8371 {
8372         switch (state) {
8373         case AMDGPU_IRQ_STATE_DISABLE:
8374         case AMDGPU_IRQ_STATE_ENABLE:
8375                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8376                                PRIV_REG_INT_ENABLE,
8377                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8378                 break;
8379         default:
8380                 break;
8381         }
8382
8383         return 0;
8384 }
8385
8386 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8387                                                struct amdgpu_irq_src *source,
8388                                                unsigned type,
8389                                                enum amdgpu_interrupt_state state)
8390 {
8391         switch (state) {
8392         case AMDGPU_IRQ_STATE_DISABLE:
8393         case AMDGPU_IRQ_STATE_ENABLE:
8394                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8395                                PRIV_INSTR_INT_ENABLE,
8396                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8397         default:
8398                 break;
8399         }
8400
8401         return 0;
8402 }
8403
8404 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8405                                         struct amdgpu_iv_entry *entry)
8406 {
8407         u8 me_id, pipe_id, queue_id;
8408         struct amdgpu_ring *ring;
8409         int i;
8410
8411         me_id = (entry->ring_id & 0x0c) >> 2;
8412         pipe_id = (entry->ring_id & 0x03) >> 0;
8413         queue_id = (entry->ring_id & 0x70) >> 4;
8414
8415         switch (me_id) {
8416         case 0:
8417                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8418                         ring = &adev->gfx.gfx_ring[i];
8419                         /* we only enabled 1 gfx queue per pipe for now */
8420                         if (ring->me == me_id && ring->pipe == pipe_id)
8421                                 drm_sched_fault(&ring->sched);
8422                 }
8423                 break;
8424         case 1:
8425         case 2:
8426                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8427                         ring = &adev->gfx.compute_ring[i];
8428                         if (ring->me == me_id && ring->pipe == pipe_id &&
8429                             ring->queue == queue_id)
8430                                 drm_sched_fault(&ring->sched);
8431                 }
8432                 break;
8433         default:
8434                 BUG();
8435         }
8436 }
8437
8438 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8439                                   struct amdgpu_irq_src *source,
8440                                   struct amdgpu_iv_entry *entry)
8441 {
8442         DRM_ERROR("Illegal register access in command stream\n");
8443         gfx_v10_0_handle_priv_fault(adev, entry);
8444         return 0;
8445 }
8446
8447 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8448                                    struct amdgpu_irq_src *source,
8449                                    struct amdgpu_iv_entry *entry)
8450 {
8451         DRM_ERROR("Illegal instruction in command stream\n");
8452         gfx_v10_0_handle_priv_fault(adev, entry);
8453         return 0;
8454 }
8455
8456 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8457                                              struct amdgpu_irq_src *src,
8458                                              unsigned int type,
8459                                              enum amdgpu_interrupt_state state)
8460 {
8461         uint32_t tmp, target;
8462         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8463
8464         if (ring->me == 1)
8465                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8466         else
8467                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8468         target += ring->pipe;
8469
8470         switch (type) {
8471         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8472                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8473                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8474                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8475                                             GENERIC2_INT_ENABLE, 0);
8476                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8477
8478                         tmp = RREG32(target);
8479                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8480                                             GENERIC2_INT_ENABLE, 0);
8481                         WREG32(target, tmp);
8482                 } else {
8483                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8484                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8485                                             GENERIC2_INT_ENABLE, 1);
8486                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8487
8488                         tmp = RREG32(target);
8489                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8490                                             GENERIC2_INT_ENABLE, 1);
8491                         WREG32(target, tmp);
8492                 }
8493                 break;
8494         default:
8495                 BUG(); /* kiq only support GENERIC2_INT now */
8496                 break;
8497         }
8498         return 0;
8499 }
8500
8501 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8502                              struct amdgpu_irq_src *source,
8503                              struct amdgpu_iv_entry *entry)
8504 {
8505         u8 me_id, pipe_id, queue_id;
8506         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8507
8508         me_id = (entry->ring_id & 0x0c) >> 2;
8509         pipe_id = (entry->ring_id & 0x03) >> 0;
8510         queue_id = (entry->ring_id & 0x70) >> 4;
8511         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8512                    me_id, pipe_id, queue_id);
8513
8514         amdgpu_fence_process(ring);
8515         return 0;
8516 }
8517
8518 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8519 {
8520         const unsigned int gcr_cntl =
8521                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8522                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8523                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8524                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8525                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8526                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8527                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8528                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8529
8530         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8531         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8532         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8533         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8534         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8535         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8536         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8537         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8538         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8539 }
8540
8541 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8542         .name = "gfx_v10_0",
8543         .early_init = gfx_v10_0_early_init,
8544         .late_init = gfx_v10_0_late_init,
8545         .sw_init = gfx_v10_0_sw_init,
8546         .sw_fini = gfx_v10_0_sw_fini,
8547         .hw_init = gfx_v10_0_hw_init,
8548         .hw_fini = gfx_v10_0_hw_fini,
8549         .suspend = gfx_v10_0_suspend,
8550         .resume = gfx_v10_0_resume,
8551         .is_idle = gfx_v10_0_is_idle,
8552         .wait_for_idle = gfx_v10_0_wait_for_idle,
8553         .soft_reset = gfx_v10_0_soft_reset,
8554         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8555         .set_powergating_state = gfx_v10_0_set_powergating_state,
8556         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8557 };
8558
8559 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8560         .type = AMDGPU_RING_TYPE_GFX,
8561         .align_mask = 0xff,
8562         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8563         .support_64bit_ptrs = true,
8564         .vmhub = AMDGPU_GFXHUB_0,
8565         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8566         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8567         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8568         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8569                 5 + /* COND_EXEC */
8570                 7 + /* PIPELINE_SYNC */
8571                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8572                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8573                 2 + /* VM_FLUSH */
8574                 8 + /* FENCE for VM_FLUSH */
8575                 20 + /* GDS switch */
8576                 4 + /* double SWITCH_BUFFER,
8577                      * the first COND_EXEC jump to the place
8578                      * just prior to this double SWITCH_BUFFER
8579                      */
8580                 5 + /* COND_EXEC */
8581                 7 + /* HDP_flush */
8582                 4 + /* VGT_flush */
8583                 14 + /* CE_META */
8584                 31 + /* DE_META */
8585                 3 + /* CNTX_CTRL */
8586                 5 + /* HDP_INVL */
8587                 8 + 8 + /* FENCE x2 */
8588                 2 + /* SWITCH_BUFFER */
8589                 8, /* gfx_v10_0_emit_mem_sync */
8590         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8591         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8592         .emit_fence = gfx_v10_0_ring_emit_fence,
8593         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8594         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8595         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8596         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8597         .test_ring = gfx_v10_0_ring_test_ring,
8598         .test_ib = gfx_v10_0_ring_test_ib,
8599         .insert_nop = amdgpu_ring_insert_nop,
8600         .pad_ib = amdgpu_ring_generic_pad_ib,
8601         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8602         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8603         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8604         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8605         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8606         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8607         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8608         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8609         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8610         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8611         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8612 };
8613
8614 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8615         .type = AMDGPU_RING_TYPE_COMPUTE,
8616         .align_mask = 0xff,
8617         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8618         .support_64bit_ptrs = true,
8619         .vmhub = AMDGPU_GFXHUB_0,
8620         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8621         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8622         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8623         .emit_frame_size =
8624                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8625                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8626                 5 + /* hdp invalidate */
8627                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8628                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8629                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8630                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8631                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8632                 8, /* gfx_v10_0_emit_mem_sync */
8633         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8634         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8635         .emit_fence = gfx_v10_0_ring_emit_fence,
8636         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8637         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8638         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8639         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8640         .test_ring = gfx_v10_0_ring_test_ring,
8641         .test_ib = gfx_v10_0_ring_test_ib,
8642         .insert_nop = amdgpu_ring_insert_nop,
8643         .pad_ib = amdgpu_ring_generic_pad_ib,
8644         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8645         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8646         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8647         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8648 };
8649
8650 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8651         .type = AMDGPU_RING_TYPE_KIQ,
8652         .align_mask = 0xff,
8653         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8654         .support_64bit_ptrs = true,
8655         .vmhub = AMDGPU_GFXHUB_0,
8656         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8657         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8658         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8659         .emit_frame_size =
8660                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8661                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8662                 5 + /*hdp invalidate */
8663                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8664                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8665                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8666                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8667                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8668         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8669         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8670         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8671         .test_ring = gfx_v10_0_ring_test_ring,
8672         .test_ib = gfx_v10_0_ring_test_ib,
8673         .insert_nop = amdgpu_ring_insert_nop,
8674         .pad_ib = amdgpu_ring_generic_pad_ib,
8675         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8676         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8677         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8678         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8679 };
8680
8681 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8682 {
8683         int i;
8684
8685         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8686
8687         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8688                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8689
8690         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8691                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8692 }
8693
8694 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8695         .set = gfx_v10_0_set_eop_interrupt_state,
8696         .process = gfx_v10_0_eop_irq,
8697 };
8698
8699 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8700         .set = gfx_v10_0_set_priv_reg_fault_state,
8701         .process = gfx_v10_0_priv_reg_irq,
8702 };
8703
8704 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8705         .set = gfx_v10_0_set_priv_inst_fault_state,
8706         .process = gfx_v10_0_priv_inst_irq,
8707 };
8708
8709 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8710         .set = gfx_v10_0_kiq_set_interrupt_state,
8711         .process = gfx_v10_0_kiq_irq,
8712 };
8713
8714 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8715 {
8716         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8717         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8718
8719         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8720         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8721
8722         adev->gfx.priv_reg_irq.num_types = 1;
8723         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8724
8725         adev->gfx.priv_inst_irq.num_types = 1;
8726         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8727 }
8728
8729 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8730 {
8731         switch (adev->asic_type) {
8732         case CHIP_NAVI10:
8733         case CHIP_NAVI14:
8734         case CHIP_SIENNA_CICHLID:
8735         case CHIP_NAVY_FLOUNDER:
8736                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8737                 break;
8738         case CHIP_NAVI12:
8739                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8740                 break;
8741         default:
8742                 break;
8743         }
8744 }
8745
8746 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8747 {
8748         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8749                             adev->gfx.config.max_sh_per_se *
8750                             adev->gfx.config.max_shader_engines;
8751
8752         adev->gds.gds_size = 0x10000;
8753         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8754         adev->gds.gws_size = 64;
8755         adev->gds.oa_size = 16;
8756 }
8757
8758 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8759                                                           u32 bitmap)
8760 {
8761         u32 data;
8762
8763         if (!bitmap)
8764                 return;
8765
8766         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8767         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8768
8769         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8770 }
8771
8772 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8773 {
8774         u32 data, wgp_bitmask;
8775         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8776         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8777
8778         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8779         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8780
8781         wgp_bitmask =
8782                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8783
8784         return (~data) & wgp_bitmask;
8785 }
8786
8787 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8788 {
8789         u32 wgp_idx, wgp_active_bitmap;
8790         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8791
8792         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8793         cu_active_bitmap = 0;
8794
8795         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8796                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8797                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8798                 if (wgp_active_bitmap & (1 << wgp_idx))
8799                         cu_active_bitmap |= cu_bitmap_per_wgp;
8800         }
8801
8802         return cu_active_bitmap;
8803 }
8804
8805 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8806                                  struct amdgpu_cu_info *cu_info)
8807 {
8808         int i, j, k, counter, active_cu_number = 0;
8809         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8810         unsigned disable_masks[4 * 2];
8811
8812         if (!adev || !cu_info)
8813                 return -EINVAL;
8814
8815         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8816
8817         mutex_lock(&adev->grbm_idx_mutex);
8818         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8819                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8820                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
8821                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
8822                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
8823                                 continue;
8824                         mask = 1;
8825                         ao_bitmap = 0;
8826                         counter = 0;
8827                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8828                         if (i < 4 && j < 2)
8829                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8830                                         adev, disable_masks[i * 2 + j]);
8831                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8832                         cu_info->bitmap[i][j] = bitmap;
8833
8834                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8835                                 if (bitmap & mask) {
8836                                         if (counter < adev->gfx.config.max_cu_per_sh)
8837                                                 ao_bitmap |= mask;
8838                                         counter++;
8839                                 }
8840                                 mask <<= 1;
8841                         }
8842                         active_cu_number += counter;
8843                         if (i < 2 && j < 2)
8844                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8845                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8846                 }
8847         }
8848         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8849         mutex_unlock(&adev->grbm_idx_mutex);
8850
8851         cu_info->number = active_cu_number;
8852         cu_info->ao_cu_mask = ao_cu_mask;
8853         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8854
8855         return 0;
8856 }
8857
8858 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
8859 {
8860         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
8861
8862         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
8863         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8864         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8865
8866         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
8867         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8868         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8869
8870         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
8871                                                 adev->gfx.config.max_shader_engines);
8872         disabled_sa = efuse_setting | vbios_setting;
8873         disabled_sa &= max_sa_mask;
8874
8875         return disabled_sa;
8876 }
8877
8878 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
8879 {
8880         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
8881         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
8882
8883         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
8884
8885         max_sa_per_se = adev->gfx.config.max_sh_per_se;
8886         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
8887         max_shader_engines = adev->gfx.config.max_shader_engines;
8888
8889         for (se_index = 0; max_shader_engines > se_index; se_index++) {
8890                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
8891                 disabled_sa_per_se &= max_sa_per_se_mask;
8892                 if (disabled_sa_per_se == max_sa_per_se_mask) {
8893                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
8894                         break;
8895                 }
8896         }
8897 }
8898
8899 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8900 {
8901         .type = AMD_IP_BLOCK_TYPE_GFX,
8902         .major = 10,
8903         .minor = 0,
8904         .rev = 0,
8905         .funcs = &gfx_v10_0_ip_funcs,
8906 };