drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drm_fourcc.h>
  25 #include <drm/drm_vblank.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_i2c.h"
  30 #include "cikd.h"
  31 #include "atom.h"
  32 #include "amdgpu_atombios.h"
  33 #include "atombios_crtc.h"
  34 #include "atombios_encoders.h"
  35 #include "amdgpu_pll.h"
  36 #include "amdgpu_connectors.h"
  37 #include "amdgpu_display.h"
  38 #include "dce_v8_0.h"
  39
  40 #include "dce/dce_8_0_d.h"
  41 #include "dce/dce_8_0_sh_mask.h"
  42
  43 #include "gca/gfx_7_2_enum.h"
  44
  45 #include "gmc/gmc_7_1_d.h"
  46 #include "gmc/gmc_7_1_sh_mask.h"
  47
  48 #include "oss/oss_2_0_d.h"
  49 #include "oss/oss_2_0_sh_mask.h"
  50
  51 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
  52 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 static const u32 crtc_offsets[6] =
  55 {
  56         CRTC0_REGISTER_OFFSET,
  57         CRTC1_REGISTER_OFFSET,
  58         CRTC2_REGISTER_OFFSET,
  59         CRTC3_REGISTER_OFFSET,
  60         CRTC4_REGISTER_OFFSET,
  61         CRTC5_REGISTER_OFFSET
  62 };
  63
  64 static const u32 hpd_offsets[] =
  65 {
  66         HPD0_REGISTER_OFFSET,
  67         HPD1_REGISTER_OFFSET,
  68         HPD2_REGISTER_OFFSET,
  69         HPD3_REGISTER_OFFSET,
  70         HPD4_REGISTER_OFFSET,
  71         HPD5_REGISTER_OFFSET
  72 };
  73
  74 static const uint32_t dig_offsets[] = {
  75         CRTC0_REGISTER_OFFSET,
  76         CRTC1_REGISTER_OFFSET,
  77         CRTC2_REGISTER_OFFSET,
  78         CRTC3_REGISTER_OFFSET,
  79         CRTC4_REGISTER_OFFSET,
  80         CRTC5_REGISTER_OFFSET,
  81         (0x13830 - 0x7030) >> 2,
  82 };
  83
  84 static const struct {
  85         uint32_t        reg;
  86         uint32_t        vblank;
  87         uint32_t        vline;
  88         uint32_t        hpd;
  89
  90 } interrupt_status_offsets[6] = { {
  91         .reg = mmDISP_INTERRUPT_STATUS,
  92         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 115 }, {
 116         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 117         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 118         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 119         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 120 } };
 121
 122 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
 123                                      u32 block_offset, u32 reg)
 124 {
 125         unsigned long flags;
 126         u32 r;
 127
 128         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 129         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 130         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 131         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 132
 133         return r;
 134 }
 135
 136 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
 137                                       u32 block_offset, u32 reg, u32 v)
 138 {
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 142         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 143         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 144         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 145 }
 146
 147 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 148 {
 149         if (crtc >= adev->mode_info.num_crtc)
 150                 return 0;
 151         else
 152                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 153 }
 154
 155 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 156 {
 157         unsigned i;
 158
 159         /* Enable pflip interrupts */
 160         for (i = 0; i < adev->mode_info.num_crtc; i++)
 161                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 162 }
 163
 164 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 165 {
 166         unsigned i;
 167
 168         /* Disable pflip interrupts */
 169         for (i = 0; i < adev->mode_info.num_crtc; i++)
 170                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 171 }
 172
 173 /**
 174  * dce_v8_0_page_flip - pageflip callback.
 175  *
 176  * @adev: amdgpu_device pointer
 177  * @crtc_id: crtc to cleanup pageflip on
 178  * @crtc_base: new address of the crtc (GPU MC address)
 179  * @async: asynchronous flip
 180  *
 181  * Triggers the actual pageflip by updating the primary
 182  * surface base address.
 183  */
 184 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
 185                                int crtc_id, u64 crtc_base, bool async)
 186 {
 187         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 188         struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
 189
 190         /* flip at hsync for async, default is vsync */
 191         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 192                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 193         /* update pitch */
 194         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
 195                fb->pitches[0] / fb->format->cpp[0]);
 196         /* update the primary scanout addresses */
 197         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 198                upper_32_bits(crtc_base));
 199         /* writing to the low address triggers the update */
 200         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 201                lower_32_bits(crtc_base));
 202         /* post the write */
 203         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 204 }
 205
 206 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 207                                         u32 *vbl, u32 *position)
 208 {
 209         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 210                 return -EINVAL;
 211
 212         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 213         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 214
 215         return 0;
 216 }
 217
 218 /**
 219  * dce_v8_0_hpd_sense - hpd sense callback.
 220  *
 221  * @adev: amdgpu_device pointer
 222  * @hpd: hpd (hotplug detect) pin
 223  *
 224  * Checks if a digital monitor is connected (evergreen+).
 225  * Returns true if connected, false if not connected.
 226  */
 227 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
 228                                enum amdgpu_hpd_id hpd)
 229 {
 230         bool connected = false;
 231
 232         if (hpd >= adev->mode_info.num_hpd)
 233                 return connected;
 234
 235         if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
 236             DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 237                 connected = true;
 238
 239         return connected;
 240 }
 241
 242 /**
 243  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
 244  *
 245  * @adev: amdgpu_device pointer
 246  * @hpd: hpd (hotplug detect) pin
 247  *
 248  * Set the polarity of the hpd pin (evergreen+).
 249  */
 250 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
 251                                       enum amdgpu_hpd_id hpd)
 252 {
 253         u32 tmp;
 254         bool connected = dce_v8_0_hpd_sense(adev, hpd);
 255
 256         if (hpd >= adev->mode_info.num_hpd)
 257                 return;
 258
 259         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
 260         if (connected)
 261                 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 262         else
 263                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 264         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 265 }
 266
 267 /**
 268  * dce_v8_0_hpd_init - hpd setup callback.
 269  *
 270  * @adev: amdgpu_device pointer
 271  *
 272  * Setup the hpd pins used by the card (evergreen+).
 273  * Enable the pin, set the polarity, and enable the hpd interrupts.
 274  */
 275 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 276 {
 277         struct drm_device *dev = adev_to_drm(adev);
 278         struct drm_connector *connector;
 279         struct drm_connector_list_iter iter;
 280         u32 tmp;
 281
 282         drm_connector_list_iter_begin(dev, &iter);
 283         drm_for_each_connector_iter(connector, &iter) {
 284                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 285
 286                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 287                         continue;
 288
 289                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 290                 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 291                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 292
 293                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 294                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 295                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 296                          * aux dp channel on imac and help (but not completely fix)
 297                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 298                          * also avoid interrupt storms during dpms.
 299                          */
 300                         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 301                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 302                         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 303                         continue;
 304                 }
 305
 306                 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 307                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 308         }
 309         drm_connector_list_iter_end(&iter);
 310 }
 311
 312 /**
 313  * dce_v8_0_hpd_fini - hpd tear down callback.
 314  *
 315  * @adev: amdgpu_device pointer
 316  *
 317  * Tear down the hpd pins used by the card (evergreen+).
 318  * Disable the hpd interrupts.
 319  */
 320 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 321 {
 322         struct drm_device *dev = adev_to_drm(adev);
 323         struct drm_connector *connector;
 324         struct drm_connector_list_iter iter;
 325         u32 tmp;
 326
 327         drm_connector_list_iter_begin(dev, &iter);
 328         drm_for_each_connector_iter(connector, &iter) {
 329                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 330
 331                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 332                         continue;
 333
 334                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 335                 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 336                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 337
 338                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 339         }
 340         drm_connector_list_iter_end(&iter);
 341 }
 342
 343 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 344 {
 345         return mmDC_GPIO_HPD_A;
 346 }
 347
 348 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
 349 {
 350         u32 crtc_hung = 0;
 351         u32 crtc_status[6];
 352         u32 i, j, tmp;
 353
 354         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 355                 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
 356                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 357                         crtc_hung |= (1 << i);
 358                 }
 359         }
 360
 361         for (j = 0; j < 10; j++) {
 362                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 363                         if (crtc_hung & (1 << i)) {
 364                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 365                                 if (tmp != crtc_status[i])
 366                                         crtc_hung &= ~(1 << i);
 367                         }
 368                 }
 369                 if (crtc_hung == 0)
 370                         return false;
 371                 udelay(100);
 372         }
 373
 374         return true;
 375 }
 376
 377 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
 378                                           bool render)
 379 {
 380         u32 tmp;
 381
 382         /* Lockout access through VGA aperture*/
 383         tmp = RREG32(mmVGA_HDP_CONTROL);
 384         if (render)
 385                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 386         else
 387                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 388         WREG32(mmVGA_HDP_CONTROL, tmp);
 389
 390         /* disable VGA render */
 391         tmp = RREG32(mmVGA_RENDER_CONTROL);
 392         if (render)
 393                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 394         else
 395                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 396         WREG32(mmVGA_RENDER_CONTROL, tmp);
 397 }
 398
 399 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
 400 {
 401         int num_crtc = 0;
 402
 403         switch (adev->asic_type) {
 404         case CHIP_BONAIRE:
 405         case CHIP_HAWAII:
 406                 num_crtc = 6;
 407                 break;
 408         case CHIP_KAVERI:
 409                 num_crtc = 4;
 410                 break;
 411         case CHIP_KABINI:
 412         case CHIP_MULLINS:
 413                 num_crtc = 2;
 414                 break;
 415         default:
 416                 num_crtc = 0;
 417         }
 418         return num_crtc;
 419 }
 420
 421 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
 422 {
 423         /*Disable VGA render and enabled crtc, if has DCE engine*/
 424         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 425                 u32 tmp;
 426                 int crtc_enabled, i;
 427
 428                 dce_v8_0_set_vga_render_state(adev, false);
 429
 430                 /*Disable crtc*/
 431                 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
 432                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 433                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 434                         if (crtc_enabled) {
 435                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 436                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 437                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 438                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 439                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 440                         }
 441                 }
 442         }
 443 }
 444
 445 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
 446 {
 447         struct drm_device *dev = encoder->dev;
 448         struct amdgpu_device *adev = drm_to_adev(dev);
 449         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 450         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 451         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 452         int bpc = 0;
 453         u32 tmp = 0;
 454         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 455
 456         if (connector) {
 457                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 458                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 459                 dither = amdgpu_connector->dither;
 460         }
 461
 462         /* LVDS/eDP FMT is set up by atom */
 463         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 464                 return;
 465
 466         /* not needed for analog */
 467         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 468             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 469                 return;
 470
 471         if (bpc == 0)
 472                 return;
 473
 474         switch (bpc) {
 475         case 6:
 476                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 477                         /* XXX sort out optimal dither settings */
 478                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 479                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 480                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 481                                 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 482                 else
 483                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 484                         (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 485                 break;
 486         case 8:
 487                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 488                         /* XXX sort out optimal dither settings */
 489                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 490                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 491                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 492                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 493                                 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 494                 else
 495                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 496                         (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 497                 break;
 498         case 10:
 499                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 500                         /* XXX sort out optimal dither settings */
 501                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 502                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 503                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 504                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 505                                 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 506                 else
 507                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 508                         (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 509                 break;
 510         default:
 511                 /* not needed */
 512                 break;
 513         }
 514
 515         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 516 }
 517
 518
 519 /* display watermark setup */
 520 /**
 521  * dce_v8_0_line_buffer_adjust - Set up the line buffer
 522  *
 523  * @adev: amdgpu_device pointer
 524  * @amdgpu_crtc: the selected display controller
 525  * @mode: the current display mode on the selected display
 526  * controller
 527  *
 528  * Setup up the line buffer allocation for
 529  * the selected display controller (CIK).
 530  * Returns the line buffer size in pixels.
 531  */
 532 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
 533                                        struct amdgpu_crtc *amdgpu_crtc,
 534                                        struct drm_display_mode *mode)
 535 {
 536         u32 tmp, buffer_alloc, i;
 537         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 538         /*
 539          * Line Buffer Setup
 540          * There are 6 line buffers, one for each display controllers.
 541          * There are 3 partitions per LB. Select the number of partitions
 542          * to enable based on the display width.  For display widths larger
 543          * than 4096, you need use to use 2 display controllers and combine
 544          * them using the stereo blender.
 545          */
 546         if (amdgpu_crtc->base.enabled && mode) {
 547                 if (mode->crtc_hdisplay < 1920) {
 548                         tmp = 1;
 549                         buffer_alloc = 2;
 550                 } else if (mode->crtc_hdisplay < 2560) {
 551                         tmp = 2;
 552                         buffer_alloc = 2;
 553                 } else if (mode->crtc_hdisplay < 4096) {
 554                         tmp = 0;
 555                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 556                 } else {
 557                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 558                         tmp = 0;
 559                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 560                 }
 561         } else {
 562                 tmp = 1;
 563                 buffer_alloc = 0;
 564         }
 565
 566         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
 567               (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
 568               (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
 569
 570         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 571                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
 572         for (i = 0; i < adev->usec_timeout; i++) {
 573                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 574                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
 575                         break;
 576                 udelay(1);
 577         }
 578
 579         if (amdgpu_crtc->base.enabled && mode) {
 580                 switch (tmp) {
 581                 case 0:
 582                 default:
 583                         return 4096 * 2;
 584                 case 1:
 585                         return 1920 * 2;
 586                 case 2:
 587                         return 2560 * 2;
 588                 }
 589         }
 590
 591         /* controller not enabled, so no lb used */
 592         return 0;
 593 }
 594
 595 /**
 596  * cik_get_number_of_dram_channels - get the number of dram channels
 597  *
 598  * @adev: amdgpu_device pointer
 599  *
 600  * Look up the number of video ram channels (CIK).
 601  * Used for display watermark bandwidth calculations
 602  * Returns the number of dram channels
 603  */
 604 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 605 {
 606         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 607
 608         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 609         case 0:
 610         default:
 611                 return 1;
 612         case 1:
 613                 return 2;
 614         case 2:
 615                 return 4;
 616         case 3:
 617                 return 8;
 618         case 4:
 619                 return 3;
 620         case 5:
 621                 return 6;
 622         case 6:
 623                 return 10;
 624         case 7:
 625                 return 12;
 626         case 8:
 627                 return 16;
 628         }
 629 }
 630
 631 struct dce8_wm_params {
 632         u32 dram_channels; /* number of dram channels */
 633         u32 yclk;          /* bandwidth per dram data pin in kHz */
 634         u32 sclk;          /* engine clock in kHz */
 635         u32 disp_clk;      /* display clock in kHz */
 636         u32 src_width;     /* viewport width */
 637         u32 active_time;   /* active display time in ns */
 638         u32 blank_time;    /* blank time in ns */
 639         bool interlaced;    /* mode is interlaced */
 640         fixed20_12 vsc;    /* vertical scale ratio */
 641         u32 num_heads;     /* number of active crtcs */
 642         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 643         u32 lb_size;       /* line buffer allocated to pipe */
 644         u32 vtaps;         /* vertical scaler taps */
 645 };
 646
 647 /**
 648  * dce_v8_0_dram_bandwidth - get the dram bandwidth
 649  *
 650  * @wm: watermark calculation data
 651  *
 652  * Calculate the raw dram bandwidth (CIK).
 653  * Used for display watermark bandwidth calculations
 654  * Returns the dram bandwidth in MBytes/s
 655  */
 656 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
 657 {
 658         /* Calculate raw DRAM Bandwidth */
 659         fixed20_12 dram_efficiency; /* 0.7 */
 660         fixed20_12 yclk, dram_channels, bandwidth;
 661         fixed20_12 a;
 662
 663         a.full = dfixed_const(1000);
 664         yclk.full = dfixed_const(wm->yclk);
 665         yclk.full = dfixed_div(yclk, a);
 666         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 667         a.full = dfixed_const(10);
 668         dram_efficiency.full = dfixed_const(7);
 669         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 670         bandwidth.full = dfixed_mul(dram_channels, yclk);
 671         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 672
 673         return dfixed_trunc(bandwidth);
 674 }
 675
 676 /**
 677  * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
 678  *
 679  * @wm: watermark calculation data
 680  *
 681  * Calculate the dram bandwidth used for display (CIK).
 682  * Used for display watermark bandwidth calculations
 683  * Returns the dram bandwidth for display in MBytes/s
 684  */
 685 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 686 {
 687         /* Calculate DRAM Bandwidth and the part allocated to display. */
 688         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 689         fixed20_12 yclk, dram_channels, bandwidth;
 690         fixed20_12 a;
 691
 692         a.full = dfixed_const(1000);
 693         yclk.full = dfixed_const(wm->yclk);
 694         yclk.full = dfixed_div(yclk, a);
 695         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 696         a.full = dfixed_const(10);
 697         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 698         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 699         bandwidth.full = dfixed_mul(dram_channels, yclk);
 700         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 701
 702         return dfixed_trunc(bandwidth);
 703 }
 704
 705 /**
 706  * dce_v8_0_data_return_bandwidth - get the data return bandwidth
 707  *
 708  * @wm: watermark calculation data
 709  *
 710  * Calculate the data return bandwidth used for display (CIK).
 711  * Used for display watermark bandwidth calculations
 712  * Returns the data return bandwidth in MBytes/s
 713  */
 714 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
 715 {
 716         /* Calculate the display Data return Bandwidth */
 717         fixed20_12 return_efficiency; /* 0.8 */
 718         fixed20_12 sclk, bandwidth;
 719         fixed20_12 a;
 720
 721         a.full = dfixed_const(1000);
 722         sclk.full = dfixed_const(wm->sclk);
 723         sclk.full = dfixed_div(sclk, a);
 724         a.full = dfixed_const(10);
 725         return_efficiency.full = dfixed_const(8);
 726         return_efficiency.full = dfixed_div(return_efficiency, a);
 727         a.full = dfixed_const(32);
 728         bandwidth.full = dfixed_mul(a, sclk);
 729         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 730
 731         return dfixed_trunc(bandwidth);
 732 }
 733
 734 /**
 735  * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
 736  *
 737  * @wm: watermark calculation data
 738  *
 739  * Calculate the dmif bandwidth used for display (CIK).
 740  * Used for display watermark bandwidth calculations
 741  * Returns the dmif bandwidth in MBytes/s
 742  */
 743 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
 744 {
 745         /* Calculate the DMIF Request Bandwidth */
 746         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 747         fixed20_12 disp_clk, bandwidth;
 748         fixed20_12 a, b;
 749
 750         a.full = dfixed_const(1000);
 751         disp_clk.full = dfixed_const(wm->disp_clk);
 752         disp_clk.full = dfixed_div(disp_clk, a);
 753         a.full = dfixed_const(32);
 754         b.full = dfixed_mul(a, disp_clk);
 755
 756         a.full = dfixed_const(10);
 757         disp_clk_request_efficiency.full = dfixed_const(8);
 758         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 759
 760         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 761
 762         return dfixed_trunc(bandwidth);
 763 }
 764
 765 /**
 766  * dce_v8_0_available_bandwidth - get the min available bandwidth
 767  *
 768  * @wm: watermark calculation data
 769  *
 770  * Calculate the min available bandwidth used for display (CIK).
 771  * Used for display watermark bandwidth calculations
 772  * Returns the min available bandwidth in MBytes/s
 773  */
 774 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
 775 {
 776         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 777         u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
 778         u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
 779         u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
 780
 781         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 782 }
 783
 784 /**
 785  * dce_v8_0_average_bandwidth - get the average available bandwidth
 786  *
 787  * @wm: watermark calculation data
 788  *
 789  * Calculate the average available bandwidth used for display (CIK).
 790  * Used for display watermark bandwidth calculations
 791  * Returns the average available bandwidth in MBytes/s
 792  */
 793 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
 794 {
 795         /* Calculate the display mode Average Bandwidth
 796          * DisplayMode should contain the source and destination dimensions,
 797          * timing, etc.
 798          */
 799         fixed20_12 bpp;
 800         fixed20_12 line_time;
 801         fixed20_12 src_width;
 802         fixed20_12 bandwidth;
 803         fixed20_12 a;
 804
 805         a.full = dfixed_const(1000);
 806         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 807         line_time.full = dfixed_div(line_time, a);
 808         bpp.full = dfixed_const(wm->bytes_per_pixel);
 809         src_width.full = dfixed_const(wm->src_width);
 810         bandwidth.full = dfixed_mul(src_width, bpp);
 811         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 812         bandwidth.full = dfixed_div(bandwidth, line_time);
 813
 814         return dfixed_trunc(bandwidth);
 815 }
 816
 817 /**
 818  * dce_v8_0_latency_watermark - get the latency watermark
 819  *
 820  * @wm: watermark calculation data
 821  *
 822  * Calculate the latency watermark (CIK).
 823  * Used for display watermark bandwidth calculations
 824  * Returns the latency watermark in ns
 825  */
 826 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
 827 {
 828         /* First calculate the latency in ns */
 829         u32 mc_latency = 2000; /* 2000 ns. */
 830         u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
 831         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 832         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 833         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 834         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 835                 (wm->num_heads * cursor_line_pair_return_time);
 836         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 837         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 838         u32 tmp, dmif_size = 12288;
 839         fixed20_12 a, b, c;
 840
 841         if (wm->num_heads == 0)
 842                 return 0;
 843
 844         a.full = dfixed_const(2);
 845         b.full = dfixed_const(1);
 846         if ((wm->vsc.full > a.full) ||
 847             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 848             (wm->vtaps >= 5) ||
 849             ((wm->vsc.full >= a.full) && wm->interlaced))
 850                 max_src_lines_per_dst_line = 4;
 851         else
 852                 max_src_lines_per_dst_line = 2;
 853
 854         a.full = dfixed_const(available_bandwidth);
 855         b.full = dfixed_const(wm->num_heads);
 856         a.full = dfixed_div(a, b);
 857         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 858         tmp = min(dfixed_trunc(a), tmp);
 859
 860         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 861
 862         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 863         b.full = dfixed_const(1000);
 864         c.full = dfixed_const(lb_fill_bw);
 865         b.full = dfixed_div(c, b);
 866         a.full = dfixed_div(a, b);
 867         line_fill_time = dfixed_trunc(a);
 868
 869         if (line_fill_time < wm->active_time)
 870                 return latency;
 871         else
 872                 return latency + (line_fill_time - wm->active_time);
 873
 874 }
 875
 876 /**
 877  * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 878  * average and available dram bandwidth
 879  *
 880  * @wm: watermark calculation data
 881  *
 882  * Check if the display average bandwidth fits in the display
 883  * dram bandwidth (CIK).
 884  * Used for display watermark bandwidth calculations
 885  * Returns true if the display fits, false if not.
 886  */
 887 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 888 {
 889         if (dce_v8_0_average_bandwidth(wm) <=
 890             (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 891                 return true;
 892         else
 893                 return false;
 894 }
 895
 896 /**
 897  * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
 898  * average and available bandwidth
 899  *
 900  * @wm: watermark calculation data
 901  *
 902  * Check if the display average bandwidth fits in the display
 903  * available bandwidth (CIK).
 904  * Used for display watermark bandwidth calculations
 905  * Returns true if the display fits, false if not.
 906  */
 907 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
 908 {
 909         if (dce_v8_0_average_bandwidth(wm) <=
 910             (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
 911                 return true;
 912         else
 913                 return false;
 914 }
 915
 916 /**
 917  * dce_v8_0_check_latency_hiding - check latency hiding
 918  *
 919  * @wm: watermark calculation data
 920  *
 921  * Check latency hiding (CIK).
 922  * Used for display watermark bandwidth calculations
 923  * Returns true if the display fits, false if not.
 924  */
 925 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
 926 {
 927         u32 lb_partitions = wm->lb_size / wm->src_width;
 928         u32 line_time = wm->active_time + wm->blank_time;
 929         u32 latency_tolerant_lines;
 930         u32 latency_hiding;
 931         fixed20_12 a;
 932
 933         a.full = dfixed_const(1);
 934         if (wm->vsc.full > a.full)
 935                 latency_tolerant_lines = 1;
 936         else {
 937                 if (lb_partitions <= (wm->vtaps + 1))
 938                         latency_tolerant_lines = 1;
 939                 else
 940                         latency_tolerant_lines = 2;
 941         }
 942
 943         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 944
 945         if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
 946                 return true;
 947         else
 948                 return false;
 949 }
 950
 951 /**
 952  * dce_v8_0_program_watermarks - program display watermarks
 953  *
 954  * @adev: amdgpu_device pointer
 955  * @amdgpu_crtc: the selected display controller
 956  * @lb_size: line buffer size
 957  * @num_heads: number of display controllers in use
 958  *
 959  * Calculate and program the display watermarks for the
 960  * selected display controller (CIK).
 961  */
 962 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 963                                         struct amdgpu_crtc *amdgpu_crtc,
 964                                         u32 lb_size, u32 num_heads)
 965 {
 966         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 967         struct dce8_wm_params wm_low, wm_high;
 968         u32 active_time;
 969         u32 line_time = 0;
 970         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 971         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 972
 973         if (amdgpu_crtc->base.enabled && num_heads && mode) {
 974                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
 975                                             (u32)mode->clock);
 976                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
 977                                           (u32)mode->clock);
 978                 line_time = min(line_time, (u32)65535);
 979
 980                 /* watermark for high clocks */
 981                 if (adev->pm.dpm_enabled) {
 982                         wm_high.yclk =
 983                                 amdgpu_dpm_get_mclk(adev, false) * 10;
 984                         wm_high.sclk =
 985                                 amdgpu_dpm_get_sclk(adev, false) * 10;
 986                 } else {
 987                         wm_high.yclk = adev->pm.current_mclk * 10;
 988                         wm_high.sclk = adev->pm.current_sclk * 10;
 989                 }
 990
 991                 wm_high.disp_clk = mode->clock;
 992                 wm_high.src_width = mode->crtc_hdisplay;
 993                 wm_high.active_time = active_time;
 994                 wm_high.blank_time = line_time - wm_high.active_time;
 995                 wm_high.interlaced = false;
 996                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 997                         wm_high.interlaced = true;
 998                 wm_high.vsc = amdgpu_crtc->vsc;
 999                 wm_high.vtaps = 1;
1000                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1001                         wm_high.vtaps = 2;
1002                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1003                 wm_high.lb_size = lb_size;
1004                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1005                 wm_high.num_heads = num_heads;
1006
1007                 /* set for high clocks */
1008                 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1009
1010                 /* possibly force display priority to high */
1011                 /* should really do this at mode validation time... */
1012                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1013                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1014                     !dce_v8_0_check_latency_hiding(&wm_high) ||
1015                     (adev->mode_info.disp_priority == 2)) {
1016                         DRM_DEBUG_KMS("force priority to high\n");
1017                 }
1018
1019                 /* watermark for low clocks */
1020                 if (adev->pm.dpm_enabled) {
1021                         wm_low.yclk =
1022                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1023                         wm_low.sclk =
1024                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1025                 } else {
1026                         wm_low.yclk = adev->pm.current_mclk * 10;
1027                         wm_low.sclk = adev->pm.current_sclk * 10;
1028                 }
1029
1030                 wm_low.disp_clk = mode->clock;
1031                 wm_low.src_width = mode->crtc_hdisplay;
1032                 wm_low.active_time = active_time;
1033                 wm_low.blank_time = line_time - wm_low.active_time;
1034                 wm_low.interlaced = false;
1035                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1036                         wm_low.interlaced = true;
1037                 wm_low.vsc = amdgpu_crtc->vsc;
1038                 wm_low.vtaps = 1;
1039                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1040                         wm_low.vtaps = 2;
1041                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1042                 wm_low.lb_size = lb_size;
1043                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1044                 wm_low.num_heads = num_heads;
1045
1046                 /* set for low clocks */
1047                 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1048
1049                 /* possibly force display priority to high */
1050                 /* should really do this at mode validation time... */
1051                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1052                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1053                     !dce_v8_0_check_latency_hiding(&wm_low) ||
1054                     (adev->mode_info.disp_priority == 2)) {
1055                         DRM_DEBUG_KMS("force priority to high\n");
1056                 }
1057                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1058         }
1059
1060         /* select wm A */
1061         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1062         tmp = wm_mask;
1063         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1064         tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1065         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1066         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1067                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1068                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1069         /* select wm B */
1070         tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1071         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1072         tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1073         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1074         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1075                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1076                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1077         /* restore original selection */
1078         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1079
1080         /* save values for DPM */
1081         amdgpu_crtc->line_time = line_time;
1082         amdgpu_crtc->wm_high = latency_watermark_a;
1083         amdgpu_crtc->wm_low = latency_watermark_b;
1084         /* Save number of lines the linebuffer leads before the scanout */
1085         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1086 }
1087
1088 /**
1089  * dce_v8_0_bandwidth_update - program display watermarks
1090  *
1091  * @adev: amdgpu_device pointer
1092  *
1093  * Calculate and program the display watermarks and line
1094  * buffer allocation (CIK).
1095  */
1096 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1097 {
1098         struct drm_display_mode *mode = NULL;
1099         u32 num_heads = 0, lb_size;
1100         int i;
1101
1102         amdgpu_display_update_priority(adev);
1103
1104         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1105                 if (adev->mode_info.crtcs[i]->base.enabled)
1106                         num_heads++;
1107         }
1108         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1109                 mode = &adev->mode_info.crtcs[i]->base.mode;
1110                 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1111                 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1112                                             lb_size, num_heads);
1113         }
1114 }
1115
1116 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1117 {
1118         int i;
1119         u32 offset, tmp;
1120
1121         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1122                 offset = adev->mode_info.audio.pin[i].offset;
1123                 tmp = RREG32_AUDIO_ENDPT(offset,
1124                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1125                 if (((tmp &
1126                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1127                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1128                         adev->mode_info.audio.pin[i].connected = false;
1129                 else
1130                         adev->mode_info.audio.pin[i].connected = true;
1131         }
1132 }
1133
1134 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1135 {
1136         int i;
1137
1138         dce_v8_0_audio_get_connected_pins(adev);
1139
1140         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1141                 if (adev->mode_info.audio.pin[i].connected)
1142                         return &adev->mode_info.audio.pin[i];
1143         }
1144         DRM_ERROR("No connected audio pins found!\n");
1145         return NULL;
1146 }
1147
1148 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1149 {
1150         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1151         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1152         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1153         u32 offset;
1154
1155         if (!dig || !dig->afmt || !dig->afmt->pin)
1156                 return;
1157
1158         offset = dig->afmt->offset;
1159
1160         WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1161                (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1162 }
1163
1164 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1165                                                 struct drm_display_mode *mode)
1166 {
1167         struct drm_device *dev = encoder->dev;
1168         struct amdgpu_device *adev = drm_to_adev(dev);
1169         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1170         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1171         struct drm_connector *connector;
1172         struct drm_connector_list_iter iter;
1173         struct amdgpu_connector *amdgpu_connector = NULL;
1174         u32 tmp = 0, offset;
1175
1176         if (!dig || !dig->afmt || !dig->afmt->pin)
1177                 return;
1178
1179         offset = dig->afmt->pin->offset;
1180
1181         drm_connector_list_iter_begin(dev, &iter);
1182         drm_for_each_connector_iter(connector, &iter) {
1183                 if (connector->encoder == encoder) {
1184                         amdgpu_connector = to_amdgpu_connector(connector);
1185                         break;
1186                 }
1187         }
1188         drm_connector_list_iter_end(&iter);
1189
1190         if (!amdgpu_connector) {
1191                 DRM_ERROR("Couldn't find encoder's connector\n");
1192                 return;
1193         }
1194
1195         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1196                 if (connector->latency_present[1])
1197                         tmp =
1198                         (connector->video_latency[1] <<
1199                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1200                         (connector->audio_latency[1] <<
1201                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1202                 else
1203                         tmp =
1204                         (0 <<
1205                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1206                         (0 <<
1207                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1208         } else {
1209                 if (connector->latency_present[0])
1210                         tmp =
1211                         (connector->video_latency[0] <<
1212                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1213                         (connector->audio_latency[0] <<
1214                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1215                 else
1216                         tmp =
1217                         (0 <<
1218                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1219                         (0 <<
1220                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1221
1222         }
1223         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1224 }
1225
1226 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1227 {
1228         struct drm_device *dev = encoder->dev;
1229         struct amdgpu_device *adev = drm_to_adev(dev);
1230         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1231         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1232         struct drm_connector *connector;
1233         struct drm_connector_list_iter iter;
1234         struct amdgpu_connector *amdgpu_connector = NULL;
1235         u32 offset, tmp;
1236         u8 *sadb = NULL;
1237         int sad_count;
1238
1239         if (!dig || !dig->afmt || !dig->afmt->pin)
1240                 return;
1241
1242         offset = dig->afmt->pin->offset;
1243
1244         drm_connector_list_iter_begin(dev, &iter);
1245         drm_for_each_connector_iter(connector, &iter) {
1246                 if (connector->encoder == encoder) {
1247                         amdgpu_connector = to_amdgpu_connector(connector);
1248                         break;
1249                 }
1250         }
1251         drm_connector_list_iter_end(&iter);
1252
1253         if (!amdgpu_connector) {
1254                 DRM_ERROR("Couldn't find encoder's connector\n");
1255                 return;
1256         }
1257
1258         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1259         if (sad_count < 0) {
1260                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1261                 sad_count = 0;
1262         }
1263
1264         /* program the speaker allocation */
1265         tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1266         tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1267                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1268         /* set HDMI mode */
1269         tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1270         if (sad_count)
1271                 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1272         else
1273                 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1274         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1275
1276         kfree(sadb);
1277 }
1278
1279 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1280 {
1281         struct drm_device *dev = encoder->dev;
1282         struct amdgpu_device *adev = drm_to_adev(dev);
1283         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1284         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1285         u32 offset;
1286         struct drm_connector *connector;
1287         struct drm_connector_list_iter iter;
1288         struct amdgpu_connector *amdgpu_connector = NULL;
1289         struct cea_sad *sads;
1290         int i, sad_count;
1291
1292         static const u16 eld_reg_to_type[][2] = {
1293                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1294                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1295                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1296                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1297                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1298                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1299                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1300                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1301                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1302                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1303                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1304                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1305         };
1306
1307         if (!dig || !dig->afmt || !dig->afmt->pin)
1308                 return;
1309
1310         offset = dig->afmt->pin->offset;
1311
1312         drm_connector_list_iter_begin(dev, &iter);
1313         drm_for_each_connector_iter(connector, &iter) {
1314                 if (connector->encoder == encoder) {
1315                         amdgpu_connector = to_amdgpu_connector(connector);
1316                         break;
1317                 }
1318         }
1319         drm_connector_list_iter_end(&iter);
1320
1321         if (!amdgpu_connector) {
1322                 DRM_ERROR("Couldn't find encoder's connector\n");
1323                 return;
1324         }
1325
1326         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1327         if (sad_count < 0)
1328                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1329         if (sad_count <= 0)
1330                 return;
1331         BUG_ON(!sads);
1332
1333         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1334                 u32 value = 0;
1335                 u8 stereo_freqs = 0;
1336                 int max_channels = -1;
1337                 int j;
1338
1339                 for (j = 0; j < sad_count; j++) {
1340                         struct cea_sad *sad = &sads[j];
1341
1342                         if (sad->format == eld_reg_to_type[i][1]) {
1343                                 if (sad->channels > max_channels) {
1344                                         value = (sad->channels <<
1345                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1346                                                 (sad->byte2 <<
1347                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1348                                                 (sad->freq <<
1349                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1350                                         max_channels = sad->channels;
1351                                 }
1352
1353                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1354                                         stereo_freqs |= sad->freq;
1355                                 else
1356                                         break;
1357                         }
1358                 }
1359
1360                 value |= (stereo_freqs <<
1361                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1362
1363                 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1364         }
1365
1366         kfree(sads);
1367 }
1368
1369 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1370                                   struct amdgpu_audio_pin *pin,
1371                                   bool enable)
1372 {
1373         if (!pin)
1374                 return;
1375
1376         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1377                 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1378 }
1379
1380 static const u32 pin_offsets[7] =
1381 {
1382         (0x1780 - 0x1780),
1383         (0x1786 - 0x1780),
1384         (0x178c - 0x1780),
1385         (0x1792 - 0x1780),
1386         (0x1798 - 0x1780),
1387         (0x179d - 0x1780),
1388         (0x17a4 - 0x1780),
1389 };
1390
1391 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1392 {
1393         int i;
1394
1395         if (!amdgpu_audio)
1396                 return 0;
1397
1398         adev->mode_info.audio.enabled = true;
1399
1400         if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1401                 adev->mode_info.audio.num_pins = 7;
1402         else if ((adev->asic_type == CHIP_KABINI) ||
1403                  (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1404                 adev->mode_info.audio.num_pins = 3;
1405         else if ((adev->asic_type == CHIP_BONAIRE) ||
1406                  (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1407                 adev->mode_info.audio.num_pins = 7;
1408         else
1409                 adev->mode_info.audio.num_pins = 3;
1410
1411         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1412                 adev->mode_info.audio.pin[i].channels = -1;
1413                 adev->mode_info.audio.pin[i].rate = -1;
1414                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1415                 adev->mode_info.audio.pin[i].status_bits = 0;
1416                 adev->mode_info.audio.pin[i].category_code = 0;
1417                 adev->mode_info.audio.pin[i].connected = false;
1418                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1419                 adev->mode_info.audio.pin[i].id = i;
1420                 /* disable audio.  it will be set up later */
1421                 /* XXX remove once we switch to ip funcs */
1422                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1423         }
1424
1425         return 0;
1426 }
1427
1428 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1429 {
1430         int i;
1431
1432         if (!amdgpu_audio)
1433                 return;
1434
1435         if (!adev->mode_info.audio.enabled)
1436                 return;
1437
1438         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1439                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1440
1441         adev->mode_info.audio.enabled = false;
1442 }
1443
1444 /*
1445  * update the N and CTS parameters for a given pixel clock rate
1446  */
1447 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1448 {
1449         struct drm_device *dev = encoder->dev;
1450         struct amdgpu_device *adev = drm_to_adev(dev);
1451         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1452         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1453         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1454         uint32_t offset = dig->afmt->offset;
1455
1456         WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1457         WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1458
1459         WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1460         WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1461
1462         WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1463         WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1464 }
1465
1466 /*
1467  * build a HDMI Video Info Frame
1468  */
1469 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1470                                                void *buffer, size_t size)
1471 {
1472         struct drm_device *dev = encoder->dev;
1473         struct amdgpu_device *adev = drm_to_adev(dev);
1474         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1475         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1476         uint32_t offset = dig->afmt->offset;
1477         uint8_t *frame = buffer + 3;
1478         uint8_t *header = buffer;
1479
1480         WREG32(mmAFMT_AVI_INFO0 + offset,
1481                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1482         WREG32(mmAFMT_AVI_INFO1 + offset,
1483                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1484         WREG32(mmAFMT_AVI_INFO2 + offset,
1485                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1486         WREG32(mmAFMT_AVI_INFO3 + offset,
1487                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1488 }
1489
1490 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1491 {
1492         struct drm_device *dev = encoder->dev;
1493         struct amdgpu_device *adev = drm_to_adev(dev);
1494         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1495         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1496         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1497         u32 dto_phase = 24 * 1000;
1498         u32 dto_modulo = clock;
1499
1500         if (!dig || !dig->afmt)
1501                 return;
1502
1503         /* XXX two dtos; generally use dto0 for hdmi */
1504         /* Express [24MHz / target pixel clock] as an exact rational
1505          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1506          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1507          */
1508         WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1509         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1510         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1511 }
1512
1513 /*
1514  * update the info frames with the data from the current display mode
1515  */
1516 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1517                                   struct drm_display_mode *mode)
1518 {
1519         struct drm_device *dev = encoder->dev;
1520         struct amdgpu_device *adev = drm_to_adev(dev);
1521         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1522         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1523         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1524         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1525         struct hdmi_avi_infoframe frame;
1526         uint32_t offset, val;
1527         ssize_t err;
1528         int bpc = 8;
1529
1530         if (!dig || !dig->afmt)
1531                 return;
1532
1533         /* Silent, r600_hdmi_enable will raise WARN for us */
1534         if (!dig->afmt->enabled)
1535                 return;
1536
1537         offset = dig->afmt->offset;
1538
1539         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1540         if (encoder->crtc) {
1541                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1542                 bpc = amdgpu_crtc->bpc;
1543         }
1544
1545         /* disable audio prior to setting up hw */
1546         dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1547         dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1548
1549         dce_v8_0_audio_set_dto(encoder, mode->clock);
1550
1551         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1552                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1553
1554         WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1555
1556         val = RREG32(mmHDMI_CONTROL + offset);
1557         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1558         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1559
1560         switch (bpc) {
1561         case 0:
1562         case 6:
1563         case 8:
1564         case 16:
1565         default:
1566                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1567                           connector->name, bpc);
1568                 break;
1569         case 10:
1570                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1571                 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1572                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1573                           connector->name);
1574                 break;
1575         case 12:
1576                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1577                 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1578                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1579                           connector->name);
1580                 break;
1581         }
1582
1583         WREG32(mmHDMI_CONTROL + offset, val);
1584
1585         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1586                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1587                HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1588                HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1589
1590         WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1591                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1592                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1593
1594         WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1595                AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1596
1597         WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1598                (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1599
1600         WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1601
1602         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1603                (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1604                (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1605
1606         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1607                AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1608
1609         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1610
1611         if (bpc > 8)
1612                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1613                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1614         else
1615                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1616                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1617                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1618
1619         dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1620
1621         WREG32(mmAFMT_60958_0 + offset,
1622                (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1623
1624         WREG32(mmAFMT_60958_1 + offset,
1625                (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1626
1627         WREG32(mmAFMT_60958_2 + offset,
1628                (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1629                (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1630                (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1631                (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1632                (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1633                (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1634
1635         dce_v8_0_audio_write_speaker_allocation(encoder);
1636
1637
1638         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1639                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1640
1641         dce_v8_0_afmt_audio_select_pin(encoder);
1642         dce_v8_0_audio_write_sad_regs(encoder);
1643         dce_v8_0_audio_write_latency_fields(encoder, mode);
1644
1645         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1646         if (err < 0) {
1647                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1648                 return;
1649         }
1650
1651         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1652         if (err < 0) {
1653                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1654                 return;
1655         }
1656
1657         dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1658
1659         WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1660                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1661                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1662
1663         WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1664                  (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1665                  ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1666
1667         WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1668                   AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1669
1670         WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1671         WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1672         WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1673         WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1674
1675         /* enable audio after setting up hw */
1676         dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1677 }
1678
1679 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1680 {
1681         struct drm_device *dev = encoder->dev;
1682         struct amdgpu_device *adev = drm_to_adev(dev);
1683         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1684         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1685
1686         if (!dig || !dig->afmt)
1687                 return;
1688
1689         /* Silent, r600_hdmi_enable will raise WARN for us */
1690         if (enable && dig->afmt->enabled)
1691                 return;
1692         if (!enable && !dig->afmt->enabled)
1693                 return;
1694
1695         if (!enable && dig->afmt->pin) {
1696                 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1697                 dig->afmt->pin = NULL;
1698         }
1699
1700         dig->afmt->enabled = enable;
1701
1702         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1703                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1704 }
1705
1706 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1707 {
1708         int i;
1709
1710         for (i = 0; i < adev->mode_info.num_dig; i++)
1711                 adev->mode_info.afmt[i] = NULL;
1712
1713         /* DCE8 has audio blocks tied to DIG encoders */
1714         for (i = 0; i < adev->mode_info.num_dig; i++) {
1715                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1716                 if (adev->mode_info.afmt[i]) {
1717                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1718                         adev->mode_info.afmt[i]->id = i;
1719                 } else {
1720                         int j;
1721                         for (j = 0; j < i; j++) {
1722                                 kfree(adev->mode_info.afmt[j]);
1723                                 adev->mode_info.afmt[j] = NULL;
1724                         }
1725                         return -ENOMEM;
1726                 }
1727         }
1728         return 0;
1729 }
1730
1731 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1732 {
1733         int i;
1734
1735         for (i = 0; i < adev->mode_info.num_dig; i++) {
1736                 kfree(adev->mode_info.afmt[i]);
1737                 adev->mode_info.afmt[i] = NULL;
1738         }
1739 }
1740
1741 static const u32 vga_control_regs[6] =
1742 {
1743         mmD1VGA_CONTROL,
1744         mmD2VGA_CONTROL,
1745         mmD3VGA_CONTROL,
1746         mmD4VGA_CONTROL,
1747         mmD5VGA_CONTROL,
1748         mmD6VGA_CONTROL,
1749 };
1750
1751 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1752 {
1753         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1754         struct drm_device *dev = crtc->dev;
1755         struct amdgpu_device *adev = drm_to_adev(dev);
1756         u32 vga_control;
1757
1758         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1759         if (enable)
1760                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1761         else
1762                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1763 }
1764
1765 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1766 {
1767         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1768         struct drm_device *dev = crtc->dev;
1769         struct amdgpu_device *adev = drm_to_adev(dev);
1770
1771         if (enable)
1772                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1773         else
1774                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1775 }
1776
1777 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1778                                      struct drm_framebuffer *fb,
1779                                      int x, int y, int atomic)
1780 {
1781         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1782         struct drm_device *dev = crtc->dev;
1783         struct amdgpu_device *adev = drm_to_adev(dev);
1784         struct drm_framebuffer *target_fb;
1785         struct drm_gem_object *obj;
1786         struct amdgpu_bo *abo;
1787         uint64_t fb_location, tiling_flags;
1788         uint32_t fb_format, fb_pitch_pixels;
1789         u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1790         u32 pipe_config;
1791         u32 viewport_w, viewport_h;
1792         int r;
1793         bool bypass_lut = false;
1794
1795         /* no fb bound */
1796         if (!atomic && !crtc->primary->fb) {
1797                 DRM_DEBUG_KMS("No FB bound\n");
1798                 return 0;
1799         }
1800
1801         if (atomic)
1802                 target_fb = fb;
1803         else
1804                 target_fb = crtc->primary->fb;
1805
1806         /* If atomic, assume fb object is pinned & idle & fenced and
1807          * just update base pointers
1808          */
1809         obj = target_fb->obj[0];
1810         abo = gem_to_amdgpu_bo(obj);
1811         r = amdgpu_bo_reserve(abo, false);
1812         if (unlikely(r != 0))
1813                 return r;
1814
1815         if (!atomic) {
1816                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1817                 if (unlikely(r != 0)) {
1818                         amdgpu_bo_unreserve(abo);
1819                         return -EINVAL;
1820                 }
1821         }
1822         fb_location = amdgpu_bo_gpu_offset(abo);
1823
1824         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1825         amdgpu_bo_unreserve(abo);
1826
1827         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1828
1829         switch (target_fb->format->format) {
1830         case DRM_FORMAT_C8:
1831                 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1832                              (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1833                 break;
1834         case DRM_FORMAT_XRGB4444:
1835         case DRM_FORMAT_ARGB4444:
1836                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1837                              (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1838 #ifdef __BIG_ENDIAN
1839                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1840 #endif
1841                 break;
1842         case DRM_FORMAT_XRGB1555:
1843         case DRM_FORMAT_ARGB1555:
1844                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1845                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1846 #ifdef __BIG_ENDIAN
1847                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1848 #endif
1849                 break;
1850         case DRM_FORMAT_BGRX5551:
1851         case DRM_FORMAT_BGRA5551:
1852                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1853                              (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1854 #ifdef __BIG_ENDIAN
1855                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1856 #endif
1857                 break;
1858         case DRM_FORMAT_RGB565:
1859                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1860                              (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1861 #ifdef __BIG_ENDIAN
1862                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1863 #endif
1864                 break;
1865         case DRM_FORMAT_XRGB8888:
1866         case DRM_FORMAT_ARGB8888:
1867                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1868                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1869 #ifdef __BIG_ENDIAN
1870                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1871 #endif
1872                 break;
1873         case DRM_FORMAT_XRGB2101010:
1874         case DRM_FORMAT_ARGB2101010:
1875                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1876                              (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1877 #ifdef __BIG_ENDIAN
1878                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1879 #endif
1880                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1881                 bypass_lut = true;
1882                 break;
1883         case DRM_FORMAT_BGRX1010102:
1884         case DRM_FORMAT_BGRA1010102:
1885                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1886                              (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1887 #ifdef __BIG_ENDIAN
1888                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1889 #endif
1890                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1891                 bypass_lut = true;
1892                 break;
1893         case DRM_FORMAT_XBGR8888:
1894         case DRM_FORMAT_ABGR8888:
1895                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1896                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1897                 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1898                            (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1899 #ifdef __BIG_ENDIAN
1900                 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1901 #endif
1902                 break;
1903         default:
1904                 DRM_ERROR("Unsupported screen format %p4cc\n",
1905                           &target_fb->format->format);
1906                 return -EINVAL;
1907         }
1908
1909         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1910                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1911
1912                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1913                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1914                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1915                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1916                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1917
1918                 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1919                 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1920                 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1921                 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1922                 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1923                 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1924                 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1925         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1926                 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1927         }
1928
1929         fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1930
1931         dce_v8_0_vga_enable(crtc, false);
1932
1933         /* Make sure surface address is updated at vertical blank rather than
1934          * horizontal blank
1935          */
1936         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1937
1938         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1939                upper_32_bits(fb_location));
1940         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1941                upper_32_bits(fb_location));
1942         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1943                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1944         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1945                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1946         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1947         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1948
1949         /*
1950          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1951          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1952          * retain the full precision throughout the pipeline.
1953          */
1954         WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1955                  (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1956                  ~LUT_10BIT_BYPASS_EN);
1957
1958         if (bypass_lut)
1959                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1960
1961         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1962         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1963         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1964         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1965         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1966         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1967
1968         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1969         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1970
1971         dce_v8_0_grph_enable(crtc, true);
1972
1973         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1974                target_fb->height);
1975
1976         x &= ~3;
1977         y &= ~1;
1978         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1979                (x << 16) | y);
1980         viewport_w = crtc->mode.hdisplay;
1981         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1982         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1983                (viewport_w << 16) | viewport_h);
1984
1985         /* set pageflip to happen anywhere in vblank interval */
1986         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1987
1988         if (!atomic && fb && fb != crtc->primary->fb) {
1989                 abo = gem_to_amdgpu_bo(fb->obj[0]);
1990                 r = amdgpu_bo_reserve(abo, true);
1991                 if (unlikely(r != 0))
1992                         return r;
1993                 amdgpu_bo_unpin(abo);
1994                 amdgpu_bo_unreserve(abo);
1995         }
1996
1997         /* Bytes per pixel may have changed */
1998         dce_v8_0_bandwidth_update(adev);
1999
2000         return 0;
2001 }
2002
2003 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2004                                     struct drm_display_mode *mode)
2005 {
2006         struct drm_device *dev = crtc->dev;
2007         struct amdgpu_device *adev = drm_to_adev(dev);
2008         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009
2010         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2011                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2012                        LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2013         else
2014                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2015 }
2016
2017 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2018 {
2019         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2020         struct drm_device *dev = crtc->dev;
2021         struct amdgpu_device *adev = drm_to_adev(dev);
2022         u16 *r, *g, *b;
2023         int i;
2024
2025         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2026
2027         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2028                ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2029                 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2030         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2031                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2032         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2033                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2034         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2035                ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2036                 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2037
2038         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2039
2040         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2041         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2042         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2043
2044         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2045         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2046         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2047
2048         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2049         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2050
2051         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2052         r = crtc->gamma_store;
2053         g = r + crtc->gamma_size;
2054         b = g + crtc->gamma_size;
2055         for (i = 0; i < 256; i++) {
2056                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2057                        ((*r++ & 0xffc0) << 14) |
2058                        ((*g++ & 0xffc0) << 4) |
2059                        (*b++ >> 6));
2060         }
2061
2062         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2063                ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2064                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2065                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2066         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2067                ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2068                 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2069         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2070                ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2071                 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2072         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2073                ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2074                 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2075         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2076         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2077         /* XXX this only needs to be programmed once per crtc at startup,
2078          * not sure where the best place for it is
2079          */
2080         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2081                ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2082 }
2083
2084 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2085 {
2086         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2087         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2088
2089         switch (amdgpu_encoder->encoder_id) {
2090         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2091                 if (dig->linkb)
2092                         return 1;
2093                 else
2094                         return 0;
2095                 break;
2096         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2097                 if (dig->linkb)
2098                         return 3;
2099                 else
2100                         return 2;
2101                 break;
2102         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2103                 if (dig->linkb)
2104                         return 5;
2105                 else
2106                         return 4;
2107                 break;
2108         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2109                 return 6;
2110                 break;
2111         default:
2112                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2113                 return 0;
2114         }
2115 }
2116
2117 /**
2118  * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2119  *
2120  * @crtc: drm crtc
2121  *
2122  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2123  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2124  * monitors a dedicated PPLL must be used.  If a particular board has
2125  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2126  * as there is no need to program the PLL itself.  If we are not able to
2127  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2128  * avoid messing up an existing monitor.
2129  *
2130  * Asic specific PLL information
2131  *
2132  * DCE 8.x
2133  * KB/KV
2134  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2135  * CI
2136  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2137  *
2138  */
2139 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2140 {
2141         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142         struct drm_device *dev = crtc->dev;
2143         struct amdgpu_device *adev = drm_to_adev(dev);
2144         u32 pll_in_use;
2145         int pll;
2146
2147         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2148                 if (adev->clock.dp_extclk)
2149                         /* skip PPLL programming if using ext clock */
2150                         return ATOM_PPLL_INVALID;
2151                 else {
2152                         /* use the same PPLL for all DP monitors */
2153                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2154                         if (pll != ATOM_PPLL_INVALID)
2155                                 return pll;
2156                 }
2157         } else {
2158                 /* use the same PPLL for all monitors with the same clock */
2159                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2160                 if (pll != ATOM_PPLL_INVALID)
2161                         return pll;
2162         }
2163         /* otherwise, pick one of the plls */
2164         if ((adev->asic_type == CHIP_KABINI) ||
2165             (adev->asic_type == CHIP_MULLINS)) {
2166                 /* KB/ML has PPLL1 and PPLL2 */
2167                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2168                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2169                         return ATOM_PPLL2;
2170                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2171                         return ATOM_PPLL1;
2172                 DRM_ERROR("unable to allocate a PPLL\n");
2173                 return ATOM_PPLL_INVALID;
2174         } else {
2175                 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2176                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2177                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2178                         return ATOM_PPLL2;
2179                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2180                         return ATOM_PPLL1;
2181                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2182                         return ATOM_PPLL0;
2183                 DRM_ERROR("unable to allocate a PPLL\n");
2184                 return ATOM_PPLL_INVALID;
2185         }
2186         return ATOM_PPLL_INVALID;
2187 }
2188
2189 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2190 {
2191         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2192         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2193         uint32_t cur_lock;
2194
2195         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2196         if (lock)
2197                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2198         else
2199                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2200         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2201 }
2202
2203 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2204 {
2205         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2206         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2207
2208         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2209                (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2210                (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2211 }
2212
2213 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2214 {
2215         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2216         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2217
2218         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2219                upper_32_bits(amdgpu_crtc->cursor_addr));
2220         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2221                lower_32_bits(amdgpu_crtc->cursor_addr));
2222
2223         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2224                CUR_CONTROL__CURSOR_EN_MASK |
2225                (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2226                (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2227 }
2228
2229 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2230                                        int x, int y)
2231 {
2232         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2233         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2234         int xorigin = 0, yorigin = 0;
2235
2236         amdgpu_crtc->cursor_x = x;
2237         amdgpu_crtc->cursor_y = y;
2238
2239         /* avivo cursor are offset into the total surface */
2240         x += crtc->x;
2241         y += crtc->y;
2242         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2243
2244         if (x < 0) {
2245                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2246                 x = 0;
2247         }
2248         if (y < 0) {
2249                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2250                 y = 0;
2251         }
2252
2253         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2254         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2255         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2256                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2257
2258         return 0;
2259 }
2260
2261 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2262                                      int x, int y)
2263 {
2264         int ret;
2265
2266         dce_v8_0_lock_cursor(crtc, true);
2267         ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2268         dce_v8_0_lock_cursor(crtc, false);
2269
2270         return ret;
2271 }
2272
2273 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2274                                      struct drm_file *file_priv,
2275                                      uint32_t handle,
2276                                      uint32_t width,
2277                                      uint32_t height,
2278                                      int32_t hot_x,
2279                                      int32_t hot_y)
2280 {
2281         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2282         struct drm_gem_object *obj;
2283         struct amdgpu_bo *aobj;
2284         int ret;
2285
2286         if (!handle) {
2287                 /* turn off cursor */
2288                 dce_v8_0_hide_cursor(crtc);
2289                 obj = NULL;
2290                 goto unpin;
2291         }
2292
2293         if ((width > amdgpu_crtc->max_cursor_width) ||
2294             (height > amdgpu_crtc->max_cursor_height)) {
2295                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2296                 return -EINVAL;
2297         }
2298
2299         obj = drm_gem_object_lookup(file_priv, handle);
2300         if (!obj) {
2301                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2302                 return -ENOENT;
2303         }
2304
2305         aobj = gem_to_amdgpu_bo(obj);
2306         ret = amdgpu_bo_reserve(aobj, false);
2307         if (ret != 0) {
2308                 drm_gem_object_put(obj);
2309                 return ret;
2310         }
2311
2312         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2313         amdgpu_bo_unreserve(aobj);
2314         if (ret) {
2315                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2316                 drm_gem_object_put(obj);
2317                 return ret;
2318         }
2319         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2320
2321         dce_v8_0_lock_cursor(crtc, true);
2322
2323         if (width != amdgpu_crtc->cursor_width ||
2324             height != amdgpu_crtc->cursor_height ||
2325             hot_x != amdgpu_crtc->cursor_hot_x ||
2326             hot_y != amdgpu_crtc->cursor_hot_y) {
2327                 int x, y;
2328
2329                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2330                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2331
2332                 dce_v8_0_cursor_move_locked(crtc, x, y);
2333
2334                 amdgpu_crtc->cursor_width = width;
2335                 amdgpu_crtc->cursor_height = height;
2336                 amdgpu_crtc->cursor_hot_x = hot_x;
2337                 amdgpu_crtc->cursor_hot_y = hot_y;
2338         }
2339
2340         dce_v8_0_show_cursor(crtc);
2341         dce_v8_0_lock_cursor(crtc, false);
2342
2343 unpin:
2344         if (amdgpu_crtc->cursor_bo) {
2345                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2346                 ret = amdgpu_bo_reserve(aobj, true);
2347                 if (likely(ret == 0)) {
2348                         amdgpu_bo_unpin(aobj);
2349                         amdgpu_bo_unreserve(aobj);
2350                 }
2351                 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2352         }
2353
2354         amdgpu_crtc->cursor_bo = obj;
2355         return 0;
2356 }
2357
2358 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2359 {
2360         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2361
2362         if (amdgpu_crtc->cursor_bo) {
2363                 dce_v8_0_lock_cursor(crtc, true);
2364
2365                 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2366                                             amdgpu_crtc->cursor_y);
2367
2368                 dce_v8_0_show_cursor(crtc);
2369
2370                 dce_v8_0_lock_cursor(crtc, false);
2371         }
2372 }
2373
2374 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2375                                    u16 *blue, uint32_t size,
2376                                    struct drm_modeset_acquire_ctx *ctx)
2377 {
2378         dce_v8_0_crtc_load_lut(crtc);
2379
2380         return 0;
2381 }
2382
2383 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2384 {
2385         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2386
2387         drm_crtc_cleanup(crtc);
2388         kfree(amdgpu_crtc);
2389 }
2390
2391 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2392         .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2393         .cursor_move = dce_v8_0_crtc_cursor_move,
2394         .gamma_set = dce_v8_0_crtc_gamma_set,
2395         .set_config = amdgpu_display_crtc_set_config,
2396         .destroy = dce_v8_0_crtc_destroy,
2397         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2398         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2399         .enable_vblank = amdgpu_enable_vblank_kms,
2400         .disable_vblank = amdgpu_disable_vblank_kms,
2401         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2402 };
2403
2404 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct amdgpu_device *adev = drm_to_adev(dev);
2408         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2409         unsigned type;
2410
2411         switch (mode) {
2412         case DRM_MODE_DPMS_ON:
2413                 amdgpu_crtc->enabled = true;
2414                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2415                 dce_v8_0_vga_enable(crtc, true);
2416                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2417                 dce_v8_0_vga_enable(crtc, false);
2418                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2419                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2420                                                 amdgpu_crtc->crtc_id);
2421                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2422                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2423                 drm_crtc_vblank_on(crtc);
2424                 dce_v8_0_crtc_load_lut(crtc);
2425                 break;
2426         case DRM_MODE_DPMS_STANDBY:
2427         case DRM_MODE_DPMS_SUSPEND:
2428         case DRM_MODE_DPMS_OFF:
2429                 drm_crtc_vblank_off(crtc);
2430                 if (amdgpu_crtc->enabled) {
2431                         dce_v8_0_vga_enable(crtc, true);
2432                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2433                         dce_v8_0_vga_enable(crtc, false);
2434                 }
2435                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2436                 amdgpu_crtc->enabled = false;
2437                 break;
2438         }
2439         /* adjust pm to dpms */
2440         amdgpu_pm_compute_clocks(adev);
2441 }
2442
2443 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2444 {
2445         /* disable crtc pair power gating before programming */
2446         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2447         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2448         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2449 }
2450
2451 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2452 {
2453         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2454         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2455 }
2456
2457 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2458 {
2459         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2460         struct drm_device *dev = crtc->dev;
2461         struct amdgpu_device *adev = drm_to_adev(dev);
2462         struct amdgpu_atom_ss ss;
2463         int i;
2464
2465         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2466         if (crtc->primary->fb) {
2467                 int r;
2468                 struct amdgpu_bo *abo;
2469
2470                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2471                 r = amdgpu_bo_reserve(abo, true);
2472                 if (unlikely(r))
2473                         DRM_ERROR("failed to reserve abo before unpin\n");
2474                 else {
2475                         amdgpu_bo_unpin(abo);
2476                         amdgpu_bo_unreserve(abo);
2477                 }
2478         }
2479         /* disable the GRPH */
2480         dce_v8_0_grph_enable(crtc, false);
2481
2482         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2483
2484         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2485                 if (adev->mode_info.crtcs[i] &&
2486                     adev->mode_info.crtcs[i]->enabled &&
2487                     i != amdgpu_crtc->crtc_id &&
2488                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2489                         /* one other crtc is using this pll don't turn
2490                          * off the pll
2491                          */
2492                         goto done;
2493                 }
2494         }
2495
2496         switch (amdgpu_crtc->pll_id) {
2497         case ATOM_PPLL1:
2498         case ATOM_PPLL2:
2499                 /* disable the ppll */
2500                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2501                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2502                 break;
2503         case ATOM_PPLL0:
2504                 /* disable the ppll */
2505                 if ((adev->asic_type == CHIP_KAVERI) ||
2506                     (adev->asic_type == CHIP_BONAIRE) ||
2507                     (adev->asic_type == CHIP_HAWAII))
2508                         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2509                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2510                 break;
2511         default:
2512                 break;
2513         }
2514 done:
2515         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2516         amdgpu_crtc->adjusted_clock = 0;
2517         amdgpu_crtc->encoder = NULL;
2518         amdgpu_crtc->connector = NULL;
2519 }
2520
2521 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2522                                   struct drm_display_mode *mode,
2523                                   struct drm_display_mode *adjusted_mode,
2524                                   int x, int y, struct drm_framebuffer *old_fb)
2525 {
2526         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2527
2528         if (!amdgpu_crtc->adjusted_clock)
2529                 return -EINVAL;
2530
2531         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2532         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2533         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2534         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2535         amdgpu_atombios_crtc_scaler_setup(crtc);
2536         dce_v8_0_cursor_reset(crtc);
2537         /* update the hw version fpr dpm */
2538         amdgpu_crtc->hw_mode = *adjusted_mode;
2539
2540         return 0;
2541 }
2542
2543 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2544                                      const struct drm_display_mode *mode,
2545                                      struct drm_display_mode *adjusted_mode)
2546 {
2547         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2548         struct drm_device *dev = crtc->dev;
2549         struct drm_encoder *encoder;
2550
2551         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2552         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2553                 if (encoder->crtc == crtc) {
2554                         amdgpu_crtc->encoder = encoder;
2555                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2556                         break;
2557                 }
2558         }
2559         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2560                 amdgpu_crtc->encoder = NULL;
2561                 amdgpu_crtc->connector = NULL;
2562                 return false;
2563         }
2564         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2565                 return false;
2566         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2567                 return false;
2568         /* pick pll */
2569         amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2570         /* if we can't get a PPLL for a non-DP encoder, fail */
2571         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2572             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2573                 return false;
2574
2575         return true;
2576 }
2577
2578 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2579                                   struct drm_framebuffer *old_fb)
2580 {
2581         return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2582 }
2583
2584 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2585                                          struct drm_framebuffer *fb,
2586                                          int x, int y, enum mode_set_atomic state)
2587 {
2588         return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2589 }
2590
2591 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2592         .dpms = dce_v8_0_crtc_dpms,
2593         .mode_fixup = dce_v8_0_crtc_mode_fixup,
2594         .mode_set = dce_v8_0_crtc_mode_set,
2595         .mode_set_base = dce_v8_0_crtc_set_base,
2596         .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2597         .prepare = dce_v8_0_crtc_prepare,
2598         .commit = dce_v8_0_crtc_commit,
2599         .disable = dce_v8_0_crtc_disable,
2600         .get_scanout_position = amdgpu_crtc_get_scanout_position,
2601 };
2602
2603 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2604 {
2605         struct amdgpu_crtc *amdgpu_crtc;
2606
2607         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2608                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2609         if (amdgpu_crtc == NULL)
2610                 return -ENOMEM;
2611
2612         drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2613
2614         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2615         amdgpu_crtc->crtc_id = index;
2616         adev->mode_info.crtcs[index] = amdgpu_crtc;
2617
2618         amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2619         amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2620         adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2621         adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2622
2623         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2624
2625         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2626         amdgpu_crtc->adjusted_clock = 0;
2627         amdgpu_crtc->encoder = NULL;
2628         amdgpu_crtc->connector = NULL;
2629         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2630
2631         return 0;
2632 }
2633
2634 static int dce_v8_0_early_init(void *handle)
2635 {
2636         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2637
2638         adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2639         adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2640
2641         dce_v8_0_set_display_funcs(adev);
2642
2643         adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2644
2645         switch (adev->asic_type) {
2646         case CHIP_BONAIRE:
2647         case CHIP_HAWAII:
2648                 adev->mode_info.num_hpd = 6;
2649                 adev->mode_info.num_dig = 6;
2650                 break;
2651         case CHIP_KAVERI:
2652                 adev->mode_info.num_hpd = 6;
2653                 adev->mode_info.num_dig = 7;
2654                 break;
2655         case CHIP_KABINI:
2656         case CHIP_MULLINS:
2657                 adev->mode_info.num_hpd = 6;
2658                 adev->mode_info.num_dig = 6; /* ? */
2659                 break;
2660         default:
2661                 /* FIXME: not supported yet */
2662                 return -EINVAL;
2663         }
2664
2665         dce_v8_0_set_irq_funcs(adev);
2666
2667         return 0;
2668 }
2669
2670 static int dce_v8_0_sw_init(void *handle)
2671 {
2672         int r, i;
2673         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2674
2675         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2676                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2677                 if (r)
2678                         return r;
2679         }
2680
2681         for (i = 8; i < 20; i += 2) {
2682                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2683                 if (r)
2684                         return r;
2685         }
2686
2687         /* HPD hotplug */
2688         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2689         if (r)
2690                 return r;
2691
2692         adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2693
2694         adev_to_drm(adev)->mode_config.async_page_flip = true;
2695
2696         adev_to_drm(adev)->mode_config.max_width = 16384;
2697         adev_to_drm(adev)->mode_config.max_height = 16384;
2698
2699         adev_to_drm(adev)->mode_config.preferred_depth = 24;
2700         adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2701
2702         adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
2703
2704         r = amdgpu_display_modeset_create_props(adev);
2705         if (r)
2706                 return r;
2707
2708         adev_to_drm(adev)->mode_config.max_width = 16384;
2709         adev_to_drm(adev)->mode_config.max_height = 16384;
2710
2711         /* allocate crtcs */
2712         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2713                 r = dce_v8_0_crtc_init(adev, i);
2714                 if (r)
2715                         return r;
2716         }
2717
2718         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2719                 amdgpu_display_print_display_setup(adev_to_drm(adev));
2720         else
2721                 return -EINVAL;
2722
2723         /* setup afmt */
2724         r = dce_v8_0_afmt_init(adev);
2725         if (r)
2726                 return r;
2727
2728         r = dce_v8_0_audio_init(adev);
2729         if (r)
2730                 return r;
2731
2732         drm_kms_helper_poll_init(adev_to_drm(adev));
2733
2734         adev->mode_info.mode_config_initialized = true;
2735         return 0;
2736 }
2737
2738 static int dce_v8_0_sw_fini(void *handle)
2739 {
2740         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2741
2742         kfree(adev->mode_info.bios_hardcoded_edid);
2743
2744         drm_kms_helper_poll_fini(adev_to_drm(adev));
2745
2746         dce_v8_0_audio_fini(adev);
2747
2748         dce_v8_0_afmt_fini(adev);
2749
2750         drm_mode_config_cleanup(adev_to_drm(adev));
2751         adev->mode_info.mode_config_initialized = false;
2752
2753         return 0;
2754 }
2755
2756 static int dce_v8_0_hw_init(void *handle)
2757 {
2758         int i;
2759         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2760
2761         /* disable vga render */
2762         dce_v8_0_set_vga_render_state(adev, false);
2763         /* init dig PHYs, disp eng pll */
2764         amdgpu_atombios_encoder_init_dig(adev);
2765         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2766
2767         /* initialize hpd */
2768         dce_v8_0_hpd_init(adev);
2769
2770         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2771                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2772         }
2773
2774         dce_v8_0_pageflip_interrupt_init(adev);
2775
2776         return 0;
2777 }
2778
2779 static int dce_v8_0_hw_fini(void *handle)
2780 {
2781         int i;
2782         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2783
2784         dce_v8_0_hpd_fini(adev);
2785
2786         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2787                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2788         }
2789
2790         dce_v8_0_pageflip_interrupt_fini(adev);
2791
2792         return 0;
2793 }
2794
2795 static int dce_v8_0_suspend(void *handle)
2796 {
2797         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2798         int r;
2799
2800         r = amdgpu_display_suspend_helper(adev);
2801         if (r)
2802                 return r;
2803
2804         adev->mode_info.bl_level =
2805                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2806
2807         return dce_v8_0_hw_fini(handle);
2808 }
2809
2810 static int dce_v8_0_resume(void *handle)
2811 {
2812         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2813         int ret;
2814
2815         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2816                                                            adev->mode_info.bl_level);
2817
2818         ret = dce_v8_0_hw_init(handle);
2819
2820         /* turn on the BL */
2821         if (adev->mode_info.bl_encoder) {
2822                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2823                                                                   adev->mode_info.bl_encoder);
2824                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2825                                                     bl_level);
2826         }
2827         if (ret)
2828                 return ret;
2829
2830         return amdgpu_display_resume_helper(adev);
2831 }
2832
2833 static bool dce_v8_0_is_idle(void *handle)
2834 {
2835         return true;
2836 }
2837
2838 static int dce_v8_0_wait_for_idle(void *handle)
2839 {
2840         return 0;
2841 }
2842
2843 static int dce_v8_0_soft_reset(void *handle)
2844 {
2845         u32 srbm_soft_reset = 0, tmp;
2846         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2847
2848         if (dce_v8_0_is_display_hung(adev))
2849                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2850
2851         if (srbm_soft_reset) {
2852                 tmp = RREG32(mmSRBM_SOFT_RESET);
2853                 tmp |= srbm_soft_reset;
2854                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2855                 WREG32(mmSRBM_SOFT_RESET, tmp);
2856                 tmp = RREG32(mmSRBM_SOFT_RESET);
2857
2858                 udelay(50);
2859
2860                 tmp &= ~srbm_soft_reset;
2861                 WREG32(mmSRBM_SOFT_RESET, tmp);
2862                 tmp = RREG32(mmSRBM_SOFT_RESET);
2863
2864                 /* Wait a little for things to settle down */
2865                 udelay(50);
2866         }
2867         return 0;
2868 }
2869
2870 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2871                                                      int crtc,
2872                                                      enum amdgpu_interrupt_state state)
2873 {
2874         u32 reg_block, lb_interrupt_mask;
2875
2876         if (crtc >= adev->mode_info.num_crtc) {
2877                 DRM_DEBUG("invalid crtc %d\n", crtc);
2878                 return;
2879         }
2880
2881         switch (crtc) {
2882         case 0:
2883                 reg_block = CRTC0_REGISTER_OFFSET;
2884                 break;
2885         case 1:
2886                 reg_block = CRTC1_REGISTER_OFFSET;
2887                 break;
2888         case 2:
2889                 reg_block = CRTC2_REGISTER_OFFSET;
2890                 break;
2891         case 3:
2892                 reg_block = CRTC3_REGISTER_OFFSET;
2893                 break;
2894         case 4:
2895                 reg_block = CRTC4_REGISTER_OFFSET;
2896                 break;
2897         case 5:
2898                 reg_block = CRTC5_REGISTER_OFFSET;
2899                 break;
2900         default:
2901                 DRM_DEBUG("invalid crtc %d\n", crtc);
2902                 return;
2903         }
2904
2905         switch (state) {
2906         case AMDGPU_IRQ_STATE_DISABLE:
2907                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2908                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2909                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2910                 break;
2911         case AMDGPU_IRQ_STATE_ENABLE:
2912                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2913                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2914                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2915                 break;
2916         default:
2917                 break;
2918         }
2919 }
2920
2921 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2922                                                     int crtc,
2923                                                     enum amdgpu_interrupt_state state)
2924 {
2925         u32 reg_block, lb_interrupt_mask;
2926
2927         if (crtc >= adev->mode_info.num_crtc) {
2928                 DRM_DEBUG("invalid crtc %d\n", crtc);
2929                 return;
2930         }
2931
2932         switch (crtc) {
2933         case 0:
2934                 reg_block = CRTC0_REGISTER_OFFSET;
2935                 break;
2936         case 1:
2937                 reg_block = CRTC1_REGISTER_OFFSET;
2938                 break;
2939         case 2:
2940                 reg_block = CRTC2_REGISTER_OFFSET;
2941                 break;
2942         case 3:
2943                 reg_block = CRTC3_REGISTER_OFFSET;
2944                 break;
2945         case 4:
2946                 reg_block = CRTC4_REGISTER_OFFSET;
2947                 break;
2948         case 5:
2949                 reg_block = CRTC5_REGISTER_OFFSET;
2950                 break;
2951         default:
2952                 DRM_DEBUG("invalid crtc %d\n", crtc);
2953                 return;
2954         }
2955
2956         switch (state) {
2957         case AMDGPU_IRQ_STATE_DISABLE:
2958                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2959                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2960                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2961                 break;
2962         case AMDGPU_IRQ_STATE_ENABLE:
2963                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2964                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2965                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2966                 break;
2967         default:
2968                 break;
2969         }
2970 }
2971
2972 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2973                                             struct amdgpu_irq_src *src,
2974                                             unsigned type,
2975                                             enum amdgpu_interrupt_state state)
2976 {
2977         u32 dc_hpd_int_cntl;
2978
2979         if (type >= adev->mode_info.num_hpd) {
2980                 DRM_DEBUG("invalid hdp %d\n", type);
2981                 return 0;
2982         }
2983
2984         switch (state) {
2985         case AMDGPU_IRQ_STATE_DISABLE:
2986                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2987                 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2988                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2989                 break;
2990         case AMDGPU_IRQ_STATE_ENABLE:
2991                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2992                 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2993                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2994                 break;
2995         default:
2996                 break;
2997         }
2998
2999         return 0;
3000 }
3001
3002 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3003                                              struct amdgpu_irq_src *src,
3004                                              unsigned type,
3005                                              enum amdgpu_interrupt_state state)
3006 {
3007         switch (type) {
3008         case AMDGPU_CRTC_IRQ_VBLANK1:
3009                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3010                 break;
3011         case AMDGPU_CRTC_IRQ_VBLANK2:
3012                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3013                 break;
3014         case AMDGPU_CRTC_IRQ_VBLANK3:
3015                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3016                 break;
3017         case AMDGPU_CRTC_IRQ_VBLANK4:
3018                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3019                 break;
3020         case AMDGPU_CRTC_IRQ_VBLANK5:
3021                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3022                 break;
3023         case AMDGPU_CRTC_IRQ_VBLANK6:
3024                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3025                 break;
3026         case AMDGPU_CRTC_IRQ_VLINE1:
3027                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3028                 break;
3029         case AMDGPU_CRTC_IRQ_VLINE2:
3030                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3031                 break;
3032         case AMDGPU_CRTC_IRQ_VLINE3:
3033                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3034                 break;
3035         case AMDGPU_CRTC_IRQ_VLINE4:
3036                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3037                 break;
3038         case AMDGPU_CRTC_IRQ_VLINE5:
3039                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3040                 break;
3041         case AMDGPU_CRTC_IRQ_VLINE6:
3042                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3043                 break;
3044         default:
3045                 break;
3046         }
3047         return 0;
3048 }
3049
3050 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3051                              struct amdgpu_irq_src *source,
3052                              struct amdgpu_iv_entry *entry)
3053 {
3054         unsigned crtc = entry->src_id - 1;
3055         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3056         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3057                                                                     crtc);
3058
3059         switch (entry->src_data[0]) {
3060         case 0: /* vblank */
3061                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3062                         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3063                 else
3064                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3065
3066                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3067                         drm_handle_vblank(adev_to_drm(adev), crtc);
3068                 }
3069                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3070                 break;
3071         case 1: /* vline */
3072                 if (disp_int & interrupt_status_offsets[crtc].vline)
3073                         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3074                 else
3075                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3076
3077                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3078                 break;
3079         default:
3080                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3081                 break;
3082         }
3083
3084         return 0;
3085 }
3086
3087 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3088                                                  struct amdgpu_irq_src *src,
3089                                                  unsigned type,
3090                                                  enum amdgpu_interrupt_state state)
3091 {
3092         u32 reg;
3093
3094         if (type >= adev->mode_info.num_crtc) {
3095                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3096                 return -EINVAL;
3097         }
3098
3099         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3100         if (state == AMDGPU_IRQ_STATE_DISABLE)
3101                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3102                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3103         else
3104                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3105                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3106
3107         return 0;
3108 }
3109
3110 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3111                                 struct amdgpu_irq_src *source,
3112                                 struct amdgpu_iv_entry *entry)
3113 {
3114         unsigned long flags;
3115         unsigned crtc_id;
3116         struct amdgpu_crtc *amdgpu_crtc;
3117         struct amdgpu_flip_work *works;
3118
3119         crtc_id = (entry->src_id - 8) >> 1;
3120         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3121
3122         if (crtc_id >= adev->mode_info.num_crtc) {
3123                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3124                 return -EINVAL;
3125         }
3126
3127         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3128             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3129                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3130                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3131
3132         /* IRQ could occur when in initial stage */
3133         if (amdgpu_crtc == NULL)
3134                 return 0;
3135
3136         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3137         works = amdgpu_crtc->pflip_works;
3138         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3139                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3140                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3141                                                 amdgpu_crtc->pflip_status,
3142                                                 AMDGPU_FLIP_SUBMITTED);
3143                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3144                 return 0;
3145         }
3146
3147         /* page flip completed. clean up */
3148         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3149         amdgpu_crtc->pflip_works = NULL;
3150
3151         /* wakeup usersapce */
3152         if (works->event)
3153                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3154
3155         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3156
3157         drm_crtc_vblank_put(&amdgpu_crtc->base);
3158         schedule_work(&works->unpin_work);
3159
3160         return 0;
3161 }
3162
3163 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3164                             struct amdgpu_irq_src *source,
3165                             struct amdgpu_iv_entry *entry)
3166 {
3167         uint32_t disp_int, mask, tmp;
3168         unsigned hpd;
3169
3170         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3171                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3172                 return 0;
3173         }
3174
3175         hpd = entry->src_data[0];
3176         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3177         mask = interrupt_status_offsets[hpd].hpd;
3178
3179         if (disp_int & mask) {
3180                 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3181                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3182                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3183                 schedule_work(&adev->hotplug_work);
3184                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3185         }
3186
3187         return 0;
3188
3189 }
3190
3191 static int dce_v8_0_set_clockgating_state(void *handle,
3192                                           enum amd_clockgating_state state)
3193 {
3194         return 0;
3195 }
3196
3197 static int dce_v8_0_set_powergating_state(void *handle,
3198                                           enum amd_powergating_state state)
3199 {
3200         return 0;
3201 }
3202
3203 static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3204         .name = "dce_v8_0",
3205         .early_init = dce_v8_0_early_init,
3206         .late_init = NULL,
3207         .sw_init = dce_v8_0_sw_init,
3208         .sw_fini = dce_v8_0_sw_fini,
3209         .hw_init = dce_v8_0_hw_init,
3210         .hw_fini = dce_v8_0_hw_fini,
3211         .suspend = dce_v8_0_suspend,
3212         .resume = dce_v8_0_resume,
3213         .is_idle = dce_v8_0_is_idle,
3214         .wait_for_idle = dce_v8_0_wait_for_idle,
3215         .soft_reset = dce_v8_0_soft_reset,
3216         .set_clockgating_state = dce_v8_0_set_clockgating_state,
3217         .set_powergating_state = dce_v8_0_set_powergating_state,
3218 };
3219
3220 static void
3221 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3222                           struct drm_display_mode *mode,
3223                           struct drm_display_mode *adjusted_mode)
3224 {
3225         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3226
3227         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3228
3229         /* need to call this here rather than in prepare() since we need some crtc info */
3230         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3231
3232         /* set scaler clears this on some chips */
3233         dce_v8_0_set_interleave(encoder->crtc, mode);
3234
3235         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3236                 dce_v8_0_afmt_enable(encoder, true);
3237                 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3238         }
3239 }
3240
3241 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3242 {
3243         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3244         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3245         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3246
3247         if ((amdgpu_encoder->active_device &
3248              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3249             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3250              ENCODER_OBJECT_ID_NONE)) {
3251                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3252                 if (dig) {
3253                         dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3254                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3255                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3256                 }
3257         }
3258
3259         amdgpu_atombios_scratch_regs_lock(adev, true);
3260
3261         if (connector) {
3262                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3263
3264                 /* select the clock/data port if it uses a router */
3265                 if (amdgpu_connector->router.cd_valid)
3266                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3267
3268                 /* turn eDP panel on for mode set */
3269                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3270                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3271                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3272         }
3273
3274         /* this is needed for the pll/ss setup to work correctly in some cases */
3275         amdgpu_atombios_encoder_set_crtc_source(encoder);
3276         /* set up the FMT blocks */
3277         dce_v8_0_program_fmt(encoder);
3278 }
3279
3280 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3281 {
3282         struct drm_device *dev = encoder->dev;
3283         struct amdgpu_device *adev = drm_to_adev(dev);
3284
3285         /* need to call this here as we need the crtc set up */
3286         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3287         amdgpu_atombios_scratch_regs_lock(adev, false);
3288 }
3289
3290 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3291 {
3292         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3293         struct amdgpu_encoder_atom_dig *dig;
3294
3295         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3296
3297         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3298                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3299                         dce_v8_0_afmt_enable(encoder, false);
3300                 dig = amdgpu_encoder->enc_priv;
3301                 dig->dig_encoder = -1;
3302         }
3303         amdgpu_encoder->active_device = 0;
3304 }
3305
3306 /* these are handled by the primary encoders */
3307 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3308 {
3309
3310 }
3311
3312 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3313 {
3314
3315 }
3316
3317 static void
3318 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3319                       struct drm_display_mode *mode,
3320                       struct drm_display_mode *adjusted_mode)
3321 {
3322
3323 }
3324
3325 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3326 {
3327
3328 }
3329
3330 static void
3331 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3332 {
3333
3334 }
3335
3336 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3337         .dpms = dce_v8_0_ext_dpms,
3338         .prepare = dce_v8_0_ext_prepare,
3339         .mode_set = dce_v8_0_ext_mode_set,
3340         .commit = dce_v8_0_ext_commit,
3341         .disable = dce_v8_0_ext_disable,
3342         /* no detect for TMDS/LVDS yet */
3343 };
3344
3345 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3346         .dpms = amdgpu_atombios_encoder_dpms,
3347         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3348         .prepare = dce_v8_0_encoder_prepare,
3349         .mode_set = dce_v8_0_encoder_mode_set,
3350         .commit = dce_v8_0_encoder_commit,
3351         .disable = dce_v8_0_encoder_disable,
3352         .detect = amdgpu_atombios_encoder_dig_detect,
3353 };
3354
3355 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3356         .dpms = amdgpu_atombios_encoder_dpms,
3357         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3358         .prepare = dce_v8_0_encoder_prepare,
3359         .mode_set = dce_v8_0_encoder_mode_set,
3360         .commit = dce_v8_0_encoder_commit,
3361         .detect = amdgpu_atombios_encoder_dac_detect,
3362 };
3363
3364 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3365 {
3366         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3367         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3368                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3369         kfree(amdgpu_encoder->enc_priv);
3370         drm_encoder_cleanup(encoder);
3371         kfree(amdgpu_encoder);
3372 }
3373
3374 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3375         .destroy = dce_v8_0_encoder_destroy,
3376 };
3377
3378 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3379                                  uint32_t encoder_enum,
3380                                  uint32_t supported_device,
3381                                  u16 caps)
3382 {
3383         struct drm_device *dev = adev_to_drm(adev);
3384         struct drm_encoder *encoder;
3385         struct amdgpu_encoder *amdgpu_encoder;
3386
3387         /* see if we already added it */
3388         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3389                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3390                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3391                         amdgpu_encoder->devices |= supported_device;
3392                         return;
3393                 }
3394
3395         }
3396
3397         /* add a new one */
3398         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3399         if (!amdgpu_encoder)
3400                 return;
3401
3402         encoder = &amdgpu_encoder->base;
3403         switch (adev->mode_info.num_crtc) {
3404         case 1:
3405                 encoder->possible_crtcs = 0x1;
3406                 break;
3407         case 2:
3408         default:
3409                 encoder->possible_crtcs = 0x3;
3410                 break;
3411         case 4:
3412                 encoder->possible_crtcs = 0xf;
3413                 break;
3414         case 6:
3415                 encoder->possible_crtcs = 0x3f;
3416                 break;
3417         }
3418
3419         amdgpu_encoder->enc_priv = NULL;
3420
3421         amdgpu_encoder->encoder_enum = encoder_enum;
3422         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3423         amdgpu_encoder->devices = supported_device;
3424         amdgpu_encoder->rmx_type = RMX_OFF;
3425         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3426         amdgpu_encoder->is_ext_encoder = false;
3427         amdgpu_encoder->caps = caps;
3428
3429         switch (amdgpu_encoder->encoder_id) {
3430         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3431         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3432                 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3433                                  DRM_MODE_ENCODER_DAC, NULL);
3434                 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3435                 break;
3436         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3437         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3438         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3439         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3440         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3441                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3442                         amdgpu_encoder->rmx_type = RMX_FULL;
3443                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3444                                          DRM_MODE_ENCODER_LVDS, NULL);
3445                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3446                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3447                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3448                                          DRM_MODE_ENCODER_DAC, NULL);
3449                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3450                 } else {
3451                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3452                                          DRM_MODE_ENCODER_TMDS, NULL);
3453                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3454                 }
3455                 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3456                 break;
3457         case ENCODER_OBJECT_ID_SI170B:
3458         case ENCODER_OBJECT_ID_CH7303:
3459         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3460         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3461         case ENCODER_OBJECT_ID_TITFP513:
3462         case ENCODER_OBJECT_ID_VT1623:
3463         case ENCODER_OBJECT_ID_HDMI_SI1930:
3464         case ENCODER_OBJECT_ID_TRAVIS:
3465         case ENCODER_OBJECT_ID_NUTMEG:
3466                 /* these are handled by the primary encoders */
3467                 amdgpu_encoder->is_ext_encoder = true;
3468                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3469                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3470                                          DRM_MODE_ENCODER_LVDS, NULL);
3471                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3472                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3473                                          DRM_MODE_ENCODER_DAC, NULL);
3474                 else
3475                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3476                                          DRM_MODE_ENCODER_TMDS, NULL);
3477                 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3478                 break;
3479         }
3480 }
3481
3482 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3483         .bandwidth_update = &dce_v8_0_bandwidth_update,
3484         .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3485         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3486         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3487         .hpd_sense = &dce_v8_0_hpd_sense,
3488         .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3489         .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3490         .page_flip = &dce_v8_0_page_flip,
3491         .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3492         .add_encoder = &dce_v8_0_encoder_add,
3493         .add_connector = &amdgpu_connector_add,
3494 };
3495
3496 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3497 {
3498         adev->mode_info.funcs = &dce_v8_0_display_funcs;
3499 }
3500
3501 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3502         .set = dce_v8_0_set_crtc_interrupt_state,
3503         .process = dce_v8_0_crtc_irq,
3504 };
3505
3506 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3507         .set = dce_v8_0_set_pageflip_interrupt_state,
3508         .process = dce_v8_0_pageflip_irq,
3509 };
3510
3511 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3512         .set = dce_v8_0_set_hpd_interrupt_state,
3513         .process = dce_v8_0_hpd_irq,
3514 };
3515
3516 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3517 {
3518         if (adev->mode_info.num_crtc > 0)
3519                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3520         else
3521                 adev->crtc_irq.num_types = 0;
3522         adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3523
3524         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3525         adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3526
3527         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3528         adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3529 }
3530
3531 const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3532 {
3533         .type = AMD_IP_BLOCK_TYPE_DCE,
3534         .major = 8,
3535         .minor = 0,
3536         .rev = 0,
3537         .funcs = &dce_v8_0_ip_funcs,
3538 };
3539
3540 const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3541 {
3542         .type = AMD_IP_BLOCK_TYPE_DCE,
3543         .major = 8,
3544         .minor = 1,
3545         .rev = 0,
3546         .funcs = &dce_v8_0_ip_funcs,
3547 };
3548
3549 const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3550 {
3551         .type = AMD_IP_BLOCK_TYPE_DCE,
3552         .major = 8,
3553         .minor = 2,
3554         .rev = 0,
3555         .funcs = &dce_v8_0_ip_funcs,
3556 };
3557
3558 const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3559 {
3560         .type = AMD_IP_BLOCK_TYPE_DCE,
3561         .major = 8,
3562         .minor = 3,
3563         .rev = 0,
3564         .funcs = &dce_v8_0_ip_funcs,
3565 };
3566
3567 const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3568 {
3569         .type = AMD_IP_BLOCK_TYPE_DCE,
3570         .major = 8,
3571         .minor = 5,
3572         .rev = 0,
3573         .funcs = &dce_v8_0_ip_funcs,
3574 };