drivers/gpu/drm/amd/amdgpu/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27
  28 #include <drm/amdgpu_drm.h>
  29 #include "amdgpu.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_atombios.h"
  37 #include <drm/drm_dp_helper.h>
  38
  39 /* move these to drm_dp_helper.c/h */
  40 #define DP_LINK_CONFIGURATION_SIZE 9
  41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  42
  43 static char *voltage_names[] = {
  44         "0.4V", "0.6V", "0.8V", "1.2V"
  45 };
  46 static char *pre_emph_names[] = {
  47         "0dB", "3.5dB", "6dB", "9.5dB"
  48 };
  49
  50 /***** amdgpu AUX functions *****/
  51
  52 union aux_channel_transaction {
  53         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  54         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  55 };
  56
  57 static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
  58                                       u8 *send, int send_bytes,
  59                                       u8 *recv, int recv_size,
  60                                       u8 delay, u8 *ack)
  61 {
  62         struct drm_device *dev = chan->dev;
  63         struct amdgpu_device *adev = drm_to_adev(dev);
  64         union aux_channel_transaction args;
  65         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  66         unsigned char *base;
  67         int recv_bytes;
  68         int r = 0;
  69
  70         memset(&args, 0, sizeof(args));
  71
  72         mutex_lock(&chan->mutex);
  73
  74         base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
  75
  76         amdgpu_atombios_copy_swap(base, send, send_bytes, true);
  77
  78         args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
  79         args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
  80         args.v2.ucDataOutLen = 0;
  81         args.v2.ucChannelID = chan->rec.i2c_id;
  82         args.v2.ucDelay = delay / 10;
  83         args.v2.ucHPD_ID = chan->rec.hpd;
  84
  85         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
  86
  87         *ack = args.v2.ucReplyStatus;
  88
  89         /* timeout */
  90         if (args.v2.ucReplyStatus == 1) {
  91                 r = -ETIMEDOUT;
  92                 goto done;
  93         }
  94
  95         /* flags not zero */
  96         if (args.v2.ucReplyStatus == 2) {
  97                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  98                 r = -EIO;
  99                 goto done;
 100         }
 101
 102         /* error */
 103         if (args.v2.ucReplyStatus == 3) {
 104                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 105                 r = -EIO;
 106                 goto done;
 107         }
 108
 109         recv_bytes = args.v1.ucDataOutLen;
 110         if (recv_bytes > recv_size)
 111                 recv_bytes = recv_size;
 112
 113         if (recv && recv_size)
 114                 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
 115
 116         r = recv_bytes;
 117 done:
 118         mutex_unlock(&chan->mutex);
 119
 120         return r;
 121 }
 122
 123 #define BARE_ADDRESS_SIZE 3
 124 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 125
 126 static ssize_t
 127 amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 128 {
 129         struct amdgpu_i2c_chan *chan =
 130                 container_of(aux, struct amdgpu_i2c_chan, aux);
 131         int ret;
 132         u8 tx_buf[20];
 133         size_t tx_size;
 134         u8 ack, delay = 0;
 135
 136         if (WARN_ON(msg->size > 16))
 137                 return -E2BIG;
 138
 139         tx_buf[0] = msg->address & 0xff;
 140         tx_buf[1] = msg->address >> 8;
 141         tx_buf[2] = (msg->request << 4) |
 142                 ((msg->address >> 16) & 0xf);
 143         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 144
 145         switch (msg->request & ~DP_AUX_I2C_MOT) {
 146         case DP_AUX_NATIVE_WRITE:
 147         case DP_AUX_I2C_WRITE:
 148                 /* tx_size needs to be 4 even for bare address packets since the atom
 149                  * table needs the info in tx_buf[3].
 150                  */
 151                 tx_size = HEADER_SIZE + msg->size;
 152                 if (msg->size == 0)
 153                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 154                 else
 155                         tx_buf[3] |= tx_size << 4;
 156                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 157                 ret = amdgpu_atombios_dp_process_aux_ch(chan,
 158                                                  tx_buf, tx_size, NULL, 0, delay, &ack);
 159                 if (ret >= 0)
 160                         /* Return payload size. */
 161                         ret = msg->size;
 162                 break;
 163         case DP_AUX_NATIVE_READ:
 164         case DP_AUX_I2C_READ:
 165                 /* tx_size needs to be 4 even for bare address packets since the atom
 166                  * table needs the info in tx_buf[3].
 167                  */
 168                 tx_size = HEADER_SIZE;
 169                 if (msg->size == 0)
 170                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 171                 else
 172                         tx_buf[3] |= tx_size << 4;
 173                 ret = amdgpu_atombios_dp_process_aux_ch(chan,
 174                                                  tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 175                 break;
 176         default:
 177                 ret = -EINVAL;
 178                 break;
 179         }
 180
 181         if (ret >= 0)
 182                 msg->reply = ack >> 4;
 183
 184         return ret;
 185 }
 186
 187 void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
 188 {
 189         amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
 190         amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
 191         drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux);
 192         amdgpu_connector->ddc_bus->has_aux = true;
 193 }
 194
 195 /***** general DP utility functions *****/
 196
 197 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 198 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 199
 200 static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
 201                                                 int lane_count,
 202                                                 u8 train_set[4])
 203 {
 204         u8 v = 0;
 205         u8 p = 0;
 206         int lane;
 207
 208         for (lane = 0; lane < lane_count; lane++) {
 209                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 210                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 211
 212                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 213                           lane,
 214                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 215                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 216
 217                 if (this_v > v)
 218                         v = this_v;
 219                 if (this_p > p)
 220                         p = this_p;
 221         }
 222
 223         if (v >= DP_VOLTAGE_MAX)
 224                 v |= DP_TRAIN_MAX_SWING_REACHED;
 225
 226         if (p >= DP_PRE_EMPHASIS_MAX)
 227                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 228
 229         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 230                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 231                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 232
 233         for (lane = 0; lane < 4; lane++)
 234                 train_set[lane] = v | p;
 235 }
 236
 237 /* convert bits per color to bits per pixel */
 238 /* get bpc from the EDID */
 239 static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
 240 {
 241         if (bpc == 0)
 242                 return 24;
 243         else
 244                 return bpc * 3;
 245 }
 246
 247 /***** amdgpu specific DP functions *****/
 248
 249 static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector,
 250                                                  const u8 dpcd[DP_DPCD_SIZE],
 251                                                  unsigned pix_clock,
 252                                                  unsigned *dp_lanes, unsigned *dp_rate)
 253 {
 254         unsigned bpp =
 255                 amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
 256         static const unsigned link_rates[3] = { 162000, 270000, 540000 };
 257         unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
 258         unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
 259         unsigned lane_num, i, max_pix_clock;
 260
 261         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 262             ENCODER_OBJECT_ID_NUTMEG) {
 263                 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 264                         max_pix_clock = (lane_num * 270000 * 8) / bpp;
 265                         if (max_pix_clock >= pix_clock) {
 266                                 *dp_lanes = lane_num;
 267                                 *dp_rate = 270000;
 268                                 return 0;
 269                         }
 270                 }
 271         } else {
 272                 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
 273                         for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 274                                 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
 275                                 if (max_pix_clock >= pix_clock) {
 276                                         *dp_lanes = lane_num;
 277                                         *dp_rate = link_rates[i];
 278                                         return 0;
 279                                 }
 280                         }
 281                 }
 282         }
 283
 284         return -EINVAL;
 285 }
 286
 287 static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
 288                                       int action, int dp_clock,
 289                                       u8 ucconfig, u8 lane_num)
 290 {
 291         DP_ENCODER_SERVICE_PARAMETERS args;
 292         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 293
 294         memset(&args, 0, sizeof(args));
 295         args.ucLinkClock = dp_clock / 10;
 296         args.ucConfig = ucconfig;
 297         args.ucAction = action;
 298         args.ucLaneNum = lane_num;
 299         args.ucStatus = 0;
 300
 301         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 302         return args.ucStatus;
 303 }
 304
 305 u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
 306 {
 307         struct drm_device *dev = amdgpu_connector->base.dev;
 308         struct amdgpu_device *adev = drm_to_adev(dev);
 309
 310         return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 311                                            amdgpu_connector->ddc_bus->rec.i2c_id, 0);
 312 }
 313
 314 static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
 315 {
 316         struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
 317         u8 buf[3];
 318
 319         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 320                 return;
 321
 322         if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 323                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 324                               buf[0], buf[1], buf[2]);
 325
 326         if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 327                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 328                               buf[0], buf[1], buf[2]);
 329 }
 330
 331 static void amdgpu_atombios_dp_ds_ports(struct amdgpu_connector *amdgpu_connector)
 332 {
 333         struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
 334         int ret;
 335
 336         if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) {
 337                 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux,
 338                                        DP_DOWNSTREAM_PORT_0,
 339                                        dig_connector->downstream_ports,
 340                                        DP_MAX_DOWNSTREAM_PORTS);
 341                 if (ret)
 342                         memset(dig_connector->downstream_ports, 0,
 343                                DP_MAX_DOWNSTREAM_PORTS);
 344         }
 345 }
 346
 347 int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
 348 {
 349         struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
 350         u8 msg[DP_DPCD_SIZE];
 351         int ret;
 352
 353         ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
 354                                msg, DP_DPCD_SIZE);
 355         if (ret == DP_DPCD_SIZE) {
 356                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 357
 358                 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
 359                               dig_connector->dpcd);
 360
 361                 amdgpu_atombios_dp_probe_oui(amdgpu_connector);
 362                 amdgpu_atombios_dp_ds_ports(amdgpu_connector);
 363                 return 0;
 364         }
 365
 366         dig_connector->dpcd[0] = 0;
 367         return -EINVAL;
 368 }
 369
 370 int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
 371                                struct drm_connector *connector)
 372 {
 373         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 374         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 375         u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
 376         u8 tmp;
 377
 378         if (!amdgpu_connector->con_priv)
 379                 return panel_mode;
 380
 381         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 382                 /* DP bridge chips */
 383                 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
 384                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 385                         if (tmp & 1)
 386                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 387                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 388                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 389                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 390                         else
 391                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 392                 }
 393         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 394                 /* eDP */
 395                 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
 396                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 397                         if (tmp & 1)
 398                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 399                 }
 400         }
 401
 402         return panel_mode;
 403 }
 404
 405 void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
 406                                  const struct drm_display_mode *mode)
 407 {
 408         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 409         struct amdgpu_connector_atom_dig *dig_connector;
 410         int ret;
 411
 412         if (!amdgpu_connector->con_priv)
 413                 return;
 414         dig_connector = amdgpu_connector->con_priv;
 415
 416         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 417             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 418                 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
 419                                                             mode->clock,
 420                                                             &dig_connector->dp_lane_count,
 421                                                             &dig_connector->dp_clock);
 422                 if (ret) {
 423                         dig_connector->dp_clock = 0;
 424                         dig_connector->dp_lane_count = 0;
 425                 }
 426         }
 427 }
 428
 429 int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
 430                                   struct drm_display_mode *mode)
 431 {
 432         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 433         struct amdgpu_connector_atom_dig *dig_connector;
 434         unsigned dp_lanes, dp_clock;
 435         int ret;
 436
 437         if (!amdgpu_connector->con_priv)
 438                 return MODE_CLOCK_HIGH;
 439         dig_connector = amdgpu_connector->con_priv;
 440
 441         ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
 442                                                     mode->clock, &dp_lanes, &dp_clock);
 443         if (ret)
 444                 return MODE_CLOCK_HIGH;
 445
 446         if ((dp_clock == 540000) &&
 447             (!amdgpu_connector_is_dp12_capable(connector)))
 448                 return MODE_CLOCK_HIGH;
 449
 450         return MODE_OK;
 451 }
 452
 453 bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
 454 {
 455         u8 link_status[DP_LINK_STATUS_SIZE];
 456         struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 457
 458         if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
 459             <= 0)
 460                 return false;
 461         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 462                 return false;
 463         return true;
 464 }
 465
 466 void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
 467                                     u8 power_state)
 468 {
 469         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 470         struct amdgpu_connector_atom_dig *dig_connector;
 471
 472         if (!amdgpu_connector->con_priv)
 473                 return;
 474
 475         dig_connector = amdgpu_connector->con_priv;
 476
 477         /* power up/down the sink */
 478         if (dig_connector->dpcd[0] >= 0x11) {
 479                 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
 480                                    DP_SET_POWER, power_state);
 481                 usleep_range(1000, 2000);
 482         }
 483 }
 484
 485 struct amdgpu_atombios_dp_link_train_info {
 486         struct amdgpu_device *adev;
 487         struct drm_encoder *encoder;
 488         struct drm_connector *connector;
 489         int dp_clock;
 490         int dp_lane_count;
 491         bool tp3_supported;
 492         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 493         u8 train_set[4];
 494         u8 link_status[DP_LINK_STATUS_SIZE];
 495         u8 tries;
 496         struct drm_dp_aux *aux;
 497 };
 498
 499 static void
 500 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
 501 {
 502         /* set the initial vs/emph on the source */
 503         amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
 504                                                ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 505                                                0, dp_info->train_set[0]); /* sets all lanes at once */
 506
 507         /* set the vs/emph on the sink */
 508         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 509                           dp_info->train_set, dp_info->dp_lane_count);
 510 }
 511
 512 static void
 513 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
 514 {
 515         int rtp = 0;
 516
 517         /* set training pattern on the source */
 518         switch (tp) {
 519         case DP_TRAINING_PATTERN_1:
 520                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 521                 break;
 522         case DP_TRAINING_PATTERN_2:
 523                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 524                 break;
 525         case DP_TRAINING_PATTERN_3:
 526                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 527                         break;
 528         }
 529         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
 530
 531         /* enable training pattern on the sink */
 532         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 533 }
 534
 535 static int
 536 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
 537 {
 538         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
 539         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 540         u8 tmp;
 541
 542         /* power up the sink */
 543         amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 544
 545         /* possibly enable downspread on the sink */
 546         if (dp_info->dpcd[3] & 0x1)
 547                 drm_dp_dpcd_writeb(dp_info->aux,
 548                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 549         else
 550                 drm_dp_dpcd_writeb(dp_info->aux,
 551                                    DP_DOWNSPREAD_CTRL, 0);
 552
 553         if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 554                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 555
 556         /* set the lane count on the sink */
 557         tmp = dp_info->dp_lane_count;
 558         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 559                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 560         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 561
 562         /* set the link rate on the sink */
 563         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 564         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 565
 566         /* start training on the source */
 567         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
 568                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 569
 570         /* disable the training pattern on the sink */
 571         drm_dp_dpcd_writeb(dp_info->aux,
 572                            DP_TRAINING_PATTERN_SET,
 573                            DP_TRAINING_PATTERN_DISABLE);
 574
 575         return 0;
 576 }
 577
 578 static int
 579 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
 580 {
 581         udelay(400);
 582
 583         /* disable the training pattern on the sink */
 584         drm_dp_dpcd_writeb(dp_info->aux,
 585                            DP_TRAINING_PATTERN_SET,
 586                            DP_TRAINING_PATTERN_DISABLE);
 587
 588         /* disable the training pattern on the source */
 589         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
 590                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 591
 592         return 0;
 593 }
 594
 595 static int
 596 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
 597 {
 598         bool clock_recovery;
 599         u8 voltage;
 600         int i;
 601
 602         amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 603         memset(dp_info->train_set, 0, 4);
 604         amdgpu_atombios_dp_update_vs_emph(dp_info);
 605
 606         udelay(400);
 607
 608         /* clock recovery loop */
 609         clock_recovery = false;
 610         dp_info->tries = 0;
 611         voltage = 0xff;
 612         while (1) {
 613                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 614
 615                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 616                                                  dp_info->link_status) <= 0) {
 617                         DRM_ERROR("displayport link status failed\n");
 618                         break;
 619                 }
 620
 621                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 622                         clock_recovery = true;
 623                         break;
 624                 }
 625
 626                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 627                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 628                                 break;
 629                 }
 630                 if (i == dp_info->dp_lane_count) {
 631                         DRM_ERROR("clock recovery reached max voltage\n");
 632                         break;
 633                 }
 634
 635                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 636                         ++dp_info->tries;
 637                         if (dp_info->tries == 5) {
 638                                 DRM_ERROR("clock recovery tried 5 times\n");
 639                                 break;
 640                         }
 641                 } else
 642                         dp_info->tries = 0;
 643
 644                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 645
 646                 /* Compute new train_set as requested by sink */
 647                 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
 648                                              dp_info->train_set);
 649
 650                 amdgpu_atombios_dp_update_vs_emph(dp_info);
 651         }
 652         if (!clock_recovery) {
 653                 DRM_ERROR("clock recovery failed\n");
 654                 return -1;
 655         } else {
 656                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 657                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 658                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 659                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 660                 return 0;
 661         }
 662 }
 663
 664 static int
 665 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
 666 {
 667         bool channel_eq;
 668
 669         if (dp_info->tp3_supported)
 670                 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 671         else
 672                 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 673
 674         /* channel equalization loop */
 675         dp_info->tries = 0;
 676         channel_eq = false;
 677         while (1) {
 678                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 679
 680                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 681                                                  dp_info->link_status) <= 0) {
 682                         DRM_ERROR("displayport link status failed\n");
 683                         break;
 684                 }
 685
 686                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 687                         channel_eq = true;
 688                         break;
 689                 }
 690
 691                 /* Try 5 times */
 692                 if (dp_info->tries > 5) {
 693                         DRM_ERROR("channel eq failed: 5 tries\n");
 694                         break;
 695                 }
 696
 697                 /* Compute new train_set as requested by sink */
 698                 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
 699                                              dp_info->train_set);
 700
 701                 amdgpu_atombios_dp_update_vs_emph(dp_info);
 702                 dp_info->tries++;
 703         }
 704
 705         if (!channel_eq) {
 706                 DRM_ERROR("channel eq failed\n");
 707                 return -1;
 708         } else {
 709                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 710                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 711                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 712                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 713                 return 0;
 714         }
 715 }
 716
 717 void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
 718                             struct drm_connector *connector)
 719 {
 720         struct drm_device *dev = encoder->dev;
 721         struct amdgpu_device *adev = drm_to_adev(dev);
 722         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 723         struct amdgpu_connector *amdgpu_connector;
 724         struct amdgpu_connector_atom_dig *dig_connector;
 725         struct amdgpu_atombios_dp_link_train_info dp_info;
 726         u8 tmp;
 727
 728         if (!amdgpu_encoder->enc_priv)
 729                 return;
 730
 731         amdgpu_connector = to_amdgpu_connector(connector);
 732         if (!amdgpu_connector->con_priv)
 733                 return;
 734         dig_connector = amdgpu_connector->con_priv;
 735
 736         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 737             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 738                 return;
 739
 740         if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 741             == 1) {
 742                 if (tmp & DP_TPS3_SUPPORTED)
 743                         dp_info.tp3_supported = true;
 744                 else
 745                         dp_info.tp3_supported = false;
 746         } else {
 747                 dp_info.tp3_supported = false;
 748         }
 749
 750         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 751         dp_info.adev = adev;
 752         dp_info.encoder = encoder;
 753         dp_info.connector = connector;
 754         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 755         dp_info.dp_clock = dig_connector->dp_clock;
 756         dp_info.aux = &amdgpu_connector->ddc_bus->aux;
 757
 758         if (amdgpu_atombios_dp_link_train_init(&dp_info))
 759                 goto done;
 760         if (amdgpu_atombios_dp_link_train_cr(&dp_info))
 761                 goto done;
 762         if (amdgpu_atombios_dp_link_train_ce(&dp_info))
 763                 goto done;
 764 done:
 765         if (amdgpu_atombios_dp_link_train_finish(&dp_info))
 766                 return;
 767 }