drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65
  66 /**
  67  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  68  * memory request.
  69  *
  70  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  71  * @type: The type of memory requested
  72  * @man: The memory type manager for each domain
  73  *
  74  * This is called by ttm_bo_init_mm() when a buffer object is being
  75  * initialized.
  76  */
  77 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  78                                 struct ttm_mem_type_manager *man)
  79 {
  80         struct amdgpu_device *adev;
  81
  82         adev = amdgpu_ttm_adev(bdev);
  83
  84         switch (type) {
  85         case TTM_PL_SYSTEM:
  86                 /* System memory */
  87                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  88                 man->available_caching = TTM_PL_MASK_CACHING;
  89                 man->default_caching = TTM_PL_FLAG_CACHED;
  90                 break;
  91         case TTM_PL_TT:
  92                 /* GTT memory  */
  93                 man->func = &amdgpu_gtt_mgr_func;
  94                 man->gpu_offset = adev->gmc.gart_start;
  95                 man->available_caching = TTM_PL_MASK_CACHING;
  96                 man->default_caching = TTM_PL_FLAG_CACHED;
  97                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  98                 break;
  99         case TTM_PL_VRAM:
 100                 /* "On-card" video ram */
 101                 man->func = &amdgpu_vram_mgr_func;
 102                 man->gpu_offset = adev->gmc.vram_start;
 103                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 104                              TTM_MEMTYPE_FLAG_MAPPABLE;
 105                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 106                 man->default_caching = TTM_PL_FLAG_WC;
 107                 break;
 108         case AMDGPU_PL_GDS:
 109         case AMDGPU_PL_GWS:
 110         case AMDGPU_PL_OA:
 111                 /* On-chip GDS memory*/
 112                 man->func = &ttm_bo_manager_func;
 113                 man->gpu_offset = 0;
 114                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 115                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 116                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 117                 break;
 118         default:
 119                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 120                 return -EINVAL;
 121         }
 122         return 0;
 123 }
 124
 125 /**
 126  * amdgpu_evict_flags - Compute placement flags
 127  *
 128  * @bo: The buffer object to evict
 129  * @placement: Possible destination(s) for evicted BO
 130  *
 131  * Fill in placement data when ttm_bo_evict() is called
 132  */
 133 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 134                                 struct ttm_placement *placement)
 135 {
 136         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 137         struct amdgpu_bo *abo;
 138         static const struct ttm_place placements = {
 139                 .fpfn = 0,
 140                 .lpfn = 0,
 141                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 142         };
 143
 144         /* Don't handle scatter gather BOs */
 145         if (bo->type == ttm_bo_type_sg) {
 146                 placement->num_placement = 0;
 147                 placement->num_busy_placement = 0;
 148                 return;
 149         }
 150
 151         /* Object isn't an AMDGPU object so ignore */
 152         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 153                 placement->placement = &placements;
 154                 placement->busy_placement = &placements;
 155                 placement->num_placement = 1;
 156                 placement->num_busy_placement = 1;
 157                 return;
 158         }
 159
 160         abo = ttm_to_amdgpu_bo(bo);
 161         switch (bo->mem.mem_type) {
 162         case AMDGPU_PL_GDS:
 163         case AMDGPU_PL_GWS:
 164         case AMDGPU_PL_OA:
 165                 placement->num_placement = 0;
 166                 placement->num_busy_placement = 0;
 167                 return;
 168
 169         case TTM_PL_VRAM:
 170                 if (!adev->mman.buffer_funcs_enabled) {
 171                         /* Move to system memory */
 172                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 173                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 174                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 175                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 176
 177                         /* Try evicting to the CPU inaccessible part of VRAM
 178                          * first, but only set GTT as busy placement, so this
 179                          * BO will be evicted to GTT rather than causing other
 180                          * BOs to be evicted from VRAM
 181                          */
 182                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 183                                                          AMDGPU_GEM_DOMAIN_GTT);
 184                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 185                         abo->placements[0].lpfn = 0;
 186                         abo->placement.busy_placement = &abo->placements[1];
 187                         abo->placement.num_busy_placement = 1;
 188                 } else {
 189                         /* Move to GTT memory */
 190                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 191                 }
 192                 break;
 193         case TTM_PL_TT:
 194         default:
 195                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 196                 break;
 197         }
 198         *placement = abo->placement;
 199 }
 200
 201 /**
 202  * amdgpu_verify_access - Verify access for a mmap call
 203  *
 204  * @bo: The buffer object to map
 205  * @filp: The file pointer from the process performing the mmap
 206  *
 207  * This is called by ttm_bo_mmap() to verify whether a process
 208  * has the right to mmap a BO to their process space.
 209  */
 210 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 211 {
 212         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 213
 214         /*
 215          * Don't verify access for KFD BOs. They don't have a GEM
 216          * object associated with them.
 217          */
 218         if (abo->kfd_bo)
 219                 return 0;
 220
 221         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 222                 return -EPERM;
 223         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 224                                           filp->private_data);
 225 }
 226
 227 /**
 228  * amdgpu_move_null - Register memory for a buffer object
 229  *
 230  * @bo: The bo to assign the memory to
 231  * @new_mem: The memory to be assigned.
 232  *
 233  * Assign the memory from new_mem to the memory of the buffer object bo.
 234  */
 235 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 236                              struct ttm_mem_reg *new_mem)
 237 {
 238         struct ttm_mem_reg *old_mem = &bo->mem;
 239
 240         BUG_ON(old_mem->mm_node != NULL);
 241         *old_mem = *new_mem;
 242         new_mem->mm_node = NULL;
 243 }
 244
 245 /**
 246  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 247  *
 248  * @bo: The bo to assign the memory to.
 249  * @mm_node: Memory manager node for drm allocator.
 250  * @mem: The region where the bo resides.
 251  *
 252  */
 253 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 254                                     struct drm_mm_node *mm_node,
 255                                     struct ttm_mem_reg *mem)
 256 {
 257         uint64_t addr = 0;
 258
 259         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 260                 addr = mm_node->start << PAGE_SHIFT;
 261                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 262         }
 263         return addr;
 264 }
 265
 266 /**
 267  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 268  * @offset. It also modifies the offset to be within the drm_mm_node returned
 269  *
 270  * @mem: The region where the bo resides.
 271  * @offset: The offset that drm_mm_node is used for finding.
 272  *
 273  */
 274 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 275                                                uint64_t *offset)
 276 {
 277         struct drm_mm_node *mm_node = mem->mm_node;
 278
 279         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 280                 *offset -= (mm_node->size << PAGE_SHIFT);
 281                 ++mm_node;
 282         }
 283         return mm_node;
 284 }
 285
 286 /**
 287  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 288  * @bo: buffer object to map
 289  * @mem: memory object to map
 290  * @mm_node: drm_mm node object to map
 291  * @num_pages: number of pages to map
 292  * @offset: offset into @mm_node where to start
 293  * @window: which GART window to use
 294  * @ring: DMA ring to use for the copy
 295  * @tmz: if we should setup a TMZ enabled mapping
 296  * @addr: resulting address inside the MC address space
 297  *
 298  * Setup one of the GART windows to access a specific piece of memory or return
 299  * the physical address for local memory.
 300  */
 301 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 302                                  struct ttm_mem_reg *mem,
 303                                  struct drm_mm_node *mm_node,
 304                                  unsigned num_pages, uint64_t offset,
 305                                  unsigned window, struct amdgpu_ring *ring,
 306                                  bool tmz, uint64_t *addr)
 307 {
 308         struct ttm_dma_tt *dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 309         struct amdgpu_device *adev = ring->adev;
 310         struct amdgpu_job *job;
 311         unsigned num_dw, num_bytes;
 312         dma_addr_t *dma_address;
 313         struct dma_fence *fence;
 314         uint64_t src_addr, dst_addr;
 315         uint64_t flags;
 316         int r;
 317
 318         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 319                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 320
 321         /* Map only what can't be accessed directly */
 322         if (mem->start != AMDGPU_BO_INVALID_OFFSET) {
 323                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 324                 return 0;
 325         }
 326
 327         *addr = adev->gmc.gart_start;
 328         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 329                 AMDGPU_GPU_PAGE_SIZE;
 330         *addr += offset & ~PAGE_MASK;
 331
 332         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 333         num_bytes = num_pages * 8;
 334
 335         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 336                                      AMDGPU_IB_POOL_NORMAL, &job);
 337         if (r)
 338                 return r;
 339
 340         src_addr = num_dw * 4;
 341         src_addr += job->ibs[0].gpu_addr;
 342
 343         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 344         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 345         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 346                                 dst_addr, num_bytes, false);
 347
 348         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 349         WARN_ON(job->ibs[0].length_dw > num_dw);
 350
 351         dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 352         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 353         if (tmz)
 354                 flags |= AMDGPU_PTE_TMZ;
 355
 356         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 357                             &job->ibs[0].ptr[num_dw]);
 358         if (r)
 359                 goto error_free;
 360
 361         r = amdgpu_job_submit(job, &adev->mman.entity,
 362                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 363         if (r)
 364                 goto error_free;
 365
 366         dma_fence_put(fence);
 367
 368         return r;
 369
 370 error_free:
 371         amdgpu_job_free(job);
 372         return r;
 373 }
 374
 375 /**
 376  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 377  * @adev: amdgpu device
 378  * @src: buffer/address where to read from
 379  * @dst: buffer/address where to write to
 380  * @size: number of bytes to copy
 381  * @tmz: if a secure copy should be used
 382  * @resv: resv object to sync to
 383  * @f: Returns the last fence if multiple jobs are submitted.
 384  *
 385  * The function copies @size bytes from {src->mem + src->offset} to
 386  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 387  * move and different for a BO to BO copy.
 388  *
 389  */
 390 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 391                                const struct amdgpu_copy_mem *src,
 392                                const struct amdgpu_copy_mem *dst,
 393                                uint64_t size, bool tmz,
 394                                struct dma_resv *resv,
 395                                struct dma_fence **f)
 396 {
 397         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 398                                         AMDGPU_GPU_PAGE_SIZE);
 399
 400         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 401         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 402         struct drm_mm_node *src_mm, *dst_mm;
 403         struct dma_fence *fence = NULL;
 404         int r = 0;
 405
 406         if (!adev->mman.buffer_funcs_enabled) {
 407                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 408                 return -EINVAL;
 409         }
 410
 411         src_offset = src->offset;
 412         src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 413         src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 414
 415         dst_offset = dst->offset;
 416         dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 417         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 418
 419         mutex_lock(&adev->mman.gtt_window_lock);
 420
 421         while (size) {
 422                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 423                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 424                 struct dma_fence *next;
 425                 uint32_t cur_size;
 426                 uint64_t from, to;
 427
 428                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 429                  * begins at an offset, then adjust the size accordingly
 430                  */
 431                 cur_size = min3(src_node_size, dst_node_size, size);
 432                 cur_size = min(GTT_MAX_BYTES - src_page_offset, cur_size);
 433                 cur_size = min(GTT_MAX_BYTES - dst_page_offset, cur_size);
 434
 435                 /* Map src to window 0 and dst to window 1. */
 436                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 437                                           PFN_UP(cur_size + src_page_offset),
 438                                           src_offset, 0, ring, tmz, &from);
 439                 if (r)
 440                         goto error;
 441
 442                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 443                                           PFN_UP(cur_size + dst_page_offset),
 444                                           dst_offset, 1, ring, tmz, &to);
 445                 if (r)
 446                         goto error;
 447
 448                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 449                                        resv, &next, false, true, tmz);
 450                 if (r)
 451                         goto error;
 452
 453                 dma_fence_put(fence);
 454                 fence = next;
 455
 456                 size -= cur_size;
 457                 if (!size)
 458                         break;
 459
 460                 src_node_size -= cur_size;
 461                 if (!src_node_size) {
 462                         ++src_mm;
 463                         src_node_size = src_mm->size << PAGE_SHIFT;
 464                         src_offset = 0;
 465                 } else {
 466                         src_offset += cur_size;
 467                 }
 468
 469                 dst_node_size -= cur_size;
 470                 if (!dst_node_size) {
 471                         ++dst_mm;
 472                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 473                         dst_offset = 0;
 474                 } else {
 475                         dst_offset += cur_size;
 476                 }
 477         }
 478 error:
 479         mutex_unlock(&adev->mman.gtt_window_lock);
 480         if (f)
 481                 *f = dma_fence_get(fence);
 482         dma_fence_put(fence);
 483         return r;
 484 }
 485
 486 /**
 487  * amdgpu_move_blit - Copy an entire buffer to another buffer
 488  *
 489  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 490  * help move buffers to and from VRAM.
 491  */
 492 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 493                             bool evict, bool no_wait_gpu,
 494                             struct ttm_mem_reg *new_mem,
 495                             struct ttm_mem_reg *old_mem)
 496 {
 497         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 498         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 499         struct amdgpu_copy_mem src, dst;
 500         struct dma_fence *fence = NULL;
 501         int r;
 502
 503         src.bo = bo;
 504         dst.bo = bo;
 505         src.mem = old_mem;
 506         dst.mem = new_mem;
 507         src.offset = 0;
 508         dst.offset = 0;
 509
 510         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 511                                        new_mem->num_pages << PAGE_SHIFT,
 512                                        amdgpu_bo_encrypted(abo),
 513                                        bo->base.resv, &fence);
 514         if (r)
 515                 goto error;
 516
 517         /* clear the space being freed */
 518         if (old_mem->mem_type == TTM_PL_VRAM &&
 519             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 520                 struct dma_fence *wipe_fence = NULL;
 521
 522                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 523                                        NULL, &wipe_fence);
 524                 if (r) {
 525                         goto error;
 526                 } else if (wipe_fence) {
 527                         dma_fence_put(fence);
 528                         fence = wipe_fence;
 529                 }
 530         }
 531
 532         /* Always block for VM page tables before committing the new location */
 533         if (bo->type == ttm_bo_type_kernel)
 534                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 535         else
 536                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 537         dma_fence_put(fence);
 538         return r;
 539
 540 error:
 541         if (fence)
 542                 dma_fence_wait(fence, false);
 543         dma_fence_put(fence);
 544         return r;
 545 }
 546
 547 /**
 548  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 549  *
 550  * Called by amdgpu_bo_move().
 551  */
 552 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 553                                 struct ttm_operation_ctx *ctx,
 554                                 struct ttm_mem_reg *new_mem)
 555 {
 556         struct ttm_mem_reg *old_mem = &bo->mem;
 557         struct ttm_mem_reg tmp_mem;
 558         struct ttm_place placements;
 559         struct ttm_placement placement;
 560         int r;
 561
 562         /* create space/pages for new_mem in GTT space */
 563         tmp_mem = *new_mem;
 564         tmp_mem.mm_node = NULL;
 565         placement.num_placement = 1;
 566         placement.placement = &placements;
 567         placement.num_busy_placement = 1;
 568         placement.busy_placement = &placements;
 569         placements.fpfn = 0;
 570         placements.lpfn = 0;
 571         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 572         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 573         if (unlikely(r)) {
 574                 pr_err("Failed to find GTT space for blit from VRAM\n");
 575                 return r;
 576         }
 577
 578         /* set caching flags */
 579         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 580         if (unlikely(r)) {
 581                 goto out_cleanup;
 582         }
 583
 584         /* Bind the memory to the GTT space */
 585         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 586         if (unlikely(r)) {
 587                 goto out_cleanup;
 588         }
 589
 590         /* blit VRAM to GTT */
 591         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 592         if (unlikely(r)) {
 593                 goto out_cleanup;
 594         }
 595
 596         /* move BO (in tmp_mem) to new_mem */
 597         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 598 out_cleanup:
 599         ttm_bo_mem_put(bo, &tmp_mem);
 600         return r;
 601 }
 602
 603 /**
 604  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 605  *
 606  * Called by amdgpu_bo_move().
 607  */
 608 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 609                                 struct ttm_operation_ctx *ctx,
 610                                 struct ttm_mem_reg *new_mem)
 611 {
 612         struct ttm_mem_reg *old_mem = &bo->mem;
 613         struct ttm_mem_reg tmp_mem;
 614         struct ttm_placement placement;
 615         struct ttm_place placements;
 616         int r;
 617
 618         /* make space in GTT for old_mem buffer */
 619         tmp_mem = *new_mem;
 620         tmp_mem.mm_node = NULL;
 621         placement.num_placement = 1;
 622         placement.placement = &placements;
 623         placement.num_busy_placement = 1;
 624         placement.busy_placement = &placements;
 625         placements.fpfn = 0;
 626         placements.lpfn = 0;
 627         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 628         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 629         if (unlikely(r)) {
 630                 pr_err("Failed to find GTT space for blit to VRAM\n");
 631                 return r;
 632         }
 633
 634         /* move/bind old memory to GTT space */
 635         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 636         if (unlikely(r)) {
 637                 goto out_cleanup;
 638         }
 639
 640         /* copy to VRAM */
 641         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 642         if (unlikely(r)) {
 643                 goto out_cleanup;
 644         }
 645 out_cleanup:
 646         ttm_bo_mem_put(bo, &tmp_mem);
 647         return r;
 648 }
 649
 650 /**
 651  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 652  *
 653  * Called by amdgpu_bo_move()
 654  */
 655 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 656                                struct ttm_mem_reg *mem)
 657 {
 658         struct drm_mm_node *nodes = mem->mm_node;
 659
 660         if (mem->mem_type == TTM_PL_SYSTEM ||
 661             mem->mem_type == TTM_PL_TT)
 662                 return true;
 663         if (mem->mem_type != TTM_PL_VRAM)
 664                 return false;
 665
 666         /* ttm_mem_reg_ioremap only supports contiguous memory */
 667         if (nodes->size != mem->num_pages)
 668                 return false;
 669
 670         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 671                 <= adev->gmc.visible_vram_size;
 672 }
 673
 674 /**
 675  * amdgpu_bo_move - Move a buffer object to a new memory location
 676  *
 677  * Called by ttm_bo_handle_move_mem()
 678  */
 679 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 680                           struct ttm_operation_ctx *ctx,
 681                           struct ttm_mem_reg *new_mem)
 682 {
 683         struct amdgpu_device *adev;
 684         struct amdgpu_bo *abo;
 685         struct ttm_mem_reg *old_mem = &bo->mem;
 686         int r;
 687
 688         /* Can't move a pinned BO */
 689         abo = ttm_to_amdgpu_bo(bo);
 690         if (WARN_ON_ONCE(abo->pin_count > 0))
 691                 return -EINVAL;
 692
 693         adev = amdgpu_ttm_adev(bo->bdev);
 694
 695         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 696                 amdgpu_move_null(bo, new_mem);
 697                 return 0;
 698         }
 699         if ((old_mem->mem_type == TTM_PL_TT &&
 700              new_mem->mem_type == TTM_PL_SYSTEM) ||
 701             (old_mem->mem_type == TTM_PL_SYSTEM &&
 702              new_mem->mem_type == TTM_PL_TT)) {
 703                 /* bind is enough */
 704                 amdgpu_move_null(bo, new_mem);
 705                 return 0;
 706         }
 707         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 708             old_mem->mem_type == AMDGPU_PL_GWS ||
 709             old_mem->mem_type == AMDGPU_PL_OA ||
 710             new_mem->mem_type == AMDGPU_PL_GDS ||
 711             new_mem->mem_type == AMDGPU_PL_GWS ||
 712             new_mem->mem_type == AMDGPU_PL_OA) {
 713                 /* Nothing to save here */
 714                 amdgpu_move_null(bo, new_mem);
 715                 return 0;
 716         }
 717
 718         if (!adev->mman.buffer_funcs_enabled) {
 719                 r = -ENODEV;
 720                 goto memcpy;
 721         }
 722
 723         if (old_mem->mem_type == TTM_PL_VRAM &&
 724             new_mem->mem_type == TTM_PL_SYSTEM) {
 725                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 726         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 727                    new_mem->mem_type == TTM_PL_VRAM) {
 728                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 729         } else {
 730                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 731                                      new_mem, old_mem);
 732         }
 733
 734         if (r) {
 735 memcpy:
 736                 /* Check that all memory is CPU accessible */
 737                 if (!amdgpu_mem_visible(adev, old_mem) ||
 738                     !amdgpu_mem_visible(adev, new_mem)) {
 739                         pr_err("Move buffer fallback to memcpy unavailable\n");
 740                         return r;
 741                 }
 742
 743                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 744                 if (r)
 745                         return r;
 746         }
 747
 748         if (bo->type == ttm_bo_type_device &&
 749             new_mem->mem_type == TTM_PL_VRAM &&
 750             old_mem->mem_type != TTM_PL_VRAM) {
 751                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 752                  * accesses the BO after it's moved.
 753                  */
 754                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 755         }
 756
 757         /* update statistics */
 758         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 759         return 0;
 760 }
 761
 762 /**
 763  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 764  *
 765  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 766  */
 767 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 768 {
 769         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 770         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 771         struct drm_mm_node *mm_node = mem->mm_node;
 772
 773         mem->bus.addr = NULL;
 774         mem->bus.offset = 0;
 775         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 776         mem->bus.base = 0;
 777         mem->bus.is_iomem = false;
 778         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 779                 return -EINVAL;
 780         switch (mem->mem_type) {
 781         case TTM_PL_SYSTEM:
 782                 /* system memory */
 783                 return 0;
 784         case TTM_PL_TT:
 785                 break;
 786         case TTM_PL_VRAM:
 787                 mem->bus.offset = mem->start << PAGE_SHIFT;
 788                 /* check if it's visible */
 789                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 790                         return -EINVAL;
 791                 /* Only physically contiguous buffers apply. In a contiguous
 792                  * buffer, size of the first mm_node would match the number of
 793                  * pages in ttm_mem_reg.
 794                  */
 795                 if (adev->mman.aper_base_kaddr &&
 796                     (mm_node->size == mem->num_pages))
 797                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 798                                         mem->bus.offset;
 799
 800                 mem->bus.base = adev->gmc.aper_base;
 801                 mem->bus.is_iomem = true;
 802                 break;
 803         default:
 804                 return -EINVAL;
 805         }
 806         return 0;
 807 }
 808
 809 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 810 {
 811 }
 812
 813 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 814                                            unsigned long page_offset)
 815 {
 816         uint64_t offset = (page_offset << PAGE_SHIFT);
 817         struct drm_mm_node *mm;
 818
 819         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 820         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 821                 (offset >> PAGE_SHIFT);
 822 }
 823
 824 /*
 825  * TTM backend functions.
 826  */
 827 struct amdgpu_ttm_tt {
 828         struct ttm_dma_tt       ttm;
 829         struct drm_gem_object   *gobj;
 830         u64                     offset;
 831         uint64_t                userptr;
 832         struct task_struct      *usertask;
 833         uint32_t                userflags;
 834 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 835         struct hmm_range        *range;
 836 #endif
 837 };
 838
 839 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 840 /* flags used by HMM internal, not related to CPU/GPU PTE flags */
 841 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
 842         (1 << 0), /* HMM_PFN_VALID */
 843         (1 << 1), /* HMM_PFN_WRITE */
 844         0 /* HMM_PFN_DEVICE_PRIVATE */
 845 };
 846
 847 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
 848         0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
 849         0, /* HMM_PFN_NONE */
 850         0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
 851 };
 852
 853 /**
 854  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 855  * memory and start HMM tracking CPU page table update
 856  *
 857  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 858  * once afterwards to stop HMM tracking
 859  */
 860 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 861 {
 862         struct ttm_tt *ttm = bo->tbo.ttm;
 863         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 864         unsigned long start = gtt->userptr;
 865         struct vm_area_struct *vma;
 866         struct hmm_range *range;
 867         unsigned long timeout;
 868         struct mm_struct *mm;
 869         unsigned long i;
 870         int r = 0;
 871
 872         mm = bo->notifier.mm;
 873         if (unlikely(!mm)) {
 874                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 875                 return -EFAULT;
 876         }
 877
 878         /* Another get_user_pages is running at the same time?? */
 879         if (WARN_ON(gtt->range))
 880                 return -EFAULT;
 881
 882         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 883                 return -ESRCH;
 884
 885         range = kzalloc(sizeof(*range), GFP_KERNEL);
 886         if (unlikely(!range)) {
 887                 r = -ENOMEM;
 888                 goto out;
 889         }
 890         range->notifier = &bo->notifier;
 891         range->flags = hmm_range_flags;
 892         range->values = hmm_range_values;
 893         range->pfn_shift = PAGE_SHIFT;
 894         range->start = bo->notifier.interval_tree.start;
 895         range->end = bo->notifier.interval_tree.last + 1;
 896         range->default_flags = hmm_range_flags[HMM_PFN_VALID];
 897         if (!amdgpu_ttm_tt_is_readonly(ttm))
 898                 range->default_flags |= range->flags[HMM_PFN_WRITE];
 899
 900         range->pfns = kvmalloc_array(ttm->num_pages, sizeof(*range->pfns),
 901                                      GFP_KERNEL);
 902         if (unlikely(!range->pfns)) {
 903                 r = -ENOMEM;
 904                 goto out_free_ranges;
 905         }
 906
 907         down_read(&mm->mmap_sem);
 908         vma = find_vma(mm, start);
 909         if (unlikely(!vma || start < vma->vm_start)) {
 910                 r = -EFAULT;
 911                 goto out_unlock;
 912         }
 913         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 914                 vma->vm_file)) {
 915                 r = -EPERM;
 916                 goto out_unlock;
 917         }
 918         up_read(&mm->mmap_sem);
 919         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 920
 921 retry:
 922         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 923
 924         down_read(&mm->mmap_sem);
 925         r = hmm_range_fault(range, 0);
 926         up_read(&mm->mmap_sem);
 927         if (unlikely(r <= 0)) {
 928                 /*
 929                  * FIXME: This timeout should encompass the retry from
 930                  * mmu_interval_read_retry() as well.
 931                  */
 932                 if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout))
 933                         goto retry;
 934                 goto out_free_pfns;
 935         }
 936
 937         for (i = 0; i < ttm->num_pages; i++) {
 938                 /* FIXME: The pages cannot be touched outside the notifier_lock */
 939                 pages[i] = hmm_device_entry_to_page(range, range->pfns[i]);
 940                 if (unlikely(!pages[i])) {
 941                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 942                                i, range->pfns[i]);
 943                         r = -ENOMEM;
 944
 945                         goto out_free_pfns;
 946                 }
 947         }
 948
 949         gtt->range = range;
 950         mmput(mm);
 951
 952         return 0;
 953
 954 out_unlock:
 955         up_read(&mm->mmap_sem);
 956 out_free_pfns:
 957         kvfree(range->pfns);
 958 out_free_ranges:
 959         kfree(range);
 960 out:
 961         mmput(mm);
 962         return r;
 963 }
 964
 965 /**
 966  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 967  * Check if the pages backing this ttm range have been invalidated
 968  *
 969  * Returns: true if pages are still valid
 970  */
 971 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 972 {
 973         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 974         bool r = false;
 975
 976         if (!gtt || !gtt->userptr)
 977                 return false;
 978
 979         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 980                 gtt->userptr, ttm->num_pages);
 981
 982         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 983                 "No user pages to check\n");
 984
 985         if (gtt->range) {
 986                 /*
 987                  * FIXME: Must always hold notifier_lock for this, and must
 988                  * not ignore the return code.
 989                  */
 990                 r = mmu_interval_read_retry(gtt->range->notifier,
 991                                          gtt->range->notifier_seq);
 992                 kvfree(gtt->range->pfns);
 993                 kfree(gtt->range);
 994                 gtt->range = NULL;
 995         }
 996
 997         return !r;
 998 }
 999 #endif
1000
1001 /**
1002  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1003  *
1004  * Called by amdgpu_cs_list_validate(). This creates the page list
1005  * that backs user memory and will ultimately be mapped into the device
1006  * address space.
1007  */
1008 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1009 {
1010         unsigned long i;
1011
1012         for (i = 0; i < ttm->num_pages; ++i)
1013                 ttm->pages[i] = pages ? pages[i] : NULL;
1014 }
1015
1016 /**
1017  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
1018  *
1019  * Called by amdgpu_ttm_backend_bind()
1020  **/
1021 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
1022 {
1023         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1024         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1025         unsigned nents;
1026         int r;
1027
1028         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1029         enum dma_data_direction direction = write ?
1030                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1031
1032         /* Allocate an SG array and squash pages into it */
1033         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1034                                       ttm->num_pages << PAGE_SHIFT,
1035                                       GFP_KERNEL);
1036         if (r)
1037                 goto release_sg;
1038
1039         /* Map SG to device */
1040         r = -ENOMEM;
1041         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1042         if (nents == 0)
1043                 goto release_sg;
1044
1045         /* convert SG to linear array of pages and dma addresses */
1046         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1047                                          gtt->ttm.dma_address, ttm->num_pages);
1048
1049         return 0;
1050
1051 release_sg:
1052         kfree(ttm->sg);
1053         return r;
1054 }
1055
1056 /**
1057  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1058  */
1059 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1060 {
1061         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1062         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1063
1064         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1065         enum dma_data_direction direction = write ?
1066                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1067
1068         /* double check that we don't free the table twice */
1069         if (!ttm->sg->sgl)
1070                 return;
1071
1072         /* unmap the pages mapped to the device */
1073         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1074
1075         sg_free_table(ttm->sg);
1076
1077 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1078         if (gtt->range) {
1079                 unsigned long i;
1080
1081                 for (i = 0; i < ttm->num_pages; i++) {
1082                         if (ttm->pages[i] !=
1083                                 hmm_device_entry_to_page(gtt->range,
1084                                               gtt->range->pfns[i]))
1085                                 break;
1086                 }
1087
1088                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1089         }
1090 #endif
1091 }
1092
1093 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1094                                 struct ttm_buffer_object *tbo,
1095                                 uint64_t flags)
1096 {
1097         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1098         struct ttm_tt *ttm = tbo->ttm;
1099         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1100         int r;
1101
1102         if (amdgpu_bo_encrypted(abo))
1103                 flags |= AMDGPU_PTE_TMZ;
1104
1105         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1106                 uint64_t page_idx = 1;
1107
1108                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1109                                 ttm->pages, gtt->ttm.dma_address, flags);
1110                 if (r)
1111                         goto gart_bind_fail;
1112
1113                 /* The memory type of the first page defaults to UC. Now
1114                  * modify the memory type to NC from the second page of
1115                  * the BO onward.
1116                  */
1117                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1118                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1119
1120                 r = amdgpu_gart_bind(adev,
1121                                 gtt->offset + (page_idx << PAGE_SHIFT),
1122                                 ttm->num_pages - page_idx,
1123                                 &ttm->pages[page_idx],
1124                                 &(gtt->ttm.dma_address[page_idx]), flags);
1125         } else {
1126                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1127                                      ttm->pages, gtt->ttm.dma_address, flags);
1128         }
1129
1130 gart_bind_fail:
1131         if (r)
1132                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1133                           ttm->num_pages, gtt->offset);
1134
1135         return r;
1136 }
1137
1138 /**
1139  * amdgpu_ttm_backend_bind - Bind GTT memory
1140  *
1141  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1142  * This handles binding GTT memory to the device address space.
1143  */
1144 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1145                                    struct ttm_mem_reg *bo_mem)
1146 {
1147         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1148         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1149         uint64_t flags;
1150         int r = 0;
1151
1152         if (gtt->userptr) {
1153                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1154                 if (r) {
1155                         DRM_ERROR("failed to pin userptr\n");
1156                         return r;
1157                 }
1158         }
1159         if (!ttm->num_pages) {
1160                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1161                      ttm->num_pages, bo_mem, ttm);
1162         }
1163
1164         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1165             bo_mem->mem_type == AMDGPU_PL_GWS ||
1166             bo_mem->mem_type == AMDGPU_PL_OA)
1167                 return -EINVAL;
1168
1169         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1170                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1171                 return 0;
1172         }
1173
1174         /* compute PTE flags relevant to this BO memory */
1175         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1176
1177         /* bind pages into GART page tables */
1178         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1179         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1180                 ttm->pages, gtt->ttm.dma_address, flags);
1181
1182         if (r)
1183                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1184                           ttm->num_pages, gtt->offset);
1185         return r;
1186 }
1187
1188 /**
1189  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1190  */
1191 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1192 {
1193         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1194         struct ttm_operation_ctx ctx = { false, false };
1195         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1196         struct ttm_mem_reg tmp;
1197         struct ttm_placement placement;
1198         struct ttm_place placements;
1199         uint64_t addr, flags;
1200         int r;
1201
1202         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1203                 return 0;
1204
1205         addr = amdgpu_gmc_agp_addr(bo);
1206         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1207                 bo->mem.start = addr >> PAGE_SHIFT;
1208         } else {
1209
1210                 /* allocate GART space */
1211                 tmp = bo->mem;
1212                 tmp.mm_node = NULL;
1213                 placement.num_placement = 1;
1214                 placement.placement = &placements;
1215                 placement.num_busy_placement = 1;
1216                 placement.busy_placement = &placements;
1217                 placements.fpfn = 0;
1218                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1219                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1220                         TTM_PL_FLAG_TT;
1221
1222                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1223                 if (unlikely(r))
1224                         return r;
1225
1226                 /* compute PTE flags for this buffer object */
1227                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1228
1229                 /* Bind pages */
1230                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1231                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1232                 if (unlikely(r)) {
1233                         ttm_bo_mem_put(bo, &tmp);
1234                         return r;
1235                 }
1236
1237                 ttm_bo_mem_put(bo, &bo->mem);
1238                 bo->mem = tmp;
1239         }
1240
1241         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1242                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1243
1244         return 0;
1245 }
1246
1247 /**
1248  * amdgpu_ttm_recover_gart - Rebind GTT pages
1249  *
1250  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1251  * rebind GTT pages during a GPU reset.
1252  */
1253 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1254 {
1255         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1256         uint64_t flags;
1257         int r;
1258
1259         if (!tbo->ttm)
1260                 return 0;
1261
1262         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1263         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1264
1265         return r;
1266 }
1267
1268 /**
1269  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1270  *
1271  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1272  * ttm_tt_destroy().
1273  */
1274 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1275 {
1276         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1277         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1278         int r;
1279
1280         /* if the pages have userptr pinning then clear that first */
1281         if (gtt->userptr)
1282                 amdgpu_ttm_tt_unpin_userptr(ttm);
1283
1284         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1285                 return 0;
1286
1287         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1288         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1289         if (r)
1290                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1291                           gtt->ttm.ttm.num_pages, gtt->offset);
1292         return r;
1293 }
1294
1295 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1296 {
1297         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1298
1299         if (gtt->usertask)
1300                 put_task_struct(gtt->usertask);
1301
1302         ttm_dma_tt_fini(&gtt->ttm);
1303         kfree(gtt);
1304 }
1305
1306 static struct ttm_backend_func amdgpu_backend_func = {
1307         .bind = &amdgpu_ttm_backend_bind,
1308         .unbind = &amdgpu_ttm_backend_unbind,
1309         .destroy = &amdgpu_ttm_backend_destroy,
1310 };
1311
1312 /**
1313  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1314  *
1315  * @bo: The buffer object to create a GTT ttm_tt object around
1316  *
1317  * Called by ttm_tt_create().
1318  */
1319 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1320                                            uint32_t page_flags)
1321 {
1322         struct amdgpu_ttm_tt *gtt;
1323
1324         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1325         if (gtt == NULL) {
1326                 return NULL;
1327         }
1328         gtt->ttm.ttm.func = &amdgpu_backend_func;
1329         gtt->gobj = &bo->base;
1330
1331         /* allocate space for the uninitialized page entries */
1332         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1333                 kfree(gtt);
1334                 return NULL;
1335         }
1336         return &gtt->ttm.ttm;
1337 }
1338
1339 /**
1340  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1341  *
1342  * Map the pages of a ttm_tt object to an address space visible
1343  * to the underlying device.
1344  */
1345 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1346                         struct ttm_operation_ctx *ctx)
1347 {
1348         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1349         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1350
1351         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1352         if (gtt && gtt->userptr) {
1353                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1354                 if (!ttm->sg)
1355                         return -ENOMEM;
1356
1357                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1358                 ttm->state = tt_unbound;
1359                 return 0;
1360         }
1361
1362         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1363                 if (!ttm->sg) {
1364                         struct dma_buf_attachment *attach;
1365                         struct sg_table *sgt;
1366
1367                         attach = gtt->gobj->import_attach;
1368                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1369                         if (IS_ERR(sgt))
1370                                 return PTR_ERR(sgt);
1371
1372                         ttm->sg = sgt;
1373                 }
1374
1375                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1376                                                  gtt->ttm.dma_address,
1377                                                  ttm->num_pages);
1378                 ttm->state = tt_unbound;
1379                 return 0;
1380         }
1381
1382 #ifdef CONFIG_SWIOTLB
1383         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1384                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1385         }
1386 #endif
1387
1388         /* fall back to generic helper to populate the page array
1389          * and map them to the device */
1390         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1391 }
1392
1393 /**
1394  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1395  *
1396  * Unmaps pages of a ttm_tt object from the device address space and
1397  * unpopulates the page array backing it.
1398  */
1399 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1400 {
1401         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1402         struct amdgpu_device *adev;
1403
1404         if (gtt && gtt->userptr) {
1405                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1406                 kfree(ttm->sg);
1407                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1408                 return;
1409         }
1410
1411         if (ttm->sg && gtt->gobj->import_attach) {
1412                 struct dma_buf_attachment *attach;
1413
1414                 attach = gtt->gobj->import_attach;
1415                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1416                 ttm->sg = NULL;
1417                 return;
1418         }
1419
1420         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1421                 return;
1422
1423         adev = amdgpu_ttm_adev(ttm->bdev);
1424
1425 #ifdef CONFIG_SWIOTLB
1426         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1427                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1428                 return;
1429         }
1430 #endif
1431
1432         /* fall back to generic helper to unmap and unpopulate array */
1433         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1434 }
1435
1436 /**
1437  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1438  * task
1439  *
1440  * @ttm: The ttm_tt object to bind this userptr object to
1441  * @addr:  The address in the current tasks VM space to use
1442  * @flags: Requirements of userptr object.
1443  *
1444  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1445  * to current task
1446  */
1447 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1448                               uint32_t flags)
1449 {
1450         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1451
1452         if (gtt == NULL)
1453                 return -EINVAL;
1454
1455         gtt->userptr = addr;
1456         gtt->userflags = flags;
1457
1458         if (gtt->usertask)
1459                 put_task_struct(gtt->usertask);
1460         gtt->usertask = current->group_leader;
1461         get_task_struct(gtt->usertask);
1462
1463         return 0;
1464 }
1465
1466 /**
1467  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1468  */
1469 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1470 {
1471         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1472
1473         if (gtt == NULL)
1474                 return NULL;
1475
1476         if (gtt->usertask == NULL)
1477                 return NULL;
1478
1479         return gtt->usertask->mm;
1480 }
1481
1482 /**
1483  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1484  * address range for the current task.
1485  *
1486  */
1487 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1488                                   unsigned long end)
1489 {
1490         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1491         unsigned long size;
1492
1493         if (gtt == NULL || !gtt->userptr)
1494                 return false;
1495
1496         /* Return false if no part of the ttm_tt object lies within
1497          * the range
1498          */
1499         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1500         if (gtt->userptr > end || gtt->userptr + size <= start)
1501                 return false;
1502
1503         return true;
1504 }
1505
1506 /**
1507  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1508  */
1509 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1510 {
1511         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1512
1513         if (gtt == NULL || !gtt->userptr)
1514                 return false;
1515
1516         return true;
1517 }
1518
1519 /**
1520  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1521  */
1522 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1523 {
1524         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1525
1526         if (gtt == NULL)
1527                 return false;
1528
1529         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1530 }
1531
1532 /**
1533  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1534  *
1535  * @ttm: The ttm_tt object to compute the flags for
1536  * @mem: The memory registry backing this ttm_tt object
1537  *
1538  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1539  */
1540 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1541 {
1542         uint64_t flags = 0;
1543
1544         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1545                 flags |= AMDGPU_PTE_VALID;
1546
1547         if (mem && mem->mem_type == TTM_PL_TT) {
1548                 flags |= AMDGPU_PTE_SYSTEM;
1549
1550                 if (ttm->caching_state == tt_cached)
1551                         flags |= AMDGPU_PTE_SNOOPED;
1552         }
1553
1554         return flags;
1555 }
1556
1557 /**
1558  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1559  *
1560  * @ttm: The ttm_tt object to compute the flags for
1561  * @mem: The memory registry backing this ttm_tt object
1562
1563  * Figure out the flags to use for a VM PTE (Page Table Entry).
1564  */
1565 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1566                                  struct ttm_mem_reg *mem)
1567 {
1568         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1569
1570         flags |= adev->gart.gart_pte_flags;
1571         flags |= AMDGPU_PTE_READABLE;
1572
1573         if (!amdgpu_ttm_tt_is_readonly(ttm))
1574                 flags |= AMDGPU_PTE_WRITEABLE;
1575
1576         return flags;
1577 }
1578
1579 /**
1580  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1581  * object.
1582  *
1583  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1584  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1585  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1586  * used to clean out a memory space.
1587  */
1588 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1589                                             const struct ttm_place *place)
1590 {
1591         unsigned long num_pages = bo->mem.num_pages;
1592         struct drm_mm_node *node = bo->mem.mm_node;
1593         struct dma_resv_list *flist;
1594         struct dma_fence *f;
1595         int i;
1596
1597         if (bo->type == ttm_bo_type_kernel &&
1598             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1599                 return false;
1600
1601         /* If bo is a KFD BO, check if the bo belongs to the current process.
1602          * If true, then return false as any KFD process needs all its BOs to
1603          * be resident to run successfully
1604          */
1605         flist = dma_resv_get_list(bo->base.resv);
1606         if (flist) {
1607                 for (i = 0; i < flist->shared_count; ++i) {
1608                         f = rcu_dereference_protected(flist->shared[i],
1609                                 dma_resv_held(bo->base.resv));
1610                         if (amdkfd_fence_check_mm(f, current->mm))
1611                                 return false;
1612                 }
1613         }
1614
1615         switch (bo->mem.mem_type) {
1616         case TTM_PL_TT:
1617                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1618                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1619                         return false;
1620                 return true;
1621
1622         case TTM_PL_VRAM:
1623                 /* Check each drm MM node individually */
1624                 while (num_pages) {
1625                         if (place->fpfn < (node->start + node->size) &&
1626                             !(place->lpfn && place->lpfn <= node->start))
1627                                 return true;
1628
1629                         num_pages -= node->size;
1630                         ++node;
1631                 }
1632                 return false;
1633
1634         default:
1635                 break;
1636         }
1637
1638         return ttm_bo_eviction_valuable(bo, place);
1639 }
1640
1641 /**
1642  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1643  *
1644  * @bo:  The buffer object to read/write
1645  * @offset:  Offset into buffer object
1646  * @buf:  Secondary buffer to write/read from
1647  * @len: Length in bytes of access
1648  * @write:  true if writing
1649  *
1650  * This is used to access VRAM that backs a buffer object via MMIO
1651  * access for debugging purposes.
1652  */
1653 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1654                                     unsigned long offset,
1655                                     void *buf, int len, int write)
1656 {
1657         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1658         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1659         struct drm_mm_node *nodes;
1660         uint32_t value = 0;
1661         int ret = 0;
1662         uint64_t pos;
1663         unsigned long flags;
1664
1665         if (bo->mem.mem_type != TTM_PL_VRAM)
1666                 return -EIO;
1667
1668         pos = offset;
1669         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1670         pos += (nodes->start << PAGE_SHIFT);
1671
1672         while (len && pos < adev->gmc.mc_vram_size) {
1673                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1674                 uint64_t bytes = 4 - (pos & 3);
1675                 uint32_t shift = (pos & 3) * 8;
1676                 uint32_t mask = 0xffffffff << shift;
1677
1678                 if (len < bytes) {
1679                         mask &= 0xffffffff >> (bytes - len) * 8;
1680                         bytes = len;
1681                 }
1682
1683                 if (mask != 0xffffffff) {
1684                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1685                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1686                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1687                         if (!write || mask != 0xffffffff)
1688                                 value = RREG32_NO_KIQ(mmMM_DATA);
1689                         if (write) {
1690                                 value &= ~mask;
1691                                 value |= (*(uint32_t *)buf << shift) & mask;
1692                                 WREG32_NO_KIQ(mmMM_DATA, value);
1693                         }
1694                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1695                         if (!write) {
1696                                 value = (value & mask) >> shift;
1697                                 memcpy(buf, &value, bytes);
1698                         }
1699                 } else {
1700                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1701                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1702
1703                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1704                                                   bytes, write);
1705                 }
1706
1707                 ret += bytes;
1708                 buf = (uint8_t *)buf + bytes;
1709                 pos += bytes;
1710                 len -= bytes;
1711                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1712                         ++nodes;
1713                         pos = (nodes->start << PAGE_SHIFT);
1714                 }
1715         }
1716
1717         return ret;
1718 }
1719
1720 static struct ttm_bo_driver amdgpu_bo_driver = {
1721         .ttm_tt_create = &amdgpu_ttm_tt_create,
1722         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1723         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1724         .init_mem_type = &amdgpu_init_mem_type,
1725         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1726         .evict_flags = &amdgpu_evict_flags,
1727         .move = &amdgpu_bo_move,
1728         .verify_access = &amdgpu_verify_access,
1729         .move_notify = &amdgpu_bo_move_notify,
1730         .release_notify = &amdgpu_bo_release_notify,
1731         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1732         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1733         .io_mem_free = &amdgpu_ttm_io_mem_free,
1734         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1735         .access_memory = &amdgpu_ttm_access_memory,
1736         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1737 };
1738
1739 /*
1740  * Firmware Reservation functions
1741  */
1742 /**
1743  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1744  *
1745  * @adev: amdgpu_device pointer
1746  *
1747  * free fw reserved vram if it has been reserved.
1748  */
1749 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1750 {
1751         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1752                 NULL, &adev->fw_vram_usage.va);
1753 }
1754
1755 /**
1756  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1757  *
1758  * @adev: amdgpu_device pointer
1759  *
1760  * create bo vram reservation from fw.
1761  */
1762 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1763 {
1764         uint64_t vram_size = adev->gmc.visible_vram_size;
1765
1766         adev->fw_vram_usage.va = NULL;
1767         adev->fw_vram_usage.reserved_bo = NULL;
1768
1769         if (adev->fw_vram_usage.size == 0 ||
1770             adev->fw_vram_usage.size > vram_size)
1771                 return 0;
1772
1773         return amdgpu_bo_create_kernel_at(adev,
1774                                           adev->fw_vram_usage.start_offset,
1775                                           adev->fw_vram_usage.size,
1776                                           AMDGPU_GEM_DOMAIN_VRAM,
1777                                           &adev->fw_vram_usage.reserved_bo,
1778                                           &adev->fw_vram_usage.va);
1779 }
1780
1781 /*
1782  * Memoy training reservation functions
1783  */
1784
1785 /**
1786  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1787  *
1788  * @adev: amdgpu_device pointer
1789  *
1790  * free memory training reserved vram if it has been reserved.
1791  */
1792 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1793 {
1794         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1795
1796         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1797         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1798         ctx->c2p_bo = NULL;
1799
1800         return 0;
1801 }
1802
1803 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1804 {
1805        if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1806                vram_size -= SZ_1M;
1807
1808        return ALIGN(vram_size, SZ_1M);
1809 }
1810
1811 /**
1812  * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1813  *
1814  * @adev: amdgpu_device pointer
1815  *
1816  * create bo vram reservation from memory training.
1817  */
1818 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1819 {
1820         int ret;
1821         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1822
1823         memset(ctx, 0, sizeof(*ctx));
1824         if (!adev->fw_vram_usage.mem_train_support) {
1825                 DRM_DEBUG("memory training does not support!\n");
1826                 return 0;
1827         }
1828
1829         ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1830         ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1831         ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1832
1833         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1834                   ctx->train_data_size,
1835                   ctx->p2c_train_data_offset,
1836                   ctx->c2p_train_data_offset);
1837
1838         ret = amdgpu_bo_create_kernel_at(adev,
1839                                          ctx->c2p_train_data_offset,
1840                                          ctx->train_data_size,
1841                                          AMDGPU_GEM_DOMAIN_VRAM,
1842                                          &ctx->c2p_bo,
1843                                          NULL);
1844         if (ret) {
1845                 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1846                 amdgpu_ttm_training_reserve_vram_fini(adev);
1847                 return ret;
1848         }
1849
1850         ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1851         return 0;
1852 }
1853
1854 /**
1855  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1856  * gtt/vram related fields.
1857  *
1858  * This initializes all of the memory space pools that the TTM layer
1859  * will need such as the GTT space (system memory mapped to the device),
1860  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1861  * can be mapped per VMID.
1862  */
1863 int amdgpu_ttm_init(struct amdgpu_device *adev)
1864 {
1865         uint64_t gtt_size;
1866         int r;
1867         u64 vis_vram_limit;
1868         void *stolen_vga_buf;
1869
1870         mutex_init(&adev->mman.gtt_window_lock);
1871
1872         /* No others user of address space so set it to 0 */
1873         r = ttm_bo_device_init(&adev->mman.bdev,
1874                                &amdgpu_bo_driver,
1875                                adev->ddev->anon_inode->i_mapping,
1876                                adev->ddev->vma_offset_manager,
1877                                dma_addressing_limited(adev->dev));
1878         if (r) {
1879                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1880                 return r;
1881         }
1882         adev->mman.initialized = true;
1883
1884         /* We opt to avoid OOM on system pages allocations */
1885         adev->mman.bdev.no_retry = true;
1886
1887         /* Initialize VRAM pool with all of VRAM divided into pages */
1888         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1889                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1890         if (r) {
1891                 DRM_ERROR("Failed initializing VRAM heap.\n");
1892                 return r;
1893         }
1894
1895         /* Reduce size of CPU-visible VRAM if requested */
1896         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1897         if (amdgpu_vis_vram_limit > 0 &&
1898             vis_vram_limit <= adev->gmc.visible_vram_size)
1899                 adev->gmc.visible_vram_size = vis_vram_limit;
1900
1901         /* Change the size here instead of the init above so only lpfn is affected */
1902         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1903 #ifdef CONFIG_64BIT
1904         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1905                                                 adev->gmc.visible_vram_size);
1906 #endif
1907
1908         /*
1909          *The reserved vram for firmware must be pinned to the specified
1910          *place on the VRAM, so reserve it early.
1911          */
1912         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1913         if (r) {
1914                 return r;
1915         }
1916
1917         /*
1918          *The reserved vram for memory training must be pinned to the specified
1919          *place on the VRAM, so reserve it early.
1920          */
1921         if (!amdgpu_sriov_vf(adev)) {
1922                 r = amdgpu_ttm_training_reserve_vram_init(adev);
1923                 if (r)
1924                         return r;
1925         }
1926
1927         /* allocate memory as required for VGA
1928          * This is used for VGA emulation and pre-OS scanout buffers to
1929          * avoid display artifacts while transitioning between pre-OS
1930          * and driver.  */
1931         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1932                                     AMDGPU_GEM_DOMAIN_VRAM,
1933                                     &adev->stolen_vga_memory,
1934                                     NULL, &stolen_vga_buf);
1935         if (r)
1936                 return r;
1937
1938         /*
1939          * reserve one TMR (64K) memory at the top of VRAM which holds
1940          * IP Discovery data and is protected by PSP.
1941          */
1942         r = amdgpu_bo_create_kernel_at(adev,
1943                                        adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1944                                        DISCOVERY_TMR_SIZE,
1945                                        AMDGPU_GEM_DOMAIN_VRAM,
1946                                        &adev->discovery_memory,
1947                                        NULL);
1948         if (r)
1949                 return r;
1950
1951         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1952                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1953
1954         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1955          * or whatever the user passed on module init */
1956         if (amdgpu_gtt_size == -1) {
1957                 struct sysinfo si;
1958
1959                 si_meminfo(&si);
1960                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1961                                adev->gmc.mc_vram_size),
1962                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1963         }
1964         else
1965                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1966
1967         /* Initialize GTT memory pool */
1968         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1969         if (r) {
1970                 DRM_ERROR("Failed initializing GTT heap.\n");
1971                 return r;
1972         }
1973         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1974                  (unsigned)(gtt_size / (1024 * 1024)));
1975
1976         /* Initialize various on-chip memory pools */
1977         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1978                            adev->gds.gds_size);
1979         if (r) {
1980                 DRM_ERROR("Failed initializing GDS heap.\n");
1981                 return r;
1982         }
1983
1984         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1985                            adev->gds.gws_size);
1986         if (r) {
1987                 DRM_ERROR("Failed initializing gws heap.\n");
1988                 return r;
1989         }
1990
1991         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1992                            adev->gds.oa_size);
1993         if (r) {
1994                 DRM_ERROR("Failed initializing oa heap.\n");
1995                 return r;
1996         }
1997
1998         return 0;
1999 }
2000
2001 /**
2002  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2003  */
2004 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2005 {
2006         void *stolen_vga_buf;
2007         /* return the VGA stolen memory (if any) back to VRAM */
2008         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2009 }
2010
2011 /**
2012  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2013  */
2014 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2015 {
2016         if (!adev->mman.initialized)
2017                 return;
2018
2019         amdgpu_ttm_training_reserve_vram_fini(adev);
2020         /* return the IP Discovery TMR memory back to VRAM */
2021         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2022         amdgpu_ttm_fw_reserve_vram_fini(adev);
2023
2024         if (adev->mman.aper_base_kaddr)
2025                 iounmap(adev->mman.aper_base_kaddr);
2026         adev->mman.aper_base_kaddr = NULL;
2027
2028         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2029         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2030         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2031         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2032         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2033         ttm_bo_device_release(&adev->mman.bdev);
2034         adev->mman.initialized = false;
2035         DRM_INFO("amdgpu: ttm finalized\n");
2036 }
2037
2038 /**
2039  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2040  *
2041  * @adev: amdgpu_device pointer
2042  * @enable: true when we can use buffer functions.
2043  *
2044  * Enable/disable use of buffer functions during suspend/resume. This should
2045  * only be called at bootup or when userspace isn't running.
2046  */
2047 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2048 {
2049         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2050         uint64_t size;
2051         int r;
2052
2053         if (!adev->mman.initialized || adev->in_gpu_reset ||
2054             adev->mman.buffer_funcs_enabled == enable)
2055                 return;
2056
2057         if (enable) {
2058                 struct amdgpu_ring *ring;
2059                 struct drm_gpu_scheduler *sched;
2060
2061                 ring = adev->mman.buffer_funcs_ring;
2062                 sched = &ring->sched;
2063                 r = drm_sched_entity_init(&adev->mman.entity,
2064                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2065                                           1, NULL);
2066                 if (r) {
2067                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2068                                   r);
2069                         return;
2070                 }
2071         } else {
2072                 drm_sched_entity_destroy(&adev->mman.entity);
2073                 dma_fence_put(man->move);
2074                 man->move = NULL;
2075         }
2076
2077         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2078         if (enable)
2079                 size = adev->gmc.real_vram_size;
2080         else
2081                 size = adev->gmc.visible_vram_size;
2082         man->size = size >> PAGE_SHIFT;
2083         adev->mman.buffer_funcs_enabled = enable;
2084 }
2085
2086 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2087 {
2088         struct drm_file *file_priv = filp->private_data;
2089         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2090
2091         if (adev == NULL)
2092                 return -EINVAL;
2093
2094         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2095 }
2096
2097 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2098                        uint64_t dst_offset, uint32_t byte_count,
2099                        struct dma_resv *resv,
2100                        struct dma_fence **fence, bool direct_submit,
2101                        bool vm_needs_flush, bool tmz)
2102 {
2103         struct amdgpu_device *adev = ring->adev;
2104         struct amdgpu_job *job;
2105
2106         uint32_t max_bytes;
2107         unsigned num_loops, num_dw;
2108         unsigned i;
2109         int r;
2110
2111         if (direct_submit && !ring->sched.ready) {
2112                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2113                 return -EINVAL;
2114         }
2115
2116         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2117         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2118         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2119
2120         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4,
2121                         direct_submit ? AMDGPU_IB_POOL_DIRECT : AMDGPU_IB_POOL_NORMAL, &job);
2122         if (r)
2123                 return r;
2124
2125         if (vm_needs_flush) {
2126                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2127                 job->vm_needs_flush = true;
2128         }
2129         if (resv) {
2130                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2131                                      AMDGPU_SYNC_ALWAYS,
2132                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2133                 if (r) {
2134                         DRM_ERROR("sync failed (%d).\n", r);
2135                         goto error_free;
2136                 }
2137         }
2138
2139         for (i = 0; i < num_loops; i++) {
2140                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2141
2142                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2143                                         dst_offset, cur_size_in_bytes, tmz);
2144
2145                 src_offset += cur_size_in_bytes;
2146                 dst_offset += cur_size_in_bytes;
2147                 byte_count -= cur_size_in_bytes;
2148         }
2149
2150         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2151         WARN_ON(job->ibs[0].length_dw > num_dw);
2152         if (direct_submit)
2153                 r = amdgpu_job_submit_direct(job, ring, fence);
2154         else
2155                 r = amdgpu_job_submit(job, &adev->mman.entity,
2156                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2157         if (r)
2158                 goto error_free;
2159
2160         return r;
2161
2162 error_free:
2163         amdgpu_job_free(job);
2164         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2165         return r;
2166 }
2167
2168 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2169                        uint32_t src_data,
2170                        struct dma_resv *resv,
2171                        struct dma_fence **fence)
2172 {
2173         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2174         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2175         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2176
2177         struct drm_mm_node *mm_node;
2178         unsigned long num_pages;
2179         unsigned int num_loops, num_dw;
2180
2181         struct amdgpu_job *job;
2182         int r;
2183
2184         if (!adev->mman.buffer_funcs_enabled) {
2185                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2186                 return -EINVAL;
2187         }
2188
2189         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2190                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2191                 if (r)
2192                         return r;
2193         }
2194
2195         num_pages = bo->tbo.num_pages;
2196         mm_node = bo->tbo.mem.mm_node;
2197         num_loops = 0;
2198         while (num_pages) {
2199                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2200
2201                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2202                 num_pages -= mm_node->size;
2203                 ++mm_node;
2204         }
2205         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2206
2207         /* for IB padding */
2208         num_dw += 64;
2209
2210         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_NORMAL, &job);
2211         if (r)
2212                 return r;
2213
2214         if (resv) {
2215                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2216                                      AMDGPU_SYNC_ALWAYS,
2217                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2218                 if (r) {
2219                         DRM_ERROR("sync failed (%d).\n", r);
2220                         goto error_free;
2221                 }
2222         }
2223
2224         num_pages = bo->tbo.num_pages;
2225         mm_node = bo->tbo.mem.mm_node;
2226
2227         while (num_pages) {
2228                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2229                 uint64_t dst_addr;
2230
2231                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2232                 while (byte_count) {
2233                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2234                                                            max_bytes);
2235
2236                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2237                                                 dst_addr, cur_size_in_bytes);
2238
2239                         dst_addr += cur_size_in_bytes;
2240                         byte_count -= cur_size_in_bytes;
2241                 }
2242
2243                 num_pages -= mm_node->size;
2244                 ++mm_node;
2245         }
2246
2247         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2248         WARN_ON(job->ibs[0].length_dw > num_dw);
2249         r = amdgpu_job_submit(job, &adev->mman.entity,
2250                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2251         if (r)
2252                 goto error_free;
2253
2254         return 0;
2255
2256 error_free:
2257         amdgpu_job_free(job);
2258         return r;
2259 }
2260
2261 #if defined(CONFIG_DEBUG_FS)
2262
2263 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2264 {
2265         struct drm_info_node *node = (struct drm_info_node *)m->private;
2266         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2267         struct drm_device *dev = node->minor->dev;
2268         struct amdgpu_device *adev = dev->dev_private;
2269         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2270         struct drm_printer p = drm_seq_file_printer(m);
2271
2272         man->func->debug(man, &p);
2273         return 0;
2274 }
2275
2276 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2277         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2278         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2279         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2280         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2281         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2282         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2283 #ifdef CONFIG_SWIOTLB
2284         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2285 #endif
2286 };
2287
2288 /**
2289  * amdgpu_ttm_vram_read - Linear read access to VRAM
2290  *
2291  * Accesses VRAM via MMIO for debugging purposes.
2292  */
2293 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2294                                     size_t size, loff_t *pos)
2295 {
2296         struct amdgpu_device *adev = file_inode(f)->i_private;
2297         ssize_t result = 0;
2298
2299         if (size & 0x3 || *pos & 0x3)
2300                 return -EINVAL;
2301
2302         if (*pos >= adev->gmc.mc_vram_size)
2303                 return -ENXIO;
2304
2305         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2306         while (size) {
2307                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2308                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2309
2310                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2311                 if (copy_to_user(buf, value, bytes))
2312                         return -EFAULT;
2313
2314                 result += bytes;
2315                 buf += bytes;
2316                 *pos += bytes;
2317                 size -= bytes;
2318         }
2319
2320         return result;
2321 }
2322
2323 /**
2324  * amdgpu_ttm_vram_write - Linear write access to VRAM
2325  *
2326  * Accesses VRAM via MMIO for debugging purposes.
2327  */
2328 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2329                                     size_t size, loff_t *pos)
2330 {
2331         struct amdgpu_device *adev = file_inode(f)->i_private;
2332         ssize_t result = 0;
2333         int r;
2334
2335         if (size & 0x3 || *pos & 0x3)
2336                 return -EINVAL;
2337
2338         if (*pos >= adev->gmc.mc_vram_size)
2339                 return -ENXIO;
2340
2341         while (size) {
2342                 unsigned long flags;
2343                 uint32_t value;
2344
2345                 if (*pos >= adev->gmc.mc_vram_size)
2346                         return result;
2347
2348                 r = get_user(value, (uint32_t *)buf);
2349                 if (r)
2350                         return r;
2351
2352                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2353                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2354                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2355                 WREG32_NO_KIQ(mmMM_DATA, value);
2356                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2357
2358                 result += 4;
2359                 buf += 4;
2360                 *pos += 4;
2361                 size -= 4;
2362         }
2363
2364         return result;
2365 }
2366
2367 static const struct file_operations amdgpu_ttm_vram_fops = {
2368         .owner = THIS_MODULE,
2369         .read = amdgpu_ttm_vram_read,
2370         .write = amdgpu_ttm_vram_write,
2371         .llseek = default_llseek,
2372 };
2373
2374 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2375
2376 /**
2377  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2378  */
2379 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2380                                    size_t size, loff_t *pos)
2381 {
2382         struct amdgpu_device *adev = file_inode(f)->i_private;
2383         ssize_t result = 0;
2384         int r;
2385
2386         while (size) {
2387                 loff_t p = *pos / PAGE_SIZE;
2388                 unsigned off = *pos & ~PAGE_MASK;
2389                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2390                 struct page *page;
2391                 void *ptr;
2392
2393                 if (p >= adev->gart.num_cpu_pages)
2394                         return result;
2395
2396                 page = adev->gart.pages[p];
2397                 if (page) {
2398                         ptr = kmap(page);
2399                         ptr += off;
2400
2401                         r = copy_to_user(buf, ptr, cur_size);
2402                         kunmap(adev->gart.pages[p]);
2403                 } else
2404                         r = clear_user(buf, cur_size);
2405
2406                 if (r)
2407                         return -EFAULT;
2408
2409                 result += cur_size;
2410                 buf += cur_size;
2411                 *pos += cur_size;
2412                 size -= cur_size;
2413         }
2414
2415         return result;
2416 }
2417
2418 static const struct file_operations amdgpu_ttm_gtt_fops = {
2419         .owner = THIS_MODULE,
2420         .read = amdgpu_ttm_gtt_read,
2421         .llseek = default_llseek
2422 };
2423
2424 #endif
2425
2426 /**
2427  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2428  *
2429  * This function is used to read memory that has been mapped to the
2430  * GPU and the known addresses are not physical addresses but instead
2431  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2432  */
2433 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2434                                  size_t size, loff_t *pos)
2435 {
2436         struct amdgpu_device *adev = file_inode(f)->i_private;
2437         struct iommu_domain *dom;
2438         ssize_t result = 0;
2439         int r;
2440
2441         /* retrieve the IOMMU domain if any for this device */
2442         dom = iommu_get_domain_for_dev(adev->dev);
2443
2444         while (size) {
2445                 phys_addr_t addr = *pos & PAGE_MASK;
2446                 loff_t off = *pos & ~PAGE_MASK;
2447                 size_t bytes = PAGE_SIZE - off;
2448                 unsigned long pfn;
2449                 struct page *p;
2450                 void *ptr;
2451
2452                 bytes = bytes < size ? bytes : size;
2453
2454                 /* Translate the bus address to a physical address.  If
2455                  * the domain is NULL it means there is no IOMMU active
2456                  * and the address translation is the identity
2457                  */
2458                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2459
2460                 pfn = addr >> PAGE_SHIFT;
2461                 if (!pfn_valid(pfn))
2462                         return -EPERM;
2463
2464                 p = pfn_to_page(pfn);
2465                 if (p->mapping != adev->mman.bdev.dev_mapping)
2466                         return -EPERM;
2467
2468                 ptr = kmap(p);
2469                 r = copy_to_user(buf, ptr + off, bytes);
2470                 kunmap(p);
2471                 if (r)
2472                         return -EFAULT;
2473
2474                 size -= bytes;
2475                 *pos += bytes;
2476                 result += bytes;
2477         }
2478
2479         return result;
2480 }
2481
2482 /**
2483  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2484  *
2485  * This function is used to write memory that has been mapped to the
2486  * GPU and the known addresses are not physical addresses but instead
2487  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2488  */
2489 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2490                                  size_t size, loff_t *pos)
2491 {
2492         struct amdgpu_device *adev = file_inode(f)->i_private;
2493         struct iommu_domain *dom;
2494         ssize_t result = 0;
2495         int r;
2496
2497         dom = iommu_get_domain_for_dev(adev->dev);
2498
2499         while (size) {
2500                 phys_addr_t addr = *pos & PAGE_MASK;
2501                 loff_t off = *pos & ~PAGE_MASK;
2502                 size_t bytes = PAGE_SIZE - off;
2503                 unsigned long pfn;
2504                 struct page *p;
2505                 void *ptr;
2506
2507                 bytes = bytes < size ? bytes : size;
2508
2509                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2510
2511                 pfn = addr >> PAGE_SHIFT;
2512                 if (!pfn_valid(pfn))
2513                         return -EPERM;
2514
2515                 p = pfn_to_page(pfn);
2516                 if (p->mapping != adev->mman.bdev.dev_mapping)
2517                         return -EPERM;
2518
2519                 ptr = kmap(p);
2520                 r = copy_from_user(ptr + off, buf, bytes);
2521                 kunmap(p);
2522                 if (r)
2523                         return -EFAULT;
2524
2525                 size -= bytes;
2526                 *pos += bytes;
2527                 result += bytes;
2528         }
2529
2530         return result;
2531 }
2532
2533 static const struct file_operations amdgpu_ttm_iomem_fops = {
2534         .owner = THIS_MODULE,
2535         .read = amdgpu_iomem_read,
2536         .write = amdgpu_iomem_write,
2537         .llseek = default_llseek
2538 };
2539
2540 static const struct {
2541         char *name;
2542         const struct file_operations *fops;
2543         int domain;
2544 } ttm_debugfs_entries[] = {
2545         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2546 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2547         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2548 #endif
2549         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2550 };
2551
2552 #endif
2553
2554 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2555 {
2556 #if defined(CONFIG_DEBUG_FS)
2557         unsigned count;
2558
2559         struct drm_minor *minor = adev->ddev->primary;
2560         struct dentry *ent, *root = minor->debugfs_root;
2561
2562         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2563                 ent = debugfs_create_file(
2564                                 ttm_debugfs_entries[count].name,
2565                                 S_IFREG | S_IRUGO, root,
2566                                 adev,
2567                                 ttm_debugfs_entries[count].fops);
2568                 if (IS_ERR(ent))
2569                         return PTR_ERR(ent);
2570                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2571                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2572                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2573                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2574                 adev->mman.debugfs_entries[count] = ent;
2575         }
2576
2577         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2578
2579 #ifdef CONFIG_SWIOTLB
2580         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2581                 --count;
2582 #endif
2583
2584         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2585 #else
2586         return 0;
2587 #endif
2588 }