drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44
  45 #include <drm/ttm/ttm_bo_api.h>
  46 #include <drm/ttm/ttm_bo_driver.h>
  47 #include <drm/ttm/ttm_placement.h>
  48
  49 #include <drm/amdgpu_drm.h>
  50
  51 #include "amdgpu.h"
  52 #include "amdgpu_object.h"
  53 #include "amdgpu_trace.h"
  54 #include "amdgpu_amdkfd.h"
  55 #include "amdgpu_sdma.h"
  56 #include "amdgpu_ras.h"
  57 #include "amdgpu_atomfirmware.h"
  58 #include "amdgpu_res_cursor.h"
  59 #include "bif/bif_4_1_d.h"
  60
  61 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  62
  63 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  64                                    struct ttm_tt *ttm,
  65                                    struct ttm_resource *bo_mem);
  66 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  67                                       struct ttm_tt *ttm);
  68
  69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  70                                     unsigned int type,
  71                                     uint64_t size_in_page)
  72 {
  73         return ttm_range_man_init(&adev->mman.bdev, type,
  74                                   false, size_in_page);
  75 }
  76
  77 /**
  78  * amdgpu_evict_flags - Compute placement flags
  79  *
  80  * @bo: The buffer object to evict
  81  * @placement: Possible destination(s) for evicted BO
  82  *
  83  * Fill in placement data when ttm_bo_evict() is called
  84  */
  85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  86                                 struct ttm_placement *placement)
  87 {
  88         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  89         struct amdgpu_bo *abo;
  90         static const struct ttm_place placements = {
  91                 .fpfn = 0,
  92                 .lpfn = 0,
  93                 .mem_type = TTM_PL_SYSTEM,
  94                 .flags = 0
  95         };
  96
  97         /* Don't handle scatter gather BOs */
  98         if (bo->type == ttm_bo_type_sg) {
  99                 placement->num_placement = 0;
 100                 placement->num_busy_placement = 0;
 101                 return;
 102         }
 103
 104         /* Object isn't an AMDGPU object so ignore */
 105         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 106                 placement->placement = &placements;
 107                 placement->busy_placement = &placements;
 108                 placement->num_placement = 1;
 109                 placement->num_busy_placement = 1;
 110                 return;
 111         }
 112
 113         abo = ttm_to_amdgpu_bo(bo);
 114         if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
 115                 struct dma_fence *fence;
 116                 struct dma_resv *resv = &bo->base._resv;
 117
 118                 rcu_read_lock();
 119                 fence = rcu_dereference(resv->fence_excl);
 120                 if (fence && !fence->ops->signaled)
 121                         dma_fence_enable_sw_signaling(fence);
 122
 123                 placement->num_placement = 0;
 124                 placement->num_busy_placement = 0;
 125                 rcu_read_unlock();
 126                 return;
 127         }
 128         switch (bo->mem.mem_type) {
 129         case AMDGPU_PL_GDS:
 130         case AMDGPU_PL_GWS:
 131         case AMDGPU_PL_OA:
 132                 placement->num_placement = 0;
 133                 placement->num_busy_placement = 0;
 134                 return;
 135
 136         case TTM_PL_VRAM:
 137                 if (!adev->mman.buffer_funcs_enabled) {
 138                         /* Move to system memory */
 139                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 140                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 141                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 142                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 143
 144                         /* Try evicting to the CPU inaccessible part of VRAM
 145                          * first, but only set GTT as busy placement, so this
 146                          * BO will be evicted to GTT rather than causing other
 147                          * BOs to be evicted from VRAM
 148                          */
 149                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 150                                                          AMDGPU_GEM_DOMAIN_GTT);
 151                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 152                         abo->placements[0].lpfn = 0;
 153                         abo->placement.busy_placement = &abo->placements[1];
 154                         abo->placement.num_busy_placement = 1;
 155                 } else {
 156                         /* Move to GTT memory */
 157                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 158                 }
 159                 break;
 160         case TTM_PL_TT:
 161         default:
 162                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 163                 break;
 164         }
 165         *placement = abo->placement;
 166 }
 167
 168 /**
 169  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 170  * @bo: buffer object to map
 171  * @mem: memory object to map
 172  * @mm_cur: range to map
 173  * @num_pages: number of pages to map
 174  * @window: which GART window to use
 175  * @ring: DMA ring to use for the copy
 176  * @tmz: if we should setup a TMZ enabled mapping
 177  * @addr: resulting address inside the MC address space
 178  *
 179  * Setup one of the GART windows to access a specific piece of memory or return
 180  * the physical address for local memory.
 181  */
 182 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 183                                  struct ttm_resource *mem,
 184                                  struct amdgpu_res_cursor *mm_cur,
 185                                  unsigned num_pages, unsigned window,
 186                                  struct amdgpu_ring *ring, bool tmz,
 187                                  uint64_t *addr)
 188 {
 189         struct amdgpu_device *adev = ring->adev;
 190         struct amdgpu_job *job;
 191         unsigned num_dw, num_bytes;
 192         struct dma_fence *fence;
 193         uint64_t src_addr, dst_addr;
 194         void *cpu_addr;
 195         uint64_t flags;
 196         unsigned int i;
 197         int r;
 198
 199         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 200                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 201
 202         /* Map only what can't be accessed directly */
 203         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 204                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 205                         mm_cur->start;
 206                 return 0;
 207         }
 208
 209         *addr = adev->gmc.gart_start;
 210         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 211                 AMDGPU_GPU_PAGE_SIZE;
 212         *addr += mm_cur->start & ~PAGE_MASK;
 213
 214         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 215         num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 216
 217         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 218                                      AMDGPU_IB_POOL_DELAYED, &job);
 219         if (r)
 220                 return r;
 221
 222         src_addr = num_dw * 4;
 223         src_addr += job->ibs[0].gpu_addr;
 224
 225         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 226         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 227         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 228                                 dst_addr, num_bytes, false);
 229
 230         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 231         WARN_ON(job->ibs[0].length_dw > num_dw);
 232
 233         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 234         if (tmz)
 235                 flags |= AMDGPU_PTE_TMZ;
 236
 237         cpu_addr = &job->ibs[0].ptr[num_dw];
 238
 239         if (mem->mem_type == TTM_PL_TT) {
 240                 dma_addr_t *dma_addr;
 241
 242                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 243                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 244                                     cpu_addr);
 245                 if (r)
 246                         goto error_free;
 247         } else {
 248                 dma_addr_t dma_address;
 249
 250                 dma_address = mm_cur->start;
 251                 dma_address += adev->vm_manager.vram_base_offset;
 252
 253                 for (i = 0; i < num_pages; ++i) {
 254                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 255                                             &dma_address, flags, cpu_addr);
 256                         if (r)
 257                                 goto error_free;
 258
 259                         dma_address += PAGE_SIZE;
 260                 }
 261         }
 262
 263         r = amdgpu_job_submit(job, &adev->mman.entity,
 264                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 265         if (r)
 266                 goto error_free;
 267
 268         dma_fence_put(fence);
 269
 270         return r;
 271
 272 error_free:
 273         amdgpu_job_free(job);
 274         return r;
 275 }
 276
 277 /**
 278  * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 279  * @adev: amdgpu device
 280  * @src: buffer/address where to read from
 281  * @dst: buffer/address where to write to
 282  * @size: number of bytes to copy
 283  * @tmz: if a secure copy should be used
 284  * @resv: resv object to sync to
 285  * @f: Returns the last fence if multiple jobs are submitted.
 286  *
 287  * The function copies @size bytes from {src->mem + src->offset} to
 288  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 289  * move and different for a BO to BO copy.
 290  *
 291  */
 292 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 293                                const struct amdgpu_copy_mem *src,
 294                                const struct amdgpu_copy_mem *dst,
 295                                uint64_t size, bool tmz,
 296                                struct dma_resv *resv,
 297                                struct dma_fence **f)
 298 {
 299         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 300                                         AMDGPU_GPU_PAGE_SIZE);
 301
 302         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 303         struct amdgpu_res_cursor src_mm, dst_mm;
 304         struct dma_fence *fence = NULL;
 305         int r = 0;
 306
 307         if (!adev->mman.buffer_funcs_enabled) {
 308                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 309                 return -EINVAL;
 310         }
 311
 312         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 313         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 314
 315         mutex_lock(&adev->mman.gtt_window_lock);
 316         while (src_mm.remaining) {
 317                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 318                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 319                 struct dma_fence *next;
 320                 uint32_t cur_size;
 321                 uint64_t from, to;
 322
 323                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 324                  * begins at an offset, then adjust the size accordingly
 325                  */
 326                 cur_size = max(src_page_offset, dst_page_offset);
 327                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 328                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 329
 330                 /* Map src to window 0 and dst to window 1. */
 331                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 332                                           PFN_UP(cur_size + src_page_offset),
 333                                           0, ring, tmz, &from);
 334                 if (r)
 335                         goto error;
 336
 337                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 338                                           PFN_UP(cur_size + dst_page_offset),
 339                                           1, ring, tmz, &to);
 340                 if (r)
 341                         goto error;
 342
 343                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 344                                        resv, &next, false, true, tmz);
 345                 if (r)
 346                         goto error;
 347
 348                 dma_fence_put(fence);
 349                 fence = next;
 350
 351                 amdgpu_res_next(&src_mm, cur_size);
 352                 amdgpu_res_next(&dst_mm, cur_size);
 353         }
 354 error:
 355         mutex_unlock(&adev->mman.gtt_window_lock);
 356         if (f)
 357                 *f = dma_fence_get(fence);
 358         dma_fence_put(fence);
 359         return r;
 360 }
 361
 362 /*
 363  * amdgpu_move_blit - Copy an entire buffer to another buffer
 364  *
 365  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 366  * help move buffers to and from VRAM.
 367  */
 368 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 369                             bool evict,
 370                             struct ttm_resource *new_mem,
 371                             struct ttm_resource *old_mem)
 372 {
 373         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 374         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 375         struct amdgpu_copy_mem src, dst;
 376         struct dma_fence *fence = NULL;
 377         int r;
 378
 379         src.bo = bo;
 380         dst.bo = bo;
 381         src.mem = old_mem;
 382         dst.mem = new_mem;
 383         src.offset = 0;
 384         dst.offset = 0;
 385
 386         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 387                                        new_mem->num_pages << PAGE_SHIFT,
 388                                        amdgpu_bo_encrypted(abo),
 389                                        bo->base.resv, &fence);
 390         if (r)
 391                 goto error;
 392
 393         /* clear the space being freed */
 394         if (old_mem->mem_type == TTM_PL_VRAM &&
 395             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 396                 struct dma_fence *wipe_fence = NULL;
 397
 398                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 399                                        NULL, &wipe_fence);
 400                 if (r) {
 401                         goto error;
 402                 } else if (wipe_fence) {
 403                         dma_fence_put(fence);
 404                         fence = wipe_fence;
 405                 }
 406         }
 407
 408         /* Always block for VM page tables before committing the new location */
 409         if (bo->type == ttm_bo_type_kernel)
 410                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 411         else
 412                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 413         dma_fence_put(fence);
 414         return r;
 415
 416 error:
 417         if (fence)
 418                 dma_fence_wait(fence, false);
 419         dma_fence_put(fence);
 420         return r;
 421 }
 422
 423 /*
 424  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 425  *
 426  * Called by amdgpu_bo_move()
 427  */
 428 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 429                                struct ttm_resource *mem)
 430 {
 431         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 432         struct amdgpu_res_cursor cursor;
 433
 434         if (mem->mem_type == TTM_PL_SYSTEM ||
 435             mem->mem_type == TTM_PL_TT)
 436                 return true;
 437         if (mem->mem_type != TTM_PL_VRAM)
 438                 return false;
 439
 440         amdgpu_res_first(mem, 0, mem_size, &cursor);
 441
 442         /* ttm_resource_ioremap only supports contiguous memory */
 443         if (cursor.size != mem_size)
 444                 return false;
 445
 446         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 447 }
 448
 449 /*
 450  * amdgpu_bo_move - Move a buffer object to a new memory location
 451  *
 452  * Called by ttm_bo_handle_move_mem()
 453  */
 454 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 455                           struct ttm_operation_ctx *ctx,
 456                           struct ttm_resource *new_mem,
 457                           struct ttm_place *hop)
 458 {
 459         struct amdgpu_device *adev;
 460         struct amdgpu_bo *abo;
 461         struct ttm_resource *old_mem = &bo->mem;
 462         int r;
 463
 464         if (new_mem->mem_type == TTM_PL_TT) {
 465                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 466                 if (r)
 467                         return r;
 468         }
 469
 470         /* Can't move a pinned BO */
 471         abo = ttm_to_amdgpu_bo(bo);
 472         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 473                 return -EINVAL;
 474
 475         adev = amdgpu_ttm_adev(bo->bdev);
 476
 477         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 478                 ttm_bo_move_null(bo, new_mem);
 479                 goto out;
 480         }
 481         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 482             new_mem->mem_type == TTM_PL_TT) {
 483                 ttm_bo_move_null(bo, new_mem);
 484                 goto out;
 485         }
 486         if (old_mem->mem_type == TTM_PL_TT &&
 487             new_mem->mem_type == TTM_PL_SYSTEM) {
 488                 r = ttm_bo_wait_ctx(bo, ctx);
 489                 if (r)
 490                         return r;
 491
 492                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 493                 ttm_resource_free(bo, &bo->mem);
 494                 ttm_bo_assign_mem(bo, new_mem);
 495                 goto out;
 496         }
 497
 498         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 499             old_mem->mem_type == AMDGPU_PL_GWS ||
 500             old_mem->mem_type == AMDGPU_PL_OA ||
 501             new_mem->mem_type == AMDGPU_PL_GDS ||
 502             new_mem->mem_type == AMDGPU_PL_GWS ||
 503             new_mem->mem_type == AMDGPU_PL_OA) {
 504                 /* Nothing to save here */
 505                 ttm_bo_move_null(bo, new_mem);
 506                 goto out;
 507         }
 508
 509         if (adev->mman.buffer_funcs_enabled) {
 510                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 511                       new_mem->mem_type == TTM_PL_VRAM) ||
 512                      (old_mem->mem_type == TTM_PL_VRAM &&
 513                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 514                         hop->fpfn = 0;
 515                         hop->lpfn = 0;
 516                         hop->mem_type = TTM_PL_TT;
 517                         hop->flags = 0;
 518                         return -EMULTIHOP;
 519                 }
 520
 521                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 522         } else {
 523                 r = -ENODEV;
 524         }
 525
 526         if (r) {
 527                 /* Check that all memory is CPU accessible */
 528                 if (!amdgpu_mem_visible(adev, old_mem) ||
 529                     !amdgpu_mem_visible(adev, new_mem)) {
 530                         pr_err("Move buffer fallback to memcpy unavailable\n");
 531                         return r;
 532                 }
 533
 534                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 535                 if (r)
 536                         return r;
 537         }
 538
 539         if (bo->type == ttm_bo_type_device &&
 540             new_mem->mem_type == TTM_PL_VRAM &&
 541             old_mem->mem_type != TTM_PL_VRAM) {
 542                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 543                  * accesses the BO after it's moved.
 544                  */
 545                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 546         }
 547
 548 out:
 549         /* update statistics */
 550         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 551         amdgpu_bo_move_notify(bo, evict, new_mem);
 552         return 0;
 553 }
 554
 555 /*
 556  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 557  *
 558  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 559  */
 560 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 561                                      struct ttm_resource *mem)
 562 {
 563         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 564         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 565
 566         switch (mem->mem_type) {
 567         case TTM_PL_SYSTEM:
 568                 /* system memory */
 569                 return 0;
 570         case TTM_PL_TT:
 571                 break;
 572         case TTM_PL_VRAM:
 573                 mem->bus.offset = mem->start << PAGE_SHIFT;
 574                 /* check if it's visible */
 575                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 576                         return -EINVAL;
 577
 578                 if (adev->mman.aper_base_kaddr &&
 579                     mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 580                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 581                                         mem->bus.offset;
 582
 583                 mem->bus.offset += adev->gmc.aper_base;
 584                 mem->bus.is_iomem = true;
 585                 if (adev->gmc.xgmi.connected_to_cpu)
 586                         mem->bus.caching = ttm_cached;
 587                 else
 588                         mem->bus.caching = ttm_write_combined;
 589                 break;
 590         default:
 591                 return -EINVAL;
 592         }
 593         return 0;
 594 }
 595
 596 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 597                                            unsigned long page_offset)
 598 {
 599         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 600         struct amdgpu_res_cursor cursor;
 601
 602         amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
 603         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 604 }
 605
 606 /**
 607  * amdgpu_ttm_domain_start - Returns GPU start address
 608  * @adev: amdgpu device object
 609  * @type: type of the memory
 610  *
 611  * Returns:
 612  * GPU start address of a memory domain
 613  */
 614
 615 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 616 {
 617         switch (type) {
 618         case TTM_PL_TT:
 619                 return adev->gmc.gart_start;
 620         case TTM_PL_VRAM:
 621                 return adev->gmc.vram_start;
 622         }
 623
 624         return 0;
 625 }
 626
 627 /*
 628  * TTM backend functions.
 629  */
 630 struct amdgpu_ttm_tt {
 631         struct ttm_tt   ttm;
 632         struct drm_gem_object   *gobj;
 633         u64                     offset;
 634         uint64_t                userptr;
 635         struct task_struct      *usertask;
 636         uint32_t                userflags;
 637         bool                    bound;
 638 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 639         struct hmm_range        *range;
 640 #endif
 641 };
 642
 643 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 644 /*
 645  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 646  * memory and start HMM tracking CPU page table update
 647  *
 648  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 649  * once afterwards to stop HMM tracking
 650  */
 651 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 652 {
 653         struct ttm_tt *ttm = bo->tbo.ttm;
 654         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 655         unsigned long start = gtt->userptr;
 656         struct vm_area_struct *vma;
 657         struct mm_struct *mm;
 658         bool readonly;
 659         int r = 0;
 660
 661         mm = bo->notifier.mm;
 662         if (unlikely(!mm)) {
 663                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 664                 return -EFAULT;
 665         }
 666
 667         /* Another get_user_pages is running at the same time?? */
 668         if (WARN_ON(gtt->range))
 669                 return -EFAULT;
 670
 671         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 672                 return -ESRCH;
 673
 674         mmap_read_lock(mm);
 675         vma = find_vma(mm, start);
 676         mmap_read_unlock(mm);
 677         if (unlikely(!vma || start < vma->vm_start)) {
 678                 r = -EFAULT;
 679                 goto out_putmm;
 680         }
 681         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 682                 vma->vm_file)) {
 683                 r = -EPERM;
 684                 goto out_putmm;
 685         }
 686
 687         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 688         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 689                                        ttm->num_pages, &gtt->range, readonly,
 690                                        false);
 691 out_putmm:
 692         mmput(mm);
 693
 694         return r;
 695 }
 696
 697 /*
 698  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 699  * Check if the pages backing this ttm range have been invalidated
 700  *
 701  * Returns: true if pages are still valid
 702  */
 703 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 704 {
 705         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 706         bool r = false;
 707
 708         if (!gtt || !gtt->userptr)
 709                 return false;
 710
 711         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 712                 gtt->userptr, ttm->num_pages);
 713
 714         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 715                 "No user pages to check\n");
 716
 717         if (gtt->range) {
 718                 /*
 719                  * FIXME: Must always hold notifier_lock for this, and must
 720                  * not ignore the return code.
 721                  */
 722                 r = amdgpu_hmm_range_get_pages_done(gtt->range);
 723                 gtt->range = NULL;
 724         }
 725
 726         return !r;
 727 }
 728 #endif
 729
 730 /*
 731  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 732  *
 733  * Called by amdgpu_cs_list_validate(). This creates the page list
 734  * that backs user memory and will ultimately be mapped into the device
 735  * address space.
 736  */
 737 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 738 {
 739         unsigned long i;
 740
 741         for (i = 0; i < ttm->num_pages; ++i)
 742                 ttm->pages[i] = pages ? pages[i] : NULL;
 743 }
 744
 745 /*
 746  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 747  *
 748  * Called by amdgpu_ttm_backend_bind()
 749  **/
 750 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 751                                      struct ttm_tt *ttm)
 752 {
 753         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 754         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 755         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 756         enum dma_data_direction direction = write ?
 757                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 758         int r;
 759
 760         /* Allocate an SG array and squash pages into it */
 761         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 762                                       (u64)ttm->num_pages << PAGE_SHIFT,
 763                                       GFP_KERNEL);
 764         if (r)
 765                 goto release_sg;
 766
 767         /* Map SG to device */
 768         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 769         if (r)
 770                 goto release_sg;
 771
 772         /* convert SG to linear array of pages and dma addresses */
 773         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 774                                        ttm->num_pages);
 775
 776         return 0;
 777
 778 release_sg:
 779         kfree(ttm->sg);
 780         ttm->sg = NULL;
 781         return r;
 782 }
 783
 784 /*
 785  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 786  */
 787 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 788                                         struct ttm_tt *ttm)
 789 {
 790         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 791         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 792         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 793         enum dma_data_direction direction = write ?
 794                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 795
 796         /* double check that we don't free the table twice */
 797         if (!ttm->sg || !ttm->sg->sgl)
 798                 return;
 799
 800         /* unmap the pages mapped to the device */
 801         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 802         sg_free_table(ttm->sg);
 803
 804 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 805         if (gtt->range) {
 806                 unsigned long i;
 807
 808                 for (i = 0; i < ttm->num_pages; i++) {
 809                         if (ttm->pages[i] !=
 810                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 811                                 break;
 812                 }
 813
 814                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 815         }
 816 #endif
 817 }
 818
 819 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 820                                 struct ttm_buffer_object *tbo,
 821                                 uint64_t flags)
 822 {
 823         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 824         struct ttm_tt *ttm = tbo->ttm;
 825         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 826         int r;
 827
 828         if (amdgpu_bo_encrypted(abo))
 829                 flags |= AMDGPU_PTE_TMZ;
 830
 831         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 832                 uint64_t page_idx = 1;
 833
 834                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 835                                 ttm->pages, gtt->ttm.dma_address, flags);
 836                 if (r)
 837                         goto gart_bind_fail;
 838
 839                 /* The memory type of the first page defaults to UC. Now
 840                  * modify the memory type to NC from the second page of
 841                  * the BO onward.
 842                  */
 843                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 844                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 845
 846                 r = amdgpu_gart_bind(adev,
 847                                 gtt->offset + (page_idx << PAGE_SHIFT),
 848                                 ttm->num_pages - page_idx,
 849                                 &ttm->pages[page_idx],
 850                                 &(gtt->ttm.dma_address[page_idx]), flags);
 851         } else {
 852                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 853                                      ttm->pages, gtt->ttm.dma_address, flags);
 854         }
 855
 856 gart_bind_fail:
 857         if (r)
 858                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 859                           ttm->num_pages, gtt->offset);
 860
 861         return r;
 862 }
 863
 864 /*
 865  * amdgpu_ttm_backend_bind - Bind GTT memory
 866  *
 867  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 868  * This handles binding GTT memory to the device address space.
 869  */
 870 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 871                                    struct ttm_tt *ttm,
 872                                    struct ttm_resource *bo_mem)
 873 {
 874         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 875         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 876         uint64_t flags;
 877         int r = 0;
 878
 879         if (!bo_mem)
 880                 return -EINVAL;
 881
 882         if (gtt->bound)
 883                 return 0;
 884
 885         if (gtt->userptr) {
 886                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 887                 if (r) {
 888                         DRM_ERROR("failed to pin userptr\n");
 889                         return r;
 890                 }
 891         } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
 892                 if (!ttm->sg) {
 893                         struct dma_buf_attachment *attach;
 894                         struct sg_table *sgt;
 895
 896                         attach = gtt->gobj->import_attach;
 897                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 898                         if (IS_ERR(sgt))
 899                                 return PTR_ERR(sgt);
 900
 901                         ttm->sg = sgt;
 902                 }
 903
 904                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 905                                                ttm->num_pages);
 906         }
 907
 908         if (!ttm->num_pages) {
 909                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 910                      ttm->num_pages, bo_mem, ttm);
 911         }
 912
 913         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 914             bo_mem->mem_type == AMDGPU_PL_GWS ||
 915             bo_mem->mem_type == AMDGPU_PL_OA)
 916                 return -EINVAL;
 917
 918         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 919                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 920                 return 0;
 921         }
 922
 923         /* compute PTE flags relevant to this BO memory */
 924         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 925
 926         /* bind pages into GART page tables */
 927         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 928         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 929                 ttm->pages, gtt->ttm.dma_address, flags);
 930
 931         if (r)
 932                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 933                           ttm->num_pages, gtt->offset);
 934         gtt->bound = true;
 935         return r;
 936 }
 937
 938 /*
 939  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 940  * through AGP or GART aperture.
 941  *
 942  * If bo is accessible through AGP aperture, then use AGP aperture
 943  * to access bo; otherwise allocate logical space in GART aperture
 944  * and map bo to GART aperture.
 945  */
 946 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 947 {
 948         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 949         struct ttm_operation_ctx ctx = { false, false };
 950         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 951         struct ttm_resource tmp;
 952         struct ttm_placement placement;
 953         struct ttm_place placements;
 954         uint64_t addr, flags;
 955         int r;
 956
 957         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
 958                 return 0;
 959
 960         addr = amdgpu_gmc_agp_addr(bo);
 961         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 962                 bo->mem.start = addr >> PAGE_SHIFT;
 963         } else {
 964
 965                 /* allocate GART space */
 966                 placement.num_placement = 1;
 967                 placement.placement = &placements;
 968                 placement.num_busy_placement = 1;
 969                 placement.busy_placement = &placements;
 970                 placements.fpfn = 0;
 971                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 972                 placements.mem_type = TTM_PL_TT;
 973                 placements.flags = bo->mem.placement;
 974
 975                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 976                 if (unlikely(r))
 977                         return r;
 978
 979                 /* compute PTE flags for this buffer object */
 980                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 981
 982                 /* Bind pages */
 983                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
 984                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
 985                 if (unlikely(r)) {
 986                         ttm_resource_free(bo, &tmp);
 987                         return r;
 988                 }
 989
 990                 ttm_resource_free(bo, &bo->mem);
 991                 bo->mem = tmp;
 992         }
 993
 994         return 0;
 995 }
 996
 997 /*
 998  * amdgpu_ttm_recover_gart - Rebind GTT pages
 999  *
1000  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1001  * rebind GTT pages during a GPU reset.
1002  */
1003 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1004 {
1005         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1006         uint64_t flags;
1007         int r;
1008
1009         if (!tbo->ttm)
1010                 return 0;
1011
1012         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1013         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1014
1015         return r;
1016 }
1017
1018 /*
1019  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1020  *
1021  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1022  * ttm_tt_destroy().
1023  */
1024 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1025                                       struct ttm_tt *ttm)
1026 {
1027         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1028         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1029         int r;
1030
1031         /* if the pages have userptr pinning then clear that first */
1032         if (gtt->userptr) {
1033                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1034         } else if (ttm->sg && gtt->gobj->import_attach) {
1035                 struct dma_buf_attachment *attach;
1036
1037                 attach = gtt->gobj->import_attach;
1038                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1039                 ttm->sg = NULL;
1040         }
1041
1042         if (!gtt->bound)
1043                 return;
1044
1045         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1046                 return;
1047
1048         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1049         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1050         if (r)
1051                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1052                           gtt->ttm.num_pages, gtt->offset);
1053         gtt->bound = false;
1054 }
1055
1056 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1057                                        struct ttm_tt *ttm)
1058 {
1059         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1060
1061         amdgpu_ttm_backend_unbind(bdev, ttm);
1062         ttm_tt_destroy_common(bdev, ttm);
1063         if (gtt->usertask)
1064                 put_task_struct(gtt->usertask);
1065
1066         ttm_tt_fini(&gtt->ttm);
1067         kfree(gtt);
1068 }
1069
1070 /**
1071  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1072  *
1073  * @bo: The buffer object to create a GTT ttm_tt object around
1074  * @page_flags: Page flags to be added to the ttm_tt object
1075  *
1076  * Called by ttm_tt_create().
1077  */
1078 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1079                                            uint32_t page_flags)
1080 {
1081         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1082         struct amdgpu_ttm_tt *gtt;
1083         enum ttm_caching caching;
1084
1085         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1086         if (gtt == NULL) {
1087                 return NULL;
1088         }
1089         gtt->gobj = &bo->base;
1090
1091         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1092                 caching = ttm_write_combined;
1093         else
1094                 caching = ttm_cached;
1095
1096         /* allocate space for the uninitialized page entries */
1097         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1098                 kfree(gtt);
1099                 return NULL;
1100         }
1101         return &gtt->ttm;
1102 }
1103
1104 /*
1105  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1106  *
1107  * Map the pages of a ttm_tt object to an address space visible
1108  * to the underlying device.
1109  */
1110 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1111                                   struct ttm_tt *ttm,
1112                                   struct ttm_operation_ctx *ctx)
1113 {
1114         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1115         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1116
1117         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1118         if (gtt && gtt->userptr) {
1119                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1120                 if (!ttm->sg)
1121                         return -ENOMEM;
1122
1123                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1124                 return 0;
1125         }
1126
1127         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1128                 return 0;
1129
1130         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1131 }
1132
1133 /*
1134  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1135  *
1136  * Unmaps pages of a ttm_tt object from the device address space and
1137  * unpopulates the page array backing it.
1138  */
1139 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1140                                      struct ttm_tt *ttm)
1141 {
1142         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1143         struct amdgpu_device *adev;
1144
1145         if (gtt && gtt->userptr) {
1146                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1147                 kfree(ttm->sg);
1148                 ttm->sg = NULL;
1149                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1150                 return;
1151         }
1152
1153         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1154                 return;
1155
1156         adev = amdgpu_ttm_adev(bdev);
1157         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1158 }
1159
1160 /**
1161  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1162  * task
1163  *
1164  * @bo: The ttm_buffer_object to bind this userptr to
1165  * @addr:  The address in the current tasks VM space to use
1166  * @flags: Requirements of userptr object.
1167  *
1168  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1169  * to current task
1170  */
1171 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1172                               uint64_t addr, uint32_t flags)
1173 {
1174         struct amdgpu_ttm_tt *gtt;
1175
1176         if (!bo->ttm) {
1177                 /* TODO: We want a separate TTM object type for userptrs */
1178                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1179                 if (bo->ttm == NULL)
1180                         return -ENOMEM;
1181         }
1182
1183         gtt = (void *)bo->ttm;
1184         gtt->userptr = addr;
1185         gtt->userflags = flags;
1186
1187         if (gtt->usertask)
1188                 put_task_struct(gtt->usertask);
1189         gtt->usertask = current->group_leader;
1190         get_task_struct(gtt->usertask);
1191
1192         return 0;
1193 }
1194
1195 /*
1196  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1197  */
1198 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1199 {
1200         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1201
1202         if (gtt == NULL)
1203                 return NULL;
1204
1205         if (gtt->usertask == NULL)
1206                 return NULL;
1207
1208         return gtt->usertask->mm;
1209 }
1210
1211 /*
1212  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1213  * address range for the current task.
1214  *
1215  */
1216 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1217                                   unsigned long end)
1218 {
1219         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1220         unsigned long size;
1221
1222         if (gtt == NULL || !gtt->userptr)
1223                 return false;
1224
1225         /* Return false if no part of the ttm_tt object lies within
1226          * the range
1227          */
1228         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1229         if (gtt->userptr > end || gtt->userptr + size <= start)
1230                 return false;
1231
1232         return true;
1233 }
1234
1235 /*
1236  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1237  */
1238 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1239 {
1240         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1241
1242         if (gtt == NULL || !gtt->userptr)
1243                 return false;
1244
1245         return true;
1246 }
1247
1248 /*
1249  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1250  */
1251 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1252 {
1253         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1254
1255         if (gtt == NULL)
1256                 return false;
1257
1258         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1259 }
1260
1261 /**
1262  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1263  *
1264  * @ttm: The ttm_tt object to compute the flags for
1265  * @mem: The memory registry backing this ttm_tt object
1266  *
1267  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1268  */
1269 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1270 {
1271         uint64_t flags = 0;
1272
1273         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1274                 flags |= AMDGPU_PTE_VALID;
1275
1276         if (mem && mem->mem_type == TTM_PL_TT) {
1277                 flags |= AMDGPU_PTE_SYSTEM;
1278
1279                 if (ttm->caching == ttm_cached)
1280                         flags |= AMDGPU_PTE_SNOOPED;
1281         }
1282
1283         if (mem && mem->mem_type == TTM_PL_VRAM &&
1284                         mem->bus.caching == ttm_cached)
1285                 flags |= AMDGPU_PTE_SNOOPED;
1286
1287         return flags;
1288 }
1289
1290 /**
1291  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1292  *
1293  * @adev: amdgpu_device pointer
1294  * @ttm: The ttm_tt object to compute the flags for
1295  * @mem: The memory registry backing this ttm_tt object
1296  *
1297  * Figure out the flags to use for a VM PTE (Page Table Entry).
1298  */
1299 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1300                                  struct ttm_resource *mem)
1301 {
1302         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1303
1304         flags |= adev->gart.gart_pte_flags;
1305         flags |= AMDGPU_PTE_READABLE;
1306
1307         if (!amdgpu_ttm_tt_is_readonly(ttm))
1308                 flags |= AMDGPU_PTE_WRITEABLE;
1309
1310         return flags;
1311 }
1312
1313 /*
1314  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1315  * object.
1316  *
1317  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1318  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1319  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1320  * used to clean out a memory space.
1321  */
1322 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1323                                             const struct ttm_place *place)
1324 {
1325         unsigned long num_pages = bo->mem.num_pages;
1326         struct amdgpu_res_cursor cursor;
1327         struct dma_resv_list *flist;
1328         struct dma_fence *f;
1329         int i;
1330
1331         if (bo->type == ttm_bo_type_kernel &&
1332             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1333                 return false;
1334
1335         /* If bo is a KFD BO, check if the bo belongs to the current process.
1336          * If true, then return false as any KFD process needs all its BOs to
1337          * be resident to run successfully
1338          */
1339         flist = dma_resv_get_list(bo->base.resv);
1340         if (flist) {
1341                 for (i = 0; i < flist->shared_count; ++i) {
1342                         f = rcu_dereference_protected(flist->shared[i],
1343                                 dma_resv_held(bo->base.resv));
1344                         if (amdkfd_fence_check_mm(f, current->mm))
1345                                 return false;
1346                 }
1347         }
1348
1349         switch (bo->mem.mem_type) {
1350         case TTM_PL_TT:
1351                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1352                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1353                         return false;
1354                 return true;
1355
1356         case TTM_PL_VRAM:
1357                 /* Check each drm MM node individually */
1358                 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT,
1359                                  &cursor);
1360                 while (cursor.remaining) {
1361                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1362                             && !(place->lpfn &&
1363                                  place->lpfn <= PFN_DOWN(cursor.start)))
1364                                 return true;
1365
1366                         amdgpu_res_next(&cursor, cursor.size);
1367                 }
1368                 return false;
1369
1370         default:
1371                 break;
1372         }
1373
1374         return ttm_bo_eviction_valuable(bo, place);
1375 }
1376
1377 /**
1378  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1379  *
1380  * @bo:  The buffer object to read/write
1381  * @offset:  Offset into buffer object
1382  * @buf:  Secondary buffer to write/read from
1383  * @len: Length in bytes of access
1384  * @write:  true if writing
1385  *
1386  * This is used to access VRAM that backs a buffer object via MMIO
1387  * access for debugging purposes.
1388  */
1389 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1390                                     unsigned long offset, void *buf, int len,
1391                                     int write)
1392 {
1393         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1394         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1395         struct amdgpu_res_cursor cursor;
1396         unsigned long flags;
1397         uint32_t value = 0;
1398         int ret = 0;
1399
1400         if (bo->mem.mem_type != TTM_PL_VRAM)
1401                 return -EIO;
1402
1403         amdgpu_res_first(&bo->mem, offset, len, &cursor);
1404         while (cursor.remaining) {
1405                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1406                 uint64_t bytes = 4 - (cursor.start & 3);
1407                 uint32_t shift = (cursor.start & 3) * 8;
1408                 uint32_t mask = 0xffffffff << shift;
1409
1410                 if (cursor.size < bytes) {
1411                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1412                         bytes = cursor.size;
1413                 }
1414
1415                 if (mask != 0xffffffff) {
1416                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1417                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1418                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1419                         value = RREG32_NO_KIQ(mmMM_DATA);
1420                         if (write) {
1421                                 value &= ~mask;
1422                                 value |= (*(uint32_t *)buf << shift) & mask;
1423                                 WREG32_NO_KIQ(mmMM_DATA, value);
1424                         }
1425                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1426                         if (!write) {
1427                                 value = (value & mask) >> shift;
1428                                 memcpy(buf, &value, bytes);
1429                         }
1430                 } else {
1431                         bytes = cursor.size & ~0x3ULL;
1432                         amdgpu_device_vram_access(adev, cursor.start,
1433                                                   (uint32_t *)buf, bytes,
1434                                                   write);
1435                 }
1436
1437                 ret += bytes;
1438                 buf = (uint8_t *)buf + bytes;
1439                 amdgpu_res_next(&cursor, bytes);
1440         }
1441
1442         return ret;
1443 }
1444
1445 static void
1446 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1447 {
1448         amdgpu_bo_move_notify(bo, false, NULL);
1449 }
1450
1451 static struct ttm_device_funcs amdgpu_bo_driver = {
1452         .ttm_tt_create = &amdgpu_ttm_tt_create,
1453         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1454         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1455         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1456         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1457         .evict_flags = &amdgpu_evict_flags,
1458         .move = &amdgpu_bo_move,
1459         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1460         .release_notify = &amdgpu_bo_release_notify,
1461         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1462         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1463         .access_memory = &amdgpu_ttm_access_memory,
1464         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1465 };
1466
1467 /*
1468  * Firmware Reservation functions
1469  */
1470 /**
1471  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1472  *
1473  * @adev: amdgpu_device pointer
1474  *
1475  * free fw reserved vram if it has been reserved.
1476  */
1477 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1478 {
1479         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1480                 NULL, &adev->mman.fw_vram_usage_va);
1481 }
1482
1483 /**
1484  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1485  *
1486  * @adev: amdgpu_device pointer
1487  *
1488  * create bo vram reservation from fw.
1489  */
1490 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1491 {
1492         uint64_t vram_size = adev->gmc.visible_vram_size;
1493
1494         adev->mman.fw_vram_usage_va = NULL;
1495         adev->mman.fw_vram_usage_reserved_bo = NULL;
1496
1497         if (adev->mman.fw_vram_usage_size == 0 ||
1498             adev->mman.fw_vram_usage_size > vram_size)
1499                 return 0;
1500
1501         return amdgpu_bo_create_kernel_at(adev,
1502                                           adev->mman.fw_vram_usage_start_offset,
1503                                           adev->mman.fw_vram_usage_size,
1504                                           AMDGPU_GEM_DOMAIN_VRAM,
1505                                           &adev->mman.fw_vram_usage_reserved_bo,
1506                                           &adev->mman.fw_vram_usage_va);
1507 }
1508
1509 /*
1510  * Memoy training reservation functions
1511  */
1512
1513 /**
1514  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1515  *
1516  * @adev: amdgpu_device pointer
1517  *
1518  * free memory training reserved vram if it has been reserved.
1519  */
1520 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1521 {
1522         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1523
1524         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1525         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1526         ctx->c2p_bo = NULL;
1527
1528         return 0;
1529 }
1530
1531 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1532 {
1533         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1534
1535         memset(ctx, 0, sizeof(*ctx));
1536
1537         ctx->c2p_train_data_offset =
1538                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1539         ctx->p2c_train_data_offset =
1540                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1541         ctx->train_data_size =
1542                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1543
1544         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1545                         ctx->train_data_size,
1546                         ctx->p2c_train_data_offset,
1547                         ctx->c2p_train_data_offset);
1548 }
1549
1550 /*
1551  * reserve TMR memory at the top of VRAM which holds
1552  * IP Discovery data and is protected by PSP.
1553  */
1554 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1555 {
1556         int ret;
1557         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1558         bool mem_train_support = false;
1559
1560         if (!amdgpu_sriov_vf(adev)) {
1561                 if (amdgpu_atomfirmware_mem_training_supported(adev))
1562                         mem_train_support = true;
1563                 else
1564                         DRM_DEBUG("memory training does not support!\n");
1565         }
1566
1567         /*
1568          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1569          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1570          *
1571          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1572          * discovery data and G6 memory training data respectively
1573          */
1574         adev->mman.discovery_tmr_size =
1575                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1576         if (!adev->mman.discovery_tmr_size)
1577                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1578
1579         if (mem_train_support) {
1580                 /* reserve vram for mem train according to TMR location */
1581                 amdgpu_ttm_training_data_block_init(adev);
1582                 ret = amdgpu_bo_create_kernel_at(adev,
1583                                          ctx->c2p_train_data_offset,
1584                                          ctx->train_data_size,
1585                                          AMDGPU_GEM_DOMAIN_VRAM,
1586                                          &ctx->c2p_bo,
1587                                          NULL);
1588                 if (ret) {
1589                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1590                         amdgpu_ttm_training_reserve_vram_fini(adev);
1591                         return ret;
1592                 }
1593                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1594         }
1595
1596         ret = amdgpu_bo_create_kernel_at(adev,
1597                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1598                                 adev->mman.discovery_tmr_size,
1599                                 AMDGPU_GEM_DOMAIN_VRAM,
1600                                 &adev->mman.discovery_memory,
1601                                 NULL);
1602         if (ret) {
1603                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1604                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1605                 return ret;
1606         }
1607
1608         return 0;
1609 }
1610
1611 /*
1612  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1613  * gtt/vram related fields.
1614  *
1615  * This initializes all of the memory space pools that the TTM layer
1616  * will need such as the GTT space (system memory mapped to the device),
1617  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1618  * can be mapped per VMID.
1619  */
1620 int amdgpu_ttm_init(struct amdgpu_device *adev)
1621 {
1622         uint64_t gtt_size;
1623         int r;
1624         u64 vis_vram_limit;
1625
1626         mutex_init(&adev->mman.gtt_window_lock);
1627
1628         /* No others user of address space so set it to 0 */
1629         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1630                                adev_to_drm(adev)->anon_inode->i_mapping,
1631                                adev_to_drm(adev)->vma_offset_manager,
1632                                adev->need_swiotlb,
1633                                dma_addressing_limited(adev->dev));
1634         if (r) {
1635                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1636                 return r;
1637         }
1638         adev->mman.initialized = true;
1639
1640         /* Initialize VRAM pool with all of VRAM divided into pages */
1641         r = amdgpu_vram_mgr_init(adev);
1642         if (r) {
1643                 DRM_ERROR("Failed initializing VRAM heap.\n");
1644                 return r;
1645         }
1646
1647         /* Reduce size of CPU-visible VRAM if requested */
1648         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1649         if (amdgpu_vis_vram_limit > 0 &&
1650             vis_vram_limit <= adev->gmc.visible_vram_size)
1651                 adev->gmc.visible_vram_size = vis_vram_limit;
1652
1653         /* Change the size here instead of the init above so only lpfn is affected */
1654         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1655 #ifdef CONFIG_64BIT
1656 #ifdef CONFIG_X86
1657         if (adev->gmc.xgmi.connected_to_cpu)
1658                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1659                                 adev->gmc.visible_vram_size);
1660
1661         else
1662 #endif
1663                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1664                                 adev->gmc.visible_vram_size);
1665 #endif
1666
1667         /*
1668          *The reserved vram for firmware must be pinned to the specified
1669          *place on the VRAM, so reserve it early.
1670          */
1671         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1672         if (r) {
1673                 return r;
1674         }
1675
1676         /*
1677          * only NAVI10 and onwards ASIC support for IP discovery.
1678          * If IP discovery enabled, a block of memory should be
1679          * reserved for IP discovey.
1680          */
1681         if (adev->mman.discovery_bin) {
1682                 r = amdgpu_ttm_reserve_tmr(adev);
1683                 if (r)
1684                         return r;
1685         }
1686
1687         /* allocate memory as required for VGA
1688          * This is used for VGA emulation and pre-OS scanout buffers to
1689          * avoid display artifacts while transitioning between pre-OS
1690          * and driver.  */
1691         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1692                                        AMDGPU_GEM_DOMAIN_VRAM,
1693                                        &adev->mman.stolen_vga_memory,
1694                                        NULL);
1695         if (r)
1696                 return r;
1697         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1698                                        adev->mman.stolen_extended_size,
1699                                        AMDGPU_GEM_DOMAIN_VRAM,
1700                                        &adev->mman.stolen_extended_memory,
1701                                        NULL);
1702         if (r)
1703                 return r;
1704
1705         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1706                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1707
1708         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1709          * or whatever the user passed on module init */
1710         if (amdgpu_gtt_size == -1) {
1711                 struct sysinfo si;
1712
1713                 si_meminfo(&si);
1714                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1715                                adev->gmc.mc_vram_size),
1716                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1717         }
1718         else
1719                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1720
1721         /* Initialize GTT memory pool */
1722         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1723         if (r) {
1724                 DRM_ERROR("Failed initializing GTT heap.\n");
1725                 return r;
1726         }
1727         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1728                  (unsigned)(gtt_size / (1024 * 1024)));
1729
1730         /* Initialize various on-chip memory pools */
1731         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1732         if (r) {
1733                 DRM_ERROR("Failed initializing GDS heap.\n");
1734                 return r;
1735         }
1736
1737         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1738         if (r) {
1739                 DRM_ERROR("Failed initializing gws heap.\n");
1740                 return r;
1741         }
1742
1743         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1744         if (r) {
1745                 DRM_ERROR("Failed initializing oa heap.\n");
1746                 return r;
1747         }
1748
1749         return 0;
1750 }
1751
1752 /*
1753  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1754  */
1755 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1756 {
1757         if (!adev->mman.initialized)
1758                 return;
1759
1760         amdgpu_ttm_training_reserve_vram_fini(adev);
1761         /* return the stolen vga memory back to VRAM */
1762         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1763         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1764         /* return the IP Discovery TMR memory back to VRAM */
1765         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1766         amdgpu_ttm_fw_reserve_vram_fini(adev);
1767
1768         amdgpu_vram_mgr_fini(adev);
1769         amdgpu_gtt_mgr_fini(adev);
1770         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1771         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1772         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1773         ttm_device_fini(&adev->mman.bdev);
1774         adev->mman.initialized = false;
1775         DRM_INFO("amdgpu: ttm finalized\n");
1776 }
1777
1778 /**
1779  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1780  *
1781  * @adev: amdgpu_device pointer
1782  * @enable: true when we can use buffer functions.
1783  *
1784  * Enable/disable use of buffer functions during suspend/resume. This should
1785  * only be called at bootup or when userspace isn't running.
1786  */
1787 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1788 {
1789         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1790         uint64_t size;
1791         int r;
1792
1793         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1794             adev->mman.buffer_funcs_enabled == enable)
1795                 return;
1796
1797         if (enable) {
1798                 struct amdgpu_ring *ring;
1799                 struct drm_gpu_scheduler *sched;
1800
1801                 ring = adev->mman.buffer_funcs_ring;
1802                 sched = &ring->sched;
1803                 r = drm_sched_entity_init(&adev->mman.entity,
1804                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1805                                           1, NULL);
1806                 if (r) {
1807                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1808                                   r);
1809                         return;
1810                 }
1811         } else {
1812                 drm_sched_entity_destroy(&adev->mman.entity);
1813                 dma_fence_put(man->move);
1814                 man->move = NULL;
1815         }
1816
1817         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1818         if (enable)
1819                 size = adev->gmc.real_vram_size;
1820         else
1821                 size = adev->gmc.visible_vram_size;
1822         man->size = size >> PAGE_SHIFT;
1823         adev->mman.buffer_funcs_enabled = enable;
1824 }
1825
1826 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1827                        uint64_t dst_offset, uint32_t byte_count,
1828                        struct dma_resv *resv,
1829                        struct dma_fence **fence, bool direct_submit,
1830                        bool vm_needs_flush, bool tmz)
1831 {
1832         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1833                 AMDGPU_IB_POOL_DELAYED;
1834         struct amdgpu_device *adev = ring->adev;
1835         struct amdgpu_job *job;
1836
1837         uint32_t max_bytes;
1838         unsigned num_loops, num_dw;
1839         unsigned i;
1840         int r;
1841
1842         if (direct_submit && !ring->sched.ready) {
1843                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1844                 return -EINVAL;
1845         }
1846
1847         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1848         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1849         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1850
1851         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1852         if (r)
1853                 return r;
1854
1855         if (vm_needs_flush) {
1856                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1857                                         adev->gmc.pdb0_bo : adev->gart.bo);
1858                 job->vm_needs_flush = true;
1859         }
1860         if (resv) {
1861                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1862                                      AMDGPU_SYNC_ALWAYS,
1863                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1864                 if (r) {
1865                         DRM_ERROR("sync failed (%d).\n", r);
1866                         goto error_free;
1867                 }
1868         }
1869
1870         for (i = 0; i < num_loops; i++) {
1871                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1872
1873                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1874                                         dst_offset, cur_size_in_bytes, tmz);
1875
1876                 src_offset += cur_size_in_bytes;
1877                 dst_offset += cur_size_in_bytes;
1878                 byte_count -= cur_size_in_bytes;
1879         }
1880
1881         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1882         WARN_ON(job->ibs[0].length_dw > num_dw);
1883         if (direct_submit)
1884                 r = amdgpu_job_submit_direct(job, ring, fence);
1885         else
1886                 r = amdgpu_job_submit(job, &adev->mman.entity,
1887                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1888         if (r)
1889                 goto error_free;
1890
1891         return r;
1892
1893 error_free:
1894         amdgpu_job_free(job);
1895         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1896         return r;
1897 }
1898
1899 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1900                        uint32_t src_data,
1901                        struct dma_resv *resv,
1902                        struct dma_fence **fence)
1903 {
1904         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1905         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1906         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1907
1908         struct amdgpu_res_cursor cursor;
1909         unsigned int num_loops, num_dw;
1910         uint64_t num_bytes;
1911
1912         struct amdgpu_job *job;
1913         int r;
1914
1915         if (!adev->mman.buffer_funcs_enabled) {
1916                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1917                 return -EINVAL;
1918         }
1919
1920         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1921                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1922                 if (r)
1923                         return r;
1924         }
1925
1926         num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT;
1927         num_loops = 0;
1928
1929         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
1930         while (cursor.remaining) {
1931                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
1932                 amdgpu_res_next(&cursor, cursor.size);
1933         }
1934         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1935
1936         /* for IB padding */
1937         num_dw += 64;
1938
1939         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1940                                      &job);
1941         if (r)
1942                 return r;
1943
1944         if (resv) {
1945                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1946                                      AMDGPU_SYNC_ALWAYS,
1947                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1948                 if (r) {
1949                         DRM_ERROR("sync failed (%d).\n", r);
1950                         goto error_free;
1951                 }
1952         }
1953
1954         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
1955         while (cursor.remaining) {
1956                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
1957                 uint64_t dst_addr = cursor.start;
1958
1959                 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
1960                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
1961                                         cur_size);
1962
1963                 amdgpu_res_next(&cursor, cur_size);
1964         }
1965
1966         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1967         WARN_ON(job->ibs[0].length_dw > num_dw);
1968         r = amdgpu_job_submit(job, &adev->mman.entity,
1969                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1970         if (r)
1971                 goto error_free;
1972
1973         return 0;
1974
1975 error_free:
1976         amdgpu_job_free(job);
1977         return r;
1978 }
1979
1980 #if defined(CONFIG_DEBUG_FS)
1981
1982 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
1983 {
1984         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1985         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
1986                                                             TTM_PL_VRAM);
1987         struct drm_printer p = drm_seq_file_printer(m);
1988
1989         man->func->debug(man, &p);
1990         return 0;
1991 }
1992
1993 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
1994 {
1995         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1996
1997         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
1998 }
1999
2000 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2001 {
2002         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2003         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2004                                                             TTM_PL_TT);
2005         struct drm_printer p = drm_seq_file_printer(m);
2006
2007         man->func->debug(man, &p);
2008         return 0;
2009 }
2010
2011 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2012 {
2013         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2014         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2015                                                             AMDGPU_PL_GDS);
2016         struct drm_printer p = drm_seq_file_printer(m);
2017
2018         man->func->debug(man, &p);
2019         return 0;
2020 }
2021
2022 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2023 {
2024         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2025         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2026                                                             AMDGPU_PL_GWS);
2027         struct drm_printer p = drm_seq_file_printer(m);
2028
2029         man->func->debug(man, &p);
2030         return 0;
2031 }
2032
2033 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2034 {
2035         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2036         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2037                                                             AMDGPU_PL_OA);
2038         struct drm_printer p = drm_seq_file_printer(m);
2039
2040         man->func->debug(man, &p);
2041         return 0;
2042 }
2043
2044 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2045 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2046 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2047 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2048 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2049 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2050
2051 /*
2052  * amdgpu_ttm_vram_read - Linear read access to VRAM
2053  *
2054  * Accesses VRAM via MMIO for debugging purposes.
2055  */
2056 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2057                                     size_t size, loff_t *pos)
2058 {
2059         struct amdgpu_device *adev = file_inode(f)->i_private;
2060         ssize_t result = 0;
2061
2062         if (size & 0x3 || *pos & 0x3)
2063                 return -EINVAL;
2064
2065         if (*pos >= adev->gmc.mc_vram_size)
2066                 return -ENXIO;
2067
2068         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2069         while (size) {
2070                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2071                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2072
2073                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2074                 if (copy_to_user(buf, value, bytes))
2075                         return -EFAULT;
2076
2077                 result += bytes;
2078                 buf += bytes;
2079                 *pos += bytes;
2080                 size -= bytes;
2081         }
2082
2083         return result;
2084 }
2085
2086 /*
2087  * amdgpu_ttm_vram_write - Linear write access to VRAM
2088  *
2089  * Accesses VRAM via MMIO for debugging purposes.
2090  */
2091 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2092                                     size_t size, loff_t *pos)
2093 {
2094         struct amdgpu_device *adev = file_inode(f)->i_private;
2095         ssize_t result = 0;
2096         int r;
2097
2098         if (size & 0x3 || *pos & 0x3)
2099                 return -EINVAL;
2100
2101         if (*pos >= adev->gmc.mc_vram_size)
2102                 return -ENXIO;
2103
2104         while (size) {
2105                 unsigned long flags;
2106                 uint32_t value;
2107
2108                 if (*pos >= adev->gmc.mc_vram_size)
2109                         return result;
2110
2111                 r = get_user(value, (uint32_t *)buf);
2112                 if (r)
2113                         return r;
2114
2115                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2116                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2117                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2118                 WREG32_NO_KIQ(mmMM_DATA, value);
2119                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2120
2121                 result += 4;
2122                 buf += 4;
2123                 *pos += 4;
2124                 size -= 4;
2125         }
2126
2127         return result;
2128 }
2129
2130 static const struct file_operations amdgpu_ttm_vram_fops = {
2131         .owner = THIS_MODULE,
2132         .read = amdgpu_ttm_vram_read,
2133         .write = amdgpu_ttm_vram_write,
2134         .llseek = default_llseek,
2135 };
2136
2137 /*
2138  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2139  *
2140  * This function is used to read memory that has been mapped to the
2141  * GPU and the known addresses are not physical addresses but instead
2142  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2143  */
2144 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2145                                  size_t size, loff_t *pos)
2146 {
2147         struct amdgpu_device *adev = file_inode(f)->i_private;
2148         struct iommu_domain *dom;
2149         ssize_t result = 0;
2150         int r;
2151
2152         /* retrieve the IOMMU domain if any for this device */
2153         dom = iommu_get_domain_for_dev(adev->dev);
2154
2155         while (size) {
2156                 phys_addr_t addr = *pos & PAGE_MASK;
2157                 loff_t off = *pos & ~PAGE_MASK;
2158                 size_t bytes = PAGE_SIZE - off;
2159                 unsigned long pfn;
2160                 struct page *p;
2161                 void *ptr;
2162
2163                 bytes = bytes < size ? bytes : size;
2164
2165                 /* Translate the bus address to a physical address.  If
2166                  * the domain is NULL it means there is no IOMMU active
2167                  * and the address translation is the identity
2168                  */
2169                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2170
2171                 pfn = addr >> PAGE_SHIFT;
2172                 if (!pfn_valid(pfn))
2173                         return -EPERM;
2174
2175                 p = pfn_to_page(pfn);
2176                 if (p->mapping != adev->mman.bdev.dev_mapping)
2177                         return -EPERM;
2178
2179                 ptr = kmap(p);
2180                 r = copy_to_user(buf, ptr + off, bytes);
2181                 kunmap(p);
2182                 if (r)
2183                         return -EFAULT;
2184
2185                 size -= bytes;
2186                 *pos += bytes;
2187                 result += bytes;
2188         }
2189
2190         return result;
2191 }
2192
2193 /*
2194  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2195  *
2196  * This function is used to write memory that has been mapped to the
2197  * GPU and the known addresses are not physical addresses but instead
2198  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2199  */
2200 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2201                                  size_t size, loff_t *pos)
2202 {
2203         struct amdgpu_device *adev = file_inode(f)->i_private;
2204         struct iommu_domain *dom;
2205         ssize_t result = 0;
2206         int r;
2207
2208         dom = iommu_get_domain_for_dev(adev->dev);
2209
2210         while (size) {
2211                 phys_addr_t addr = *pos & PAGE_MASK;
2212                 loff_t off = *pos & ~PAGE_MASK;
2213                 size_t bytes = PAGE_SIZE - off;
2214                 unsigned long pfn;
2215                 struct page *p;
2216                 void *ptr;
2217
2218                 bytes = bytes < size ? bytes : size;
2219
2220                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2221
2222                 pfn = addr >> PAGE_SHIFT;
2223                 if (!pfn_valid(pfn))
2224                         return -EPERM;
2225
2226                 p = pfn_to_page(pfn);
2227                 if (p->mapping != adev->mman.bdev.dev_mapping)
2228                         return -EPERM;
2229
2230                 ptr = kmap(p);
2231                 r = copy_from_user(ptr + off, buf, bytes);
2232                 kunmap(p);
2233                 if (r)
2234                         return -EFAULT;
2235
2236                 size -= bytes;
2237                 *pos += bytes;
2238                 result += bytes;
2239         }
2240
2241         return result;
2242 }
2243
2244 static const struct file_operations amdgpu_ttm_iomem_fops = {
2245         .owner = THIS_MODULE,
2246         .read = amdgpu_iomem_read,
2247         .write = amdgpu_iomem_write,
2248         .llseek = default_llseek
2249 };
2250
2251 #endif
2252
2253 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2254 {
2255 #if defined(CONFIG_DEBUG_FS)
2256         struct drm_minor *minor = adev_to_drm(adev)->primary;
2257         struct dentry *root = minor->debugfs_root;
2258
2259         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2260                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2261         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2262                             &amdgpu_ttm_iomem_fops);
2263         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2264                             &amdgpu_mm_vram_table_fops);
2265         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2266                             &amdgpu_mm_tt_table_fops);
2267         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2268                             &amdgpu_mm_gds_table_fops);
2269         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2270                             &amdgpu_mm_gws_table_fops);
2271         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2272                             &amdgpu_mm_oa_table_fops);
2273         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2274                             &amdgpu_ttm_page_pool_fops);
2275 #endif
2276 }