drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "ta_ras_if.h"
  32 #include "amdgpu_ras_eeprom.h"
  33
  34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  35 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET         (0x1 << 1)
  36
  37 enum amdgpu_ras_block {
  38         AMDGPU_RAS_BLOCK__UMC = 0,
  39         AMDGPU_RAS_BLOCK__SDMA,
  40         AMDGPU_RAS_BLOCK__GFX,
  41         AMDGPU_RAS_BLOCK__MMHUB,
  42         AMDGPU_RAS_BLOCK__ATHUB,
  43         AMDGPU_RAS_BLOCK__PCIE_BIF,
  44         AMDGPU_RAS_BLOCK__HDP,
  45         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  46         AMDGPU_RAS_BLOCK__DF,
  47         AMDGPU_RAS_BLOCK__SMN,
  48         AMDGPU_RAS_BLOCK__SEM,
  49         AMDGPU_RAS_BLOCK__MP0,
  50         AMDGPU_RAS_BLOCK__MP1,
  51         AMDGPU_RAS_BLOCK__FUSE,
  52
  53         AMDGPU_RAS_BLOCK__LAST
  54 };
  55
  56 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
  57 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
  58
  59 enum amdgpu_ras_gfx_subblock {
  60         /* CPC */
  61         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
  62         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
  63                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
  64         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
  65         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
  66         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
  67         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
  68         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
  69         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
  70         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  71         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
  72                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  73         /* CPF */
  74         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  75         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
  76                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  77         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
  78         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  79         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  80         /* CPG */
  81         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  82         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
  83                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  84         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
  85         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  86         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  87         /* GDS */
  88         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  89         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  90         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
  91         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
  92         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
  93         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
  94         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
  95                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
  96         /* SPI */
  97         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
  98         /* SQ */
  99         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 100         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 101         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 102         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 103         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 104         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 105         /* SQC (3 ranges) */
 106         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 107         /* SQC range 0 */
 108         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 109                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 110         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 111                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 112         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 113         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 114         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 115         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 116         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 117         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 118         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 119                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 120         /* SQC range 1 */
 121         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 122         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 123                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 124         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 125         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 126         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 127         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 128         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 129         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 130         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 131         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 132         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 133                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 134         /* SQC range 2 */
 135         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 136         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 137                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 138         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 139         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 140         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 141         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 142         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 143         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 144         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 145         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 146         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 147                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 148         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 149                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 150         /* TA */
 151         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 152         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 153                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 154         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 155         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 156         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 157         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 158         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 159         /* TCA */
 160         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 161         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 162                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 163         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 164         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 165                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 166         /* TCC (5 sub-ranges) */
 167         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 168         /* TCC range 0 */
 169         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 170                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 171         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 172                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 173         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 174         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 175         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 176         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 177         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 178         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 179         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 180         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 181                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 182         /* TCC range 1 */
 183         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 184         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 185                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 186         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 187         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 188                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 189         /* TCC range 2 */
 190         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 191         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 192                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 193         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 194         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 195         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 196         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 197         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 198         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 199         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 200         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 201                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 202         /* TCC range 3 */
 203         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 204         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 205                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 206         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 207         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 208                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 209         /* TCC range 4 */
 210         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 211         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 212                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 213         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 214         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 215                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 216         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 217                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 218         /* TCI */
 219         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 220         /* TCP */
 221         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 222         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 223                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 224         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 225         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 226         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 227         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 228         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 229         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 230         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 231                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 232         /* TD */
 233         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 234         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 235                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 236         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 237         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 238         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 239         /* EA (3 sub-ranges) */
 240         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 241         /* EA range 0 */
 242         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 243                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 244         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 245                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 246         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 247         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 248         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 249         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 250         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 251         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 252         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 253         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 254                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 255         /* EA range 1 */
 256         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 257         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 258                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 259         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 260         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 261         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 262         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 263         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 264         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 265         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 266                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 267         /* EA range 2 */
 268         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 269         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 270                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 271         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 272         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 273         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 274         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 275                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 276         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 277                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 278         /* UTC VM L2 bank */
 279         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 280         /* UTC VM walker */
 281         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 282         /* UTC ATC L2 2MB cache */
 283         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 284         /* UTC ATC L2 4KB cache */
 285         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 286         AMDGPU_RAS_BLOCK__GFX_MAX
 287 };
 288
 289 enum amdgpu_ras_error_type {
 290         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 291         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 292         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 293         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 294         AMDGPU_RAS_ERROR__POISON                                                = 8,
 295 };
 296
 297 enum amdgpu_ras_ret {
 298         AMDGPU_RAS_SUCCESS = 0,
 299         AMDGPU_RAS_FAIL,
 300         AMDGPU_RAS_UE,
 301         AMDGPU_RAS_CE,
 302         AMDGPU_RAS_PT,
 303 };
 304
 305 struct ras_common_if {
 306         enum amdgpu_ras_block block;
 307         enum amdgpu_ras_error_type type;
 308         uint32_t sub_block_index;
 309         /* block name */
 310         char name[32];
 311 };
 312
 313 struct amdgpu_ras {
 314         /* ras infrastructure */
 315         /* for ras itself. */
 316         uint32_t features;
 317         struct list_head head;
 318         /* sysfs */
 319         struct device_attribute features_attr;
 320         struct bin_attribute badpages_attr;
 321         /* block array */
 322         struct ras_manager *objs;
 323
 324         /* gpu recovery */
 325         struct work_struct recovery_work;
 326         atomic_t in_recovery;
 327         struct amdgpu_device *adev;
 328         /* error handler data */
 329         struct ras_err_handler_data *eh_data;
 330         struct mutex recovery_lock;
 331
 332         uint32_t flags;
 333         bool reboot;
 334         struct amdgpu_ras_eeprom_control eeprom_control;
 335
 336         bool error_query_ready;
 337
 338         /* bad page count threshold */
 339         uint32_t bad_page_cnt_threshold;
 340
 341         /* disable ras error count harvest in recovery */
 342         bool disable_ras_err_cnt_harvest;
 343
 344         /* RAS count errors delayed work */
 345         struct delayed_work ras_counte_delay_work;
 346         atomic_t ras_ue_count;
 347         atomic_t ras_ce_count;
 348 };
 349
 350 struct ras_fs_data {
 351         char sysfs_name[32];
 352         char debugfs_name[32];
 353 };
 354
 355 struct ras_err_data {
 356         unsigned long ue_count;
 357         unsigned long ce_count;
 358         unsigned long err_addr_cnt;
 359         struct eeprom_table_record *err_addr;
 360 };
 361
 362 struct ras_err_handler_data {
 363         /* point to bad page records array */
 364         struct eeprom_table_record *bps;
 365         /* the count of entries */
 366         int count;
 367         /* the space can place new entries */
 368         int space_left;
 369 };
 370
 371 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 372                 void *err_data,
 373                 struct amdgpu_iv_entry *entry);
 374
 375 struct ras_ih_data {
 376         /* interrupt bottom half */
 377         struct work_struct ih_work;
 378         int inuse;
 379         /* IP callback */
 380         ras_ih_cb cb;
 381         /* full of entries */
 382         unsigned char *ring;
 383         unsigned int ring_size;
 384         unsigned int element_size;
 385         unsigned int aligned_element_size;
 386         unsigned int rptr;
 387         unsigned int wptr;
 388 };
 389
 390 struct ras_manager {
 391         struct ras_common_if head;
 392         /* reference count */
 393         int use;
 394         /* ras block link */
 395         struct list_head node;
 396         /* the device */
 397         struct amdgpu_device *adev;
 398         /* sysfs */
 399         struct device_attribute sysfs_attr;
 400         int attr_inuse;
 401
 402         /* fs node name */
 403         struct ras_fs_data fs_data;
 404
 405         /* IH data */
 406         struct ras_ih_data ih_data;
 407
 408         struct ras_err_data err_data;
 409 };
 410
 411 struct ras_badpage {
 412         unsigned int bp;
 413         unsigned int size;
 414         unsigned int flags;
 415 };
 416
 417 /* interfaces for IP */
 418 struct ras_fs_if {
 419         struct ras_common_if head;
 420         char sysfs_name[32];
 421         char debugfs_name[32];
 422 };
 423
 424 struct ras_query_if {
 425         struct ras_common_if head;
 426         unsigned long ue_count;
 427         unsigned long ce_count;
 428 };
 429
 430 struct ras_inject_if {
 431         struct ras_common_if head;
 432         uint64_t address;
 433         uint64_t value;
 434 };
 435
 436 struct ras_cure_if {
 437         struct ras_common_if head;
 438         uint64_t address;
 439 };
 440
 441 struct ras_ih_if {
 442         struct ras_common_if head;
 443         ras_ih_cb cb;
 444 };
 445
 446 struct ras_dispatch_if {
 447         struct ras_common_if head;
 448         struct amdgpu_iv_entry *entry;
 449 };
 450
 451 struct ras_debug_if {
 452         union {
 453                 struct ras_common_if head;
 454                 struct ras_inject_if inject;
 455         };
 456         int op;
 457 };
 458 /* work flow
 459  * vbios
 460  * 1: ras feature enable (enabled by default)
 461  * psp
 462  * 2: ras framework init (in ip_init)
 463  * IP
 464  * 3: IH add
 465  * 4: debugfs/sysfs create
 466  * 5: query/inject
 467  * 6: debugfs/sysfs remove
 468  * 7: IH remove
 469  * 8: feature disable
 470  */
 471
 472 #define amdgpu_ras_get_context(adev)            ((adev)->psp.ras.ras)
 473 #define amdgpu_ras_set_context(adev, ras_con)   ((adev)->psp.ras.ras = (ras_con))
 474
 475 /* check if ras is supported on block, say, sdma, gfx */
 476 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
 477                 unsigned int block)
 478 {
 479         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 480
 481         if (block >= AMDGPU_RAS_BLOCK_COUNT)
 482                 return 0;
 483         return ras && (adev->ras_enabled & (1 << block));
 484 }
 485
 486 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 487 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
 488                 unsigned int block);
 489
 490 void amdgpu_ras_resume(struct amdgpu_device *adev);
 491 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 492
 493 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 494                                  unsigned long *ce_count,
 495                                  unsigned long *ue_count);
 496
 497 /* error handling functions */
 498 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 499                 struct eeprom_table_record *bps, int pages);
 500
 501 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
 502
 503 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
 504 {
 505         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 506
 507         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
 508                 schedule_work(&ras->recovery_work);
 509         return 0;
 510 }
 511
 512 static inline enum ta_ras_block
 513 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 514         switch (block) {
 515         case AMDGPU_RAS_BLOCK__UMC:
 516                 return TA_RAS_BLOCK__UMC;
 517         case AMDGPU_RAS_BLOCK__SDMA:
 518                 return TA_RAS_BLOCK__SDMA;
 519         case AMDGPU_RAS_BLOCK__GFX:
 520                 return TA_RAS_BLOCK__GFX;
 521         case AMDGPU_RAS_BLOCK__MMHUB:
 522                 return TA_RAS_BLOCK__MMHUB;
 523         case AMDGPU_RAS_BLOCK__ATHUB:
 524                 return TA_RAS_BLOCK__ATHUB;
 525         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 526                 return TA_RAS_BLOCK__PCIE_BIF;
 527         case AMDGPU_RAS_BLOCK__HDP:
 528                 return TA_RAS_BLOCK__HDP;
 529         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 530                 return TA_RAS_BLOCK__XGMI_WAFL;
 531         case AMDGPU_RAS_BLOCK__DF:
 532                 return TA_RAS_BLOCK__DF;
 533         case AMDGPU_RAS_BLOCK__SMN:
 534                 return TA_RAS_BLOCK__SMN;
 535         case AMDGPU_RAS_BLOCK__SEM:
 536                 return TA_RAS_BLOCK__SEM;
 537         case AMDGPU_RAS_BLOCK__MP0:
 538                 return TA_RAS_BLOCK__MP0;
 539         case AMDGPU_RAS_BLOCK__MP1:
 540                 return TA_RAS_BLOCK__MP1;
 541         case AMDGPU_RAS_BLOCK__FUSE:
 542                 return TA_RAS_BLOCK__FUSE;
 543         default:
 544                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 545                 return TA_RAS_BLOCK__UMC;
 546         }
 547 }
 548
 549 static inline enum ta_ras_error_type
 550 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 551         switch (error) {
 552         case AMDGPU_RAS_ERROR__NONE:
 553                 return TA_RAS_ERROR__NONE;
 554         case AMDGPU_RAS_ERROR__PARITY:
 555                 return TA_RAS_ERROR__PARITY;
 556         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 557                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 558         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 559                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 560         case AMDGPU_RAS_ERROR__POISON:
 561                 return TA_RAS_ERROR__POISON;
 562         default:
 563                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 564                 return TA_RAS_ERROR__NONE;
 565         }
 566 }
 567
 568 /* called in ip_init and ip_fini */
 569 int amdgpu_ras_init(struct amdgpu_device *adev);
 570 int amdgpu_ras_fini(struct amdgpu_device *adev);
 571 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 572 int amdgpu_ras_late_init(struct amdgpu_device *adev,
 573                          struct ras_common_if *ras_block,
 574                          struct ras_fs_if *fs_info,
 575                          struct ras_ih_if *ih_info);
 576 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
 577                           struct ras_common_if *ras_block,
 578                           struct ras_ih_if *ih_info);
 579
 580 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 581                 struct ras_common_if *head, bool enable);
 582
 583 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 584                 struct ras_common_if *head, bool enable);
 585
 586 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 587                 struct ras_fs_if *head);
 588
 589 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 590                 struct ras_common_if *head);
 591
 592 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 593
 594 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 595                 struct ras_query_if *info);
 596
 597 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 598                 enum amdgpu_ras_block block);
 599
 600 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 601                 struct ras_inject_if *info);
 602
 603 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 604                 struct ras_ih_if *info);
 605
 606 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 607                 struct ras_ih_if *info);
 608
 609 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 610                 struct ras_dispatch_if *info);
 611
 612 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 613                 struct ras_common_if *head);
 614
 615 extern atomic_t amdgpu_ras_in_intr;
 616
 617 static inline bool amdgpu_ras_intr_triggered(void)
 618 {
 619         return !!atomic_read(&amdgpu_ras_in_intr);
 620 }
 621
 622 static inline void amdgpu_ras_intr_cleared(void)
 623 {
 624         atomic_set(&amdgpu_ras_in_intr, 0);
 625 }
 626
 627 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 628
 629 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 630
 631 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 632
 633 void amdgpu_release_ras_context(struct amdgpu_device *adev);
 634
 635 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
 636
 637 #endif