drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 103 {
 104         struct ras_err_data err_data = {0, 0, 0, NULL};
 105         struct eeprom_table_record err_rec;
 106
 107         if ((address >= adev->gmc.mc_vram_size) ||
 108             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 109                 dev_warn(adev->dev,
 110                          "RAS WARN: input address 0x%llx is invalid.\n",
 111                          address);
 112                 return -EINVAL;
 113         }
 114
 115         if (amdgpu_ras_check_bad_page(adev, address)) {
 116                 dev_warn(adev->dev,
 117                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 118                          address);
 119                 return 0;
 120         }
 121
 122         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 123
 124         err_rec.address = address;
 125         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 126         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 127         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 128
 129         err_data.err_addr = &err_rec;
 130         err_data.err_addr_cnt = 1;
 131
 132         if (amdgpu_bad_page_threshold != 0) {
 133                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 134                                          err_data.err_addr_cnt);
 135                 amdgpu_ras_save_bad_pages(adev);
 136         }
 137
 138         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 139         dev_warn(adev->dev, "Clear EEPROM:\n");
 140         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 141
 142         return 0;
 143 }
 144
 145 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 146                                         size_t size, loff_t *pos)
 147 {
 148         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 149         struct ras_query_if info = {
 150                 .head = obj->head,
 151         };
 152         ssize_t s;
 153         char val[128];
 154
 155         if (amdgpu_ras_query_error_status(obj->adev, &info))
 156                 return -EINVAL;
 157
 158         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 159                         "ue", info.ue_count,
 160                         "ce", info.ce_count);
 161         if (*pos >= s)
 162                 return 0;
 163
 164         s -= *pos;
 165         s = min_t(u64, s, size);
 166
 167
 168         if (copy_to_user(buf, &val[*pos], s))
 169                 return -EINVAL;
 170
 171         *pos += s;
 172
 173         return s;
 174 }
 175
 176 static const struct file_operations amdgpu_ras_debugfs_ops = {
 177         .owner = THIS_MODULE,
 178         .read = amdgpu_ras_debugfs_read,
 179         .write = NULL,
 180         .llseek = default_llseek
 181 };
 182
 183 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 184 {
 185         int i;
 186
 187         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 188                 *block_id = i;
 189                 if (strcmp(name, ras_block_str(i)) == 0)
 190                         return 0;
 191         }
 192         return -EINVAL;
 193 }
 194
 195 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 196                 const char __user *buf, size_t size,
 197                 loff_t *pos, struct ras_debug_if *data)
 198 {
 199         ssize_t s = min_t(u64, 64, size);
 200         char str[65];
 201         char block_name[33];
 202         char err[9] = "ue";
 203         int op = -1;
 204         int block_id;
 205         uint32_t sub_block;
 206         u64 address, value;
 207
 208         if (*pos)
 209                 return -EINVAL;
 210         *pos = size;
 211
 212         memset(str, 0, sizeof(str));
 213         memset(data, 0, sizeof(*data));
 214
 215         if (copy_from_user(str, buf, s))
 216                 return -EINVAL;
 217
 218         if (sscanf(str, "disable %32s", block_name) == 1)
 219                 op = 0;
 220         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 221                 op = 1;
 222         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 223                 op = 2;
 224         else if (strstr(str, "retire_page") != NULL)
 225                 op = 3;
 226         else if (str[0] && str[1] && str[2] && str[3])
 227                 /* ascii string, but commands are not matched. */
 228                 return -EINVAL;
 229
 230         if (op != -1) {
 231                 if (op == 3) {
 232                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 233                             sscanf(str, "%*s %llu", &address) != 1)
 234                                 return -EINVAL;
 235
 236                         data->op = op;
 237                         data->inject.address = address;
 238
 239                         return 0;
 240                 }
 241
 242                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 243                         return -EINVAL;
 244
 245                 data->head.block = block_id;
 246                 /* only ue and ce errors are supported */
 247                 if (!memcmp("ue", err, 2))
 248                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 249                 else if (!memcmp("ce", err, 2))
 250                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 251                 else
 252                         return -EINVAL;
 253
 254                 data->op = op;
 255
 256                 if (op == 2) {
 257                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 258                                    &sub_block, &address, &value) != 3 &&
 259                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 260                                    &sub_block, &address, &value) != 3)
 261                                 return -EINVAL;
 262                         data->head.sub_block_index = sub_block;
 263                         data->inject.address = address;
 264                         data->inject.value = value;
 265                 }
 266         } else {
 267                 if (size < sizeof(*data))
 268                         return -EINVAL;
 269
 270                 if (copy_from_user(data, buf, sizeof(*data)))
 271                         return -EINVAL;
 272         }
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * DOC: AMDGPU RAS debugfs control interface
 279  *
 280  * The control interface accepts struct ras_debug_if which has two members.
 281  *
 282  * First member: ras_debug_if::head or ras_debug_if::inject.
 283  *
 284  * head is used to indicate which IP block will be under control.
 285  *
 286  * head has four members, they are block, type, sub_block_index, name.
 287  * block: which IP will be under control.
 288  * type: what kind of error will be enabled/disabled/injected.
 289  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 290  * name: the name of IP.
 291  *
 292  * inject has two more members than head, they are address, value.
 293  * As their names indicate, inject operation will write the
 294  * value to the address.
 295  *
 296  * The second member: struct ras_debug_if::op.
 297  * It has three kinds of operations.
 298  *
 299  * - 0: disable RAS on the block. Take ::head as its data.
 300  * - 1: enable RAS on the block. Take ::head as its data.
 301  * - 2: inject errors on the block. Take ::inject as its data.
 302  *
 303  * How to use the interface?
 304  *
 305  * In a program
 306  *
 307  * Copy the struct ras_debug_if in your code and initialize it.
 308  * Write the struct to the control interface.
 309  *
 310  * From shell
 311  *
 312  * .. code-block:: bash
 313  *
 314  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 315  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 316  *      echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 317  *
 318  * Where N, is the card which you want to affect.
 319  *
 320  * "disable" requires only the block.
 321  * "enable" requires the block and error type.
 322  * "inject" requires the block, error type, address, and value.
 323  * The block is one of: umc, sdma, gfx, etc.
 324  *      see ras_block_string[] for details
 325  * The error type is one of: ue, ce, where,
 326  *      ue is multi-uncorrectable
 327  *      ce is single-correctable
 328  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 329  * The address and value are hexadecimal numbers, leading 0x is optional.
 330  *
 331  * For instance,
 332  *
 333  * .. code-block:: bash
 334  *
 335  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 336  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 337  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 338  *
 339  * How to check the result of the operation?
 340  *
 341  * To check disable/enable, see "ras" features at,
 342  * /sys/class/drm/card[0/1/2...]/device/ras/features
 343  *
 344  * To check inject, see the corresponding error count at,
 345  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 346  *
 347  * .. note::
 348  *      Operations are only allowed on blocks which are supported.
 349  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 350  *      to see which blocks support RAS on a particular asic.
 351  *
 352  */
 353 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 354                 size_t size, loff_t *pos)
 355 {
 356         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 357         struct ras_debug_if data;
 358         int ret = 0;
 359
 360         if (!amdgpu_ras_get_error_query_ready(adev)) {
 361                 dev_warn(adev->dev, "RAS WARN: error injection "
 362                                 "currently inaccessible\n");
 363                 return size;
 364         }
 365
 366         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 367         if (ret)
 368                 return -EINVAL;
 369
 370         if (data.op == 3) {
 371                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 372                 if (!ret)
 373                         return size;
 374                 else
 375                         return ret;
 376         }
 377
 378         if (!amdgpu_ras_is_supported(adev, data.head.block))
 379                 return -EINVAL;
 380
 381         switch (data.op) {
 382         case 0:
 383                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 384                 break;
 385         case 1:
 386                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 387                 break;
 388         case 2:
 389                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 390                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 391                         dev_warn(adev->dev, "RAS WARN: input address "
 392                                         "0x%llx is invalid.",
 393                                         data.inject.address);
 394                         ret = -EINVAL;
 395                         break;
 396                 }
 397
 398                 /* umc ce/ue error injection for a bad page is not allowed */
 399                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 400                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 401                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 402                                         "as bad before error injection!\n",
 403                                         data.inject.address);
 404                         break;
 405                 }
 406
 407                 /* data.inject.address is offset instead of absolute gpu address */
 408                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 409                 break;
 410         default:
 411                 ret = -EINVAL;
 412                 break;
 413         }
 414
 415         if (ret)
 416                 return -EINVAL;
 417
 418         return size;
 419 }
 420
 421 /**
 422  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 423  *
 424  * Some boards contain an EEPROM which is used to persistently store a list of
 425  * bad pages which experiences ECC errors in vram.  This interface provides
 426  * a way to reset the EEPROM, e.g., after testing error injection.
 427  *
 428  * Usage:
 429  *
 430  * .. code-block:: bash
 431  *
 432  *      echo 1 > ../ras/ras_eeprom_reset
 433  *
 434  * will reset EEPROM table to 0 entries.
 435  *
 436  */
 437 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 438                 size_t size, loff_t *pos)
 439 {
 440         struct amdgpu_device *adev =
 441                 (struct amdgpu_device *)file_inode(f)->i_private;
 442         int ret;
 443
 444         ret = amdgpu_ras_eeprom_reset_table(
 445                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 446
 447         if (ret == 1) {
 448                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 449                 return size;
 450         } else {
 451                 return -EIO;
 452         }
 453 }
 454
 455 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 456         .owner = THIS_MODULE,
 457         .read = NULL,
 458         .write = amdgpu_ras_debugfs_ctrl_write,
 459         .llseek = default_llseek
 460 };
 461
 462 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 463         .owner = THIS_MODULE,
 464         .read = NULL,
 465         .write = amdgpu_ras_debugfs_eeprom_write,
 466         .llseek = default_llseek
 467 };
 468
 469 /**
 470  * DOC: AMDGPU RAS sysfs Error Count Interface
 471  *
 472  * It allows the user to read the error count for each IP block on the gpu through
 473  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 474  *
 475  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 476  * (ce) error counts.
 477  *
 478  * The format of one line is below,
 479  *
 480  * [ce|ue]: count
 481  *
 482  * Example:
 483  *
 484  * .. code-block:: bash
 485  *
 486  *      ue: 0
 487  *      ce: 1
 488  *
 489  */
 490 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 491                 struct device_attribute *attr, char *buf)
 492 {
 493         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 494         struct ras_query_if info = {
 495                 .head = obj->head,
 496         };
 497
 498         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 499                 return sysfs_emit(buf, "Query currently inaccessible\n");
 500
 501         if (amdgpu_ras_query_error_status(obj->adev, &info))
 502                 return -EINVAL;
 503
 504
 505         if (obj->adev->asic_type == CHIP_ALDEBARAN) {
 506                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 507                         DRM_WARN("Failed to reset error counter and error status");
 508         }
 509
 510         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 511                           "ce", info.ce_count);
 512 }
 513
 514 /* obj begin */
 515
 516 #define get_obj(obj) do { (obj)->use++; } while (0)
 517 #define alive_obj(obj) ((obj)->use)
 518
 519 static inline void put_obj(struct ras_manager *obj)
 520 {
 521         if (obj && (--obj->use == 0))
 522                 list_del(&obj->node);
 523         if (obj && (obj->use < 0))
 524                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 525 }
 526
 527 /* make one obj and return it. */
 528 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 529                 struct ras_common_if *head)
 530 {
 531         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 532         struct ras_manager *obj;
 533
 534         if (!adev->ras_features || !con)
 535                 return NULL;
 536
 537         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 538                 return NULL;
 539
 540         obj = &con->objs[head->block];
 541         /* already exist. return obj? */
 542         if (alive_obj(obj))
 543                 return NULL;
 544
 545         obj->head = *head;
 546         obj->adev = adev;
 547         list_add(&obj->node, &con->head);
 548         get_obj(obj);
 549
 550         return obj;
 551 }
 552
 553 /* return an obj equal to head, or the first when head is NULL */
 554 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 555                 struct ras_common_if *head)
 556 {
 557         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 558         struct ras_manager *obj;
 559         int i;
 560
 561         if (!adev->ras_features || !con)
 562                 return NULL;
 563
 564         if (head) {
 565                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 566                         return NULL;
 567
 568                 obj = &con->objs[head->block];
 569
 570                 if (alive_obj(obj)) {
 571                         WARN_ON(head->block != obj->head.block);
 572                         return obj;
 573                 }
 574         } else {
 575                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 576                         obj = &con->objs[i];
 577                         if (alive_obj(obj)) {
 578                                 WARN_ON(i != obj->head.block);
 579                                 return obj;
 580                         }
 581                 }
 582         }
 583
 584         return NULL;
 585 }
 586 /* obj end */
 587
 588 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 589                                          const char* invoke_type,
 590                                          const char* block_name,
 591                                          enum ta_ras_status ret)
 592 {
 593         switch (ret) {
 594         case TA_RAS_STATUS__SUCCESS:
 595                 return;
 596         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 597                 dev_warn(adev->dev,
 598                         "RAS WARN: %s %s currently unavailable\n",
 599                         invoke_type,
 600                         block_name);
 601                 break;
 602         default:
 603                 dev_err(adev->dev,
 604                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 605                         invoke_type,
 606                         block_name,
 607                         ret);
 608         }
 609 }
 610
 611 /* feature ctl begin */
 612 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 613                 struct ras_common_if *head)
 614 {
 615         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 616
 617         return con->hw_supported & BIT(head->block);
 618 }
 619
 620 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 621                 struct ras_common_if *head)
 622 {
 623         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 624
 625         return con->features & BIT(head->block);
 626 }
 627
 628 /*
 629  * if obj is not created, then create one.
 630  * set feature enable flag.
 631  */
 632 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 633                 struct ras_common_if *head, int enable)
 634 {
 635         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 636         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 637
 638         /* If hardware does not support ras, then do not create obj.
 639          * But if hardware support ras, we can create the obj.
 640          * Ras framework checks con->hw_supported to see if it need do
 641          * corresponding initialization.
 642          * IP checks con->support to see if it need disable ras.
 643          */
 644         if (!amdgpu_ras_is_feature_allowed(adev, head))
 645                 return 0;
 646         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 647                 return 0;
 648
 649         if (enable) {
 650                 if (!obj) {
 651                         obj = amdgpu_ras_create_obj(adev, head);
 652                         if (!obj)
 653                                 return -EINVAL;
 654                 } else {
 655                         /* In case we create obj somewhere else */
 656                         get_obj(obj);
 657                 }
 658                 con->features |= BIT(head->block);
 659         } else {
 660                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 661                         /* skip clean gfx ras context feature for VEGA20 Gaming.
 662                          * will clean later
 663                          */
 664                         if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)))
 665                                 con->features &= ~BIT(head->block);
 666                         put_obj(obj);
 667                 }
 668         }
 669
 670         return 0;
 671 }
 672
 673 /* wrapper of psp_ras_enable_features */
 674 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 675                 struct ras_common_if *head, bool enable)
 676 {
 677         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 678         union ta_ras_cmd_input *info;
 679         int ret;
 680
 681         if (!con)
 682                 return -EINVAL;
 683
 684         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 685         if (!info)
 686                 return -ENOMEM;
 687
 688         if (!enable) {
 689                 info->disable_features = (struct ta_ras_disable_features_input) {
 690                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 691                         .error_type = amdgpu_ras_error_to_ta(head->type),
 692                 };
 693         } else {
 694                 info->enable_features = (struct ta_ras_enable_features_input) {
 695                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 696                         .error_type = amdgpu_ras_error_to_ta(head->type),
 697                 };
 698         }
 699
 700         /* Do not enable if it is not allowed. */
 701         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 702         /* Are we alerady in that state we are going to set? */
 703         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 704                 ret = 0;
 705                 goto out;
 706         }
 707
 708         if (!amdgpu_ras_intr_triggered()) {
 709                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 710                 if (ret) {
 711                         amdgpu_ras_parse_status_code(adev,
 712                                                      enable ? "enable":"disable",
 713                                                      ras_block_str(head->block),
 714                                                     (enum ta_ras_status)ret);
 715                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 716                                 ret = -EAGAIN;
 717                         else
 718                                 ret = -EINVAL;
 719
 720                         goto out;
 721                 }
 722         }
 723
 724         /* setup the obj */
 725         __amdgpu_ras_feature_enable(adev, head, enable);
 726         ret = 0;
 727 out:
 728         kfree(info);
 729         return ret;
 730 }
 731
 732 /* Only used in device probe stage and called only once. */
 733 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 734                 struct ras_common_if *head, bool enable)
 735 {
 736         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 737         int ret;
 738
 739         if (!con)
 740                 return -EINVAL;
 741
 742         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 743                 if (enable) {
 744                         /* There is no harm to issue a ras TA cmd regardless of
 745                          * the currecnt ras state.
 746                          * If current state == target state, it will do nothing
 747                          * But sometimes it requests driver to reset and repost
 748                          * with error code -EAGAIN.
 749                          */
 750                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 751                         /* With old ras TA, we might fail to enable ras.
 752                          * Log it and just setup the object.
 753                          * TODO need remove this WA in the future.
 754                          */
 755                         if (ret == -EINVAL) {
 756                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 757                                 if (!ret)
 758                                         dev_info(adev->dev,
 759                                                 "RAS INFO: %s setup object\n",
 760                                                 ras_block_str(head->block));
 761                         }
 762                 } else {
 763                         /* setup the object then issue a ras TA disable cmd.*/
 764                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 765                         if (ret)
 766                                 return ret;
 767
 768                         /* gfx block ras dsiable cmd must send to ras-ta */
 769                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 770                                 con->features |= BIT(head->block);
 771
 772                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 773                 }
 774         } else
 775                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 776
 777         return ret;
 778 }
 779
 780 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 781                 bool bypass)
 782 {
 783         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 784         struct ras_manager *obj, *tmp;
 785
 786         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 787                 /* bypass psp.
 788                  * aka just release the obj and corresponding flags
 789                  */
 790                 if (bypass) {
 791                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 792                                 break;
 793                 } else {
 794                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 795                                 break;
 796                 }
 797         }
 798
 799         return con->features;
 800 }
 801
 802 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 803                 bool bypass)
 804 {
 805         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 806         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 807         int i;
 808         const enum amdgpu_ras_error_type default_ras_type =
 809                 AMDGPU_RAS_ERROR__NONE;
 810
 811         for (i = 0; i < ras_block_count; i++) {
 812                 struct ras_common_if head = {
 813                         .block = i,
 814                         .type = default_ras_type,
 815                         .sub_block_index = 0,
 816                 };
 817                 strcpy(head.name, ras_block_str(i));
 818                 if (bypass) {
 819                         /*
 820                          * bypass psp. vbios enable ras for us.
 821                          * so just create the obj
 822                          */
 823                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 824                                 break;
 825                 } else {
 826                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 827                                 break;
 828                 }
 829         }
 830
 831         return con->features;
 832 }
 833 /* feature ctl end */
 834
 835 /* query/inject/cure begin */
 836 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 837         struct ras_query_if *info)
 838 {
 839         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 840         struct ras_err_data err_data = {0, 0, 0, NULL};
 841         int i;
 842
 843         if (!obj)
 844                 return -EINVAL;
 845
 846         switch (info->head.block) {
 847         case AMDGPU_RAS_BLOCK__UMC:
 848                 if (adev->umc.ras_funcs &&
 849                     adev->umc.ras_funcs->query_ras_error_count)
 850                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 851                 /* umc query_ras_error_address is also responsible for clearing
 852                  * error status
 853                  */
 854                 if (adev->umc.ras_funcs &&
 855                     adev->umc.ras_funcs->query_ras_error_address)
 856                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 857                 break;
 858         case AMDGPU_RAS_BLOCK__SDMA:
 859                 if (adev->sdma.funcs->query_ras_error_count) {
 860                         for (i = 0; i < adev->sdma.num_instances; i++)
 861                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 862                                                                         &err_data);
 863                 }
 864                 break;
 865         case AMDGPU_RAS_BLOCK__GFX:
 866                 if (adev->gfx.ras_funcs &&
 867                     adev->gfx.ras_funcs->query_ras_error_count)
 868                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 869
 870                 if (adev->gfx.ras_funcs &&
 871                     adev->gfx.ras_funcs->query_ras_error_status)
 872                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 873                 break;
 874         case AMDGPU_RAS_BLOCK__MMHUB:
 875                 if (adev->mmhub.ras_funcs &&
 876                     adev->mmhub.ras_funcs->query_ras_error_count)
 877                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 878
 879                 if (adev->mmhub.ras_funcs &&
 880                     adev->mmhub.ras_funcs->query_ras_error_status)
 881                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 882                 break;
 883         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 884                 if (adev->nbio.ras_funcs &&
 885                     adev->nbio.ras_funcs->query_ras_error_count)
 886                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 887                 break;
 888         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 889                 if (adev->gmc.xgmi.ras_funcs &&
 890                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 891                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 892                 break;
 893         default:
 894                 break;
 895         }
 896
 897         obj->err_data.ue_count += err_data.ue_count;
 898         obj->err_data.ce_count += err_data.ce_count;
 899
 900         info->ue_count = obj->err_data.ue_count;
 901         info->ce_count = obj->err_data.ce_count;
 902
 903         if (err_data.ce_count) {
 904                 dev_info(adev->dev, "%ld correctable hardware errors "
 905                                         "detected in %s block, no user "
 906                                         "action is needed.\n",
 907                                         obj->err_data.ce_count,
 908                                         ras_block_str(info->head.block));
 909         }
 910         if (err_data.ue_count) {
 911                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 912                                         "detected in %s block\n",
 913                                         obj->err_data.ue_count,
 914                                         ras_block_str(info->head.block));
 915         }
 916
 917         return 0;
 918 }
 919
 920 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 921                 enum amdgpu_ras_block block)
 922 {
 923         if (!amdgpu_ras_is_supported(adev, block))
 924                 return -EINVAL;
 925
 926         switch (block) {
 927         case AMDGPU_RAS_BLOCK__GFX:
 928                 if (adev->gfx.ras_funcs &&
 929                     adev->gfx.ras_funcs->reset_ras_error_count)
 930                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
 931
 932                 if (adev->gfx.ras_funcs &&
 933                     adev->gfx.ras_funcs->reset_ras_error_status)
 934                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
 935                 break;
 936         case AMDGPU_RAS_BLOCK__MMHUB:
 937                 if (adev->mmhub.ras_funcs &&
 938                     adev->mmhub.ras_funcs->reset_ras_error_count)
 939                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
 940                 break;
 941         case AMDGPU_RAS_BLOCK__SDMA:
 942                 if (adev->sdma.funcs->reset_ras_error_count)
 943                         adev->sdma.funcs->reset_ras_error_count(adev);
 944                 break;
 945         default:
 946                 break;
 947         }
 948
 949         return 0;
 950 }
 951
 952 /* Trigger XGMI/WAFL error */
 953 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 954                                  struct ta_ras_trigger_error_input *block_info)
 955 {
 956         int ret;
 957
 958         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 959                 dev_warn(adev->dev, "Failed to disallow df cstate");
 960
 961         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 962                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 963
 964         ret = psp_ras_trigger_error(&adev->psp, block_info);
 965
 966         if (amdgpu_ras_intr_triggered())
 967                 return ret;
 968
 969         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 970                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 971
 972         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 973                 dev_warn(adev->dev, "Failed to allow df cstate");
 974
 975         return ret;
 976 }
 977
 978 /* wrapper of psp_ras_trigger_error */
 979 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 980                 struct ras_inject_if *info)
 981 {
 982         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 983         struct ta_ras_trigger_error_input block_info = {
 984                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 985                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 986                 .sub_block_index = info->head.sub_block_index,
 987                 .address = info->address,
 988                 .value = info->value,
 989         };
 990         int ret = 0;
 991
 992         if (!obj)
 993                 return -EINVAL;
 994
 995         /* Calculate XGMI relative offset */
 996         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 997                 block_info.address =
 998                         amdgpu_xgmi_get_relative_phy_addr(adev,
 999                                                           block_info.address);
1000         }
1001
1002         switch (info->head.block) {
1003         case AMDGPU_RAS_BLOCK__GFX:
1004                 if (adev->gfx.ras_funcs &&
1005                     adev->gfx.ras_funcs->ras_error_inject)
1006                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1007                 else
1008                         ret = -EINVAL;
1009                 break;
1010         case AMDGPU_RAS_BLOCK__UMC:
1011         case AMDGPU_RAS_BLOCK__SDMA:
1012         case AMDGPU_RAS_BLOCK__MMHUB:
1013         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1014                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1015                 break;
1016         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1017                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1018                 break;
1019         default:
1020                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1021                          ras_block_str(info->head.block));
1022                 ret = -EINVAL;
1023         }
1024
1025         amdgpu_ras_parse_status_code(adev,
1026                                      "inject",
1027                                      ras_block_str(info->head.block),
1028                                      (enum ta_ras_status)ret);
1029
1030         return ret;
1031 }
1032
1033 /* get the total error counts on all IPs */
1034 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1035                 bool is_ce)
1036 {
1037         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1038         struct ras_manager *obj;
1039         struct ras_err_data data = {0, 0};
1040
1041         if (!adev->ras_features || !con)
1042                 return 0;
1043
1044         list_for_each_entry(obj, &con->head, node) {
1045                 struct ras_query_if info = {
1046                         .head = obj->head,
1047                 };
1048
1049                 if (amdgpu_ras_query_error_status(adev, &info))
1050                         return 0;
1051
1052                 data.ce_count += info.ce_count;
1053                 data.ue_count += info.ue_count;
1054         }
1055
1056         return is_ce ? data.ce_count : data.ue_count;
1057 }
1058 /* query/inject/cure end */
1059
1060
1061 /* sysfs begin */
1062
1063 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1064                 struct ras_badpage **bps, unsigned int *count);
1065
1066 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1067 {
1068         switch (flags) {
1069         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1070                 return "R";
1071         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1072                 return "P";
1073         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1074         default:
1075                 return "F";
1076         }
1077 }
1078
1079 /**
1080  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1081  *
1082  * It allows user to read the bad pages of vram on the gpu through
1083  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1084  *
1085  * It outputs multiple lines, and each line stands for one gpu page.
1086  *
1087  * The format of one line is below,
1088  * gpu pfn : gpu page size : flags
1089  *
1090  * gpu pfn and gpu page size are printed in hex format.
1091  * flags can be one of below character,
1092  *
1093  * R: reserved, this gpu page is reserved and not able to use.
1094  *
1095  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1096  * in next window of page_reserve.
1097  *
1098  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1099  *
1100  * Examples:
1101  *
1102  * .. code-block:: bash
1103  *
1104  *      0x00000001 : 0x00001000 : R
1105  *      0x00000002 : 0x00001000 : P
1106  *
1107  */
1108
1109 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1110                 struct kobject *kobj, struct bin_attribute *attr,
1111                 char *buf, loff_t ppos, size_t count)
1112 {
1113         struct amdgpu_ras *con =
1114                 container_of(attr, struct amdgpu_ras, badpages_attr);
1115         struct amdgpu_device *adev = con->adev;
1116         const unsigned int element_size =
1117                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1118         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1119         unsigned int end = div64_ul(ppos + count - 1, element_size);
1120         ssize_t s = 0;
1121         struct ras_badpage *bps = NULL;
1122         unsigned int bps_count = 0;
1123
1124         memset(buf, 0, count);
1125
1126         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1127                 return 0;
1128
1129         for (; start < end && start < bps_count; start++)
1130                 s += scnprintf(&buf[s], element_size + 1,
1131                                 "0x%08x : 0x%08x : %1s\n",
1132                                 bps[start].bp,
1133                                 bps[start].size,
1134                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1135
1136         kfree(bps);
1137
1138         return s;
1139 }
1140
1141 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1142                 struct device_attribute *attr, char *buf)
1143 {
1144         struct amdgpu_ras *con =
1145                 container_of(attr, struct amdgpu_ras, features_attr);
1146
1147         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1148 }
1149
1150 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1151 {
1152         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1153
1154         sysfs_remove_file_from_group(&adev->dev->kobj,
1155                                 &con->badpages_attr.attr,
1156                                 RAS_FS_NAME);
1157 }
1158
1159 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1160 {
1161         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1162         struct attribute *attrs[] = {
1163                 &con->features_attr.attr,
1164                 NULL
1165         };
1166         struct attribute_group group = {
1167                 .name = RAS_FS_NAME,
1168                 .attrs = attrs,
1169         };
1170
1171         sysfs_remove_group(&adev->dev->kobj, &group);
1172
1173         return 0;
1174 }
1175
1176 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1177                 struct ras_fs_if *head)
1178 {
1179         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1180
1181         if (!obj || obj->attr_inuse)
1182                 return -EINVAL;
1183
1184         get_obj(obj);
1185
1186         memcpy(obj->fs_data.sysfs_name,
1187                         head->sysfs_name,
1188                         sizeof(obj->fs_data.sysfs_name));
1189
1190         obj->sysfs_attr = (struct device_attribute){
1191                 .attr = {
1192                         .name = obj->fs_data.sysfs_name,
1193                         .mode = S_IRUGO,
1194                 },
1195                         .show = amdgpu_ras_sysfs_read,
1196         };
1197         sysfs_attr_init(&obj->sysfs_attr.attr);
1198
1199         if (sysfs_add_file_to_group(&adev->dev->kobj,
1200                                 &obj->sysfs_attr.attr,
1201                                 RAS_FS_NAME)) {
1202                 put_obj(obj);
1203                 return -EINVAL;
1204         }
1205
1206         obj->attr_inuse = 1;
1207
1208         return 0;
1209 }
1210
1211 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1212                 struct ras_common_if *head)
1213 {
1214         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1215
1216         if (!obj || !obj->attr_inuse)
1217                 return -EINVAL;
1218
1219         sysfs_remove_file_from_group(&adev->dev->kobj,
1220                                 &obj->sysfs_attr.attr,
1221                                 RAS_FS_NAME);
1222         obj->attr_inuse = 0;
1223         put_obj(obj);
1224
1225         return 0;
1226 }
1227
1228 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1229 {
1230         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1231         struct ras_manager *obj, *tmp;
1232
1233         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1234                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1235         }
1236
1237         if (amdgpu_bad_page_threshold != 0)
1238                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1239
1240         amdgpu_ras_sysfs_remove_feature_node(adev);
1241
1242         return 0;
1243 }
1244 /* sysfs end */
1245
1246 /**
1247  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1248  *
1249  * Normally when there is an uncorrectable error, the driver will reset
1250  * the GPU to recover.  However, in the event of an unrecoverable error,
1251  * the driver provides an interface to reboot the system automatically
1252  * in that event.
1253  *
1254  * The following file in debugfs provides that interface:
1255  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1256  *
1257  * Usage:
1258  *
1259  * .. code-block:: bash
1260  *
1261  *      echo true > .../ras/auto_reboot
1262  *
1263  */
1264 /* debugfs begin */
1265 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1266 {
1267         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1268         struct dentry *dir;
1269         struct drm_minor *minor = adev_to_drm(adev)->primary;
1270
1271         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1272         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1273                             &amdgpu_ras_debugfs_ctrl_ops);
1274         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1275                             &amdgpu_ras_debugfs_eeprom_ops);
1276         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1277                            &con->bad_page_cnt_threshold);
1278
1279         /*
1280          * After one uncorrectable error happens, usually GPU recovery will
1281          * be scheduled. But due to the known problem in GPU recovery failing
1282          * to bring GPU back, below interface provides one direct way to
1283          * user to reboot system automatically in such case within
1284          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1285          * will never be called.
1286          */
1287         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1288
1289         /*
1290          * User could set this not to clean up hardware's error count register
1291          * of RAS IPs during ras recovery.
1292          */
1293         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1294                             &con->disable_ras_err_cnt_harvest);
1295         return dir;
1296 }
1297
1298 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1299                                       struct ras_fs_if *head,
1300                                       struct dentry *dir)
1301 {
1302         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1303
1304         if (!obj || !dir)
1305                 return;
1306
1307         get_obj(obj);
1308
1309         memcpy(obj->fs_data.debugfs_name,
1310                         head->debugfs_name,
1311                         sizeof(obj->fs_data.debugfs_name));
1312
1313         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1314                             obj, &amdgpu_ras_debugfs_ops);
1315 }
1316
1317 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1318 {
1319         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1320         struct dentry *dir;
1321         struct ras_manager *obj;
1322         struct ras_fs_if fs_info;
1323
1324         /*
1325          * it won't be called in resume path, no need to check
1326          * suspend and gpu reset status
1327          */
1328         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1329                 return;
1330
1331         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1332
1333         list_for_each_entry(obj, &con->head, node) {
1334                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1335                         (obj->attr_inuse == 1)) {
1336                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1337                                         ras_block_str(obj->head.block));
1338                         fs_info.head = obj->head;
1339                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1340                 }
1341         }
1342 }
1343
1344 /* debugfs end */
1345
1346 /* ras fs */
1347 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1348                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1349 static DEVICE_ATTR(features, S_IRUGO,
1350                 amdgpu_ras_sysfs_features_read, NULL);
1351 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1352 {
1353         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1354         struct attribute_group group = {
1355                 .name = RAS_FS_NAME,
1356         };
1357         struct attribute *attrs[] = {
1358                 &con->features_attr.attr,
1359                 NULL
1360         };
1361         struct bin_attribute *bin_attrs[] = {
1362                 NULL,
1363                 NULL,
1364         };
1365         int r;
1366
1367         /* add features entry */
1368         con->features_attr = dev_attr_features;
1369         group.attrs = attrs;
1370         sysfs_attr_init(attrs[0]);
1371
1372         if (amdgpu_bad_page_threshold != 0) {
1373                 /* add bad_page_features entry */
1374                 bin_attr_gpu_vram_bad_pages.private = NULL;
1375                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1376                 bin_attrs[0] = &con->badpages_attr;
1377                 group.bin_attrs = bin_attrs;
1378                 sysfs_bin_attr_init(bin_attrs[0]);
1379         }
1380
1381         r = sysfs_create_group(&adev->dev->kobj, &group);
1382         if (r)
1383                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1384
1385         return 0;
1386 }
1387
1388 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1389 {
1390         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1391         struct ras_manager *con_obj, *ip_obj, *tmp;
1392
1393         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1394                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1395                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1396                         if (ip_obj)
1397                                 put_obj(ip_obj);
1398                 }
1399         }
1400
1401         amdgpu_ras_sysfs_remove_all(adev);
1402         return 0;
1403 }
1404 /* ras fs end */
1405
1406 /* ih begin */
1407 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1408 {
1409         struct ras_ih_data *data = &obj->ih_data;
1410         struct amdgpu_iv_entry entry;
1411         int ret;
1412         struct ras_err_data err_data = {0, 0, 0, NULL};
1413
1414         while (data->rptr != data->wptr) {
1415                 rmb();
1416                 memcpy(&entry, &data->ring[data->rptr],
1417                                 data->element_size);
1418
1419                 wmb();
1420                 data->rptr = (data->aligned_element_size +
1421                                 data->rptr) % data->ring_size;
1422
1423                 /* Let IP handle its data, maybe we need get the output
1424                  * from the callback to udpate the error type/count, etc
1425                  */
1426                 if (data->cb) {
1427                         ret = data->cb(obj->adev, &err_data, &entry);
1428                         /* ue will trigger an interrupt, and in that case
1429                          * we need do a reset to recovery the whole system.
1430                          * But leave IP do that recovery, here we just dispatch
1431                          * the error.
1432                          */
1433                         if (ret == AMDGPU_RAS_SUCCESS) {
1434                                 /* these counts could be left as 0 if
1435                                  * some blocks do not count error number
1436                                  */
1437                                 obj->err_data.ue_count += err_data.ue_count;
1438                                 obj->err_data.ce_count += err_data.ce_count;
1439                         }
1440                 }
1441         }
1442 }
1443
1444 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1445 {
1446         struct ras_ih_data *data =
1447                 container_of(work, struct ras_ih_data, ih_work);
1448         struct ras_manager *obj =
1449                 container_of(data, struct ras_manager, ih_data);
1450
1451         amdgpu_ras_interrupt_handler(obj);
1452 }
1453
1454 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1455                 struct ras_dispatch_if *info)
1456 {
1457         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1458         struct ras_ih_data *data = &obj->ih_data;
1459
1460         if (!obj)
1461                 return -EINVAL;
1462
1463         if (data->inuse == 0)
1464                 return 0;
1465
1466         /* Might be overflow... */
1467         memcpy(&data->ring[data->wptr], info->entry,
1468                         data->element_size);
1469
1470         wmb();
1471         data->wptr = (data->aligned_element_size +
1472                         data->wptr) % data->ring_size;
1473
1474         schedule_work(&data->ih_work);
1475
1476         return 0;
1477 }
1478
1479 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1480                 struct ras_ih_if *info)
1481 {
1482         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1483         struct ras_ih_data *data;
1484
1485         if (!obj)
1486                 return -EINVAL;
1487
1488         data = &obj->ih_data;
1489         if (data->inuse == 0)
1490                 return 0;
1491
1492         cancel_work_sync(&data->ih_work);
1493
1494         kfree(data->ring);
1495         memset(data, 0, sizeof(*data));
1496         put_obj(obj);
1497
1498         return 0;
1499 }
1500
1501 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1502                 struct ras_ih_if *info)
1503 {
1504         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1505         struct ras_ih_data *data;
1506
1507         if (!obj) {
1508                 /* in case we registe the IH before enable ras feature */
1509                 obj = amdgpu_ras_create_obj(adev, &info->head);
1510                 if (!obj)
1511                         return -EINVAL;
1512         } else
1513                 get_obj(obj);
1514
1515         data = &obj->ih_data;
1516         /* add the callback.etc */
1517         *data = (struct ras_ih_data) {
1518                 .inuse = 0,
1519                 .cb = info->cb,
1520                 .element_size = sizeof(struct amdgpu_iv_entry),
1521                 .rptr = 0,
1522                 .wptr = 0,
1523         };
1524
1525         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1526
1527         data->aligned_element_size = ALIGN(data->element_size, 8);
1528         /* the ring can store 64 iv entries. */
1529         data->ring_size = 64 * data->aligned_element_size;
1530         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1531         if (!data->ring) {
1532                 put_obj(obj);
1533                 return -ENOMEM;
1534         }
1535
1536         /* IH is ready */
1537         data->inuse = 1;
1538
1539         return 0;
1540 }
1541
1542 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1543 {
1544         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1545         struct ras_manager *obj, *tmp;
1546
1547         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1548                 struct ras_ih_if info = {
1549                         .head = obj->head,
1550                 };
1551                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1552         }
1553
1554         return 0;
1555 }
1556 /* ih end */
1557
1558 /* traversal all IPs except NBIO to query error counter */
1559 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1560 {
1561         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1562         struct ras_manager *obj;
1563
1564         if (!adev->ras_features || !con)
1565                 return;
1566
1567         list_for_each_entry(obj, &con->head, node) {
1568                 struct ras_query_if info = {
1569                         .head = obj->head,
1570                 };
1571
1572                 /*
1573                  * PCIE_BIF IP has one different isr by ras controller
1574                  * interrupt, the specific ras counter query will be
1575                  * done in that isr. So skip such block from common
1576                  * sync flood interrupt isr calling.
1577                  */
1578                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1579                         continue;
1580
1581                 amdgpu_ras_query_error_status(adev, &info);
1582         }
1583 }
1584
1585 /* Parse RdRspStatus and WrRspStatus */
1586 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1587                                           struct ras_query_if *info)
1588 {
1589         /*
1590          * Only two block need to query read/write
1591          * RspStatus at current state
1592          */
1593         switch (info->head.block) {
1594         case AMDGPU_RAS_BLOCK__GFX:
1595                 if (adev->gfx.ras_funcs &&
1596                     adev->gfx.ras_funcs->query_ras_error_status)
1597                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1598                 break;
1599         case AMDGPU_RAS_BLOCK__MMHUB:
1600                 if (adev->mmhub.ras_funcs &&
1601                     adev->mmhub.ras_funcs->query_ras_error_status)
1602                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1603                 break;
1604         default:
1605                 break;
1606         }
1607 }
1608
1609 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1610 {
1611         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1612         struct ras_manager *obj;
1613
1614         if (!adev->ras_features || !con)
1615                 return;
1616
1617         list_for_each_entry(obj, &con->head, node) {
1618                 struct ras_query_if info = {
1619                         .head = obj->head,
1620                 };
1621
1622                 amdgpu_ras_error_status_query(adev, &info);
1623         }
1624 }
1625
1626 /* recovery begin */
1627
1628 /* return 0 on success.
1629  * caller need free bps.
1630  */
1631 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1632                 struct ras_badpage **bps, unsigned int *count)
1633 {
1634         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1635         struct ras_err_handler_data *data;
1636         int i = 0;
1637         int ret = 0, status;
1638
1639         if (!con || !con->eh_data || !bps || !count)
1640                 return -EINVAL;
1641
1642         mutex_lock(&con->recovery_lock);
1643         data = con->eh_data;
1644         if (!data || data->count == 0) {
1645                 *bps = NULL;
1646                 ret = -EINVAL;
1647                 goto out;
1648         }
1649
1650         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1651         if (!*bps) {
1652                 ret = -ENOMEM;
1653                 goto out;
1654         }
1655
1656         for (; i < data->count; i++) {
1657                 (*bps)[i] = (struct ras_badpage){
1658                         .bp = data->bps[i].retired_page,
1659                         .size = AMDGPU_GPU_PAGE_SIZE,
1660                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1661                 };
1662                 status = amdgpu_vram_mgr_query_page_status(
1663                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1664                                 data->bps[i].retired_page);
1665                 if (status == -EBUSY)
1666                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1667                 else if (status == -ENOENT)
1668                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1669         }
1670
1671         *count = data->count;
1672 out:
1673         mutex_unlock(&con->recovery_lock);
1674         return ret;
1675 }
1676
1677 static void amdgpu_ras_do_recovery(struct work_struct *work)
1678 {
1679         struct amdgpu_ras *ras =
1680                 container_of(work, struct amdgpu_ras, recovery_work);
1681         struct amdgpu_device *remote_adev = NULL;
1682         struct amdgpu_device *adev = ras->adev;
1683         struct list_head device_list, *device_list_handle =  NULL;
1684
1685         if (!ras->disable_ras_err_cnt_harvest) {
1686                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1687
1688                 /* Build list of devices to query RAS related errors */
1689                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1690                         device_list_handle = &hive->device_list;
1691                 } else {
1692                         INIT_LIST_HEAD(&device_list);
1693                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1694                         device_list_handle = &device_list;
1695                 }
1696
1697                 list_for_each_entry(remote_adev,
1698                                 device_list_handle, gmc.xgmi.head) {
1699                         amdgpu_ras_query_err_status(remote_adev);
1700                         amdgpu_ras_log_on_err_counter(remote_adev);
1701                 }
1702
1703                 amdgpu_put_xgmi_hive(hive);
1704         }
1705
1706         if (amdgpu_device_should_recover_gpu(ras->adev))
1707                 amdgpu_device_gpu_recover(ras->adev, NULL);
1708         atomic_set(&ras->in_recovery, 0);
1709 }
1710
1711 /* alloc/realloc bps array */
1712 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1713                 struct ras_err_handler_data *data, int pages)
1714 {
1715         unsigned int old_space = data->count + data->space_left;
1716         unsigned int new_space = old_space + pages;
1717         unsigned int align_space = ALIGN(new_space, 512);
1718         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1719
1720         if (!bps) {
1721                 kfree(bps);
1722                 return -ENOMEM;
1723         }
1724
1725         if (data->bps) {
1726                 memcpy(bps, data->bps,
1727                                 data->count * sizeof(*data->bps));
1728                 kfree(data->bps);
1729         }
1730
1731         data->bps = bps;
1732         data->space_left += align_space - old_space;
1733         return 0;
1734 }
1735
1736 /* it deal with vram only. */
1737 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1738                 struct eeprom_table_record *bps, int pages)
1739 {
1740         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1741         struct ras_err_handler_data *data;
1742         int ret = 0;
1743         uint32_t i;
1744
1745         if (!con || !con->eh_data || !bps || pages <= 0)
1746                 return 0;
1747
1748         mutex_lock(&con->recovery_lock);
1749         data = con->eh_data;
1750         if (!data)
1751                 goto out;
1752
1753         for (i = 0; i < pages; i++) {
1754                 if (amdgpu_ras_check_bad_page_unlock(con,
1755                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1756                         continue;
1757
1758                 if (!data->space_left &&
1759                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1760                         ret = -ENOMEM;
1761                         goto out;
1762                 }
1763
1764                 amdgpu_vram_mgr_reserve_range(
1765                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1766                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1767                         AMDGPU_GPU_PAGE_SIZE);
1768
1769                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1770                 data->count++;
1771                 data->space_left--;
1772         }
1773 out:
1774         mutex_unlock(&con->recovery_lock);
1775
1776         return ret;
1777 }
1778
1779 /*
1780  * write error record array to eeprom, the function should be
1781  * protected by recovery_lock
1782  */
1783 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1784 {
1785         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1786         struct ras_err_handler_data *data;
1787         struct amdgpu_ras_eeprom_control *control;
1788         int save_count;
1789
1790         if (!con || !con->eh_data)
1791                 return 0;
1792
1793         control = &con->eeprom_control;
1794         data = con->eh_data;
1795         save_count = data->count - control->num_recs;
1796         /* only new entries are saved */
1797         if (save_count > 0) {
1798                 if (amdgpu_ras_eeprom_process_recods(control,
1799                                                         &data->bps[control->num_recs],
1800                                                         true,
1801                                                         save_count)) {
1802                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1803                         return -EIO;
1804                 }
1805
1806                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1807         }
1808
1809         return 0;
1810 }
1811
1812 /*
1813  * read error record array in eeprom and reserve enough space for
1814  * storing new bad pages
1815  */
1816 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1817 {
1818         struct amdgpu_ras_eeprom_control *control =
1819                                         &adev->psp.ras.ras->eeprom_control;
1820         struct eeprom_table_record *bps = NULL;
1821         int ret = 0;
1822
1823         /* no bad page record, skip eeprom access */
1824         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1825                 return ret;
1826
1827         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1828         if (!bps)
1829                 return -ENOMEM;
1830
1831         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1832                 control->num_recs)) {
1833                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1834                 ret = -EIO;
1835                 goto out;
1836         }
1837
1838         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1839
1840 out:
1841         kfree(bps);
1842         return ret;
1843 }
1844
1845 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1846                                 uint64_t addr)
1847 {
1848         struct ras_err_handler_data *data = con->eh_data;
1849         int i;
1850
1851         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1852         for (i = 0; i < data->count; i++)
1853                 if (addr == data->bps[i].retired_page)
1854                         return true;
1855
1856         return false;
1857 }
1858
1859 /*
1860  * check if an address belongs to bad page
1861  *
1862  * Note: this check is only for umc block
1863  */
1864 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1865                                 uint64_t addr)
1866 {
1867         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1868         bool ret = false;
1869
1870         if (!con || !con->eh_data)
1871                 return ret;
1872
1873         mutex_lock(&con->recovery_lock);
1874         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1875         mutex_unlock(&con->recovery_lock);
1876         return ret;
1877 }
1878
1879 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1880                                         uint32_t max_length)
1881 {
1882         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1883         int tmp_threshold = amdgpu_bad_page_threshold;
1884         u64 val;
1885
1886         /*
1887          * Justification of value bad_page_cnt_threshold in ras structure
1888          *
1889          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1890          * in eeprom, and introduce two scenarios accordingly.
1891          *
1892          * Bad page retirement enablement:
1893          *    - If amdgpu_bad_page_threshold = -1,
1894          *      bad_page_cnt_threshold = typical value by formula.
1895          *
1896          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1897          *      max record length in eeprom, use it directly.
1898          *
1899          * Bad page retirement disablement:
1900          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1901          *      functionality is disabled, and bad_page_cnt_threshold will
1902          *      take no effect.
1903          */
1904
1905         if (tmp_threshold < -1)
1906                 tmp_threshold = -1;
1907         else if (tmp_threshold > max_length)
1908                 tmp_threshold = max_length;
1909
1910         if (tmp_threshold == -1) {
1911                 val = adev->gmc.mc_vram_size;
1912                 do_div(val, RAS_BAD_PAGE_RATE);
1913                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1914                                                 max_length);
1915         } else {
1916                 con->bad_page_cnt_threshold = tmp_threshold;
1917         }
1918 }
1919
1920 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1921 {
1922         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1923         struct ras_err_handler_data **data;
1924         uint32_t max_eeprom_records_len = 0;
1925         bool exc_err_limit = false;
1926         int ret;
1927
1928         if (adev->ras_features && con)
1929                 data = &con->eh_data;
1930         else
1931                 return 0;
1932
1933         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1934         if (!*data) {
1935                 ret = -ENOMEM;
1936                 goto out;
1937         }
1938
1939         mutex_init(&con->recovery_lock);
1940         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1941         atomic_set(&con->in_recovery, 0);
1942         con->adev = adev;
1943
1944         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1945         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1946
1947         /* Todo: During test the SMU might fail to read the eeprom through I2C
1948          * when the GPU is pending on XGMI reset during probe time
1949          * (Mostly after second bus reset), skip it now
1950          */
1951         if (adev->gmc.xgmi.pending_reset)
1952                 return 0;
1953         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1954         /*
1955          * This calling fails when exc_err_limit is true or
1956          * ret != 0.
1957          */
1958         if (exc_err_limit || ret)
1959                 goto free;
1960
1961         if (con->eeprom_control.num_recs) {
1962                 ret = amdgpu_ras_load_bad_pages(adev);
1963                 if (ret)
1964                         goto free;
1965         }
1966
1967         return 0;
1968
1969 free:
1970         kfree((*data)->bps);
1971         kfree(*data);
1972         con->eh_data = NULL;
1973 out:
1974         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1975
1976         /*
1977          * Except error threshold exceeding case, other failure cases in this
1978          * function would not fail amdgpu driver init.
1979          */
1980         if (!exc_err_limit)
1981                 ret = 0;
1982         else
1983                 ret = -EINVAL;
1984
1985         return ret;
1986 }
1987
1988 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1989 {
1990         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1991         struct ras_err_handler_data *data = con->eh_data;
1992
1993         /* recovery_init failed to init it, fini is useless */
1994         if (!data)
1995                 return 0;
1996
1997         cancel_work_sync(&con->recovery_work);
1998
1999         mutex_lock(&con->recovery_lock);
2000         con->eh_data = NULL;
2001         kfree(data->bps);
2002         kfree(data);
2003         mutex_unlock(&con->recovery_lock);
2004
2005         return 0;
2006 }
2007 /* recovery end */
2008
2009 /* return 0 if ras will reset gpu and repost.*/
2010 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2011                 unsigned int block)
2012 {
2013         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2014
2015         if (!ras)
2016                 return -EINVAL;
2017
2018         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2019         return 0;
2020 }
2021
2022 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2023 {
2024         return adev->asic_type == CHIP_VEGA10 ||
2025                 adev->asic_type == CHIP_VEGA20 ||
2026                 adev->asic_type == CHIP_ARCTURUS ||
2027                 adev->asic_type == CHIP_ALDEBARAN ||
2028                 adev->asic_type == CHIP_SIENNA_CICHLID;
2029 }
2030
2031 /*
2032  * check hardware's ras ability which will be saved in hw_supported.
2033  * if hardware does not support ras, we can skip some ras initializtion and
2034  * forbid some ras operations from IP.
2035  * if software itself, say boot parameter, limit the ras ability. We still
2036  * need allow IP do some limited operations, like disable. In such case,
2037  * we have to initialize ras as normal. but need check if operation is
2038  * allowed or not in each function.
2039  */
2040 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
2041                 uint32_t *hw_supported, uint32_t *supported)
2042 {
2043         *hw_supported = 0;
2044         *supported = 0;
2045
2046         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2047             !amdgpu_ras_asic_supported(adev))
2048                 return;
2049
2050         if (!adev->gmc.xgmi.connected_to_cpu) {
2051                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2052                         dev_info(adev->dev, "MEM ECC is active.\n");
2053                         *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
2054                                         1 << AMDGPU_RAS_BLOCK__DF);
2055                 } else {
2056                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2057                 }
2058
2059                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2060                         dev_info(adev->dev, "SRAM ECC is active.\n");
2061                         *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2062                                         1 << AMDGPU_RAS_BLOCK__DF);
2063                 } else {
2064                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2065                 }
2066         } else {
2067                 /* driver only manages a few IP blocks RAS feature
2068                  * when GPU is connected cpu through XGMI */
2069                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX |
2070                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2071                                 1 << AMDGPU_RAS_BLOCK__MMHUB);
2072         }
2073
2074         /* hw_supported needs to be aligned with RAS block mask. */
2075         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
2076
2077         *supported = amdgpu_ras_enable == 0 ?
2078                         0 : *hw_supported & amdgpu_ras_mask;
2079         adev->ras_features = *supported;
2080 }
2081
2082 int amdgpu_ras_init(struct amdgpu_device *adev)
2083 {
2084         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2085         int r;
2086
2087         if (con)
2088                 return 0;
2089
2090         con = kmalloc(sizeof(struct amdgpu_ras) +
2091                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2092                         GFP_KERNEL|__GFP_ZERO);
2093         if (!con)
2094                 return -ENOMEM;
2095
2096         con->objs = (struct ras_manager *)(con + 1);
2097
2098         amdgpu_ras_set_context(adev, con);
2099
2100         amdgpu_ras_check_supported(adev, &con->hw_supported,
2101                         &con->supported);
2102         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2103                 /* set gfx block ras context feature for VEGA20 Gaming
2104                  * send ras disable cmd to ras ta during ras late init.
2105                  */
2106                 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2107                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2108
2109                         return 0;
2110                 }
2111
2112                 r = 0;
2113                 goto release_con;
2114         }
2115
2116         con->features = 0;
2117         INIT_LIST_HEAD(&con->head);
2118         /* Might need get this flag from vbios. */
2119         con->flags = RAS_DEFAULT_FLAGS;
2120
2121         /* initialize nbio ras function ahead of any other
2122          * ras functions so hardware fatal error interrupt
2123          * can be enabled as early as possible */
2124         switch (adev->asic_type) {
2125         case CHIP_VEGA20:
2126         case CHIP_ARCTURUS:
2127         case CHIP_ALDEBARAN:
2128                 if (!adev->gmc.xgmi.connected_to_cpu)
2129                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2130                 break;
2131         default:
2132                 /* nbio ras is not available */
2133                 break;
2134         }
2135
2136         if (adev->nbio.ras_funcs &&
2137             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2138                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2139                 if (r)
2140                         goto release_con;
2141         }
2142
2143         if (adev->nbio.ras_funcs &&
2144             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2145                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2146                 if (r)
2147                         goto release_con;
2148         }
2149
2150         if (amdgpu_ras_fs_init(adev)) {
2151                 r = -EINVAL;
2152                 goto release_con;
2153         }
2154
2155         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2156                         "hardware ability[%x] ras_mask[%x]\n",
2157                         con->hw_supported, con->supported);
2158         return 0;
2159 release_con:
2160         amdgpu_ras_set_context(adev, NULL);
2161         kfree(con);
2162
2163         return r;
2164 }
2165
2166 static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2167 {
2168         if (adev->gmc.xgmi.connected_to_cpu)
2169                 return 1;
2170         return 0;
2171 }
2172
2173 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2174                                         struct ras_common_if *ras_block)
2175 {
2176         struct ras_query_if info = {
2177                 .head = *ras_block,
2178         };
2179
2180         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2181                 return 0;
2182
2183         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2184                 DRM_WARN("RAS init harvest failure");
2185
2186         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2187                 DRM_WARN("RAS init harvest reset failure");
2188
2189         return 0;
2190 }
2191
2192 /* helper function to handle common stuff in ip late init phase */
2193 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2194                          struct ras_common_if *ras_block,
2195                          struct ras_fs_if *fs_info,
2196                          struct ras_ih_if *ih_info)
2197 {
2198         int r;
2199
2200         /* disable RAS feature per IP block if it is not supported */
2201         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2202                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2203                 return 0;
2204         }
2205
2206         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2207         if (r) {
2208                 if (r == -EAGAIN) {
2209                         /* request gpu reset. will run again */
2210                         amdgpu_ras_request_reset_on_boot(adev,
2211                                         ras_block->block);
2212                         return 0;
2213                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2214                         /* in resume phase, if fail to enable ras,
2215                          * clean up all ras fs nodes, and disable ras */
2216                         goto cleanup;
2217                 } else
2218                         return r;
2219         }
2220
2221         /* check for errors on warm reset edc persisant supported ASIC */
2222         amdgpu_persistent_edc_harvesting(adev, ras_block);
2223
2224         /* in resume phase, no need to create ras fs node */
2225         if (adev->in_suspend || amdgpu_in_reset(adev))
2226                 return 0;
2227
2228         if (ih_info->cb) {
2229                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2230                 if (r)
2231                         goto interrupt;
2232         }
2233
2234         r = amdgpu_ras_sysfs_create(adev, fs_info);
2235         if (r)
2236                 goto sysfs;
2237
2238         return 0;
2239 cleanup:
2240         amdgpu_ras_sysfs_remove(adev, ras_block);
2241 sysfs:
2242         if (ih_info->cb)
2243                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2244 interrupt:
2245         amdgpu_ras_feature_enable(adev, ras_block, 0);
2246         return r;
2247 }
2248
2249 /* helper function to remove ras fs node and interrupt handler */
2250 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2251                           struct ras_common_if *ras_block,
2252                           struct ras_ih_if *ih_info)
2253 {
2254         if (!ras_block || !ih_info)
2255                 return;
2256
2257         amdgpu_ras_sysfs_remove(adev, ras_block);
2258         if (ih_info->cb)
2259                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2260         amdgpu_ras_feature_enable(adev, ras_block, 0);
2261 }
2262
2263 /* do some init work after IP late init as dependence.
2264  * and it runs in resume/gpu reset/booting up cases.
2265  */
2266 void amdgpu_ras_resume(struct amdgpu_device *adev)
2267 {
2268         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2269         struct ras_manager *obj, *tmp;
2270
2271         if (!adev->ras_features || !con) {
2272                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2273                 amdgpu_release_ras_context(adev);
2274
2275                 return;
2276         }
2277
2278         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2279                 /* Set up all other IPs which are not implemented. There is a
2280                  * tricky thing that IP's actual ras error type should be
2281                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2282                  * ERROR_NONE make sense anyway.
2283                  */
2284                 amdgpu_ras_enable_all_features(adev, 1);
2285
2286                 /* We enable ras on all hw_supported block, but as boot
2287                  * parameter might disable some of them and one or more IP has
2288                  * not implemented yet. So we disable them on behalf.
2289                  */
2290                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2291                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2292                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2293                                 /* there should be no any reference. */
2294                                 WARN_ON(alive_obj(obj));
2295                         }
2296                 }
2297         }
2298
2299         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2300                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2301                 /* setup ras obj state as disabled.
2302                  * for init_by_vbios case.
2303                  * if we want to enable ras, just enable it in a normal way.
2304                  * If we want do disable it, need setup ras obj as enabled,
2305                  * then issue another TA disable cmd.
2306                  * See feature_enable_on_boot
2307                  */
2308                 amdgpu_ras_disable_all_features(adev, 1);
2309                 amdgpu_ras_reset_gpu(adev);
2310         }
2311 }
2312
2313 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2314 {
2315         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2316
2317         if (!adev->ras_features || !con)
2318                 return;
2319
2320         amdgpu_ras_disable_all_features(adev, 0);
2321         /* Make sure all ras objects are disabled. */
2322         if (con->features)
2323                 amdgpu_ras_disable_all_features(adev, 1);
2324 }
2325
2326 /* do some fini work before IP fini as dependence */
2327 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2328 {
2329         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2330
2331         if (!adev->ras_features || !con)
2332                 return 0;
2333
2334         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2335         amdgpu_ras_disable_all_features(adev, 0);
2336         amdgpu_ras_recovery_fini(adev);
2337         return 0;
2338 }
2339
2340 int amdgpu_ras_fini(struct amdgpu_device *adev)
2341 {
2342         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2343
2344         if (!adev->ras_features || !con)
2345                 return 0;
2346
2347         amdgpu_ras_fs_fini(adev);
2348         amdgpu_ras_interrupt_remove_all(adev);
2349
2350         WARN(con->features, "Feature mask is not cleared");
2351
2352         if (con->features)
2353                 amdgpu_ras_disable_all_features(adev, 1);
2354
2355         amdgpu_ras_set_context(adev, NULL);
2356         kfree(con);
2357
2358         return 0;
2359 }
2360
2361 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2362 {
2363         uint32_t hw_supported, supported;
2364
2365         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2366         if (!hw_supported)
2367                 return;
2368
2369         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2370                 dev_info(adev->dev, "uncorrectable hardware error"
2371                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2372
2373                 amdgpu_ras_reset_gpu(adev);
2374         }
2375 }
2376
2377 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2378 {
2379         if (adev->asic_type == CHIP_VEGA20 &&
2380             adev->pm.fw_version <= 0x283400) {
2381                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2382                                 amdgpu_ras_intr_triggered();
2383         }
2384
2385         return false;
2386 }
2387
2388 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2389 {
2390         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2391
2392         if (!con)
2393                 return;
2394
2395         if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2396                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2397                 amdgpu_ras_set_context(adev, NULL);
2398                 kfree(con);
2399         }
2400 }