2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
28 #include <linux/reboot.h>
29 #include <linux/syscalls.h>
32 #include "amdgpu_ras.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_xgmi.h"
35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
37 static const char *RAS_FS_NAME = "ras";
39 const char *ras_error_string[] = {
43 "multi_uncorrectable",
47 const char *ras_block_string[] = {
64 #define ras_err_str(i) (ras_error_string[ffs(i)])
65 #define ras_block_str(i) (ras_block_string[i])
67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
69 /* inject address is 52 bits */
70 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
73 #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL)
75 enum amdgpu_ras_retire_page_reservation {
76 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
77 AMDGPU_RAS_RETIRE_PAGE_PENDING,
78 AMDGPU_RAS_RETIRE_PAGE_FAULT,
81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
90 if (adev && amdgpu_ras_get_context(adev))
91 amdgpu_ras_get_context(adev)->error_query_ready = ready;
94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
96 if (adev && amdgpu_ras_get_context(adev))
97 return amdgpu_ras_get_context(adev)->error_query_ready;
102 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
104 struct ras_err_data err_data = {0, 0, 0, NULL};
105 struct eeprom_table_record err_rec;
107 if ((address >= adev->gmc.mc_vram_size) ||
108 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
110 "RAS WARN: input address 0x%llx is invalid.\n",
115 if (amdgpu_ras_check_bad_page(adev, address)) {
117 "RAS WARN: 0x%llx has already been marked as bad page!\n",
122 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
124 err_rec.address = address;
125 err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
126 err_rec.ts = (uint64_t)ktime_get_real_seconds();
127 err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
129 err_data.err_addr = &err_rec;
130 err_data.err_addr_cnt = 1;
132 if (amdgpu_bad_page_threshold != 0) {
133 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
134 err_data.err_addr_cnt);
135 amdgpu_ras_save_bad_pages(adev);
138 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
139 dev_warn(adev->dev, "Clear EEPROM:\n");
140 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
145 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
146 size_t size, loff_t *pos)
148 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
149 struct ras_query_if info = {
155 if (amdgpu_ras_query_error_status(obj->adev, &info))
158 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
160 "ce", info.ce_count);
165 s = min_t(u64, s, size);
168 if (copy_to_user(buf, &val[*pos], s))
176 static const struct file_operations amdgpu_ras_debugfs_ops = {
177 .owner = THIS_MODULE,
178 .read = amdgpu_ras_debugfs_read,
180 .llseek = default_llseek
183 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
187 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
189 if (strcmp(name, ras_block_str(i)) == 0)
195 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
196 const char __user *buf, size_t size,
197 loff_t *pos, struct ras_debug_if *data)
199 ssize_t s = min_t(u64, 64, size);
212 memset(str, 0, sizeof(str));
213 memset(data, 0, sizeof(*data));
215 if (copy_from_user(str, buf, s))
218 if (sscanf(str, "disable %32s", block_name) == 1)
220 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
222 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
224 else if (strstr(str, "retire_page") != NULL)
226 else if (str[0] && str[1] && str[2] && str[3])
227 /* ascii string, but commands are not matched. */
232 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
233 sscanf(str, "%*s %llu", &address) != 1)
237 data->inject.address = address;
242 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
245 data->head.block = block_id;
246 /* only ue and ce errors are supported */
247 if (!memcmp("ue", err, 2))
248 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
249 else if (!memcmp("ce", err, 2))
250 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
257 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
258 &sub_block, &address, &value) != 3 &&
259 sscanf(str, "%*s %*s %*s %u %llu %llu",
260 &sub_block, &address, &value) != 3)
262 data->head.sub_block_index = sub_block;
263 data->inject.address = address;
264 data->inject.value = value;
267 if (size < sizeof(*data))
270 if (copy_from_user(data, buf, sizeof(*data)))
278 * DOC: AMDGPU RAS debugfs control interface
280 * The control interface accepts struct ras_debug_if which has two members.
282 * First member: ras_debug_if::head or ras_debug_if::inject.
284 * head is used to indicate which IP block will be under control.
286 * head has four members, they are block, type, sub_block_index, name.
287 * block: which IP will be under control.
288 * type: what kind of error will be enabled/disabled/injected.
289 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
290 * name: the name of IP.
292 * inject has two more members than head, they are address, value.
293 * As their names indicate, inject operation will write the
294 * value to the address.
296 * The second member: struct ras_debug_if::op.
297 * It has three kinds of operations.
299 * - 0: disable RAS on the block. Take ::head as its data.
300 * - 1: enable RAS on the block. Take ::head as its data.
301 * - 2: inject errors on the block. Take ::inject as its data.
303 * How to use the interface?
307 * Copy the struct ras_debug_if in your code and initialize it.
308 * Write the struct to the control interface.
312 * .. code-block:: bash
314 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
315 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
316 * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
318 * Where N, is the card which you want to affect.
320 * "disable" requires only the block.
321 * "enable" requires the block and error type.
322 * "inject" requires the block, error type, address, and value.
323 * The block is one of: umc, sdma, gfx, etc.
324 * see ras_block_string[] for details
325 * The error type is one of: ue, ce, where,
326 * ue is multi-uncorrectable
327 * ce is single-correctable
328 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
329 * The address and value are hexadecimal numbers, leading 0x is optional.
333 * .. code-block:: bash
335 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
336 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
337 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
339 * How to check the result of the operation?
341 * To check disable/enable, see "ras" features at,
342 * /sys/class/drm/card[0/1/2...]/device/ras/features
344 * To check inject, see the corresponding error count at,
345 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
348 * Operations are only allowed on blocks which are supported.
349 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
350 * to see which blocks support RAS on a particular asic.
353 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
354 size_t size, loff_t *pos)
356 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
357 struct ras_debug_if data;
360 if (!amdgpu_ras_get_error_query_ready(adev)) {
361 dev_warn(adev->dev, "RAS WARN: error injection "
362 "currently inaccessible\n");
366 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
371 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
378 if (!amdgpu_ras_is_supported(adev, data.head.block))
383 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
386 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
389 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
390 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
391 dev_warn(adev->dev, "RAS WARN: input address "
392 "0x%llx is invalid.",
393 data.inject.address);
398 /* umc ce/ue error injection for a bad page is not allowed */
399 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
400 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
401 dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
402 "as bad before error injection!\n",
403 data.inject.address);
407 /* data.inject.address is offset instead of absolute gpu address */
408 ret = amdgpu_ras_error_inject(adev, &data.inject);
422 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
424 * Some boards contain an EEPROM which is used to persistently store a list of
425 * bad pages which experiences ECC errors in vram. This interface provides
426 * a way to reset the EEPROM, e.g., after testing error injection.
430 * .. code-block:: bash
432 * echo 1 > ../ras/ras_eeprom_reset
434 * will reset EEPROM table to 0 entries.
437 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
438 size_t size, loff_t *pos)
440 struct amdgpu_device *adev =
441 (struct amdgpu_device *)file_inode(f)->i_private;
444 ret = amdgpu_ras_eeprom_reset_table(
445 &(amdgpu_ras_get_context(adev)->eeprom_control));
448 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
455 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
456 .owner = THIS_MODULE,
458 .write = amdgpu_ras_debugfs_ctrl_write,
459 .llseek = default_llseek
462 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
463 .owner = THIS_MODULE,
465 .write = amdgpu_ras_debugfs_eeprom_write,
466 .llseek = default_llseek
470 * DOC: AMDGPU RAS sysfs Error Count Interface
472 * It allows the user to read the error count for each IP block on the gpu through
473 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
475 * It outputs the multiple lines which report the uncorrected (ue) and corrected
478 * The format of one line is below,
484 * .. code-block:: bash
490 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
491 struct device_attribute *attr, char *buf)
493 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
494 struct ras_query_if info = {
498 if (!amdgpu_ras_get_error_query_ready(obj->adev))
499 return sysfs_emit(buf, "Query currently inaccessible\n");
501 if (amdgpu_ras_query_error_status(obj->adev, &info))
505 if (obj->adev->asic_type == CHIP_ALDEBARAN) {
506 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
507 DRM_WARN("Failed to reset error counter and error status");
510 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
511 "ce", info.ce_count);
516 #define get_obj(obj) do { (obj)->use++; } while (0)
517 #define alive_obj(obj) ((obj)->use)
519 static inline void put_obj(struct ras_manager *obj)
521 if (obj && (--obj->use == 0))
522 list_del(&obj->node);
523 if (obj && (obj->use < 0))
524 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
527 /* make one obj and return it. */
528 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
529 struct ras_common_if *head)
531 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
532 struct ras_manager *obj;
534 if (!adev->ras_features || !con)
537 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
540 obj = &con->objs[head->block];
541 /* already exist. return obj? */
547 list_add(&obj->node, &con->head);
553 /* return an obj equal to head, or the first when head is NULL */
554 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
555 struct ras_common_if *head)
557 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
558 struct ras_manager *obj;
561 if (!adev->ras_features || !con)
565 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
568 obj = &con->objs[head->block];
570 if (alive_obj(obj)) {
571 WARN_ON(head->block != obj->head.block);
575 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
577 if (alive_obj(obj)) {
578 WARN_ON(i != obj->head.block);
588 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
589 const char* invoke_type,
590 const char* block_name,
591 enum ta_ras_status ret)
594 case TA_RAS_STATUS__SUCCESS:
596 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
598 "RAS WARN: %s %s currently unavailable\n",
604 "RAS ERROR: %s %s error failed ret 0x%X\n",
611 /* feature ctl begin */
612 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
613 struct ras_common_if *head)
615 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
617 return con->hw_supported & BIT(head->block);
620 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
621 struct ras_common_if *head)
623 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
625 return con->features & BIT(head->block);
629 * if obj is not created, then create one.
630 * set feature enable flag.
632 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
633 struct ras_common_if *head, int enable)
635 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
636 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
638 /* If hardware does not support ras, then do not create obj.
639 * But if hardware support ras, we can create the obj.
640 * Ras framework checks con->hw_supported to see if it need do
641 * corresponding initialization.
642 * IP checks con->support to see if it need disable ras.
644 if (!amdgpu_ras_is_feature_allowed(adev, head))
646 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
651 obj = amdgpu_ras_create_obj(adev, head);
655 /* In case we create obj somewhere else */
658 con->features |= BIT(head->block);
660 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
661 con->features &= ~BIT(head->block);
669 /* wrapper of psp_ras_enable_features */
670 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
671 struct ras_common_if *head, bool enable)
673 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
674 union ta_ras_cmd_input *info;
680 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
685 info->disable_features = (struct ta_ras_disable_features_input) {
686 .block_id = amdgpu_ras_block_to_ta(head->block),
687 .error_type = amdgpu_ras_error_to_ta(head->type),
690 info->enable_features = (struct ta_ras_enable_features_input) {
691 .block_id = amdgpu_ras_block_to_ta(head->block),
692 .error_type = amdgpu_ras_error_to_ta(head->type),
696 /* Do not enable if it is not allowed. */
697 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
698 /* Are we alerady in that state we are going to set? */
699 if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
704 if (!amdgpu_ras_intr_triggered()) {
705 ret = psp_ras_enable_features(&adev->psp, info, enable);
707 amdgpu_ras_parse_status_code(adev,
708 enable ? "enable":"disable",
709 ras_block_str(head->block),
710 (enum ta_ras_status)ret);
711 if (ret == TA_RAS_STATUS__RESET_NEEDED)
721 __amdgpu_ras_feature_enable(adev, head, enable);
728 /* Only used in device probe stage and called only once. */
729 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
730 struct ras_common_if *head, bool enable)
732 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
738 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
740 /* There is no harm to issue a ras TA cmd regardless of
741 * the currecnt ras state.
742 * If current state == target state, it will do nothing
743 * But sometimes it requests driver to reset and repost
744 * with error code -EAGAIN.
746 ret = amdgpu_ras_feature_enable(adev, head, 1);
747 /* With old ras TA, we might fail to enable ras.
748 * Log it and just setup the object.
749 * TODO need remove this WA in the future.
751 if (ret == -EINVAL) {
752 ret = __amdgpu_ras_feature_enable(adev, head, 1);
755 "RAS INFO: %s setup object\n",
756 ras_block_str(head->block));
759 /* setup the object then issue a ras TA disable cmd.*/
760 ret = __amdgpu_ras_feature_enable(adev, head, 1);
764 /* gfx block ras dsiable cmd must send to ras-ta */
765 if (head->block == AMDGPU_RAS_BLOCK__GFX)
766 con->features |= BIT(head->block);
768 ret = amdgpu_ras_feature_enable(adev, head, 0);
770 /* clean gfx block ras features flag */
771 if (adev->ras_features && head->block == AMDGPU_RAS_BLOCK__GFX)
772 con->features &= ~BIT(head->block);
775 ret = amdgpu_ras_feature_enable(adev, head, enable);
780 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
783 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
784 struct ras_manager *obj, *tmp;
786 list_for_each_entry_safe(obj, tmp, &con->head, node) {
788 * aka just release the obj and corresponding flags
791 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
794 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
799 return con->features;
802 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
805 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
806 int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
808 const enum amdgpu_ras_error_type default_ras_type =
809 AMDGPU_RAS_ERROR__NONE;
811 for (i = 0; i < ras_block_count; i++) {
812 struct ras_common_if head = {
814 .type = default_ras_type,
815 .sub_block_index = 0,
817 strcpy(head.name, ras_block_str(i));
820 * bypass psp. vbios enable ras for us.
821 * so just create the obj
823 if (__amdgpu_ras_feature_enable(adev, &head, 1))
826 if (amdgpu_ras_feature_enable(adev, &head, 1))
831 return con->features;
833 /* feature ctl end */
835 /* query/inject/cure begin */
836 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
837 struct ras_query_if *info)
839 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
840 struct ras_err_data err_data = {0, 0, 0, NULL};
846 switch (info->head.block) {
847 case AMDGPU_RAS_BLOCK__UMC:
848 if (adev->umc.ras_funcs &&
849 adev->umc.ras_funcs->query_ras_error_count)
850 adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
851 /* umc query_ras_error_address is also responsible for clearing
854 if (adev->umc.ras_funcs &&
855 adev->umc.ras_funcs->query_ras_error_address)
856 adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
858 case AMDGPU_RAS_BLOCK__SDMA:
859 if (adev->sdma.funcs->query_ras_error_count) {
860 for (i = 0; i < adev->sdma.num_instances; i++)
861 adev->sdma.funcs->query_ras_error_count(adev, i,
865 case AMDGPU_RAS_BLOCK__GFX:
866 if (adev->gfx.ras_funcs &&
867 adev->gfx.ras_funcs->query_ras_error_count)
868 adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
870 if (adev->gfx.ras_funcs &&
871 adev->gfx.ras_funcs->query_ras_error_status)
872 adev->gfx.ras_funcs->query_ras_error_status(adev);
874 case AMDGPU_RAS_BLOCK__MMHUB:
875 if (adev->mmhub.ras_funcs &&
876 adev->mmhub.ras_funcs->query_ras_error_count)
877 adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
879 if (adev->mmhub.ras_funcs &&
880 adev->mmhub.ras_funcs->query_ras_error_status)
881 adev->mmhub.ras_funcs->query_ras_error_status(adev);
883 case AMDGPU_RAS_BLOCK__PCIE_BIF:
884 if (adev->nbio.ras_funcs &&
885 adev->nbio.ras_funcs->query_ras_error_count)
886 adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
888 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
889 if (adev->gmc.xgmi.ras_funcs &&
890 adev->gmc.xgmi.ras_funcs->query_ras_error_count)
891 adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
893 case AMDGPU_RAS_BLOCK__HDP:
894 if (adev->hdp.ras_funcs &&
895 adev->hdp.ras_funcs->query_ras_error_count)
896 adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
902 obj->err_data.ue_count += err_data.ue_count;
903 obj->err_data.ce_count += err_data.ce_count;
905 info->ue_count = obj->err_data.ue_count;
906 info->ce_count = obj->err_data.ce_count;
908 if (err_data.ce_count) {
909 if (adev->smuio.funcs &&
910 adev->smuio.funcs->get_socket_id &&
911 adev->smuio.funcs->get_die_id) {
912 dev_info(adev->dev, "socket: %d, die: %d "
913 "%ld correctable hardware errors "
914 "detected in %s block, no user "
915 "action is needed.\n",
916 adev->smuio.funcs->get_socket_id(adev),
917 adev->smuio.funcs->get_die_id(adev),
918 obj->err_data.ce_count,
919 ras_block_str(info->head.block));
921 dev_info(adev->dev, "%ld correctable hardware errors "
922 "detected in %s block, no user "
923 "action is needed.\n",
924 obj->err_data.ce_count,
925 ras_block_str(info->head.block));
928 if (err_data.ue_count) {
929 if (adev->smuio.funcs &&
930 adev->smuio.funcs->get_socket_id &&
931 adev->smuio.funcs->get_die_id) {
932 dev_info(adev->dev, "socket: %d, die: %d "
933 "%ld uncorrectable hardware errors "
934 "detected in %s block\n",
935 adev->smuio.funcs->get_socket_id(adev),
936 adev->smuio.funcs->get_die_id(adev),
937 obj->err_data.ue_count,
938 ras_block_str(info->head.block));
940 dev_info(adev->dev, "%ld uncorrectable hardware errors "
941 "detected in %s block\n",
942 obj->err_data.ue_count,
943 ras_block_str(info->head.block));
950 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
951 enum amdgpu_ras_block block)
953 if (!amdgpu_ras_is_supported(adev, block))
957 case AMDGPU_RAS_BLOCK__GFX:
958 if (adev->gfx.ras_funcs &&
959 adev->gfx.ras_funcs->reset_ras_error_count)
960 adev->gfx.ras_funcs->reset_ras_error_count(adev);
962 if (adev->gfx.ras_funcs &&
963 adev->gfx.ras_funcs->reset_ras_error_status)
964 adev->gfx.ras_funcs->reset_ras_error_status(adev);
966 case AMDGPU_RAS_BLOCK__MMHUB:
967 if (adev->mmhub.ras_funcs &&
968 adev->mmhub.ras_funcs->reset_ras_error_count)
969 adev->mmhub.ras_funcs->reset_ras_error_count(adev);
971 case AMDGPU_RAS_BLOCK__SDMA:
972 if (adev->sdma.funcs->reset_ras_error_count)
973 adev->sdma.funcs->reset_ras_error_count(adev);
975 case AMDGPU_RAS_BLOCK__HDP:
976 if (adev->hdp.ras_funcs &&
977 adev->hdp.ras_funcs->reset_ras_error_count)
978 adev->hdp.ras_funcs->reset_ras_error_count(adev);
987 /* Trigger XGMI/WAFL error */
988 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
989 struct ta_ras_trigger_error_input *block_info)
993 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
994 dev_warn(adev->dev, "Failed to disallow df cstate");
996 if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
997 dev_warn(adev->dev, "Failed to disallow XGMI power down");
999 ret = psp_ras_trigger_error(&adev->psp, block_info);
1001 if (amdgpu_ras_intr_triggered())
1004 if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
1005 dev_warn(adev->dev, "Failed to allow XGMI power down");
1007 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
1008 dev_warn(adev->dev, "Failed to allow df cstate");
1013 /* wrapper of psp_ras_trigger_error */
1014 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1015 struct ras_inject_if *info)
1017 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1018 struct ta_ras_trigger_error_input block_info = {
1019 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1020 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1021 .sub_block_index = info->head.sub_block_index,
1022 .address = info->address,
1023 .value = info->value,
1030 /* Calculate XGMI relative offset */
1031 if (adev->gmc.xgmi.num_physical_nodes > 1) {
1032 block_info.address =
1033 amdgpu_xgmi_get_relative_phy_addr(adev,
1034 block_info.address);
1037 switch (info->head.block) {
1038 case AMDGPU_RAS_BLOCK__GFX:
1039 if (adev->gfx.ras_funcs &&
1040 adev->gfx.ras_funcs->ras_error_inject)
1041 ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1045 case AMDGPU_RAS_BLOCK__UMC:
1046 case AMDGPU_RAS_BLOCK__SDMA:
1047 case AMDGPU_RAS_BLOCK__MMHUB:
1048 case AMDGPU_RAS_BLOCK__PCIE_BIF:
1049 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1051 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1052 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1055 dev_info(adev->dev, "%s error injection is not supported yet\n",
1056 ras_block_str(info->head.block));
1060 amdgpu_ras_parse_status_code(adev,
1062 ras_block_str(info->head.block),
1063 (enum ta_ras_status)ret);
1068 /* get the total error counts on all IPs */
1069 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1072 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1073 struct ras_manager *obj;
1074 struct ras_err_data data = {0, 0};
1076 if (!adev->ras_features || !con)
1079 list_for_each_entry(obj, &con->head, node) {
1080 struct ras_query_if info = {
1084 if (amdgpu_ras_query_error_status(adev, &info))
1087 data.ce_count += info.ce_count;
1088 data.ue_count += info.ue_count;
1091 return is_ce ? data.ce_count : data.ue_count;
1093 /* query/inject/cure end */
1098 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1099 struct ras_badpage **bps, unsigned int *count);
1101 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1104 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1106 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1108 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1115 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1117 * It allows user to read the bad pages of vram on the gpu through
1118 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1120 * It outputs multiple lines, and each line stands for one gpu page.
1122 * The format of one line is below,
1123 * gpu pfn : gpu page size : flags
1125 * gpu pfn and gpu page size are printed in hex format.
1126 * flags can be one of below character,
1128 * R: reserved, this gpu page is reserved and not able to use.
1130 * P: pending for reserve, this gpu page is marked as bad, will be reserved
1131 * in next window of page_reserve.
1133 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1137 * .. code-block:: bash
1139 * 0x00000001 : 0x00001000 : R
1140 * 0x00000002 : 0x00001000 : P
1144 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1145 struct kobject *kobj, struct bin_attribute *attr,
1146 char *buf, loff_t ppos, size_t count)
1148 struct amdgpu_ras *con =
1149 container_of(attr, struct amdgpu_ras, badpages_attr);
1150 struct amdgpu_device *adev = con->adev;
1151 const unsigned int element_size =
1152 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1153 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1154 unsigned int end = div64_ul(ppos + count - 1, element_size);
1156 struct ras_badpage *bps = NULL;
1157 unsigned int bps_count = 0;
1159 memset(buf, 0, count);
1161 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1164 for (; start < end && start < bps_count; start++)
1165 s += scnprintf(&buf[s], element_size + 1,
1166 "0x%08x : 0x%08x : %1s\n",
1169 amdgpu_ras_badpage_flags_str(bps[start].flags));
1176 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1177 struct device_attribute *attr, char *buf)
1179 struct amdgpu_ras *con =
1180 container_of(attr, struct amdgpu_ras, features_attr);
1182 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1185 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1187 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1189 sysfs_remove_file_from_group(&adev->dev->kobj,
1190 &con->badpages_attr.attr,
1194 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1196 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1197 struct attribute *attrs[] = {
1198 &con->features_attr.attr,
1201 struct attribute_group group = {
1202 .name = RAS_FS_NAME,
1206 sysfs_remove_group(&adev->dev->kobj, &group);
1211 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1212 struct ras_fs_if *head)
1214 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1216 if (!obj || obj->attr_inuse)
1221 memcpy(obj->fs_data.sysfs_name,
1223 sizeof(obj->fs_data.sysfs_name));
1225 obj->sysfs_attr = (struct device_attribute){
1227 .name = obj->fs_data.sysfs_name,
1230 .show = amdgpu_ras_sysfs_read,
1232 sysfs_attr_init(&obj->sysfs_attr.attr);
1234 if (sysfs_add_file_to_group(&adev->dev->kobj,
1235 &obj->sysfs_attr.attr,
1241 obj->attr_inuse = 1;
1246 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1247 struct ras_common_if *head)
1249 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1251 if (!obj || !obj->attr_inuse)
1254 sysfs_remove_file_from_group(&adev->dev->kobj,
1255 &obj->sysfs_attr.attr,
1257 obj->attr_inuse = 0;
1263 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1265 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1266 struct ras_manager *obj, *tmp;
1268 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1269 amdgpu_ras_sysfs_remove(adev, &obj->head);
1272 if (amdgpu_bad_page_threshold != 0)
1273 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1275 amdgpu_ras_sysfs_remove_feature_node(adev);
1282 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1284 * Normally when there is an uncorrectable error, the driver will reset
1285 * the GPU to recover. However, in the event of an unrecoverable error,
1286 * the driver provides an interface to reboot the system automatically
1289 * The following file in debugfs provides that interface:
1290 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1294 * .. code-block:: bash
1296 * echo true > .../ras/auto_reboot
1300 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1302 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1304 struct drm_minor *minor = adev_to_drm(adev)->primary;
1306 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1307 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1308 &amdgpu_ras_debugfs_ctrl_ops);
1309 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1310 &amdgpu_ras_debugfs_eeprom_ops);
1311 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1312 &con->bad_page_cnt_threshold);
1315 * After one uncorrectable error happens, usually GPU recovery will
1316 * be scheduled. But due to the known problem in GPU recovery failing
1317 * to bring GPU back, below interface provides one direct way to
1318 * user to reboot system automatically in such case within
1319 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1320 * will never be called.
1322 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1325 * User could set this not to clean up hardware's error count register
1326 * of RAS IPs during ras recovery.
1328 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1329 &con->disable_ras_err_cnt_harvest);
1333 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1334 struct ras_fs_if *head,
1337 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1344 memcpy(obj->fs_data.debugfs_name,
1346 sizeof(obj->fs_data.debugfs_name));
1348 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1349 obj, &amdgpu_ras_debugfs_ops);
1352 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1354 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1356 struct ras_manager *obj;
1357 struct ras_fs_if fs_info;
1360 * it won't be called in resume path, no need to check
1361 * suspend and gpu reset status
1363 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1366 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1368 list_for_each_entry(obj, &con->head, node) {
1369 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1370 (obj->attr_inuse == 1)) {
1371 sprintf(fs_info.debugfs_name, "%s_err_inject",
1372 ras_block_str(obj->head.block));
1373 fs_info.head = obj->head;
1374 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1382 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1383 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1384 static DEVICE_ATTR(features, S_IRUGO,
1385 amdgpu_ras_sysfs_features_read, NULL);
1386 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1388 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1389 struct attribute_group group = {
1390 .name = RAS_FS_NAME,
1392 struct attribute *attrs[] = {
1393 &con->features_attr.attr,
1396 struct bin_attribute *bin_attrs[] = {
1402 /* add features entry */
1403 con->features_attr = dev_attr_features;
1404 group.attrs = attrs;
1405 sysfs_attr_init(attrs[0]);
1407 if (amdgpu_bad_page_threshold != 0) {
1408 /* add bad_page_features entry */
1409 bin_attr_gpu_vram_bad_pages.private = NULL;
1410 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1411 bin_attrs[0] = &con->badpages_attr;
1412 group.bin_attrs = bin_attrs;
1413 sysfs_bin_attr_init(bin_attrs[0]);
1416 r = sysfs_create_group(&adev->dev->kobj, &group);
1418 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1423 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1425 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1426 struct ras_manager *con_obj, *ip_obj, *tmp;
1428 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1429 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1430 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1436 amdgpu_ras_sysfs_remove_all(adev);
1442 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1444 struct ras_ih_data *data = &obj->ih_data;
1445 struct amdgpu_iv_entry entry;
1447 struct ras_err_data err_data = {0, 0, 0, NULL};
1449 while (data->rptr != data->wptr) {
1451 memcpy(&entry, &data->ring[data->rptr],
1452 data->element_size);
1455 data->rptr = (data->aligned_element_size +
1456 data->rptr) % data->ring_size;
1458 /* Let IP handle its data, maybe we need get the output
1459 * from the callback to udpate the error type/count, etc
1462 ret = data->cb(obj->adev, &err_data, &entry);
1463 /* ue will trigger an interrupt, and in that case
1464 * we need do a reset to recovery the whole system.
1465 * But leave IP do that recovery, here we just dispatch
1468 if (ret == AMDGPU_RAS_SUCCESS) {
1469 /* these counts could be left as 0 if
1470 * some blocks do not count error number
1472 obj->err_data.ue_count += err_data.ue_count;
1473 obj->err_data.ce_count += err_data.ce_count;
1479 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1481 struct ras_ih_data *data =
1482 container_of(work, struct ras_ih_data, ih_work);
1483 struct ras_manager *obj =
1484 container_of(data, struct ras_manager, ih_data);
1486 amdgpu_ras_interrupt_handler(obj);
1489 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1490 struct ras_dispatch_if *info)
1492 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1493 struct ras_ih_data *data = &obj->ih_data;
1498 if (data->inuse == 0)
1501 /* Might be overflow... */
1502 memcpy(&data->ring[data->wptr], info->entry,
1503 data->element_size);
1506 data->wptr = (data->aligned_element_size +
1507 data->wptr) % data->ring_size;
1509 schedule_work(&data->ih_work);
1514 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1515 struct ras_ih_if *info)
1517 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1518 struct ras_ih_data *data;
1523 data = &obj->ih_data;
1524 if (data->inuse == 0)
1527 cancel_work_sync(&data->ih_work);
1530 memset(data, 0, sizeof(*data));
1536 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1537 struct ras_ih_if *info)
1539 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1540 struct ras_ih_data *data;
1543 /* in case we registe the IH before enable ras feature */
1544 obj = amdgpu_ras_create_obj(adev, &info->head);
1550 data = &obj->ih_data;
1551 /* add the callback.etc */
1552 *data = (struct ras_ih_data) {
1555 .element_size = sizeof(struct amdgpu_iv_entry),
1560 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1562 data->aligned_element_size = ALIGN(data->element_size, 8);
1563 /* the ring can store 64 iv entries. */
1564 data->ring_size = 64 * data->aligned_element_size;
1565 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1577 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1579 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1580 struct ras_manager *obj, *tmp;
1582 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1583 struct ras_ih_if info = {
1586 amdgpu_ras_interrupt_remove_handler(adev, &info);
1593 /* traversal all IPs except NBIO to query error counter */
1594 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1596 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1597 struct ras_manager *obj;
1599 if (!adev->ras_features || !con)
1602 list_for_each_entry(obj, &con->head, node) {
1603 struct ras_query_if info = {
1608 * PCIE_BIF IP has one different isr by ras controller
1609 * interrupt, the specific ras counter query will be
1610 * done in that isr. So skip such block from common
1611 * sync flood interrupt isr calling.
1613 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1616 amdgpu_ras_query_error_status(adev, &info);
1620 /* Parse RdRspStatus and WrRspStatus */
1621 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1622 struct ras_query_if *info)
1625 * Only two block need to query read/write
1626 * RspStatus at current state
1628 switch (info->head.block) {
1629 case AMDGPU_RAS_BLOCK__GFX:
1630 if (adev->gfx.ras_funcs &&
1631 adev->gfx.ras_funcs->query_ras_error_status)
1632 adev->gfx.ras_funcs->query_ras_error_status(adev);
1634 case AMDGPU_RAS_BLOCK__MMHUB:
1635 if (adev->mmhub.ras_funcs &&
1636 adev->mmhub.ras_funcs->query_ras_error_status)
1637 adev->mmhub.ras_funcs->query_ras_error_status(adev);
1644 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1646 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1647 struct ras_manager *obj;
1649 if (!adev->ras_features || !con)
1652 list_for_each_entry(obj, &con->head, node) {
1653 struct ras_query_if info = {
1657 amdgpu_ras_error_status_query(adev, &info);
1661 /* recovery begin */
1663 /* return 0 on success.
1664 * caller need free bps.
1666 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1667 struct ras_badpage **bps, unsigned int *count)
1669 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1670 struct ras_err_handler_data *data;
1672 int ret = 0, status;
1674 if (!con || !con->eh_data || !bps || !count)
1677 mutex_lock(&con->recovery_lock);
1678 data = con->eh_data;
1679 if (!data || data->count == 0) {
1685 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1691 for (; i < data->count; i++) {
1692 (*bps)[i] = (struct ras_badpage){
1693 .bp = data->bps[i].retired_page,
1694 .size = AMDGPU_GPU_PAGE_SIZE,
1695 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1697 status = amdgpu_vram_mgr_query_page_status(
1698 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1699 data->bps[i].retired_page);
1700 if (status == -EBUSY)
1701 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1702 else if (status == -ENOENT)
1703 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1706 *count = data->count;
1708 mutex_unlock(&con->recovery_lock);
1712 static void amdgpu_ras_do_recovery(struct work_struct *work)
1714 struct amdgpu_ras *ras =
1715 container_of(work, struct amdgpu_ras, recovery_work);
1716 struct amdgpu_device *remote_adev = NULL;
1717 struct amdgpu_device *adev = ras->adev;
1718 struct list_head device_list, *device_list_handle = NULL;
1720 if (!ras->disable_ras_err_cnt_harvest) {
1721 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1723 /* Build list of devices to query RAS related errors */
1724 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1725 device_list_handle = &hive->device_list;
1727 INIT_LIST_HEAD(&device_list);
1728 list_add_tail(&adev->gmc.xgmi.head, &device_list);
1729 device_list_handle = &device_list;
1732 list_for_each_entry(remote_adev,
1733 device_list_handle, gmc.xgmi.head) {
1734 amdgpu_ras_query_err_status(remote_adev);
1735 amdgpu_ras_log_on_err_counter(remote_adev);
1738 amdgpu_put_xgmi_hive(hive);
1741 if (amdgpu_device_should_recover_gpu(ras->adev))
1742 amdgpu_device_gpu_recover(ras->adev, NULL);
1743 atomic_set(&ras->in_recovery, 0);
1746 /* alloc/realloc bps array */
1747 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1748 struct ras_err_handler_data *data, int pages)
1750 unsigned int old_space = data->count + data->space_left;
1751 unsigned int new_space = old_space + pages;
1752 unsigned int align_space = ALIGN(new_space, 512);
1753 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1761 memcpy(bps, data->bps,
1762 data->count * sizeof(*data->bps));
1767 data->space_left += align_space - old_space;
1771 /* it deal with vram only. */
1772 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1773 struct eeprom_table_record *bps, int pages)
1775 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1776 struct ras_err_handler_data *data;
1780 if (!con || !con->eh_data || !bps || pages <= 0)
1783 mutex_lock(&con->recovery_lock);
1784 data = con->eh_data;
1788 for (i = 0; i < pages; i++) {
1789 if (amdgpu_ras_check_bad_page_unlock(con,
1790 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1793 if (!data->space_left &&
1794 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1799 amdgpu_vram_mgr_reserve_range(
1800 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1801 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1802 AMDGPU_GPU_PAGE_SIZE);
1804 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1809 mutex_unlock(&con->recovery_lock);
1815 * write error record array to eeprom, the function should be
1816 * protected by recovery_lock
1818 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1820 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1821 struct ras_err_handler_data *data;
1822 struct amdgpu_ras_eeprom_control *control;
1825 if (!con || !con->eh_data)
1828 control = &con->eeprom_control;
1829 data = con->eh_data;
1830 save_count = data->count - control->num_recs;
1831 /* only new entries are saved */
1832 if (save_count > 0) {
1833 if (amdgpu_ras_eeprom_process_recods(control,
1834 &data->bps[control->num_recs],
1837 dev_err(adev->dev, "Failed to save EEPROM table data!");
1841 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1848 * read error record array in eeprom and reserve enough space for
1849 * storing new bad pages
1851 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1853 struct amdgpu_ras_eeprom_control *control =
1854 &adev->psp.ras.ras->eeprom_control;
1855 struct eeprom_table_record *bps = NULL;
1858 /* no bad page record, skip eeprom access */
1859 if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1862 bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1866 if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1867 control->num_recs)) {
1868 dev_err(adev->dev, "Failed to load EEPROM table records!");
1873 ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1880 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1883 struct ras_err_handler_data *data = con->eh_data;
1886 addr >>= AMDGPU_GPU_PAGE_SHIFT;
1887 for (i = 0; i < data->count; i++)
1888 if (addr == data->bps[i].retired_page)
1895 * check if an address belongs to bad page
1897 * Note: this check is only for umc block
1899 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1902 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1905 if (!con || !con->eh_data)
1908 mutex_lock(&con->recovery_lock);
1909 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1910 mutex_unlock(&con->recovery_lock);
1914 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1915 uint32_t max_length)
1917 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1918 int tmp_threshold = amdgpu_bad_page_threshold;
1922 * Justification of value bad_page_cnt_threshold in ras structure
1924 * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1925 * in eeprom, and introduce two scenarios accordingly.
1927 * Bad page retirement enablement:
1928 * - If amdgpu_bad_page_threshold = -1,
1929 * bad_page_cnt_threshold = typical value by formula.
1931 * - When the value from user is 0 < amdgpu_bad_page_threshold <
1932 * max record length in eeprom, use it directly.
1934 * Bad page retirement disablement:
1935 * - If amdgpu_bad_page_threshold = 0, bad page retirement
1936 * functionality is disabled, and bad_page_cnt_threshold will
1940 if (tmp_threshold < -1)
1942 else if (tmp_threshold > max_length)
1943 tmp_threshold = max_length;
1945 if (tmp_threshold == -1) {
1946 val = adev->gmc.mc_vram_size;
1947 do_div(val, RAS_BAD_PAGE_RATE);
1948 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1951 con->bad_page_cnt_threshold = tmp_threshold;
1955 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1957 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1958 struct ras_err_handler_data **data;
1959 uint32_t max_eeprom_records_len = 0;
1960 bool exc_err_limit = false;
1963 if (adev->ras_features && con)
1964 data = &con->eh_data;
1968 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1974 mutex_init(&con->recovery_lock);
1975 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1976 atomic_set(&con->in_recovery, 0);
1979 max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1980 amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1982 /* Todo: During test the SMU might fail to read the eeprom through I2C
1983 * when the GPU is pending on XGMI reset during probe time
1984 * (Mostly after second bus reset), skip it now
1986 if (adev->gmc.xgmi.pending_reset)
1988 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1990 * This calling fails when exc_err_limit is true or
1993 if (exc_err_limit || ret)
1996 if (con->eeprom_control.num_recs) {
1997 ret = amdgpu_ras_load_bad_pages(adev);
2005 kfree((*data)->bps);
2007 con->eh_data = NULL;
2009 dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
2012 * Except error threshold exceeding case, other failure cases in this
2013 * function would not fail amdgpu driver init.
2023 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2025 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2026 struct ras_err_handler_data *data = con->eh_data;
2028 /* recovery_init failed to init it, fini is useless */
2032 cancel_work_sync(&con->recovery_work);
2034 mutex_lock(&con->recovery_lock);
2035 con->eh_data = NULL;
2038 mutex_unlock(&con->recovery_lock);
2044 /* return 0 if ras will reset gpu and repost.*/
2045 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2048 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2053 ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2057 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2059 return adev->asic_type == CHIP_VEGA10 ||
2060 adev->asic_type == CHIP_VEGA20 ||
2061 adev->asic_type == CHIP_ARCTURUS ||
2062 adev->asic_type == CHIP_ALDEBARAN ||
2063 adev->asic_type == CHIP_SIENNA_CICHLID;
2067 * check hardware's ras ability which will be saved in hw_supported.
2068 * if hardware does not support ras, we can skip some ras initializtion and
2069 * forbid some ras operations from IP.
2070 * if software itself, say boot parameter, limit the ras ability. We still
2071 * need allow IP do some limited operations, like disable. In such case,
2072 * we have to initialize ras as normal. but need check if operation is
2073 * allowed or not in each function.
2075 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
2076 uint32_t *hw_supported, uint32_t *supported)
2081 if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2082 !amdgpu_ras_asic_supported(adev))
2085 if (!adev->gmc.xgmi.connected_to_cpu) {
2086 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2087 dev_info(adev->dev, "MEM ECC is active.\n");
2088 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
2089 1 << AMDGPU_RAS_BLOCK__DF);
2091 dev_info(adev->dev, "MEM ECC is not presented.\n");
2094 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2095 dev_info(adev->dev, "SRAM ECC is active.\n");
2096 *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2097 1 << AMDGPU_RAS_BLOCK__DF);
2099 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2102 /* driver only manages a few IP blocks RAS feature
2103 * when GPU is connected cpu through XGMI */
2104 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__SDMA |
2105 1 << AMDGPU_RAS_BLOCK__MMHUB);
2108 /* hw_supported needs to be aligned with RAS block mask. */
2109 *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
2111 *supported = amdgpu_ras_enable == 0 ?
2112 0 : *hw_supported & amdgpu_ras_mask;
2113 adev->ras_features = *supported;
2116 int amdgpu_ras_init(struct amdgpu_device *adev)
2118 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2124 con = kmalloc(sizeof(struct amdgpu_ras) +
2125 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2126 GFP_KERNEL|__GFP_ZERO);
2130 con->objs = (struct ras_manager *)(con + 1);
2132 amdgpu_ras_set_context(adev, con);
2134 amdgpu_ras_check_supported(adev, &con->hw_supported,
2136 if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2137 /* set gfx block ras context feature for VEGA20 Gaming
2138 * send ras disable cmd to ras ta during ras late init.
2140 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2141 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2151 INIT_LIST_HEAD(&con->head);
2152 /* Might need get this flag from vbios. */
2153 con->flags = RAS_DEFAULT_FLAGS;
2155 /* initialize nbio ras function ahead of any other
2156 * ras functions so hardware fatal error interrupt
2157 * can be enabled as early as possible */
2158 switch (adev->asic_type) {
2161 case CHIP_ALDEBARAN:
2162 if (!adev->gmc.xgmi.connected_to_cpu)
2163 adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2166 /* nbio ras is not available */
2170 if (adev->nbio.ras_funcs &&
2171 adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2172 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2177 if (adev->nbio.ras_funcs &&
2178 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2179 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2184 if (amdgpu_ras_fs_init(adev)) {
2189 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2190 "hardware ability[%x] ras_mask[%x]\n",
2191 con->hw_supported, con->supported);
2194 amdgpu_ras_set_context(adev, NULL);
2200 static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2202 if (adev->gmc.xgmi.connected_to_cpu)
2207 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2208 struct ras_common_if *ras_block)
2210 struct ras_query_if info = {
2214 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2217 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2218 DRM_WARN("RAS init harvest failure");
2220 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2221 DRM_WARN("RAS init harvest reset failure");
2226 /* helper function to handle common stuff in ip late init phase */
2227 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2228 struct ras_common_if *ras_block,
2229 struct ras_fs_if *fs_info,
2230 struct ras_ih_if *ih_info)
2234 /* disable RAS feature per IP block if it is not supported */
2235 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2236 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2240 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2243 /* request gpu reset. will run again */
2244 amdgpu_ras_request_reset_on_boot(adev,
2247 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2248 /* in resume phase, if fail to enable ras,
2249 * clean up all ras fs nodes, and disable ras */
2255 /* check for errors on warm reset edc persisant supported ASIC */
2256 amdgpu_persistent_edc_harvesting(adev, ras_block);
2258 /* in resume phase, no need to create ras fs node */
2259 if (adev->in_suspend || amdgpu_in_reset(adev))
2263 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2268 r = amdgpu_ras_sysfs_create(adev, fs_info);
2274 amdgpu_ras_sysfs_remove(adev, ras_block);
2277 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2279 amdgpu_ras_feature_enable(adev, ras_block, 0);
2283 /* helper function to remove ras fs node and interrupt handler */
2284 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2285 struct ras_common_if *ras_block,
2286 struct ras_ih_if *ih_info)
2288 if (!ras_block || !ih_info)
2291 amdgpu_ras_sysfs_remove(adev, ras_block);
2293 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2294 amdgpu_ras_feature_enable(adev, ras_block, 0);
2297 /* do some init work after IP late init as dependence.
2298 * and it runs in resume/gpu reset/booting up cases.
2300 void amdgpu_ras_resume(struct amdgpu_device *adev)
2302 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2303 struct ras_manager *obj, *tmp;
2305 if (!adev->ras_features || !con) {
2306 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2307 amdgpu_release_ras_context(adev);
2312 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2313 /* Set up all other IPs which are not implemented. There is a
2314 * tricky thing that IP's actual ras error type should be
2315 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2316 * ERROR_NONE make sense anyway.
2318 amdgpu_ras_enable_all_features(adev, 1);
2320 /* We enable ras on all hw_supported block, but as boot
2321 * parameter might disable some of them and one or more IP has
2322 * not implemented yet. So we disable them on behalf.
2324 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2325 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2326 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2327 /* there should be no any reference. */
2328 WARN_ON(alive_obj(obj));
2333 if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2334 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2335 /* setup ras obj state as disabled.
2336 * for init_by_vbios case.
2337 * if we want to enable ras, just enable it in a normal way.
2338 * If we want do disable it, need setup ras obj as enabled,
2339 * then issue another TA disable cmd.
2340 * See feature_enable_on_boot
2342 amdgpu_ras_disable_all_features(adev, 1);
2343 amdgpu_ras_reset_gpu(adev);
2347 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2349 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2351 if (!adev->ras_features || !con)
2354 amdgpu_ras_disable_all_features(adev, 0);
2355 /* Make sure all ras objects are disabled. */
2357 amdgpu_ras_disable_all_features(adev, 1);
2360 /* do some fini work before IP fini as dependence */
2361 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2363 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2365 if (!adev->ras_features || !con)
2368 /* Need disable ras on all IPs here before ip [hw/sw]fini */
2369 amdgpu_ras_disable_all_features(adev, 0);
2370 amdgpu_ras_recovery_fini(adev);
2374 int amdgpu_ras_fini(struct amdgpu_device *adev)
2376 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2378 if (!adev->ras_features || !con)
2381 amdgpu_ras_fs_fini(adev);
2382 amdgpu_ras_interrupt_remove_all(adev);
2384 WARN(con->features, "Feature mask is not cleared");
2387 amdgpu_ras_disable_all_features(adev, 1);
2389 amdgpu_ras_set_context(adev, NULL);
2395 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2397 uint32_t hw_supported, supported;
2399 amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2403 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2404 dev_info(adev->dev, "uncorrectable hardware error"
2405 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2407 amdgpu_ras_reset_gpu(adev);
2411 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2413 if (adev->asic_type == CHIP_VEGA20 &&
2414 adev->pm.fw_version <= 0x283400) {
2415 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2416 amdgpu_ras_intr_triggered();
2422 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2424 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2429 if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2430 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2431 amdgpu_ras_set_context(adev, NULL);