2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
27 #include <linux/dma-mapping.h>
28 #include <drm/drm_drv.h>
31 #include "amdgpu_psp.h"
32 #include "amdgpu_ucode.h"
33 #include "soc15_common.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v12_0.h"
38 #include "psp_v13_0.h"
40 #include "amdgpu_ras.h"
41 #include "amdgpu_securedisplay.h"
42 #include "amdgpu_atomfirmware.h"
44 #include <drm/drm_drv.h>
46 static int psp_sysfs_init(struct amdgpu_device *adev);
47 static void psp_sysfs_fini(struct amdgpu_device *adev);
49 static int psp_load_smu_fw(struct psp_context *psp);
52 * Due to DF Cstate management centralized to PMFW, the firmware
53 * loading sequence will be updated as below:
59 * - Load other non-psp fw
61 * - Load XGMI/RAS/HDCP/DTM TA if any
63 * This new sequence is required for
64 * - Arcturus and onwards
65 * - Navi12 and onwards
67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
69 struct amdgpu_device *adev = psp->adev;
71 psp->pmfw_centralized_cstate_management = false;
73 if (amdgpu_sriov_vf(adev))
76 if (adev->flags & AMD_IS_APU)
79 if ((adev->asic_type >= CHIP_ARCTURUS) ||
80 (adev->asic_type >= CHIP_NAVI12))
81 psp->pmfw_centralized_cstate_management = true;
84 static int psp_early_init(void *handle)
86 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
87 struct psp_context *psp = &adev->psp;
89 switch (adev->asic_type) {
92 psp_v3_1_set_psp_funcs(psp);
93 psp->autoload_supported = false;
96 psp_v10_0_set_psp_funcs(psp);
97 psp->autoload_supported = false;
101 psp_v11_0_set_psp_funcs(psp);
102 psp->autoload_supported = false;
107 case CHIP_SIENNA_CICHLID:
108 case CHIP_NAVY_FLOUNDER:
110 case CHIP_DIMGREY_CAVEFISH:
111 case CHIP_BEIGE_GOBY:
112 psp_v11_0_set_psp_funcs(psp);
113 psp->autoload_supported = true;
116 psp_v12_0_set_psp_funcs(psp);
119 psp_v13_0_set_psp_funcs(psp);
121 case CHIP_YELLOW_CARP:
122 psp_v13_0_set_psp_funcs(psp);
123 psp->autoload_supported = true;
131 psp_check_pmfw_centralized_cstate_management(psp);
136 static void psp_memory_training_fini(struct psp_context *psp)
138 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
140 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
141 kfree(ctx->sys_cache);
142 ctx->sys_cache = NULL;
145 static int psp_memory_training_init(struct psp_context *psp)
148 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
150 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
151 DRM_DEBUG("memory training is not supported!\n");
155 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
156 if (ctx->sys_cache == NULL) {
157 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
162 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
163 ctx->train_data_size,
164 ctx->p2c_train_data_offset,
165 ctx->c2p_train_data_offset);
166 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
170 psp_memory_training_fini(psp);
175 * Helper funciton to query psp runtime database entry
177 * @adev: amdgpu_device pointer
178 * @entry_type: the type of psp runtime database entry
179 * @db_entry: runtime database entry pointer
181 * Return false if runtime database doesn't exit or entry is invalid
182 * or true if the specific database entry is found, and copy to @db_entry
184 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
185 enum psp_runtime_entry_type entry_type,
188 uint64_t db_header_pos, db_dir_pos;
189 struct psp_runtime_data_header db_header = {0};
190 struct psp_runtime_data_directory db_dir = {0};
194 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
195 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
197 /* read runtime db header from vram */
198 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
199 sizeof(struct psp_runtime_data_header), false);
201 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
202 /* runtime db doesn't exist, exit */
203 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
207 /* read runtime database entry from vram */
208 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
209 sizeof(struct psp_runtime_data_directory), false);
211 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
212 /* invalid db entry count, exit */
213 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
217 /* look up for requested entry type */
218 for (i = 0; i < db_dir.entry_count && !ret; i++) {
219 if (db_dir.entry_list[i].entry_type == entry_type) {
220 switch (entry_type) {
221 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
222 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
223 /* invalid db entry size */
224 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
227 /* read runtime database entry */
228 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
229 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
242 static int psp_sw_init(void *handle)
244 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
245 struct psp_context *psp = &adev->psp;
247 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
248 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
250 if (!amdgpu_sriov_vf(adev)) {
251 ret = psp_init_microcode(psp);
253 DRM_ERROR("Failed to load psp firmware!\n");
256 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
257 ret = psp_init_ta_microcode(psp, "aldebaran");
259 DRM_ERROR("Failed to initialize ta microcode!\n");
264 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
265 if (psp_get_runtime_db_entry(adev,
266 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
268 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
269 if ((psp->boot_cfg_bitmask) &
270 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
271 /* If psp runtime database exists, then
272 * only enable two stage memory training
273 * when TWO_STAGE_DRAM_TRAINING bit is set
274 * in runtime database */
275 mem_training_ctx->enable_mem_training = true;
279 /* If psp runtime database doesn't exist or
280 * is invalid, force enable two stage memory
282 mem_training_ctx->enable_mem_training = true;
285 if (mem_training_ctx->enable_mem_training) {
286 ret = psp_memory_training_init(psp);
288 DRM_ERROR("Failed to initialize memory training!\n");
292 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
294 DRM_ERROR("Failed to process memory training!\n");
299 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
300 ret= psp_sysfs_init(adev);
309 static int psp_sw_fini(void *handle)
311 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
313 psp_memory_training_fini(&adev->psp);
314 if (adev->psp.sos_fw) {
315 release_firmware(adev->psp.sos_fw);
316 adev->psp.sos_fw = NULL;
318 if (adev->psp.asd_fw) {
319 release_firmware(adev->psp.asd_fw);
320 adev->psp.asd_fw = NULL;
322 if (adev->psp.ta_fw) {
323 release_firmware(adev->psp.ta_fw);
324 adev->psp.ta_fw = NULL;
327 if (adev->asic_type == CHIP_NAVI10 ||
328 adev->asic_type == CHIP_SIENNA_CICHLID)
329 psp_sysfs_fini(adev);
334 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
335 uint32_t reg_val, uint32_t mask, bool check_changed)
339 struct amdgpu_device *adev = psp->adev;
341 if (psp->adev->no_hw_access)
344 for (i = 0; i < adev->usec_timeout; i++) {
345 val = RREG32(reg_index);
350 if ((val & mask) == reg_val)
360 psp_cmd_submit_buf(struct psp_context *psp,
361 struct amdgpu_firmware_info *ucode,
362 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
367 bool ras_intr = false;
368 bool skip_unsupport = false;
370 if (psp->adev->no_hw_access)
373 if (!drm_dev_enter(&psp->adev->ddev, &idx))
376 mutex_lock(&psp->mutex);
378 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
380 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
382 index = atomic_inc_return(&psp->fence_value);
383 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
385 atomic_dec(&psp->fence_value);
389 amdgpu_device_invalidate_hdp(psp->adev, NULL);
390 while (*((unsigned int *)psp->fence_buf) != index) {
394 * Shouldn't wait for timeout when err_event_athub occurs,
395 * because gpu reset thread triggered and lock resource should
396 * be released for psp resume sequence.
398 ras_intr = amdgpu_ras_intr_triggered();
401 usleep_range(10, 100);
402 amdgpu_device_invalidate_hdp(psp->adev, NULL);
405 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
406 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
407 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
409 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
411 /* In some cases, psp response status is not 0 even there is no
412 * problem while the command is submitted. Some version of PSP FW
413 * doesn't write 0 to that field.
414 * So here we would like to only print a warning instead of an error
415 * during psp initialization to avoid breaking hw_init and it doesn't
418 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
420 DRM_WARN("failed to load ucode id (%d) ",
422 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
423 psp->cmd_buf_mem->cmd_id,
424 psp->cmd_buf_mem->resp.status);
432 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
433 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
437 mutex_unlock(&psp->mutex);
442 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
443 struct psp_gfx_cmd_resp *cmd,
444 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
446 struct amdgpu_device *adev = psp->adev;
447 uint32_t size = amdgpu_bo_size(tmr_bo);
448 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
450 if (amdgpu_sriov_vf(psp->adev))
451 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
453 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
454 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
455 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
456 cmd->cmd.cmd_setup_tmr.buf_size = size;
457 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
458 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
459 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
462 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
463 uint64_t pri_buf_mc, uint32_t size)
465 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
466 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
467 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
468 cmd->cmd.cmd_load_toc.toc_size = size;
471 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
472 static int psp_load_toc(struct psp_context *psp,
476 struct psp_gfx_cmd_resp *cmd;
478 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
481 /* Copy toc to psp firmware private buffer */
482 psp_copy_fw(psp, psp->toc_start_addr, psp->toc_bin_size);
484 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
486 ret = psp_cmd_submit_buf(psp, NULL, cmd,
487 psp->fence_buf_mc_addr);
489 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
494 /* Set up Trusted Memory Region */
495 static int psp_tmr_init(struct psp_context *psp)
503 * According to HW engineer, they prefer the TMR address be "naturally
504 * aligned" , e.g. the start address be an integer divide of TMR size.
506 * Note: this memory need be reserved till the driver
509 tmr_size = PSP_TMR_SIZE(psp->adev);
511 /* For ASICs support RLC autoload, psp will parse the toc
512 * and calculate the total size of TMR needed */
513 if (!amdgpu_sriov_vf(psp->adev) &&
514 psp->toc_start_addr &&
517 ret = psp_load_toc(psp, &tmr_size);
519 DRM_ERROR("Failed to load toc\n");
524 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
525 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
526 AMDGPU_GEM_DOMAIN_VRAM,
527 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
532 static bool psp_skip_tmr(struct psp_context *psp)
534 switch (psp->adev->asic_type) {
536 case CHIP_SIENNA_CICHLID:
544 static int psp_tmr_load(struct psp_context *psp)
547 struct psp_gfx_cmd_resp *cmd;
549 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
550 * Already set up by host driver.
552 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
555 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
559 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
560 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
561 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
563 ret = psp_cmd_submit_buf(psp, NULL, cmd,
564 psp->fence_buf_mc_addr);
571 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
572 struct psp_gfx_cmd_resp *cmd)
574 if (amdgpu_sriov_vf(psp->adev))
575 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
577 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
580 static int psp_tmr_unload(struct psp_context *psp)
583 struct psp_gfx_cmd_resp *cmd;
585 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
589 psp_prep_tmr_unload_cmd_buf(psp, cmd);
590 DRM_INFO("free PSP TMR buffer\n");
592 ret = psp_cmd_submit_buf(psp, NULL, cmd,
593 psp->fence_buf_mc_addr);
600 static int psp_tmr_terminate(struct psp_context *psp)
606 ret = psp_tmr_unload(psp);
610 /* free TMR memory buffer */
611 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
612 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
617 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
618 uint64_t *output_ptr)
621 struct psp_gfx_cmd_resp *cmd;
626 if (amdgpu_sriov_vf(psp->adev))
629 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
633 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
635 ret = psp_cmd_submit_buf(psp, NULL, cmd,
636 psp->fence_buf_mc_addr);
639 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
640 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
648 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
650 struct psp_context *psp = &adev->psp;
651 struct psp_gfx_cmd_resp *cmd = psp->cmd;
654 if (amdgpu_sriov_vf(adev))
657 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
659 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
660 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
662 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
665 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
671 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
673 struct psp_context *psp = &adev->psp;
674 struct psp_gfx_cmd_resp *cmd = psp->cmd;
676 if (amdgpu_sriov_vf(adev))
679 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
681 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
682 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
683 cmd->cmd.boot_cfg.boot_config = boot_cfg;
684 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
686 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
689 static int psp_rl_load(struct amdgpu_device *adev)
691 struct psp_context *psp = &adev->psp;
692 struct psp_gfx_cmd_resp *cmd = psp->cmd;
694 if (psp->rl_bin_size == 0)
697 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
698 memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size);
700 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
702 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
703 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
704 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
705 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size;
706 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
708 return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
711 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
712 uint64_t asd_mc, uint32_t size)
714 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
715 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
716 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
717 cmd->cmd.cmd_load_ta.app_len = size;
719 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
720 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
721 cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
724 static int psp_asd_load(struct psp_context *psp)
727 struct psp_gfx_cmd_resp *cmd;
729 /* If PSP version doesn't match ASD version, asd loading will be failed.
730 * add workaround to bypass it for sriov now.
731 * TODO: add version check to make it common
733 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size)
736 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
740 psp_copy_fw(psp, psp->asd_start_addr, psp->asd_ucode_size);
742 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
743 psp->asd_ucode_size);
745 ret = psp_cmd_submit_buf(psp, NULL, cmd,
746 psp->fence_buf_mc_addr);
748 psp->asd_context.asd_initialized = true;
749 psp->asd_context.session_id = cmd->resp.session_id;
757 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
760 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
761 cmd->cmd.cmd_unload_ta.session_id = session_id;
764 static int psp_asd_unload(struct psp_context *psp)
767 struct psp_gfx_cmd_resp *cmd;
769 if (amdgpu_sriov_vf(psp->adev))
772 if (!psp->asd_context.asd_initialized)
775 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
779 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
781 ret = psp_cmd_submit_buf(psp, NULL, cmd,
782 psp->fence_buf_mc_addr);
784 psp->asd_context.asd_initialized = false;
791 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
792 uint32_t id, uint32_t value)
794 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
795 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
796 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
799 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
802 struct psp_gfx_cmd_resp *cmd = NULL;
805 if (reg >= PSP_REG_LAST)
808 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
812 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
813 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
815 DRM_ERROR("PSP failed to program reg id %d", reg);
821 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
823 uint32_t ta_bin_size,
824 uint64_t ta_shared_mc,
825 uint32_t ta_shared_size)
827 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
828 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
829 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
830 cmd->cmd.cmd_load_ta.app_len = ta_bin_size;
832 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
833 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
834 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size;
837 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
842 * Allocate 16k memory aligned to 4k from Frame Buffer (local
843 * physical) for xgmi ta <-> Driver
845 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
846 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
847 &psp->xgmi_context.xgmi_shared_bo,
848 &psp->xgmi_context.xgmi_shared_mc_addr,
849 &psp->xgmi_context.xgmi_shared_buf);
854 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
858 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
859 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
860 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
863 static int psp_ta_invoke(struct psp_context *psp,
868 struct psp_gfx_cmd_resp *cmd;
870 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
874 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
876 ret = psp_cmd_submit_buf(psp, NULL, cmd,
877 psp->fence_buf_mc_addr);
884 static int psp_xgmi_load(struct psp_context *psp)
887 struct psp_gfx_cmd_resp *cmd;
890 * TODO: bypass the loading in sriov for now
893 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
897 psp_copy_fw(psp, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
899 psp_prep_ta_load_cmd_buf(cmd,
901 psp->ta_xgmi_ucode_size,
902 psp->xgmi_context.xgmi_shared_mc_addr,
903 PSP_XGMI_SHARED_MEM_SIZE);
905 ret = psp_cmd_submit_buf(psp, NULL, cmd,
906 psp->fence_buf_mc_addr);
909 psp->xgmi_context.initialized = 1;
910 psp->xgmi_context.session_id = cmd->resp.session_id;
918 static int psp_xgmi_unload(struct psp_context *psp)
921 struct psp_gfx_cmd_resp *cmd;
922 struct amdgpu_device *adev = psp->adev;
924 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
925 if (adev->asic_type == CHIP_ARCTURUS ||
926 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
930 * TODO: bypass the unloading in sriov for now
933 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
937 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
939 ret = psp_cmd_submit_buf(psp, NULL, cmd,
940 psp->fence_buf_mc_addr);
947 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
949 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
952 int psp_xgmi_terminate(struct psp_context *psp)
956 if (!psp->xgmi_context.initialized)
959 ret = psp_xgmi_unload(psp);
963 psp->xgmi_context.initialized = 0;
965 /* free xgmi shared memory */
966 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
967 &psp->xgmi_context.xgmi_shared_mc_addr,
968 &psp->xgmi_context.xgmi_shared_buf);
973 int psp_xgmi_initialize(struct psp_context *psp)
975 struct ta_xgmi_shared_memory *xgmi_cmd;
978 if (!psp->adev->psp.ta_fw ||
979 !psp->adev->psp.ta_xgmi_ucode_size ||
980 !psp->adev->psp.ta_xgmi_start_addr)
983 if (!psp->xgmi_context.initialized) {
984 ret = psp_xgmi_init_shared_buf(psp);
990 ret = psp_xgmi_load(psp);
994 /* Initialize XGMI session */
995 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
996 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
997 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
999 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1004 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1006 struct ta_xgmi_shared_memory *xgmi_cmd;
1009 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
1010 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1012 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1014 /* Invoke xgmi ta to get hive id */
1015 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1019 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1024 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1026 struct ta_xgmi_shared_memory *xgmi_cmd;
1029 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
1030 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1032 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1034 /* Invoke xgmi ta to get the node id */
1035 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1039 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1044 int psp_xgmi_get_topology_info(struct psp_context *psp,
1046 struct psp_xgmi_topology_info *topology)
1048 struct ta_xgmi_shared_memory *xgmi_cmd;
1049 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1050 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1054 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1057 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
1058 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1060 /* Fill in the shared memory with topology information as input */
1061 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1062 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1063 topology_info_input->num_nodes = number_devices;
1065 for (i = 0; i < topology_info_input->num_nodes; i++) {
1066 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1067 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1068 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1069 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1072 /* Invoke xgmi ta to get the topology information */
1073 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1077 /* Read the output topology information from the shared memory */
1078 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1079 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1080 for (i = 0; i < topology->num_nodes; i++) {
1081 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1082 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1083 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
1084 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
1090 int psp_xgmi_set_topology_info(struct psp_context *psp,
1092 struct psp_xgmi_topology_info *topology)
1094 struct ta_xgmi_shared_memory *xgmi_cmd;
1095 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1098 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1101 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
1102 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1104 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1105 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1106 topology_info_input->num_nodes = number_devices;
1108 for (i = 0; i < topology_info_input->num_nodes; i++) {
1109 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1110 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1111 topology_info_input->nodes[i].is_sharing_enabled = 1;
1112 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1115 /* Invoke xgmi ta to set topology information */
1116 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1120 static int psp_ras_init_shared_buf(struct psp_context *psp)
1125 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1126 * physical) for ras ta <-> Driver
1128 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
1129 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1130 &psp->ras.ras_shared_bo,
1131 &psp->ras.ras_shared_mc_addr,
1132 &psp->ras.ras_shared_buf);
1137 static int psp_ras_load(struct psp_context *psp)
1140 struct psp_gfx_cmd_resp *cmd;
1141 struct ta_ras_shared_memory *ras_cmd;
1144 * TODO: bypass the loading in sriov for now
1146 if (amdgpu_sriov_vf(psp->adev))
1149 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1153 psp_copy_fw(psp, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
1155 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1157 if (psp->adev->gmc.xgmi.connected_to_cpu)
1158 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1160 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1162 psp_prep_ta_load_cmd_buf(cmd,
1163 psp->fw_pri_mc_addr,
1164 psp->ta_ras_ucode_size,
1165 psp->ras.ras_shared_mc_addr,
1166 PSP_RAS_SHARED_MEM_SIZE);
1168 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1169 psp->fence_buf_mc_addr);
1172 psp->ras.session_id = cmd->resp.session_id;
1174 if (!ras_cmd->ras_status)
1175 psp->ras.ras_initialized = true;
1177 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1180 if (ret || ras_cmd->ras_status)
1181 amdgpu_ras_fini(psp->adev);
1188 static int psp_ras_unload(struct psp_context *psp)
1191 struct psp_gfx_cmd_resp *cmd;
1194 * TODO: bypass the unloading in sriov for now
1196 if (amdgpu_sriov_vf(psp->adev))
1199 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1203 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
1205 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1206 psp->fence_buf_mc_addr);
1213 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1215 struct ta_ras_shared_memory *ras_cmd;
1218 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1221 * TODO: bypass the loading in sriov for now
1223 if (amdgpu_sriov_vf(psp->adev))
1226 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1228 if (amdgpu_ras_intr_triggered())
1231 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1233 DRM_WARN("RAS: Unsupported Interface");
1238 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1239 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1241 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1243 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1244 dev_warn(psp->adev->dev,
1245 "RAS internal register access blocked\n");
1251 static int psp_ras_status_to_errno(struct amdgpu_device *adev,
1252 enum ta_ras_status ras_status)
1256 switch (ras_status) {
1257 case TA_RAS_STATUS__SUCCESS:
1260 case TA_RAS_STATUS__RESET_NEEDED:
1263 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
1264 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");
1266 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:
1267 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");
1270 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);
1276 int psp_ras_enable_features(struct psp_context *psp,
1277 union ta_ras_cmd_input *info, bool enable)
1279 struct ta_ras_shared_memory *ras_cmd;
1282 if (!psp->ras.ras_initialized)
1285 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1286 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1289 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1291 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1293 ras_cmd->ras_in_message = *info;
1295 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1299 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1302 static int psp_ras_terminate(struct psp_context *psp)
1307 * TODO: bypass the terminate in sriov for now
1309 if (amdgpu_sriov_vf(psp->adev))
1312 if (!psp->ras.ras_initialized)
1315 ret = psp_ras_unload(psp);
1319 psp->ras.ras_initialized = false;
1321 /* free ras shared memory */
1322 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1323 &psp->ras.ras_shared_mc_addr,
1324 &psp->ras.ras_shared_buf);
1329 static int psp_ras_initialize(struct psp_context *psp)
1332 uint32_t boot_cfg = 0xFF;
1333 struct amdgpu_device *adev = psp->adev;
1336 * TODO: bypass the initialize in sriov for now
1338 if (amdgpu_sriov_vf(adev))
1341 if (!adev->psp.ta_ras_ucode_size ||
1342 !adev->psp.ta_ras_start_addr) {
1343 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1347 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1348 /* query GECC enablement status from boot config
1349 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1351 ret = psp_boot_config_get(adev, &boot_cfg);
1353 dev_warn(adev->dev, "PSP get boot config failed\n");
1355 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1357 dev_info(adev->dev, "GECC is disabled\n");
1359 /* disable GECC in next boot cycle if ras is
1360 * disabled by module parameter amdgpu_ras_enable
1361 * and/or amdgpu_ras_mask, or boot_config_get call
1364 ret = psp_boot_config_set(adev, 0);
1366 dev_warn(adev->dev, "PSP set boot config failed\n");
1368 dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1369 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1372 if (1 == boot_cfg) {
1373 dev_info(adev->dev, "GECC is enabled\n");
1375 /* enable GECC in next boot cycle if it is disabled
1376 * in boot config, or force enable GECC if failed to
1377 * get boot configuration
1379 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1381 dev_warn(adev->dev, "PSP set boot config failed\n");
1383 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1388 if (!psp->ras.ras_initialized) {
1389 ret = psp_ras_init_shared_buf(psp);
1394 ret = psp_ras_load(psp);
1401 int psp_ras_trigger_error(struct psp_context *psp,
1402 struct ta_ras_trigger_error_input *info)
1404 struct ta_ras_shared_memory *ras_cmd;
1407 if (!psp->ras.ras_initialized)
1410 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1411 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1413 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1414 ras_cmd->ras_in_message.trigger_error = *info;
1416 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1420 /* If err_event_athub occurs error inject was successful, however
1421 return status from TA is no long reliable */
1422 if (amdgpu_ras_intr_triggered())
1425 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1430 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1435 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1436 * physical) for hdcp ta <-> Driver
1438 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1439 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1440 &psp->hdcp_context.hdcp_shared_bo,
1441 &psp->hdcp_context.hdcp_shared_mc_addr,
1442 &psp->hdcp_context.hdcp_shared_buf);
1447 static int psp_hdcp_load(struct psp_context *psp)
1450 struct psp_gfx_cmd_resp *cmd;
1453 * TODO: bypass the loading in sriov for now
1455 if (amdgpu_sriov_vf(psp->adev))
1458 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1462 psp_copy_fw(psp, psp->ta_hdcp_start_addr,
1463 psp->ta_hdcp_ucode_size);
1465 psp_prep_ta_load_cmd_buf(cmd,
1466 psp->fw_pri_mc_addr,
1467 psp->ta_hdcp_ucode_size,
1468 psp->hdcp_context.hdcp_shared_mc_addr,
1469 PSP_HDCP_SHARED_MEM_SIZE);
1471 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1474 psp->hdcp_context.hdcp_initialized = true;
1475 psp->hdcp_context.session_id = cmd->resp.session_id;
1476 mutex_init(&psp->hdcp_context.mutex);
1483 static int psp_hdcp_initialize(struct psp_context *psp)
1488 * TODO: bypass the initialize in sriov for now
1490 if (amdgpu_sriov_vf(psp->adev))
1493 if (!psp->adev->psp.ta_hdcp_ucode_size ||
1494 !psp->adev->psp.ta_hdcp_start_addr) {
1495 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1499 if (!psp->hdcp_context.hdcp_initialized) {
1500 ret = psp_hdcp_init_shared_buf(psp);
1505 ret = psp_hdcp_load(psp);
1512 static int psp_hdcp_unload(struct psp_context *psp)
1515 struct psp_gfx_cmd_resp *cmd;
1518 * TODO: bypass the unloading in sriov for now
1520 if (amdgpu_sriov_vf(psp->adev))
1523 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1527 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1529 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1536 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1539 * TODO: bypass the loading in sriov for now
1541 if (amdgpu_sriov_vf(psp->adev))
1544 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1547 static int psp_hdcp_terminate(struct psp_context *psp)
1552 * TODO: bypass the terminate in sriov for now
1554 if (amdgpu_sriov_vf(psp->adev))
1557 if (!psp->hdcp_context.hdcp_initialized) {
1558 if (psp->hdcp_context.hdcp_shared_buf)
1564 ret = psp_hdcp_unload(psp);
1568 psp->hdcp_context.hdcp_initialized = false;
1571 /* free hdcp shared memory */
1572 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1573 &psp->hdcp_context.hdcp_shared_mc_addr,
1574 &psp->hdcp_context.hdcp_shared_buf);
1581 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1586 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1587 * physical) for dtm ta <-> Driver
1589 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1590 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1591 &psp->dtm_context.dtm_shared_bo,
1592 &psp->dtm_context.dtm_shared_mc_addr,
1593 &psp->dtm_context.dtm_shared_buf);
1598 static int psp_dtm_load(struct psp_context *psp)
1601 struct psp_gfx_cmd_resp *cmd;
1604 * TODO: bypass the loading in sriov for now
1606 if (amdgpu_sriov_vf(psp->adev))
1609 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1613 psp_copy_fw(psp, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1615 psp_prep_ta_load_cmd_buf(cmd,
1616 psp->fw_pri_mc_addr,
1617 psp->ta_dtm_ucode_size,
1618 psp->dtm_context.dtm_shared_mc_addr,
1619 PSP_DTM_SHARED_MEM_SIZE);
1621 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1624 psp->dtm_context.dtm_initialized = true;
1625 psp->dtm_context.session_id = cmd->resp.session_id;
1626 mutex_init(&psp->dtm_context.mutex);
1634 static int psp_dtm_initialize(struct psp_context *psp)
1639 * TODO: bypass the initialize in sriov for now
1641 if (amdgpu_sriov_vf(psp->adev))
1644 if (!psp->adev->psp.ta_dtm_ucode_size ||
1645 !psp->adev->psp.ta_dtm_start_addr) {
1646 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1650 if (!psp->dtm_context.dtm_initialized) {
1651 ret = psp_dtm_init_shared_buf(psp);
1656 ret = psp_dtm_load(psp);
1663 static int psp_dtm_unload(struct psp_context *psp)
1666 struct psp_gfx_cmd_resp *cmd;
1669 * TODO: bypass the unloading in sriov for now
1671 if (amdgpu_sriov_vf(psp->adev))
1674 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1678 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1680 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1687 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1690 * TODO: bypass the loading in sriov for now
1692 if (amdgpu_sriov_vf(psp->adev))
1695 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1698 static int psp_dtm_terminate(struct psp_context *psp)
1703 * TODO: bypass the terminate in sriov for now
1705 if (amdgpu_sriov_vf(psp->adev))
1708 if (!psp->dtm_context.dtm_initialized) {
1709 if (psp->dtm_context.dtm_shared_buf)
1715 ret = psp_dtm_unload(psp);
1719 psp->dtm_context.dtm_initialized = false;
1722 /* free hdcp shared memory */
1723 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1724 &psp->dtm_context.dtm_shared_mc_addr,
1725 &psp->dtm_context.dtm_shared_buf);
1732 static int psp_rap_init_shared_buf(struct psp_context *psp)
1737 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1738 * physical) for rap ta <-> Driver
1740 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1741 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1742 &psp->rap_context.rap_shared_bo,
1743 &psp->rap_context.rap_shared_mc_addr,
1744 &psp->rap_context.rap_shared_buf);
1749 static int psp_rap_load(struct psp_context *psp)
1752 struct psp_gfx_cmd_resp *cmd;
1754 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1758 psp_copy_fw(psp, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1760 psp_prep_ta_load_cmd_buf(cmd,
1761 psp->fw_pri_mc_addr,
1762 psp->ta_rap_ucode_size,
1763 psp->rap_context.rap_shared_mc_addr,
1764 PSP_RAP_SHARED_MEM_SIZE);
1766 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1769 psp->rap_context.rap_initialized = true;
1770 psp->rap_context.session_id = cmd->resp.session_id;
1771 mutex_init(&psp->rap_context.mutex);
1779 static int psp_rap_unload(struct psp_context *psp)
1782 struct psp_gfx_cmd_resp *cmd;
1784 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1788 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1790 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1797 static int psp_rap_initialize(struct psp_context *psp)
1800 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1803 * TODO: bypass the initialize in sriov for now
1805 if (amdgpu_sriov_vf(psp->adev))
1808 if (!psp->adev->psp.ta_rap_ucode_size ||
1809 !psp->adev->psp.ta_rap_start_addr) {
1810 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1814 if (!psp->rap_context.rap_initialized) {
1815 ret = psp_rap_init_shared_buf(psp);
1820 ret = psp_rap_load(psp);
1824 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1825 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1826 psp_rap_unload(psp);
1828 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1829 &psp->rap_context.rap_shared_mc_addr,
1830 &psp->rap_context.rap_shared_buf);
1832 psp->rap_context.rap_initialized = false;
1834 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1843 static int psp_rap_terminate(struct psp_context *psp)
1847 if (!psp->rap_context.rap_initialized)
1850 ret = psp_rap_unload(psp);
1852 psp->rap_context.rap_initialized = false;
1854 /* free rap shared memory */
1855 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1856 &psp->rap_context.rap_shared_mc_addr,
1857 &psp->rap_context.rap_shared_buf);
1862 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1864 struct ta_rap_shared_memory *rap_cmd;
1867 if (!psp->rap_context.rap_initialized)
1870 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1871 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1874 mutex_lock(&psp->rap_context.mutex);
1876 rap_cmd = (struct ta_rap_shared_memory *)
1877 psp->rap_context.rap_shared_buf;
1878 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1880 rap_cmd->cmd_id = ta_cmd_id;
1881 rap_cmd->validation_method_id = METHOD_A;
1883 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1888 *status = rap_cmd->rap_status;
1891 mutex_unlock(&psp->rap_context.mutex);
1897 /* securedisplay start */
1898 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1903 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1904 * physical) for sa ta <-> Driver
1906 ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE,
1907 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1908 &psp->securedisplay_context.securedisplay_shared_bo,
1909 &psp->securedisplay_context.securedisplay_shared_mc_addr,
1910 &psp->securedisplay_context.securedisplay_shared_buf);
1915 static int psp_securedisplay_load(struct psp_context *psp)
1918 struct psp_gfx_cmd_resp *cmd;
1920 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1924 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1925 memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size);
1927 psp_prep_ta_load_cmd_buf(cmd,
1928 psp->fw_pri_mc_addr,
1929 psp->ta_securedisplay_ucode_size,
1930 psp->securedisplay_context.securedisplay_shared_mc_addr,
1931 PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
1933 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1938 psp->securedisplay_context.securedisplay_initialized = true;
1939 psp->securedisplay_context.session_id = cmd->resp.session_id;
1940 mutex_init(&psp->securedisplay_context.mutex);
1947 static int psp_securedisplay_unload(struct psp_context *psp)
1950 struct psp_gfx_cmd_resp *cmd;
1952 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1956 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id);
1958 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1965 static int psp_securedisplay_initialize(struct psp_context *psp)
1968 struct securedisplay_cmd *securedisplay_cmd;
1971 * TODO: bypass the initialize in sriov for now
1973 if (amdgpu_sriov_vf(psp->adev))
1976 if (!psp->adev->psp.ta_securedisplay_ucode_size ||
1977 !psp->adev->psp.ta_securedisplay_start_addr) {
1978 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1982 if (!psp->securedisplay_context.securedisplay_initialized) {
1983 ret = psp_securedisplay_init_shared_buf(psp);
1988 ret = psp_securedisplay_load(psp);
1992 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1993 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1995 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1997 psp_securedisplay_unload(psp);
1999 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
2000 &psp->securedisplay_context.securedisplay_shared_mc_addr,
2001 &psp->securedisplay_context.securedisplay_shared_buf);
2003 psp->securedisplay_context.securedisplay_initialized = false;
2005 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2009 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2010 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2011 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2012 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2018 static int psp_securedisplay_terminate(struct psp_context *psp)
2023 * TODO:bypass the terminate in sriov for now
2025 if (amdgpu_sriov_vf(psp->adev))
2028 if (!psp->securedisplay_context.securedisplay_initialized)
2031 ret = psp_securedisplay_unload(psp);
2035 psp->securedisplay_context.securedisplay_initialized = false;
2037 /* free securedisplay shared memory */
2038 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
2039 &psp->securedisplay_context.securedisplay_shared_mc_addr,
2040 &psp->securedisplay_context.securedisplay_shared_buf);
2045 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2049 if (!psp->securedisplay_context.securedisplay_initialized)
2052 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2053 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2056 mutex_lock(&psp->securedisplay_context.mutex);
2058 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id);
2060 mutex_unlock(&psp->securedisplay_context.mutex);
2064 /* SECUREDISPLAY end */
2066 static int psp_hw_start(struct psp_context *psp)
2068 struct amdgpu_device *adev = psp->adev;
2071 if (!amdgpu_sriov_vf(adev)) {
2072 if (psp->kdb_bin_size &&
2073 (psp->funcs->bootloader_load_kdb != NULL)) {
2074 ret = psp_bootloader_load_kdb(psp);
2076 DRM_ERROR("PSP load kdb failed!\n");
2081 if (psp->spl_bin_size) {
2082 ret = psp_bootloader_load_spl(psp);
2084 DRM_ERROR("PSP load spl failed!\n");
2089 ret = psp_bootloader_load_sysdrv(psp);
2091 DRM_ERROR("PSP load sysdrv failed!\n");
2095 ret = psp_bootloader_load_sos(psp);
2097 DRM_ERROR("PSP load sos failed!\n");
2102 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2104 DRM_ERROR("PSP create ring failed!\n");
2108 ret = psp_tmr_init(psp);
2110 DRM_ERROR("PSP tmr init failed!\n");
2115 * For ASICs with DF Cstate management centralized
2116 * to PMFW, TMR setup should be performed after PMFW
2117 * loaded and before other non-psp firmware loaded.
2119 if (psp->pmfw_centralized_cstate_management) {
2120 ret = psp_load_smu_fw(psp);
2125 ret = psp_tmr_load(psp);
2127 DRM_ERROR("PSP load tmr failed!\n");
2134 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2135 enum psp_gfx_fw_type *type)
2137 switch (ucode->ucode_id) {
2138 case AMDGPU_UCODE_ID_SDMA0:
2139 *type = GFX_FW_TYPE_SDMA0;
2141 case AMDGPU_UCODE_ID_SDMA1:
2142 *type = GFX_FW_TYPE_SDMA1;
2144 case AMDGPU_UCODE_ID_SDMA2:
2145 *type = GFX_FW_TYPE_SDMA2;
2147 case AMDGPU_UCODE_ID_SDMA3:
2148 *type = GFX_FW_TYPE_SDMA3;
2150 case AMDGPU_UCODE_ID_SDMA4:
2151 *type = GFX_FW_TYPE_SDMA4;
2153 case AMDGPU_UCODE_ID_SDMA5:
2154 *type = GFX_FW_TYPE_SDMA5;
2156 case AMDGPU_UCODE_ID_SDMA6:
2157 *type = GFX_FW_TYPE_SDMA6;
2159 case AMDGPU_UCODE_ID_SDMA7:
2160 *type = GFX_FW_TYPE_SDMA7;
2162 case AMDGPU_UCODE_ID_CP_MES:
2163 *type = GFX_FW_TYPE_CP_MES;
2165 case AMDGPU_UCODE_ID_CP_MES_DATA:
2166 *type = GFX_FW_TYPE_MES_STACK;
2168 case AMDGPU_UCODE_ID_CP_CE:
2169 *type = GFX_FW_TYPE_CP_CE;
2171 case AMDGPU_UCODE_ID_CP_PFP:
2172 *type = GFX_FW_TYPE_CP_PFP;
2174 case AMDGPU_UCODE_ID_CP_ME:
2175 *type = GFX_FW_TYPE_CP_ME;
2177 case AMDGPU_UCODE_ID_CP_MEC1:
2178 *type = GFX_FW_TYPE_CP_MEC;
2180 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2181 *type = GFX_FW_TYPE_CP_MEC_ME1;
2183 case AMDGPU_UCODE_ID_CP_MEC2:
2184 *type = GFX_FW_TYPE_CP_MEC;
2186 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2187 *type = GFX_FW_TYPE_CP_MEC_ME2;
2189 case AMDGPU_UCODE_ID_RLC_G:
2190 *type = GFX_FW_TYPE_RLC_G;
2192 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2193 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2195 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2196 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2198 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2199 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2201 case AMDGPU_UCODE_ID_RLC_IRAM:
2202 *type = GFX_FW_TYPE_RLC_IRAM;
2204 case AMDGPU_UCODE_ID_RLC_DRAM:
2205 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2207 case AMDGPU_UCODE_ID_SMC:
2208 *type = GFX_FW_TYPE_SMU;
2210 case AMDGPU_UCODE_ID_UVD:
2211 *type = GFX_FW_TYPE_UVD;
2213 case AMDGPU_UCODE_ID_UVD1:
2214 *type = GFX_FW_TYPE_UVD1;
2216 case AMDGPU_UCODE_ID_VCE:
2217 *type = GFX_FW_TYPE_VCE;
2219 case AMDGPU_UCODE_ID_VCN:
2220 *type = GFX_FW_TYPE_VCN;
2222 case AMDGPU_UCODE_ID_VCN1:
2223 *type = GFX_FW_TYPE_VCN1;
2225 case AMDGPU_UCODE_ID_DMCU_ERAM:
2226 *type = GFX_FW_TYPE_DMCU_ERAM;
2228 case AMDGPU_UCODE_ID_DMCU_INTV:
2229 *type = GFX_FW_TYPE_DMCU_ISR;
2231 case AMDGPU_UCODE_ID_VCN0_RAM:
2232 *type = GFX_FW_TYPE_VCN0_RAM;
2234 case AMDGPU_UCODE_ID_VCN1_RAM:
2235 *type = GFX_FW_TYPE_VCN1_RAM;
2237 case AMDGPU_UCODE_ID_DMCUB:
2238 *type = GFX_FW_TYPE_DMUB;
2240 case AMDGPU_UCODE_ID_MAXIMUM:
2248 static void psp_print_fw_hdr(struct psp_context *psp,
2249 struct amdgpu_firmware_info *ucode)
2251 struct amdgpu_device *adev = psp->adev;
2252 struct common_firmware_header *hdr;
2254 switch (ucode->ucode_id) {
2255 case AMDGPU_UCODE_ID_SDMA0:
2256 case AMDGPU_UCODE_ID_SDMA1:
2257 case AMDGPU_UCODE_ID_SDMA2:
2258 case AMDGPU_UCODE_ID_SDMA3:
2259 case AMDGPU_UCODE_ID_SDMA4:
2260 case AMDGPU_UCODE_ID_SDMA5:
2261 case AMDGPU_UCODE_ID_SDMA6:
2262 case AMDGPU_UCODE_ID_SDMA7:
2263 hdr = (struct common_firmware_header *)
2264 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2265 amdgpu_ucode_print_sdma_hdr(hdr);
2267 case AMDGPU_UCODE_ID_CP_CE:
2268 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2269 amdgpu_ucode_print_gfx_hdr(hdr);
2271 case AMDGPU_UCODE_ID_CP_PFP:
2272 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2273 amdgpu_ucode_print_gfx_hdr(hdr);
2275 case AMDGPU_UCODE_ID_CP_ME:
2276 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2277 amdgpu_ucode_print_gfx_hdr(hdr);
2279 case AMDGPU_UCODE_ID_CP_MEC1:
2280 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2281 amdgpu_ucode_print_gfx_hdr(hdr);
2283 case AMDGPU_UCODE_ID_RLC_G:
2284 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2285 amdgpu_ucode_print_rlc_hdr(hdr);
2287 case AMDGPU_UCODE_ID_SMC:
2288 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2289 amdgpu_ucode_print_smc_hdr(hdr);
2296 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2297 struct psp_gfx_cmd_resp *cmd)
2300 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2302 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
2304 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2305 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2306 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2307 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2309 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2311 DRM_ERROR("Unknown firmware type\n");
2316 static int psp_execute_np_fw_load(struct psp_context *psp,
2317 struct amdgpu_firmware_info *ucode)
2321 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
2325 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
2326 psp->fence_buf_mc_addr);
2331 static int psp_load_smu_fw(struct psp_context *psp)
2334 struct amdgpu_device *adev = psp->adev;
2335 struct amdgpu_firmware_info *ucode =
2336 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2337 struct amdgpu_ras *ras = psp->ras.ras;
2339 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2342 if ((amdgpu_in_reset(adev) &&
2343 ras && adev->ras_enabled &&
2344 (adev->asic_type == CHIP_ARCTURUS ||
2345 adev->asic_type == CHIP_VEGA20))) {
2346 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2348 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2352 ret = psp_execute_np_fw_load(psp, ucode);
2355 DRM_ERROR("PSP load smu failed!\n");
2360 static bool fw_load_skip_check(struct psp_context *psp,
2361 struct amdgpu_firmware_info *ucode)
2366 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2367 (psp_smu_reload_quirk(psp) ||
2368 psp->autoload_supported ||
2369 psp->pmfw_centralized_cstate_management))
2372 if (amdgpu_sriov_vf(psp->adev) &&
2373 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2374 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2375 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2376 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2377 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2378 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2379 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2380 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2381 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2382 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2383 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2384 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2385 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2386 /*skip ucode loading in SRIOV VF */
2389 if (psp->autoload_supported &&
2390 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2391 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2392 /* skip mec JT when autoload is enabled */
2398 int psp_load_fw_list(struct psp_context *psp,
2399 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2402 struct amdgpu_firmware_info *ucode;
2404 for (i = 0; i < ucode_count; ++i) {
2405 ucode = ucode_list[i];
2406 psp_print_fw_hdr(psp, ucode);
2407 ret = psp_execute_np_fw_load(psp, ucode);
2414 static int psp_np_fw_load(struct psp_context *psp)
2417 struct amdgpu_firmware_info *ucode;
2418 struct amdgpu_device *adev = psp->adev;
2420 if (psp->autoload_supported &&
2421 !psp->pmfw_centralized_cstate_management) {
2422 ret = psp_load_smu_fw(psp);
2427 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2428 ucode = &adev->firmware.ucode[i];
2430 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2431 !fw_load_skip_check(psp, ucode)) {
2432 ret = psp_load_smu_fw(psp);
2438 if (fw_load_skip_check(psp, ucode))
2441 if (psp->autoload_supported &&
2442 (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2443 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2444 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2445 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2446 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2447 /* PSP only receive one SDMA fw for sienna_cichlid,
2448 * as all four sdma fw are same */
2451 psp_print_fw_hdr(psp, ucode);
2453 ret = psp_execute_np_fw_load(psp, ucode);
2457 /* Start rlc autoload after psp recieved all the gfx firmware */
2458 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2459 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2460 ret = psp_rlc_autoload_start(psp);
2462 DRM_ERROR("Failed to start rlc autoload\n");
2471 static int psp_load_fw(struct amdgpu_device *adev)
2474 struct psp_context *psp = &adev->psp;
2476 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2477 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2481 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2485 if (amdgpu_sriov_vf(adev)) {
2486 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2487 AMDGPU_GEM_DOMAIN_VRAM,
2489 &psp->fw_pri_mc_addr,
2492 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2493 AMDGPU_GEM_DOMAIN_GTT,
2495 &psp->fw_pri_mc_addr,
2502 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2503 AMDGPU_GEM_DOMAIN_VRAM,
2505 &psp->fence_buf_mc_addr,
2510 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2511 AMDGPU_GEM_DOMAIN_VRAM,
2512 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2513 (void **)&psp->cmd_buf_mem);
2517 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2519 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2521 DRM_ERROR("PSP ring init failed!\n");
2526 ret = psp_hw_start(psp);
2530 ret = psp_np_fw_load(psp);
2534 ret = psp_asd_load(psp);
2536 DRM_ERROR("PSP load asd failed!\n");
2540 ret = psp_rl_load(adev);
2542 DRM_ERROR("PSP load RL failed!\n");
2546 if (psp->adev->psp.ta_fw) {
2547 ret = psp_ras_initialize(psp);
2549 dev_err(psp->adev->dev,
2550 "RAS: Failed to initialize RAS\n");
2552 ret = psp_hdcp_initialize(psp);
2554 dev_err(psp->adev->dev,
2555 "HDCP: Failed to initialize HDCP\n");
2557 ret = psp_dtm_initialize(psp);
2559 dev_err(psp->adev->dev,
2560 "DTM: Failed to initialize DTM\n");
2562 ret = psp_rap_initialize(psp);
2564 dev_err(psp->adev->dev,
2565 "RAP: Failed to initialize RAP\n");
2567 ret = psp_securedisplay_initialize(psp);
2569 dev_err(psp->adev->dev,
2570 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2577 * all cleanup jobs (xgmi terminate, ras terminate,
2578 * ring destroy, cmd/fence/fw buffers destory,
2579 * psp->cmd destory) are delayed to psp_hw_fini
2584 static int psp_hw_init(void *handle)
2587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2589 mutex_lock(&adev->firmware.mutex);
2591 * This sequence is just used on hw_init only once, no need on
2594 ret = amdgpu_ucode_init_bo(adev);
2598 ret = psp_load_fw(adev);
2600 DRM_ERROR("PSP firmware loading failed\n");
2604 mutex_unlock(&adev->firmware.mutex);
2608 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2609 mutex_unlock(&adev->firmware.mutex);
2613 static int psp_hw_fini(void *handle)
2615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2616 struct psp_context *psp = &adev->psp;
2618 if (psp->adev->psp.ta_fw) {
2619 psp_ras_terminate(psp);
2620 psp_securedisplay_terminate(psp);
2621 psp_rap_terminate(psp);
2622 psp_dtm_terminate(psp);
2623 psp_hdcp_terminate(psp);
2626 psp_asd_unload(psp);
2628 psp_tmr_terminate(psp);
2629 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2631 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2632 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2633 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2634 &psp->fence_buf_mc_addr, &psp->fence_buf);
2635 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2636 (void **)&psp->cmd_buf_mem);
2644 static int psp_suspend(void *handle)
2647 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2648 struct psp_context *psp = &adev->psp;
2650 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2651 psp->xgmi_context.initialized == 1) {
2652 ret = psp_xgmi_terminate(psp);
2654 DRM_ERROR("Failed to terminate xgmi ta\n");
2659 if (psp->adev->psp.ta_fw) {
2660 ret = psp_ras_terminate(psp);
2662 DRM_ERROR("Failed to terminate ras ta\n");
2665 ret = psp_hdcp_terminate(psp);
2667 DRM_ERROR("Failed to terminate hdcp ta\n");
2670 ret = psp_dtm_terminate(psp);
2672 DRM_ERROR("Failed to terminate dtm ta\n");
2675 ret = psp_rap_terminate(psp);
2677 DRM_ERROR("Failed to terminate rap ta\n");
2680 ret = psp_securedisplay_terminate(psp);
2682 DRM_ERROR("Failed to terminate securedisplay ta\n");
2687 ret = psp_asd_unload(psp);
2689 DRM_ERROR("Failed to unload asd\n");
2693 ret = psp_tmr_terminate(psp);
2695 DRM_ERROR("Failed to terminate tmr\n");
2699 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2701 DRM_ERROR("PSP ring stop failed\n");
2708 static int psp_resume(void *handle)
2711 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2712 struct psp_context *psp = &adev->psp;
2714 DRM_INFO("PSP is resuming...\n");
2716 if (psp->mem_train_ctx.enable_mem_training) {
2717 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2719 DRM_ERROR("Failed to process memory training!\n");
2724 mutex_lock(&adev->firmware.mutex);
2726 ret = psp_hw_start(psp);
2730 ret = psp_np_fw_load(psp);
2734 ret = psp_asd_load(psp);
2736 DRM_ERROR("PSP load asd failed!\n");
2740 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2741 ret = psp_xgmi_initialize(psp);
2742 /* Warning the XGMI seesion initialize failure
2743 * Instead of stop driver initialization
2746 dev_err(psp->adev->dev,
2747 "XGMI: Failed to initialize XGMI session\n");
2750 if (psp->adev->psp.ta_fw) {
2751 ret = psp_ras_initialize(psp);
2753 dev_err(psp->adev->dev,
2754 "RAS: Failed to initialize RAS\n");
2756 ret = psp_hdcp_initialize(psp);
2758 dev_err(psp->adev->dev,
2759 "HDCP: Failed to initialize HDCP\n");
2761 ret = psp_dtm_initialize(psp);
2763 dev_err(psp->adev->dev,
2764 "DTM: Failed to initialize DTM\n");
2766 ret = psp_rap_initialize(psp);
2768 dev_err(psp->adev->dev,
2769 "RAP: Failed to initialize RAP\n");
2771 ret = psp_securedisplay_initialize(psp);
2773 dev_err(psp->adev->dev,
2774 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2777 mutex_unlock(&adev->firmware.mutex);
2782 DRM_ERROR("PSP resume failed\n");
2783 mutex_unlock(&adev->firmware.mutex);
2787 int psp_gpu_reset(struct amdgpu_device *adev)
2791 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2794 mutex_lock(&adev->psp.mutex);
2795 ret = psp_mode1_reset(&adev->psp);
2796 mutex_unlock(&adev->psp.mutex);
2801 int psp_rlc_autoload_start(struct psp_context *psp)
2804 struct psp_gfx_cmd_resp *cmd;
2806 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2810 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2812 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2813 psp->fence_buf_mc_addr);
2818 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2819 uint64_t cmd_gpu_addr, int cmd_size)
2821 struct amdgpu_firmware_info ucode = {0};
2823 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2824 AMDGPU_UCODE_ID_VCN0_RAM;
2825 ucode.mc_addr = cmd_gpu_addr;
2826 ucode.ucode_size = cmd_size;
2828 return psp_execute_np_fw_load(&adev->psp, &ucode);
2831 int psp_ring_cmd_submit(struct psp_context *psp,
2832 uint64_t cmd_buf_mc_addr,
2833 uint64_t fence_mc_addr,
2836 unsigned int psp_write_ptr_reg = 0;
2837 struct psp_gfx_rb_frame *write_frame;
2838 struct psp_ring *ring = &psp->km_ring;
2839 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2840 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2841 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2842 struct amdgpu_device *adev = psp->adev;
2843 uint32_t ring_size_dw = ring->ring_size / 4;
2844 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2846 /* KM (GPCOM) prepare write pointer */
2847 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2849 /* Update KM RB frame pointer to new frame */
2850 /* write_frame ptr increments by size of rb_frame in bytes */
2851 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2852 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2853 write_frame = ring_buffer_start;
2855 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2856 /* Check invalid write_frame ptr address */
2857 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2858 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2859 ring_buffer_start, ring_buffer_end, write_frame);
2860 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2864 /* Initialize KM RB frame */
2865 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2867 /* Update KM RB frame */
2868 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2869 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2870 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2871 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2872 write_frame->fence_value = index;
2873 amdgpu_device_flush_hdp(adev, NULL);
2875 /* Update the write Pointer in DWORDs */
2876 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2877 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2881 int psp_init_asd_microcode(struct psp_context *psp,
2882 const char *chip_name)
2884 struct amdgpu_device *adev = psp->adev;
2885 char fw_name[PSP_FW_NAME_LEN];
2886 const struct psp_firmware_header_v1_0 *asd_hdr;
2890 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2894 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2895 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2899 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2903 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2904 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2905 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2906 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2907 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2908 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2911 dev_err(adev->dev, "fail to initialize asd microcode\n");
2912 release_firmware(adev->psp.asd_fw);
2913 adev->psp.asd_fw = NULL;
2917 int psp_init_toc_microcode(struct psp_context *psp,
2918 const char *chip_name)
2920 struct amdgpu_device *adev = psp->adev;
2922 const struct psp_firmware_header_v1_0 *toc_hdr;
2926 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2930 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2931 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2935 err = amdgpu_ucode_validate(adev->psp.toc_fw);
2939 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2940 adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2941 adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2942 adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2943 adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2944 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2947 dev_err(adev->dev, "fail to request/validate toc microcode\n");
2948 release_firmware(adev->psp.toc_fw);
2949 adev->psp.toc_fw = NULL;
2953 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
2955 const struct psp_firmware_header_v1_0 *sos_hdr;
2956 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2957 uint8_t *ucode_array_start_addr;
2959 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2960 ucode_array_start_addr = (uint8_t *)sos_hdr +
2961 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2963 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) {
2964 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2965 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
2967 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos.offset_bytes);
2968 adev->psp.sys_start_addr = ucode_array_start_addr;
2970 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos.size_bytes);
2971 adev->psp.sos_start_addr = ucode_array_start_addr +
2972 le32_to_cpu(sos_hdr->sos.offset_bytes);
2974 /* Load alternate PSP SOS FW */
2975 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2977 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2978 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2980 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
2981 adev->psp.sys_start_addr = ucode_array_start_addr +
2982 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
2984 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
2985 adev->psp.sos_start_addr = ucode_array_start_addr +
2986 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
2989 if ((adev->psp.sys_bin_size == 0) || (adev->psp.sos_bin_size == 0)) {
2990 dev_warn(adev->dev, "PSP SOS FW not available");
2997 int psp_init_sos_microcode(struct psp_context *psp,
2998 const char *chip_name)
3000 struct amdgpu_device *adev = psp->adev;
3001 char fw_name[PSP_FW_NAME_LEN];
3002 const struct psp_firmware_header_v1_0 *sos_hdr;
3003 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3004 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3005 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3007 uint8_t *ucode_array_start_addr;
3010 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3014 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3015 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3019 err = amdgpu_ucode_validate(adev->psp.sos_fw);
3023 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3024 ucode_array_start_addr = (uint8_t *)sos_hdr +
3025 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3026 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3028 switch (sos_hdr->header.header_version_major) {
3030 err = psp_init_sos_base_fw(adev);
3034 if (sos_hdr->header.header_version_minor == 1) {
3035 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3036 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3037 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
3038 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3039 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3040 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
3041 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3043 if (sos_hdr->header.header_version_minor == 2) {
3044 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3045 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3046 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
3047 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3049 if (sos_hdr->header.header_version_minor == 3) {
3050 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3051 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3052 adev->psp.toc_start_addr = ucode_array_start_addr +
3053 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3054 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3055 adev->psp.kdb_start_addr = ucode_array_start_addr +
3056 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3057 adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3058 adev->psp.spl_start_addr = ucode_array_start_addr +
3059 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3060 adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3061 adev->psp.rl_start_addr = ucode_array_start_addr +
3062 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3067 "unsupported psp sos firmware\n");
3075 "failed to init sos firmware\n");
3076 release_firmware(adev->psp.sos_fw);
3077 adev->psp.sos_fw = NULL;
3082 static int parse_ta_bin_descriptor(struct psp_context *psp,
3083 const struct ta_fw_bin_desc *desc,
3084 const struct ta_firmware_header_v2_0 *ta_hdr)
3086 uint8_t *ucode_start_addr = NULL;
3088 if (!psp || !desc || !ta_hdr)
3091 ucode_start_addr = (uint8_t *)ta_hdr +
3092 le32_to_cpu(desc->offset_bytes) +
3093 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3095 switch (desc->fw_type) {
3096 case TA_FW_TYPE_PSP_ASD:
3097 psp->asd_fw_version = le32_to_cpu(desc->fw_version);
3098 psp->asd_feature_version = le32_to_cpu(desc->fw_version);
3099 psp->asd_ucode_size = le32_to_cpu(desc->size_bytes);
3100 psp->asd_start_addr = ucode_start_addr;
3102 case TA_FW_TYPE_PSP_XGMI:
3103 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
3104 psp->ta_xgmi_ucode_size = le32_to_cpu(desc->size_bytes);
3105 psp->ta_xgmi_start_addr = ucode_start_addr;
3107 case TA_FW_TYPE_PSP_RAS:
3108 psp->ta_ras_ucode_version = le32_to_cpu(desc->fw_version);
3109 psp->ta_ras_ucode_size = le32_to_cpu(desc->size_bytes);
3110 psp->ta_ras_start_addr = ucode_start_addr;
3112 case TA_FW_TYPE_PSP_HDCP:
3113 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
3114 psp->ta_hdcp_ucode_size = le32_to_cpu(desc->size_bytes);
3115 psp->ta_hdcp_start_addr = ucode_start_addr;
3117 case TA_FW_TYPE_PSP_DTM:
3118 psp->ta_dtm_ucode_version = le32_to_cpu(desc->fw_version);
3119 psp->ta_dtm_ucode_size = le32_to_cpu(desc->size_bytes);
3120 psp->ta_dtm_start_addr = ucode_start_addr;
3122 case TA_FW_TYPE_PSP_RAP:
3123 psp->ta_rap_ucode_version = le32_to_cpu(desc->fw_version);
3124 psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes);
3125 psp->ta_rap_start_addr = ucode_start_addr;
3127 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3128 psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version);
3129 psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes);
3130 psp->ta_securedisplay_start_addr = ucode_start_addr;
3133 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3140 int psp_init_ta_microcode(struct psp_context *psp,
3141 const char *chip_name)
3143 struct amdgpu_device *adev = psp->adev;
3144 char fw_name[PSP_FW_NAME_LEN];
3145 const struct ta_firmware_header_v2_0 *ta_hdr;
3150 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3154 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3155 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3159 err = amdgpu_ucode_validate(adev->psp.ta_fw);
3163 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3165 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3166 dev_err(adev->dev, "unsupported TA header version\n");
3171 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
3172 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3177 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3178 err = parse_ta_bin_descriptor(psp,
3179 &ta_hdr->ta_fw_bin[ta_index],
3187 dev_err(adev->dev, "fail to initialize ta microcode\n");
3188 release_firmware(adev->psp.ta_fw);
3189 adev->psp.ta_fw = NULL;
3193 static int psp_set_clockgating_state(void *handle,
3194 enum amd_clockgating_state state)
3199 static int psp_set_powergating_state(void *handle,
3200 enum amd_powergating_state state)
3205 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3206 struct device_attribute *attr,
3209 struct drm_device *ddev = dev_get_drvdata(dev);
3210 struct amdgpu_device *adev = drm_to_adev(ddev);
3214 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3215 DRM_INFO("PSP block is not ready yet.");
3219 mutex_lock(&adev->psp.mutex);
3220 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3221 mutex_unlock(&adev->psp.mutex);
3224 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3228 return sysfs_emit(buf, "%x\n", fw_ver);
3231 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3232 struct device_attribute *attr,
3236 struct drm_device *ddev = dev_get_drvdata(dev);
3237 struct amdgpu_device *adev = drm_to_adev(ddev);
3239 dma_addr_t dma_addr;
3242 const struct firmware *usbc_pd_fw;
3244 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3245 DRM_INFO("PSP block is not ready yet.");
3249 if (!drm_dev_enter(ddev, &idx))
3252 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3253 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3257 /* We need contiguous physical mem to place the FW for psp to access */
3258 cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
3260 ret = dma_mapping_error(adev->dev, dma_addr);
3264 memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3267 * x86 specific workaround.
3268 * Without it the buffer is invisible in PSP.
3270 * TODO Remove once PSP starts snooping CPU cache
3273 clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
3276 mutex_lock(&adev->psp.mutex);
3277 ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
3278 mutex_unlock(&adev->psp.mutex);
3281 dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
3282 release_firmware(usbc_pd_fw);
3285 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3293 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3297 if (!drm_dev_enter(&psp->adev->ddev, &idx))
3300 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3301 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3306 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3307 psp_usbc_pd_fw_sysfs_read,
3308 psp_usbc_pd_fw_sysfs_write);
3312 const struct amd_ip_funcs psp_ip_funcs = {
3314 .early_init = psp_early_init,
3316 .sw_init = psp_sw_init,
3317 .sw_fini = psp_sw_fini,
3318 .hw_init = psp_hw_init,
3319 .hw_fini = psp_hw_fini,
3320 .suspend = psp_suspend,
3321 .resume = psp_resume,
3323 .check_soft_reset = NULL,
3324 .wait_for_idle = NULL,
3326 .set_clockgating_state = psp_set_clockgating_state,
3327 .set_powergating_state = psp_set_powergating_state,
3330 static int psp_sysfs_init(struct amdgpu_device *adev)
3332 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3335 DRM_ERROR("Failed to create USBC PD FW control file!");
3340 static void psp_sysfs_fini(struct amdgpu_device *adev)
3342 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3345 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3347 .type = AMD_IP_BLOCK_TYPE_PSP,
3351 .funcs = &psp_ip_funcs,
3354 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3356 .type = AMD_IP_BLOCK_TYPE_PSP,
3360 .funcs = &psp_ip_funcs,
3363 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3365 .type = AMD_IP_BLOCK_TYPE_PSP,
3369 .funcs = &psp_ip_funcs,
3372 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3374 .type = AMD_IP_BLOCK_TYPE_PSP,
3378 .funcs = &psp_ip_funcs,
3381 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3382 .type = AMD_IP_BLOCK_TYPE_PSP,
3386 .funcs = &psp_ip_funcs,