drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include <asm/div64.h>
  34
  35 #include <linux/pci.h>
  36 #include <linux/pm_runtime.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_edid.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_fb_helper.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_vblank.h>
  43
  44 static void amdgpu_display_flip_callback(struct dma_fence *f,
  45                                          struct dma_fence_cb *cb)
  46 {
  47         struct amdgpu_flip_work *work =
  48                 container_of(cb, struct amdgpu_flip_work, cb);
  49
  50         dma_fence_put(f);
  51         schedule_work(&work->flip_work.work);
  52 }
  53
  54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  55                                              struct dma_fence **f)
  56 {
  57         struct dma_fence *fence= *f;
  58
  59         if (fence == NULL)
  60                 return false;
  61
  62         *f = NULL;
  63
  64         if (!dma_fence_add_callback(fence, &work->cb,
  65                                     amdgpu_display_flip_callback))
  66                 return true;
  67
  68         dma_fence_put(fence);
  69         return false;
  70 }
  71
  72 static void amdgpu_display_flip_work_func(struct work_struct *__work)
  73 {
  74         struct delayed_work *delayed_work =
  75                 container_of(__work, struct delayed_work, work);
  76         struct amdgpu_flip_work *work =
  77                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  78         struct amdgpu_device *adev = work->adev;
  79         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  80
  81         struct drm_crtc *crtc = &amdgpu_crtc->base;
  82         unsigned long flags;
  83         unsigned i;
  84         int vpos, hpos;
  85
  86         if (amdgpu_display_flip_handle_fence(work, &work->excl))
  87                 return;
  88
  89         for (i = 0; i < work->shared_count; ++i)
  90                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
  91                         return;
  92
  93         /* Wait until we're out of the vertical blank period before the one
  94          * targeted by the flip
  95          */
  96         if (amdgpu_crtc->enabled &&
  97             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
  98                                                 &vpos, &hpos, NULL, NULL,
  99                                                 &crtc->hwmode)
 100              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 101             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 102             (int)(work->target_vblank -
 103                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 104                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 105                 return;
 106         }
 107
 108         /* We borrow the event spin lock for protecting flip_status */
 109         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 110
 111         /* Do the flip (mmio) */
 112         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 113
 114         /* Set the flip status */
 115         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 116         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 117
 118
 119         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 120                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 121
 122 }
 123
 124 /*
 125  * Handle unpin events outside the interrupt handler proper.
 126  */
 127 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 128 {
 129         struct amdgpu_flip_work *work =
 130                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 131         int r;
 132
 133         /* unpin of the old buffer */
 134         r = amdgpu_bo_reserve(work->old_abo, true);
 135         if (likely(r == 0)) {
 136                 amdgpu_bo_unpin(work->old_abo);
 137                 amdgpu_bo_unreserve(work->old_abo);
 138         } else
 139                 DRM_ERROR("failed to reserve buffer after flip\n");
 140
 141         amdgpu_bo_unref(&work->old_abo);
 142         kfree(work->shared);
 143         kfree(work);
 144 }
 145
 146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 147                                 struct drm_framebuffer *fb,
 148                                 struct drm_pending_vblank_event *event,
 149                                 uint32_t page_flip_flags, uint32_t target,
 150                                 struct drm_modeset_acquire_ctx *ctx)
 151 {
 152         struct drm_device *dev = crtc->dev;
 153         struct amdgpu_device *adev = drm_to_adev(dev);
 154         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 155         struct drm_gem_object *obj;
 156         struct amdgpu_flip_work *work;
 157         struct amdgpu_bo *new_abo;
 158         unsigned long flags;
 159         u64 tiling_flags;
 160         int i, r;
 161
 162         work = kzalloc(sizeof *work, GFP_KERNEL);
 163         if (work == NULL)
 164                 return -ENOMEM;
 165
 166         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 167         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 168
 169         work->event = event;
 170         work->adev = adev;
 171         work->crtc_id = amdgpu_crtc->crtc_id;
 172         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 173
 174         /* schedule unpin of the old buffer */
 175         obj = crtc->primary->fb->obj[0];
 176
 177         /* take a reference to the old object */
 178         work->old_abo = gem_to_amdgpu_bo(obj);
 179         amdgpu_bo_ref(work->old_abo);
 180
 181         obj = fb->obj[0];
 182         new_abo = gem_to_amdgpu_bo(obj);
 183
 184         /* pin the new buffer */
 185         r = amdgpu_bo_reserve(new_abo, false);
 186         if (unlikely(r != 0)) {
 187                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 188                 goto cleanup;
 189         }
 190
 191         if (!adev->enable_virtual_display) {
 192                 r = amdgpu_bo_pin(new_abo,
 193                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 194                 if (unlikely(r != 0)) {
 195                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 196                         goto unreserve;
 197                 }
 198         }
 199
 200         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 201         if (unlikely(r != 0)) {
 202                 DRM_ERROR("%p bind failed\n", new_abo);
 203                 goto unpin;
 204         }
 205
 206         r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,
 207                                               &work->shared_count,
 208                                               &work->shared);
 209         if (unlikely(r != 0)) {
 210                 DRM_ERROR("failed to get fences for buffer\n");
 211                 goto unpin;
 212         }
 213
 214         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 215         amdgpu_bo_unreserve(new_abo);
 216
 217         if (!adev->enable_virtual_display)
 218                 work->base = amdgpu_bo_gpu_offset(new_abo);
 219         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 220                 amdgpu_get_vblank_counter_kms(crtc);
 221
 222         /* we borrow the event spin lock for protecting flip_wrok */
 223         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 224         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 225                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 226                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 227                 r = -EBUSY;
 228                 goto pflip_cleanup;
 229         }
 230
 231         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 232         amdgpu_crtc->pflip_works = work;
 233
 234
 235         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 236                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 237         /* update crtc fb */
 238         crtc->primary->fb = fb;
 239         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 240         amdgpu_display_flip_work_func(&work->flip_work.work);
 241         return 0;
 242
 243 pflip_cleanup:
 244         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 245                 DRM_ERROR("failed to reserve new abo in error path\n");
 246                 goto cleanup;
 247         }
 248 unpin:
 249         if (!adev->enable_virtual_display)
 250                 amdgpu_bo_unpin(new_abo);
 251
 252 unreserve:
 253         amdgpu_bo_unreserve(new_abo);
 254
 255 cleanup:
 256         amdgpu_bo_unref(&work->old_abo);
 257         dma_fence_put(work->excl);
 258         for (i = 0; i < work->shared_count; ++i)
 259                 dma_fence_put(work->shared[i]);
 260         kfree(work->shared);
 261         kfree(work);
 262
 263         return r;
 264 }
 265
 266 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 267                                    struct drm_modeset_acquire_ctx *ctx)
 268 {
 269         struct drm_device *dev;
 270         struct amdgpu_device *adev;
 271         struct drm_crtc *crtc;
 272         bool active = false;
 273         int ret;
 274
 275         if (!set || !set->crtc)
 276                 return -EINVAL;
 277
 278         dev = set->crtc->dev;
 279
 280         ret = pm_runtime_get_sync(dev->dev);
 281         if (ret < 0)
 282                 goto out;
 283
 284         ret = drm_crtc_helper_set_config(set, ctx);
 285
 286         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 287                 if (crtc->enabled)
 288                         active = true;
 289
 290         pm_runtime_mark_last_busy(dev->dev);
 291
 292         adev = drm_to_adev(dev);
 293         /* if we have active crtcs and we don't have a power ref,
 294            take the current one */
 295         if (active && !adev->have_disp_power_ref) {
 296                 adev->have_disp_power_ref = true;
 297                 return ret;
 298         }
 299         /* if we have no active crtcs, then drop the power ref
 300            we got before */
 301         if (!active && adev->have_disp_power_ref) {
 302                 pm_runtime_put_autosuspend(dev->dev);
 303                 adev->have_disp_power_ref = false;
 304         }
 305
 306 out:
 307         /* drop the power reference we got coming in here */
 308         pm_runtime_put_autosuspend(dev->dev);
 309         return ret;
 310 }
 311
 312 static const char *encoder_names[41] = {
 313         "NONE",
 314         "INTERNAL_LVDS",
 315         "INTERNAL_TMDS1",
 316         "INTERNAL_TMDS2",
 317         "INTERNAL_DAC1",
 318         "INTERNAL_DAC2",
 319         "INTERNAL_SDVOA",
 320         "INTERNAL_SDVOB",
 321         "SI170B",
 322         "CH7303",
 323         "CH7301",
 324         "INTERNAL_DVO1",
 325         "EXTERNAL_SDVOA",
 326         "EXTERNAL_SDVOB",
 327         "TITFP513",
 328         "INTERNAL_LVTM1",
 329         "VT1623",
 330         "HDMI_SI1930",
 331         "HDMI_INTERNAL",
 332         "INTERNAL_KLDSCP_TMDS1",
 333         "INTERNAL_KLDSCP_DVO1",
 334         "INTERNAL_KLDSCP_DAC1",
 335         "INTERNAL_KLDSCP_DAC2",
 336         "SI178",
 337         "MVPU_FPGA",
 338         "INTERNAL_DDI",
 339         "VT1625",
 340         "HDMI_SI1932",
 341         "DP_AN9801",
 342         "DP_DP501",
 343         "INTERNAL_UNIPHY",
 344         "INTERNAL_KLDSCP_LVTMA",
 345         "INTERNAL_UNIPHY1",
 346         "INTERNAL_UNIPHY2",
 347         "NUTMEG",
 348         "TRAVIS",
 349         "INTERNAL_VCE",
 350         "INTERNAL_UNIPHY3",
 351         "HDMI_ANX9805",
 352         "INTERNAL_AMCLK",
 353         "VIRTUAL",
 354 };
 355
 356 static const char *hpd_names[6] = {
 357         "HPD1",
 358         "HPD2",
 359         "HPD3",
 360         "HPD4",
 361         "HPD5",
 362         "HPD6",
 363 };
 364
 365 void amdgpu_display_print_display_setup(struct drm_device *dev)
 366 {
 367         struct drm_connector *connector;
 368         struct amdgpu_connector *amdgpu_connector;
 369         struct drm_encoder *encoder;
 370         struct amdgpu_encoder *amdgpu_encoder;
 371         struct drm_connector_list_iter iter;
 372         uint32_t devices;
 373         int i = 0;
 374
 375         drm_connector_list_iter_begin(dev, &iter);
 376         DRM_INFO("AMDGPU Display Connectors\n");
 377         drm_for_each_connector_iter(connector, &iter) {
 378                 amdgpu_connector = to_amdgpu_connector(connector);
 379                 DRM_INFO("Connector %d:\n", i);
 380                 DRM_INFO("  %s\n", connector->name);
 381                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 382                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 383                 if (amdgpu_connector->ddc_bus) {
 384                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 385                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 386                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 387                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 388                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 389                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 390                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 391                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 392                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 393                         if (amdgpu_connector->router.ddc_valid)
 394                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 395                                          amdgpu_connector->router.ddc_mux_control_pin,
 396                                          amdgpu_connector->router.ddc_mux_state);
 397                         if (amdgpu_connector->router.cd_valid)
 398                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 399                                          amdgpu_connector->router.cd_mux_control_pin,
 400                                          amdgpu_connector->router.cd_mux_state);
 401                 } else {
 402                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 403                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 404                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 405                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 406                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 407                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 408                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 409                 }
 410                 DRM_INFO("  Encoders:\n");
 411                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 412                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 413                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 414                         if (devices) {
 415                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 416                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 417                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 418                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 419                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 420                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 421                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 422                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 423                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 424                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 425                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 426                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 427                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 428                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 429                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 430                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 431                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 432                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 433                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 434                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 435                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 436                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 437                         }
 438                 }
 439                 i++;
 440         }
 441         drm_connector_list_iter_end(&iter);
 442 }
 443
 444 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 445                               bool use_aux)
 446 {
 447         u8 out = 0x0;
 448         u8 buf[8];
 449         int ret;
 450         struct i2c_msg msgs[] = {
 451                 {
 452                         .addr = DDC_ADDR,
 453                         .flags = 0,
 454                         .len = 1,
 455                         .buf = &out,
 456                 },
 457                 {
 458                         .addr = DDC_ADDR,
 459                         .flags = I2C_M_RD,
 460                         .len = 8,
 461                         .buf = buf,
 462                 }
 463         };
 464
 465         /* on hw with routers, select right port */
 466         if (amdgpu_connector->router.ddc_valid)
 467                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 468
 469         if (use_aux) {
 470                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 471         } else {
 472                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 473         }
 474
 475         if (ret != 2)
 476                 /* Couldn't find an accessible DDC on this connector */
 477                 return false;
 478         /* Probe also for valid EDID header
 479          * EDID header starts with:
 480          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 481          * Only the first 6 bytes must be valid as
 482          * drm_edid_block_valid() can fix the last 2 bytes */
 483         if (drm_edid_header_is_valid(buf) < 6) {
 484                 /* Couldn't find an accessible EDID on this
 485                  * connector */
 486                 return false;
 487         }
 488         return true;
 489 }
 490
 491 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 492         .destroy = drm_gem_fb_destroy,
 493         .create_handle = drm_gem_fb_create_handle,
 494 };
 495
 496 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 497                                           uint64_t bo_flags)
 498 {
 499         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 500
 501 #if defined(CONFIG_DRM_AMD_DC)
 502         /*
 503          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 504          * is not supported for this board. But this mapping is required
 505          * to avoid hang caused by placement of scanout BO in GTT on certain
 506          * APUs. So force the BO placement to VRAM in case this architecture
 507          * will not allow USWC mappings.
 508          * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 509          */
 510         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 511             amdgpu_bo_support_uswc(bo_flags) &&
 512             amdgpu_device_asic_has_dc_support(adev->asic_type)) {
 513                 switch (adev->asic_type) {
 514                 case CHIP_CARRIZO:
 515                 case CHIP_STONEY:
 516                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 517                         break;
 518                 case CHIP_RAVEN:
 519                         /* enable S/G on PCO and RV2 */
 520                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
 521                             (adev->apu_flags & AMD_APU_IS_PICASSO))
 522                                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 523                         break;
 524                 case CHIP_RENOIR:
 525                 case CHIP_VANGOGH:
 526                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 527                         break;
 528
 529                 default:
 530                         break;
 531                 }
 532         }
 533 #endif
 534
 535         return domain;
 536 }
 537
 538 static const struct drm_format_info dcc_formats[] = {
 539         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 540           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 541          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 542           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 543         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 544           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 545            .has_alpha = true, },
 546         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 547           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 548           .has_alpha = true, },
 549         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 550           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 551           .has_alpha = true, },
 552         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 553           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 554         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 555           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 556         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 557           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 558           .has_alpha = true, },
 559         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 560           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 561           .has_alpha = true, },
 562         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 563           .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 564 };
 565
 566 static const struct drm_format_info dcc_retile_formats[] = {
 567         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 568           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 569          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 570           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 571         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 572           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 573            .has_alpha = true, },
 574         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 575           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 576           .has_alpha = true, },
 577         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 578           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 579           .has_alpha = true, },
 580         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 581           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 582         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 583           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 584         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 585           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 586           .has_alpha = true, },
 587         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 588           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 589           .has_alpha = true, },
 590         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 591           .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 592 };
 593
 594 static const struct drm_format_info *
 595 lookup_format_info(const struct drm_format_info formats[],
 596                   int num_formats, u32 format)
 597 {
 598         int i;
 599
 600         for (i = 0; i < num_formats; i++) {
 601                 if (formats[i].format == format)
 602                         return &formats[i];
 603         }
 604
 605         return NULL;
 606 }
 607
 608 const struct drm_format_info *
 609 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 610 {
 611         if (!IS_AMD_FMT_MOD(modifier))
 612                 return NULL;
 613
 614         if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 615                 return lookup_format_info(dcc_retile_formats,
 616                                           ARRAY_SIZE(dcc_retile_formats),
 617                                           format);
 618
 619         if (AMD_FMT_MOD_GET(DCC, modifier))
 620                 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 621                                           format);
 622
 623         /* returning NULL will cause the default format structs to be used. */
 624         return NULL;
 625 }
 626
 627
 628 /*
 629  * Tries to extract the renderable DCC offset from the opaque metadata attached
 630  * to the buffer.
 631  */
 632 static int
 633 extract_render_dcc_offset(struct amdgpu_device *adev,
 634                           struct drm_gem_object *obj,
 635                           uint64_t *offset)
 636 {
 637         struct amdgpu_bo *rbo;
 638         int r = 0;
 639         uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 640         uint32_t size;
 641
 642         rbo = gem_to_amdgpu_bo(obj);
 643         r = amdgpu_bo_reserve(rbo, false);
 644
 645         if (unlikely(r)) {
 646                 /* Don't show error message when returning -ERESTARTSYS */
 647                 if (r != -ERESTARTSYS)
 648                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 649                 return r;
 650         }
 651
 652         r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 653         amdgpu_bo_unreserve(rbo);
 654
 655         if (r)
 656                 return r;
 657
 658         /*
 659          * The first word is the metadata version, and we need space for at least
 660          * the version + pci vendor+device id + 8 words for a descriptor.
 661          */
 662         if (size < 40  || metadata[0] != 1)
 663                 return -EINVAL;
 664
 665         if (adev->family >= AMDGPU_FAMILY_NV) {
 666                 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
 667                 *offset = ((u64)metadata[9] << 16u) |
 668                           ((metadata[8] & 0xFF000000u) >> 16);
 669         } else {
 670                 /* resource word 5/7 META_DATA_ADDRESS */
 671                 *offset = ((u64)metadata[9] << 8u) |
 672                           ((u64)(metadata[7] & 0x1FE0000u) << 23);
 673         }
 674
 675         return 0;
 676 }
 677
 678 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 679 {
 680         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 681         uint64_t modifier = 0;
 682
 683         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 684                 modifier = DRM_FORMAT_MOD_LINEAR;
 685         } else {
 686                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 687                 bool has_xor = swizzle >= 16;
 688                 int block_size_bits;
 689                 int version;
 690                 int pipe_xor_bits = 0;
 691                 int bank_xor_bits = 0;
 692                 int packers = 0;
 693                 int rb = 0;
 694                 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
 695                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 696
 697                 switch (swizzle >> 2) {
 698                 case 0: /* 256B */
 699                         block_size_bits = 8;
 700                         break;
 701                 case 1: /* 4KiB */
 702                 case 5: /* 4KiB _X */
 703                         block_size_bits = 12;
 704                         break;
 705                 case 2: /* 64KiB */
 706                 case 4: /* 64 KiB _T */
 707                 case 6: /* 64 KiB _X */
 708                         block_size_bits = 16;
 709                         break;
 710                 default:
 711                         /* RESERVED or VAR */
 712                         return -EINVAL;
 713                 }
 714
 715                 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 716                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 717                 else if (adev->family == AMDGPU_FAMILY_NV)
 718                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 719                 else
 720                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 721
 722                 switch (swizzle & 3) {
 723                 case 0: /* Z microtiling */
 724                         return -EINVAL;
 725                 case 1: /* S microtiling */
 726                         if (!has_xor)
 727                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 728                         break;
 729                 case 2:
 730                         if (!has_xor && afb->base.format->cpp[0] != 4)
 731                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 732                         break;
 733                 case 3:
 734                         break;
 735                 }
 736
 737                 if (has_xor) {
 738                         switch (version) {
 739                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 740                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 741                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 742                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 743                                 break;
 744                         case AMD_FMT_MOD_TILE_VER_GFX10:
 745                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 746                                 break;
 747                         case AMD_FMT_MOD_TILE_VER_GFX9:
 748                                 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 749                                      ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 750                                 pipe_xor_bits = min(block_size_bits - 8, pipes +
 751                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 752                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 753                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 754                                 break;
 755                         }
 756                 }
 757
 758                 modifier = AMD_FMT_MOD |
 759                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 760                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 761                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 762                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 763                            AMD_FMT_MOD_SET(PACKERS, packers);
 764
 765                 if (dcc_offset != 0) {
 766                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 767                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 768                         const struct drm_format_info *format_info;
 769                         u64 render_dcc_offset;
 770
 771                         /* Enable constant encode on RAVEN2 and later. */
 772                         bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
 773                                                    (adev->asic_type == CHIP_RAVEN &&
 774                                                     adev->external_rev_id >= 0x81);
 775
 776                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 777                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 778                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 779
 780                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 781                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 782                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 783                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 784                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 785
 786                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 787                         afb->base.pitches[1] =
 788                                 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 789
 790                         /*
 791                          * If the userspace driver uses retiling the tiling flags do not contain
 792                          * info on the renderable DCC buffer. Luckily the opaque metadata contains
 793                          * the info so we can try to extract it. The kernel does not use this info
 794                          * but we should convert it to a modifier plane for getfb2, so the
 795                          * userspace driver that gets it doesn't have to juggle around another DCC
 796                          * plane internally.
 797                          */
 798                         if (extract_render_dcc_offset(adev, afb->base.obj[0],
 799                                                       &render_dcc_offset) == 0 &&
 800                             render_dcc_offset != 0 &&
 801                             render_dcc_offset != afb->base.offsets[1] &&
 802                             render_dcc_offset < UINT_MAX) {
 803                                 uint32_t dcc_block_bits;  /* of base surface data */
 804
 805                                 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 806                                 afb->base.offsets[2] = render_dcc_offset;
 807
 808                                 if (adev->family >= AMDGPU_FAMILY_NV) {
 809                                         int extra_pipe = 0;
 810
 811                                         if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 812                                             pipes == packers && pipes > 1)
 813                                                 extra_pipe = 1;
 814
 815                                         dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 816                                 } else {
 817                                         modifier |= AMD_FMT_MOD_SET(RB, rb) |
 818                                                     AMD_FMT_MOD_SET(PIPE, pipes);
 819                                         dcc_block_bits = max(20, 18 + rb);
 820                                 }
 821
 822                                 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 823                                 afb->base.pitches[2] = ALIGN(afb->base.width,
 824                                                              1u << ((dcc_block_bits + 1) / 2));
 825                         }
 826                         format_info = amdgpu_lookup_format_info(afb->base.format->format,
 827                                                                 modifier);
 828                         if (!format_info)
 829                                 return -EINVAL;
 830
 831                         afb->base.format = format_info;
 832                 }
 833         }
 834
 835         afb->base.modifier = modifier;
 836         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 837         return 0;
 838 }
 839
 840 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
 841                                       uint64_t *tiling_flags, bool *tmz_surface)
 842 {
 843         struct amdgpu_bo *rbo;
 844         int r;
 845
 846         if (!amdgpu_fb) {
 847                 *tiling_flags = 0;
 848                 *tmz_surface = false;
 849                 return 0;
 850         }
 851
 852         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
 853         r = amdgpu_bo_reserve(rbo, false);
 854
 855         if (unlikely(r)) {
 856                 /* Don't show error message when returning -ERESTARTSYS */
 857                 if (r != -ERESTARTSYS)
 858                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 859                 return r;
 860         }
 861
 862         if (tiling_flags)
 863                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
 864
 865         if (tmz_surface)
 866                 *tmz_surface = amdgpu_bo_encrypted(rbo);
 867
 868         amdgpu_bo_unreserve(rbo);
 869
 870         return r;
 871 }
 872
 873 int amdgpu_display_gem_fb_init(struct drm_device *dev,
 874                                struct amdgpu_framebuffer *rfb,
 875                                const struct drm_mode_fb_cmd2 *mode_cmd,
 876                                struct drm_gem_object *obj)
 877 {
 878         int ret;
 879
 880         rfb->base.obj[0] = obj;
 881         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
 882         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 883         if (ret)
 884                 goto err;
 885
 886         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
 887         if (ret)
 888                 goto err;
 889
 890         return 0;
 891 err:
 892         drm_err(dev, "Failed to init gem fb: %d\n", ret);
 893         rfb->base.obj[0] = NULL;
 894         return ret;
 895 }
 896
 897 int amdgpu_display_gem_fb_verify_and_init(
 898         struct drm_device *dev, struct amdgpu_framebuffer *rfb,
 899         struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
 900         struct drm_gem_object *obj)
 901 {
 902         int ret;
 903
 904         rfb->base.obj[0] = obj;
 905
 906         /* Verify that bo size can fit the fb size. */
 907         ret = drm_gem_fb_init_with_funcs(dev, &rfb->base, file_priv, mode_cmd,
 908                                          &amdgpu_fb_funcs);
 909         if (ret)
 910                 goto err;
 911         /* Verify that the modifier is supported. */
 912         if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
 913                                       mode_cmd->modifier[0])) {
 914                 struct drm_format_name_buf format_name;
 915                 drm_dbg_kms(dev,
 916                             "unsupported pixel format %s / modifier 0x%llx\n",
 917                             drm_get_format_name(mode_cmd->pixel_format,
 918                                                 &format_name),
 919                             mode_cmd->modifier[0]);
 920
 921                 ret = -EINVAL;
 922                 goto err;
 923         }
 924
 925         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
 926         if (ret)
 927                 goto err;
 928
 929         return 0;
 930 err:
 931         drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);
 932         rfb->base.obj[0] = NULL;
 933         return ret;
 934 }
 935
 936 int amdgpu_display_framebuffer_init(struct drm_device *dev,
 937                                     struct amdgpu_framebuffer *rfb,
 938                                     const struct drm_mode_fb_cmd2 *mode_cmd,
 939                                     struct drm_gem_object *obj)
 940 {
 941         int ret, i;
 942
 943         /*
 944          * This needs to happen before modifier conversion as that might change
 945          * the number of planes.
 946          */
 947         for (i = 1; i < rfb->base.format->num_planes; ++i) {
 948                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
 949                         drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
 950                                     i, mode_cmd->handles[0], mode_cmd->handles[i]);
 951                         ret = -EINVAL;
 952                         return ret;
 953                 }
 954         }
 955
 956         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
 957         if (ret)
 958                 return ret;
 959
 960         if (dev->mode_config.allow_fb_modifiers &&
 961             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
 962                 ret = convert_tiling_flags_to_modifier(rfb);
 963                 if (ret) {
 964                         drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
 965                                     rfb->tiling_flags);
 966                         return ret;
 967                 }
 968         }
 969
 970         for (i = 1; i < rfb->base.format->num_planes; ++i) {
 971                 drm_gem_object_get(rfb->base.obj[0]);
 972                 drm_gem_object_put(rfb->base.obj[i]);
 973                 rfb->base.obj[i] = rfb->base.obj[0];
 974         }
 975
 976         return 0;
 977 }
 978
 979 struct drm_framebuffer *
 980 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
 981                                        struct drm_file *file_priv,
 982                                        const struct drm_mode_fb_cmd2 *mode_cmd)
 983 {
 984         struct amdgpu_framebuffer *amdgpu_fb;
 985         struct drm_gem_object *obj;
 986         struct amdgpu_bo *bo;
 987         uint32_t domains;
 988         int ret;
 989
 990         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
 991         if (obj ==  NULL) {
 992                 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
 993                             "can't create framebuffer\n", mode_cmd->handles[0]);
 994                 return ERR_PTR(-ENOENT);
 995         }
 996
 997         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
 998         bo = gem_to_amdgpu_bo(obj);
 999         domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1000         if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1001                 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1002                 return ERR_PTR(-EINVAL);
1003         }
1004
1005         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1006         if (amdgpu_fb == NULL) {
1007                 drm_gem_object_put(obj);
1008                 return ERR_PTR(-ENOMEM);
1009         }
1010
1011         ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1012                                                     mode_cmd, obj);
1013         if (ret) {
1014                 kfree(amdgpu_fb);
1015                 drm_gem_object_put(obj);
1016                 return ERR_PTR(ret);
1017         }
1018
1019         drm_gem_object_put(obj);
1020         return &amdgpu_fb->base;
1021 }
1022
1023 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1024         .fb_create = amdgpu_display_user_framebuffer_create,
1025         .output_poll_changed = drm_fb_helper_output_poll_changed,
1026 };
1027
1028 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1029 {       { UNDERSCAN_OFF, "off" },
1030         { UNDERSCAN_ON, "on" },
1031         { UNDERSCAN_AUTO, "auto" },
1032 };
1033
1034 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1035 {       { AMDGPU_AUDIO_DISABLE, "off" },
1036         { AMDGPU_AUDIO_ENABLE, "on" },
1037         { AMDGPU_AUDIO_AUTO, "auto" },
1038 };
1039
1040 /* XXX support different dither options? spatial, temporal, both, etc. */
1041 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1042 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
1043         { AMDGPU_FMT_DITHER_ENABLE, "on" },
1044 };
1045
1046 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1047 {
1048         int sz;
1049
1050         adev->mode_info.coherent_mode_property =
1051                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1052         if (!adev->mode_info.coherent_mode_property)
1053                 return -ENOMEM;
1054
1055         adev->mode_info.load_detect_property =
1056                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1057         if (!adev->mode_info.load_detect_property)
1058                 return -ENOMEM;
1059
1060         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1061
1062         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1063         adev->mode_info.underscan_property =
1064                 drm_property_create_enum(adev_to_drm(adev), 0,
1065                                          "underscan",
1066                                          amdgpu_underscan_enum_list, sz);
1067
1068         adev->mode_info.underscan_hborder_property =
1069                 drm_property_create_range(adev_to_drm(adev), 0,
1070                                           "underscan hborder", 0, 128);
1071         if (!adev->mode_info.underscan_hborder_property)
1072                 return -ENOMEM;
1073
1074         adev->mode_info.underscan_vborder_property =
1075                 drm_property_create_range(adev_to_drm(adev), 0,
1076                                           "underscan vborder", 0, 128);
1077         if (!adev->mode_info.underscan_vborder_property)
1078                 return -ENOMEM;
1079
1080         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1081         adev->mode_info.audio_property =
1082                 drm_property_create_enum(adev_to_drm(adev), 0,
1083                                          "audio",
1084                                          amdgpu_audio_enum_list, sz);
1085
1086         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1087         adev->mode_info.dither_property =
1088                 drm_property_create_enum(adev_to_drm(adev), 0,
1089                                          "dither",
1090                                          amdgpu_dither_enum_list, sz);
1091
1092         if (amdgpu_device_has_dc_support(adev)) {
1093                 adev->mode_info.abm_level_property =
1094                         drm_property_create_range(adev_to_drm(adev), 0,
1095                                                   "abm level", 0, 4);
1096                 if (!adev->mode_info.abm_level_property)
1097                         return -ENOMEM;
1098         }
1099
1100         return 0;
1101 }
1102
1103 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1104 {
1105         /* adjustment options for the display watermarks */
1106         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1107                 adev->mode_info.disp_priority = 0;
1108         else
1109                 adev->mode_info.disp_priority = amdgpu_disp_priority;
1110
1111 }
1112
1113 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1114 {
1115         /* try and guess if this is a tv or a monitor */
1116         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1117             (mode->vdisplay == 576) || /* 576p */
1118             (mode->vdisplay == 720) || /* 720p */
1119             (mode->vdisplay == 1080)) /* 1080p */
1120                 return true;
1121         else
1122                 return false;
1123 }
1124
1125 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1126                                         const struct drm_display_mode *mode,
1127                                         struct drm_display_mode *adjusted_mode)
1128 {
1129         struct drm_device *dev = crtc->dev;
1130         struct drm_encoder *encoder;
1131         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1132         struct amdgpu_encoder *amdgpu_encoder;
1133         struct drm_connector *connector;
1134         u32 src_v = 1, dst_v = 1;
1135         u32 src_h = 1, dst_h = 1;
1136
1137         amdgpu_crtc->h_border = 0;
1138         amdgpu_crtc->v_border = 0;
1139
1140         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1141                 if (encoder->crtc != crtc)
1142                         continue;
1143                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1144                 connector = amdgpu_get_connector_for_encoder(encoder);
1145
1146                 /* set scaling */
1147                 if (amdgpu_encoder->rmx_type == RMX_OFF)
1148                         amdgpu_crtc->rmx_type = RMX_OFF;
1149                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1150                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1151                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1152                 else
1153                         amdgpu_crtc->rmx_type = RMX_OFF;
1154                 /* copy native mode */
1155                 memcpy(&amdgpu_crtc->native_mode,
1156                        &amdgpu_encoder->native_mode,
1157                        sizeof(struct drm_display_mode));
1158                 src_v = crtc->mode.vdisplay;
1159                 dst_v = amdgpu_crtc->native_mode.vdisplay;
1160                 src_h = crtc->mode.hdisplay;
1161                 dst_h = amdgpu_crtc->native_mode.hdisplay;
1162
1163                 /* fix up for overscan on hdmi */
1164                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1165                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1166                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1167                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
1168                       amdgpu_display_is_hdtv_mode(mode)))) {
1169                         if (amdgpu_encoder->underscan_hborder != 0)
1170                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1171                         else
1172                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1173                         if (amdgpu_encoder->underscan_vborder != 0)
1174                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1175                         else
1176                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1177                         amdgpu_crtc->rmx_type = RMX_FULL;
1178                         src_v = crtc->mode.vdisplay;
1179                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1180                         src_h = crtc->mode.hdisplay;
1181                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1182                 }
1183         }
1184         if (amdgpu_crtc->rmx_type != RMX_OFF) {
1185                 fixed20_12 a, b;
1186                 a.full = dfixed_const(src_v);
1187                 b.full = dfixed_const(dst_v);
1188                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1189                 a.full = dfixed_const(src_h);
1190                 b.full = dfixed_const(dst_h);
1191                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1192         } else {
1193                 amdgpu_crtc->vsc.full = dfixed_const(1);
1194                 amdgpu_crtc->hsc.full = dfixed_const(1);
1195         }
1196         return true;
1197 }
1198
1199 /*
1200  * Retrieve current video scanout position of crtc on a given gpu, and
1201  * an optional accurate timestamp of when query happened.
1202  *
1203  * \param dev Device to query.
1204  * \param pipe Crtc to query.
1205  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1206  *              For driver internal use only also supports these flags:
1207  *
1208  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1209  *              of a fudged earlier start of vblank.
1210  *
1211  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1212  *              fudged earlier start of vblank in *vpos and the distance
1213  *              to true start of vblank in *hpos.
1214  *
1215  * \param *vpos Location where vertical scanout position should be stored.
1216  * \param *hpos Location where horizontal scanout position should go.
1217  * \param *stime Target location for timestamp taken immediately before
1218  *               scanout position query. Can be NULL to skip timestamp.
1219  * \param *etime Target location for timestamp taken immediately after
1220  *               scanout position query. Can be NULL to skip timestamp.
1221  *
1222  * Returns vpos as a positive number while in active scanout area.
1223  * Returns vpos as a negative number inside vblank, counting the number
1224  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1225  * until start of active scanout / end of vblank."
1226  *
1227  * \return Flags, or'ed together as follows:
1228  *
1229  * DRM_SCANOUTPOS_VALID = Query successful.
1230  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1231  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1232  * this flag means that returned position may be offset by a constant but
1233  * unknown small number of scanlines wrt. real scanout position.
1234  *
1235  */
1236 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1237                         unsigned int pipe, unsigned int flags, int *vpos,
1238                         int *hpos, ktime_t *stime, ktime_t *etime,
1239                         const struct drm_display_mode *mode)
1240 {
1241         u32 vbl = 0, position = 0;
1242         int vbl_start, vbl_end, vtotal, ret = 0;
1243         bool in_vbl = true;
1244
1245         struct amdgpu_device *adev = drm_to_adev(dev);
1246
1247         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1248
1249         /* Get optional system timestamp before query. */
1250         if (stime)
1251                 *stime = ktime_get();
1252
1253         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1254                 ret |= DRM_SCANOUTPOS_VALID;
1255
1256         /* Get optional system timestamp after query. */
1257         if (etime)
1258                 *etime = ktime_get();
1259
1260         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1261
1262         /* Decode into vertical and horizontal scanout position. */
1263         *vpos = position & 0x1fff;
1264         *hpos = (position >> 16) & 0x1fff;
1265
1266         /* Valid vblank area boundaries from gpu retrieved? */
1267         if (vbl > 0) {
1268                 /* Yes: Decode. */
1269                 ret |= DRM_SCANOUTPOS_ACCURATE;
1270                 vbl_start = vbl & 0x1fff;
1271                 vbl_end = (vbl >> 16) & 0x1fff;
1272         }
1273         else {
1274                 /* No: Fake something reasonable which gives at least ok results. */
1275                 vbl_start = mode->crtc_vdisplay;
1276                 vbl_end = 0;
1277         }
1278
1279         /* Called from driver internal vblank counter query code? */
1280         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1281             /* Caller wants distance from real vbl_start in *hpos */
1282             *hpos = *vpos - vbl_start;
1283         }
1284
1285         /* Fudge vblank to start a few scanlines earlier to handle the
1286          * problem that vblank irqs fire a few scanlines before start
1287          * of vblank. Some driver internal callers need the true vblank
1288          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1289          *
1290          * The cause of the "early" vblank irq is that the irq is triggered
1291          * by the line buffer logic when the line buffer read position enters
1292          * the vblank, whereas our crtc scanout position naturally lags the
1293          * line buffer read position.
1294          */
1295         if (!(flags & USE_REAL_VBLANKSTART))
1296                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1297
1298         /* Test scanout position against vblank region. */
1299         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1300                 in_vbl = false;
1301
1302         /* In vblank? */
1303         if (in_vbl)
1304             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1305
1306         /* Called from driver internal vblank counter query code? */
1307         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1308                 /* Caller wants distance from fudged earlier vbl_start */
1309                 *vpos -= vbl_start;
1310                 return ret;
1311         }
1312
1313         /* Check if inside vblank area and apply corrective offsets:
1314          * vpos will then be >=0 in video scanout area, but negative
1315          * within vblank area, counting down the number of lines until
1316          * start of scanout.
1317          */
1318
1319         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1320         if (in_vbl && (*vpos >= vbl_start)) {
1321                 vtotal = mode->crtc_vtotal;
1322
1323                 /* With variable refresh rate displays the vpos can exceed
1324                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1325                  * of guessing the remaining number of lines until scanout.
1326                  */
1327                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1328         }
1329
1330         /* Correct for shifted end of vbl at vbl_end. */
1331         *vpos = *vpos - vbl_end;
1332
1333         return ret;
1334 }
1335
1336 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1337 {
1338         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1339                 return AMDGPU_CRTC_IRQ_NONE;
1340
1341         switch (crtc) {
1342         case 0:
1343                 return AMDGPU_CRTC_IRQ_VBLANK1;
1344         case 1:
1345                 return AMDGPU_CRTC_IRQ_VBLANK2;
1346         case 2:
1347                 return AMDGPU_CRTC_IRQ_VBLANK3;
1348         case 3:
1349                 return AMDGPU_CRTC_IRQ_VBLANK4;
1350         case 4:
1351                 return AMDGPU_CRTC_IRQ_VBLANK5;
1352         case 5:
1353                 return AMDGPU_CRTC_IRQ_VBLANK6;
1354         default:
1355                 return AMDGPU_CRTC_IRQ_NONE;
1356         }
1357 }
1358
1359 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1360                         bool in_vblank_irq, int *vpos,
1361                         int *hpos, ktime_t *stime, ktime_t *etime,
1362                         const struct drm_display_mode *mode)
1363 {
1364         struct drm_device *dev = crtc->dev;
1365         unsigned int pipe = crtc->index;
1366
1367         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1368                                                   stime, etime, mode);
1369 }
1370
1371 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1372 {
1373         struct drm_device *dev = adev_to_drm(adev);
1374         struct drm_crtc *crtc;
1375         struct drm_connector *connector;
1376         struct drm_connector_list_iter iter;
1377         int r;
1378
1379         /* turn off display hw */
1380         drm_modeset_lock_all(dev);
1381         drm_connector_list_iter_begin(dev, &iter);
1382         drm_for_each_connector_iter(connector, &iter)
1383                 drm_helper_connector_dpms(connector,
1384                                           DRM_MODE_DPMS_OFF);
1385         drm_connector_list_iter_end(&iter);
1386         drm_modeset_unlock_all(dev);
1387         /* unpin the front buffers and cursors */
1388         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1389                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1390                 struct drm_framebuffer *fb = crtc->primary->fb;
1391                 struct amdgpu_bo *robj;
1392
1393                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1394                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1395                         r = amdgpu_bo_reserve(aobj, true);
1396                         if (r == 0) {
1397                                 amdgpu_bo_unpin(aobj);
1398                                 amdgpu_bo_unreserve(aobj);
1399                         }
1400                 }
1401
1402                 if (fb == NULL || fb->obj[0] == NULL) {
1403                         continue;
1404                 }
1405                 robj = gem_to_amdgpu_bo(fb->obj[0]);
1406                 /* don't unpin kernel fb objects */
1407                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1408                         r = amdgpu_bo_reserve(robj, true);
1409                         if (r == 0) {
1410                                 amdgpu_bo_unpin(robj);
1411                                 amdgpu_bo_unreserve(robj);
1412                         }
1413                 }
1414         }
1415         return r;
1416 }
1417
1418 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1419 {
1420         struct drm_device *dev = adev_to_drm(adev);
1421         struct drm_connector *connector;
1422         struct drm_connector_list_iter iter;
1423         struct drm_crtc *crtc;
1424         int r;
1425
1426         /* pin cursors */
1427         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1428                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1429
1430                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1431                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1432                         r = amdgpu_bo_reserve(aobj, true);
1433                         if (r == 0) {
1434                                 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1435                                 if (r != 0)
1436                                         dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1437                                 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1438                                 amdgpu_bo_unreserve(aobj);
1439                         }
1440                 }
1441         }
1442
1443         drm_helper_resume_force_mode(dev);
1444
1445         /* turn on display hw */
1446         drm_modeset_lock_all(dev);
1447
1448         drm_connector_list_iter_begin(dev, &iter);
1449         drm_for_each_connector_iter(connector, &iter)
1450                 drm_helper_connector_dpms(connector,
1451                                           DRM_MODE_DPMS_ON);
1452         drm_connector_list_iter_end(&iter);
1453
1454         drm_modeset_unlock_all(dev);
1455
1456         return 0;
1457 }
1458