drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/console.h>
  31 #include <linux/slab.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <linux/vgaarb.h>
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/efi.h>
  39 #include "amdgpu.h"
  40 #include "amdgpu_trace.h"
  41 #include "amdgpu_i2c.h"
  42 #include "atom.h"
  43 #include "amdgpu_atombios.h"
  44 #include "amdgpu_atomfirmware.h"
  45 #include "amd_pcie.h"
  46 #ifdef CONFIG_DRM_AMDGPU_SI
  47 #include "si.h"
  48 #endif
  49 #ifdef CONFIG_DRM_AMDGPU_CIK
  50 #include "cik.h"
  51 #endif
  52 #include "vi.h"
  53 #include "soc15.h"
  54 #include "bif/bif_4_1_d.h"
  55 #include <linux/pci.h>
  56 #include <linux/firmware.h>
  57 #include "amdgpu_vf_error.h"
  58
  59 #include "amdgpu_amdkfd.h"
  60 #include "amdgpu_pm.h"
  61
  62 #include "amdgpu_xgmi.h"
  63 #include "amdgpu_ras.h"
  64
  65 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  66 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
  67 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  68 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
  69 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
  70
  71 #define AMDGPU_RESUME_MS                2000
  72
  73 static const char *amdgpu_asic_name[] = {
  74         "TAHITI",
  75         "PITCAIRN",
  76         "VERDE",
  77         "OLAND",
  78         "HAINAN",
  79         "BONAIRE",
  80         "KAVERI",
  81         "KABINI",
  82         "HAWAII",
  83         "MULLINS",
  84         "TOPAZ",
  85         "TONGA",
  86         "FIJI",
  87         "CARRIZO",
  88         "STONEY",
  89         "POLARIS10",
  90         "POLARIS11",
  91         "POLARIS12",
  92         "VEGAM",
  93         "VEGA10",
  94         "VEGA12",
  95         "VEGA20",
  96         "RAVEN",
  97         "LAST",
  98 };
  99
 100 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 101
 102 /**
 103  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 104  *
 105  * @dev: drm_device pointer
 106  *
 107  * Returns true if the device is a dGPU with HG/PX power control,
 108  * otherwise return false.
 109  */
 110 bool amdgpu_device_is_px(struct drm_device *dev)
 111 {
 112         struct amdgpu_device *adev = dev->dev_private;
 113
 114         if (adev->flags & AMD_IS_PX)
 115                 return true;
 116         return false;
 117 }
 118
 119 /*
 120  * MMIO register access helper functions.
 121  */
 122 /**
 123  * amdgpu_mm_rreg - read a memory mapped IO register
 124  *
 125  * @adev: amdgpu_device pointer
 126  * @reg: dword aligned register offset
 127  * @acc_flags: access flags which require special behavior
 128  *
 129  * Returns the 32 bit value from the offset specified.
 130  */
 131 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 132                         uint32_t acc_flags)
 133 {
 134         uint32_t ret;
 135
 136         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 137                 return amdgpu_virt_kiq_rreg(adev, reg);
 138
 139         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 140                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 141         else {
 142                 unsigned long flags;
 143
 144                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 145                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 146                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 147                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 148         }
 149         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 150         return ret;
 151 }
 152
 153 /*
 154  * MMIO register read with bytes helper functions
 155  * @offset:bytes offset from MMIO start
 156  *
 157 */
 158
 159 /**
 160  * amdgpu_mm_rreg8 - read a memory mapped IO register
 161  *
 162  * @adev: amdgpu_device pointer
 163  * @offset: byte aligned register offset
 164  *
 165  * Returns the 8 bit value from the offset specified.
 166  */
 167 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 168         if (offset < adev->rmmio_size)
 169                 return (readb(adev->rmmio + offset));
 170         BUG();
 171 }
 172
 173 /*
 174  * MMIO register write with bytes helper functions
 175  * @offset:bytes offset from MMIO start
 176  * @value: the value want to be written to the register
 177  *
 178 */
 179 /**
 180  * amdgpu_mm_wreg8 - read a memory mapped IO register
 181  *
 182  * @adev: amdgpu_device pointer
 183  * @offset: byte aligned register offset
 184  * @value: 8 bit value to write
 185  *
 186  * Writes the value specified to the offset specified.
 187  */
 188 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 189         if (offset < adev->rmmio_size)
 190                 writeb(value, adev->rmmio + offset);
 191         else
 192                 BUG();
 193 }
 194
 195 /**
 196  * amdgpu_mm_wreg - write to a memory mapped IO register
 197  *
 198  * @adev: amdgpu_device pointer
 199  * @reg: dword aligned register offset
 200  * @v: 32 bit value to write to the register
 201  * @acc_flags: access flags which require special behavior
 202  *
 203  * Writes the value specified to the offset specified.
 204  */
 205 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 206                     uint32_t acc_flags)
 207 {
 208         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 209
 210         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 211                 adev->last_mm_index = v;
 212         }
 213
 214         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 215                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 216
 217         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 218                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 219         else {
 220                 unsigned long flags;
 221
 222                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 223                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 224                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 225                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 226         }
 227
 228         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 229                 udelay(500);
 230         }
 231 }
 232
 233 /**
 234  * amdgpu_io_rreg - read an IO register
 235  *
 236  * @adev: amdgpu_device pointer
 237  * @reg: dword aligned register offset
 238  *
 239  * Returns the 32 bit value from the offset specified.
 240  */
 241 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 242 {
 243         if ((reg * 4) < adev->rio_mem_size)
 244                 return ioread32(adev->rio_mem + (reg * 4));
 245         else {
 246                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 247                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 248         }
 249 }
 250
 251 /**
 252  * amdgpu_io_wreg - write to an IO register
 253  *
 254  * @adev: amdgpu_device pointer
 255  * @reg: dword aligned register offset
 256  * @v: 32 bit value to write to the register
 257  *
 258  * Writes the value specified to the offset specified.
 259  */
 260 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 261 {
 262         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 263                 adev->last_mm_index = v;
 264         }
 265
 266         if ((reg * 4) < adev->rio_mem_size)
 267                 iowrite32(v, adev->rio_mem + (reg * 4));
 268         else {
 269                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 270                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 271         }
 272
 273         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 274                 udelay(500);
 275         }
 276 }
 277
 278 /**
 279  * amdgpu_mm_rdoorbell - read a doorbell dword
 280  *
 281  * @adev: amdgpu_device pointer
 282  * @index: doorbell index
 283  *
 284  * Returns the value in the doorbell aperture at the
 285  * requested doorbell index (CIK).
 286  */
 287 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 288 {
 289         if (index < adev->doorbell.num_doorbells) {
 290                 return readl(adev->doorbell.ptr + index);
 291         } else {
 292                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 293                 return 0;
 294         }
 295 }
 296
 297 /**
 298  * amdgpu_mm_wdoorbell - write a doorbell dword
 299  *
 300  * @adev: amdgpu_device pointer
 301  * @index: doorbell index
 302  * @v: value to write
 303  *
 304  * Writes @v to the doorbell aperture at the
 305  * requested doorbell index (CIK).
 306  */
 307 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 308 {
 309         if (index < adev->doorbell.num_doorbells) {
 310                 writel(v, adev->doorbell.ptr + index);
 311         } else {
 312                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 313         }
 314 }
 315
 316 /**
 317  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 318  *
 319  * @adev: amdgpu_device pointer
 320  * @index: doorbell index
 321  *
 322  * Returns the value in the doorbell aperture at the
 323  * requested doorbell index (VEGA10+).
 324  */
 325 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 326 {
 327         if (index < adev->doorbell.num_doorbells) {
 328                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 329         } else {
 330                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 331                 return 0;
 332         }
 333 }
 334
 335 /**
 336  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 337  *
 338  * @adev: amdgpu_device pointer
 339  * @index: doorbell index
 340  * @v: value to write
 341  *
 342  * Writes @v to the doorbell aperture at the
 343  * requested doorbell index (VEGA10+).
 344  */
 345 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 346 {
 347         if (index < adev->doorbell.num_doorbells) {
 348                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 349         } else {
 350                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 351         }
 352 }
 353
 354 /**
 355  * amdgpu_invalid_rreg - dummy reg read function
 356  *
 357  * @adev: amdgpu device pointer
 358  * @reg: offset of register
 359  *
 360  * Dummy register read function.  Used for register blocks
 361  * that certain asics don't have (all asics).
 362  * Returns the value in the register.
 363  */
 364 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 365 {
 366         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 367         BUG();
 368         return 0;
 369 }
 370
 371 /**
 372  * amdgpu_invalid_wreg - dummy reg write function
 373  *
 374  * @adev: amdgpu device pointer
 375  * @reg: offset of register
 376  * @v: value to write to the register
 377  *
 378  * Dummy register read function.  Used for register blocks
 379  * that certain asics don't have (all asics).
 380  */
 381 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 382 {
 383         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 384                   reg, v);
 385         BUG();
 386 }
 387
 388 /**
 389  * amdgpu_block_invalid_rreg - dummy reg read function
 390  *
 391  * @adev: amdgpu device pointer
 392  * @block: offset of instance
 393  * @reg: offset of register
 394  *
 395  * Dummy register read function.  Used for register blocks
 396  * that certain asics don't have (all asics).
 397  * Returns the value in the register.
 398  */
 399 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 400                                           uint32_t block, uint32_t reg)
 401 {
 402         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 403                   reg, block);
 404         BUG();
 405         return 0;
 406 }
 407
 408 /**
 409  * amdgpu_block_invalid_wreg - dummy reg write function
 410  *
 411  * @adev: amdgpu device pointer
 412  * @block: offset of instance
 413  * @reg: offset of register
 414  * @v: value to write to the register
 415  *
 416  * Dummy register read function.  Used for register blocks
 417  * that certain asics don't have (all asics).
 418  */
 419 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 420                                       uint32_t block,
 421                                       uint32_t reg, uint32_t v)
 422 {
 423         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 424                   reg, block, v);
 425         BUG();
 426 }
 427
 428 /**
 429  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 430  *
 431  * @adev: amdgpu device pointer
 432  *
 433  * Allocates a scratch page of VRAM for use by various things in the
 434  * driver.
 435  */
 436 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 437 {
 438         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 439                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 440                                        &adev->vram_scratch.robj,
 441                                        &adev->vram_scratch.gpu_addr,
 442                                        (void **)&adev->vram_scratch.ptr);
 443 }
 444
 445 /**
 446  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 447  *
 448  * @adev: amdgpu device pointer
 449  *
 450  * Frees the VRAM scratch page.
 451  */
 452 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 453 {
 454         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 455 }
 456
 457 /**
 458  * amdgpu_device_program_register_sequence - program an array of registers.
 459  *
 460  * @adev: amdgpu_device pointer
 461  * @registers: pointer to the register array
 462  * @array_size: size of the register array
 463  *
 464  * Programs an array or registers with and and or masks.
 465  * This is a helper for setting golden registers.
 466  */
 467 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 468                                              const u32 *registers,
 469                                              const u32 array_size)
 470 {
 471         u32 tmp, reg, and_mask, or_mask;
 472         int i;
 473
 474         if (array_size % 3)
 475                 return;
 476
 477         for (i = 0; i < array_size; i +=3) {
 478                 reg = registers[i + 0];
 479                 and_mask = registers[i + 1];
 480                 or_mask = registers[i + 2];
 481
 482                 if (and_mask == 0xffffffff) {
 483                         tmp = or_mask;
 484                 } else {
 485                         tmp = RREG32(reg);
 486                         tmp &= ~and_mask;
 487                         tmp |= or_mask;
 488                 }
 489                 WREG32(reg, tmp);
 490         }
 491 }
 492
 493 /**
 494  * amdgpu_device_pci_config_reset - reset the GPU
 495  *
 496  * @adev: amdgpu_device pointer
 497  *
 498  * Resets the GPU using the pci config reset sequence.
 499  * Only applicable to asics prior to vega10.
 500  */
 501 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 502 {
 503         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 504 }
 505
 506 /*
 507  * GPU doorbell aperture helpers function.
 508  */
 509 /**
 510  * amdgpu_device_doorbell_init - Init doorbell driver information.
 511  *
 512  * @adev: amdgpu_device pointer
 513  *
 514  * Init doorbell driver information (CIK)
 515  * Returns 0 on success, error on failure.
 516  */
 517 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 518 {
 519
 520         /* No doorbell on SI hardware generation */
 521         if (adev->asic_type < CHIP_BONAIRE) {
 522                 adev->doorbell.base = 0;
 523                 adev->doorbell.size = 0;
 524                 adev->doorbell.num_doorbells = 0;
 525                 adev->doorbell.ptr = NULL;
 526                 return 0;
 527         }
 528
 529         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 530                 return -EINVAL;
 531
 532         amdgpu_asic_init_doorbell_index(adev);
 533
 534         /* doorbell bar mapping */
 535         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 536         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 537
 538         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 539                                              adev->doorbell_index.max_assignment+1);
 540         if (adev->doorbell.num_doorbells == 0)
 541                 return -EINVAL;
 542
 543         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
 544          * paging queue doorbell use the second page. The
 545          * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
 546          * doorbells are in the first page. So with paging queue enabled,
 547          * the max num_doorbells should + 1 page (0x400 in dword)
 548          */
 549         if (adev->asic_type >= CHIP_VEGA10)
 550                 adev->doorbell.num_doorbells += 0x400;
 551
 552         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 553                                      adev->doorbell.num_doorbells *
 554                                      sizeof(u32));
 555         if (adev->doorbell.ptr == NULL)
 556                 return -ENOMEM;
 557
 558         return 0;
 559 }
 560
 561 /**
 562  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 563  *
 564  * @adev: amdgpu_device pointer
 565  *
 566  * Tear down doorbell driver information (CIK)
 567  */
 568 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 569 {
 570         iounmap(adev->doorbell.ptr);
 571         adev->doorbell.ptr = NULL;
 572 }
 573
 574
 575
 576 /*
 577  * amdgpu_device_wb_*()
 578  * Writeback is the method by which the GPU updates special pages in memory
 579  * with the status of certain GPU events (fences, ring pointers,etc.).
 580  */
 581
 582 /**
 583  * amdgpu_device_wb_fini - Disable Writeback and free memory
 584  *
 585  * @adev: amdgpu_device pointer
 586  *
 587  * Disables Writeback and frees the Writeback memory (all asics).
 588  * Used at driver shutdown.
 589  */
 590 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 591 {
 592         if (adev->wb.wb_obj) {
 593                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 594                                       &adev->wb.gpu_addr,
 595                                       (void **)&adev->wb.wb);
 596                 adev->wb.wb_obj = NULL;
 597         }
 598 }
 599
 600 /**
 601  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 602  *
 603  * @adev: amdgpu_device pointer
 604  *
 605  * Initializes writeback and allocates writeback memory (all asics).
 606  * Used at driver startup.
 607  * Returns 0 on success or an -error on failure.
 608  */
 609 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 610 {
 611         int r;
 612
 613         if (adev->wb.wb_obj == NULL) {
 614                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 615                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 616                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 617                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 618                                             (void **)&adev->wb.wb);
 619                 if (r) {
 620                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 621                         return r;
 622                 }
 623
 624                 adev->wb.num_wb = AMDGPU_MAX_WB;
 625                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 626
 627                 /* clear wb memory */
 628                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 629         }
 630
 631         return 0;
 632 }
 633
 634 /**
 635  * amdgpu_device_wb_get - Allocate a wb entry
 636  *
 637  * @adev: amdgpu_device pointer
 638  * @wb: wb index
 639  *
 640  * Allocate a wb slot for use by the driver (all asics).
 641  * Returns 0 on success or -EINVAL on failure.
 642  */
 643 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 644 {
 645         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 646
 647         if (offset < adev->wb.num_wb) {
 648                 __set_bit(offset, adev->wb.used);
 649                 *wb = offset << 3; /* convert to dw offset */
 650                 return 0;
 651         } else {
 652                 return -EINVAL;
 653         }
 654 }
 655
 656 /**
 657  * amdgpu_device_wb_free - Free a wb entry
 658  *
 659  * @adev: amdgpu_device pointer
 660  * @wb: wb index
 661  *
 662  * Free a wb slot allocated for use by the driver (all asics)
 663  */
 664 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 665 {
 666         wb >>= 3;
 667         if (wb < adev->wb.num_wb)
 668                 __clear_bit(wb, adev->wb.used);
 669 }
 670
 671 /**
 672  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 673  *
 674  * @adev: amdgpu_device pointer
 675  *
 676  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 677  * to fail, but if any of the BARs is not accessible after the size we abort
 678  * driver loading by returning -ENODEV.
 679  */
 680 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 681 {
 682         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 683         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 684         struct pci_bus *root;
 685         struct resource *res;
 686         unsigned i;
 687         u16 cmd;
 688         int r;
 689
 690         /* Bypass for VF */
 691         if (amdgpu_sriov_vf(adev))
 692                 return 0;
 693
 694         /* Check if the root BUS has 64bit memory resources */
 695         root = adev->pdev->bus;
 696         while (root->parent)
 697                 root = root->parent;
 698
 699         pci_bus_for_each_resource(root, res, i) {
 700                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 701                     res->start > 0x100000000ull)
 702                         break;
 703         }
 704
 705         /* Trying to resize is pointless without a root hub window above 4GB */
 706         if (!res)
 707                 return 0;
 708
 709         /* Disable memory decoding while we change the BAR addresses and size */
 710         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 711         pci_write_config_word(adev->pdev, PCI_COMMAND,
 712                               cmd & ~PCI_COMMAND_MEMORY);
 713
 714         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 715         amdgpu_device_doorbell_fini(adev);
 716         if (adev->asic_type >= CHIP_BONAIRE)
 717                 pci_release_resource(adev->pdev, 2);
 718
 719         pci_release_resource(adev->pdev, 0);
 720
 721         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 722         if (r == -ENOSPC)
 723                 DRM_INFO("Not enough PCI address space for a large BAR.");
 724         else if (r && r != -ENOTSUPP)
 725                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 726
 727         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 728
 729         /* When the doorbell or fb BAR isn't available we have no chance of
 730          * using the device.
 731          */
 732         r = amdgpu_device_doorbell_init(adev);
 733         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 734                 return -ENODEV;
 735
 736         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 737
 738         return 0;
 739 }
 740
 741 /*
 742  * GPU helpers function.
 743  */
 744 /**
 745  * amdgpu_device_need_post - check if the hw need post or not
 746  *
 747  * @adev: amdgpu_device pointer
 748  *
 749  * Check if the asic has been initialized (all asics) at driver startup
 750  * or post is needed if  hw reset is performed.
 751  * Returns true if need or false if not.
 752  */
 753 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 754 {
 755         uint32_t reg;
 756
 757         if (amdgpu_sriov_vf(adev))
 758                 return false;
 759
 760         if (amdgpu_passthrough(adev)) {
 761                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 762                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 763                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 764                  * vpost executed for smc version below 22.15
 765                  */
 766                 if (adev->asic_type == CHIP_FIJI) {
 767                         int err;
 768                         uint32_t fw_ver;
 769                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 770                         /* force vPost if error occured */
 771                         if (err)
 772                                 return true;
 773
 774                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 775                         if (fw_ver < 0x00160e00)
 776                                 return true;
 777                 }
 778         }
 779
 780         if (adev->has_hw_reset) {
 781                 adev->has_hw_reset = false;
 782                 return true;
 783         }
 784
 785         /* bios scratch used on CIK+ */
 786         if (adev->asic_type >= CHIP_BONAIRE)
 787                 return amdgpu_atombios_scratch_need_asic_init(adev);
 788
 789         /* check MEM_SIZE for older asics */
 790         reg = amdgpu_asic_get_config_memsize(adev);
 791
 792         if ((reg != 0) && (reg != 0xffffffff))
 793                 return false;
 794
 795         return true;
 796 }
 797
 798 /* if we get transitioned to only one device, take VGA back */
 799 /**
 800  * amdgpu_device_vga_set_decode - enable/disable vga decode
 801  *
 802  * @cookie: amdgpu_device pointer
 803  * @state: enable/disable vga decode
 804  *
 805  * Enable/disable vga decode (all asics).
 806  * Returns VGA resource flags.
 807  */
 808 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 809 {
 810         struct amdgpu_device *adev = cookie;
 811         amdgpu_asic_set_vga_state(adev, state);
 812         if (state)
 813                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 814                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 815         else
 816                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 817 }
 818
 819 /**
 820  * amdgpu_device_check_block_size - validate the vm block size
 821  *
 822  * @adev: amdgpu_device pointer
 823  *
 824  * Validates the vm block size specified via module parameter.
 825  * The vm block size defines number of bits in page table versus page directory,
 826  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 827  * page table and the remaining bits are in the page directory.
 828  */
 829 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 830 {
 831         /* defines number of bits in page table versus page directory,
 832          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 833          * page table and the remaining bits are in the page directory */
 834         if (amdgpu_vm_block_size == -1)
 835                 return;
 836
 837         if (amdgpu_vm_block_size < 9) {
 838                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 839                          amdgpu_vm_block_size);
 840                 amdgpu_vm_block_size = -1;
 841         }
 842 }
 843
 844 /**
 845  * amdgpu_device_check_vm_size - validate the vm size
 846  *
 847  * @adev: amdgpu_device pointer
 848  *
 849  * Validates the vm size in GB specified via module parameter.
 850  * The VM size is the size of the GPU virtual memory space in GB.
 851  */
 852 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 853 {
 854         /* no need to check the default value */
 855         if (amdgpu_vm_size == -1)
 856                 return;
 857
 858         if (amdgpu_vm_size < 1) {
 859                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 860                          amdgpu_vm_size);
 861                 amdgpu_vm_size = -1;
 862         }
 863 }
 864
 865 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 866 {
 867         struct sysinfo si;
 868         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 869         uint64_t total_memory;
 870         uint64_t dram_size_seven_GB = 0x1B8000000;
 871         uint64_t dram_size_three_GB = 0xB8000000;
 872
 873         if (amdgpu_smu_memory_pool_size == 0)
 874                 return;
 875
 876         if (!is_os_64) {
 877                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 878                 goto def_value;
 879         }
 880         si_meminfo(&si);
 881         total_memory = (uint64_t)si.totalram * si.mem_unit;
 882
 883         if ((amdgpu_smu_memory_pool_size == 1) ||
 884                 (amdgpu_smu_memory_pool_size == 2)) {
 885                 if (total_memory < dram_size_three_GB)
 886                         goto def_value1;
 887         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 888                 (amdgpu_smu_memory_pool_size == 8)) {
 889                 if (total_memory < dram_size_seven_GB)
 890                         goto def_value1;
 891         } else {
 892                 DRM_WARN("Smu memory pool size not supported\n");
 893                 goto def_value;
 894         }
 895         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 896
 897         return;
 898
 899 def_value1:
 900         DRM_WARN("No enough system memory\n");
 901 def_value:
 902         adev->pm.smu_prv_buffer_size = 0;
 903 }
 904
 905 /**
 906  * amdgpu_device_check_arguments - validate module params
 907  *
 908  * @adev: amdgpu_device pointer
 909  *
 910  * Validates certain module parameters and updates
 911  * the associated values used by the driver (all asics).
 912  */
 913 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
 914 {
 915         if (amdgpu_sched_jobs < 4) {
 916                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 917                          amdgpu_sched_jobs);
 918                 amdgpu_sched_jobs = 4;
 919         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 920                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 921                          amdgpu_sched_jobs);
 922                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 923         }
 924
 925         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 926                 /* gart size must be greater or equal to 32M */
 927                 dev_warn(adev->dev, "gart size (%d) too small\n",
 928                          amdgpu_gart_size);
 929                 amdgpu_gart_size = -1;
 930         }
 931
 932         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 933                 /* gtt size must be greater or equal to 32M */
 934                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 935                                  amdgpu_gtt_size);
 936                 amdgpu_gtt_size = -1;
 937         }
 938
 939         /* valid range is between 4 and 9 inclusive */
 940         if (amdgpu_vm_fragment_size != -1 &&
 941             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 942                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 943                 amdgpu_vm_fragment_size = -1;
 944         }
 945
 946         amdgpu_device_check_smu_prv_buffer_size(adev);
 947
 948         amdgpu_device_check_vm_size(adev);
 949
 950         amdgpu_device_check_block_size(adev);
 951
 952         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
 953             !is_power_of_2(amdgpu_vram_page_split))) {
 954                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
 955                          amdgpu_vram_page_split);
 956                 amdgpu_vram_page_split = 1024;
 957         }
 958
 959         if (amdgpu_lockup_timeout == 0) {
 960                 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
 961                 amdgpu_lockup_timeout = 10000;
 962         }
 963
 964         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 965 }
 966
 967 /**
 968  * amdgpu_switcheroo_set_state - set switcheroo state
 969  *
 970  * @pdev: pci dev pointer
 971  * @state: vga_switcheroo state
 972  *
 973  * Callback for the switcheroo driver.  Suspends or resumes the
 974  * the asics before or after it is powered up using ACPI methods.
 975  */
 976 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 977 {
 978         struct drm_device *dev = pci_get_drvdata(pdev);
 979
 980         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
 981                 return;
 982
 983         if (state == VGA_SWITCHEROO_ON) {
 984                 pr_info("amdgpu: switched on\n");
 985                 /* don't suspend or resume card normally */
 986                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 987
 988                 amdgpu_device_resume(dev, true, true);
 989
 990                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 991                 drm_kms_helper_poll_enable(dev);
 992         } else {
 993                 pr_info("amdgpu: switched off\n");
 994                 drm_kms_helper_poll_disable(dev);
 995                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 996                 amdgpu_device_suspend(dev, true, true);
 997                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 998         }
 999 }
1000
1001 /**
1002  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1003  *
1004  * @pdev: pci dev pointer
1005  *
1006  * Callback for the switcheroo driver.  Check of the switcheroo
1007  * state can be changed.
1008  * Returns true if the state can be changed, false if not.
1009  */
1010 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1011 {
1012         struct drm_device *dev = pci_get_drvdata(pdev);
1013
1014         /*
1015         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1016         * locking inversion with the driver load path. And the access here is
1017         * completely racy anyway. So don't bother with locking for now.
1018         */
1019         return dev->open_count == 0;
1020 }
1021
1022 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1023         .set_gpu_state = amdgpu_switcheroo_set_state,
1024         .reprobe = NULL,
1025         .can_switch = amdgpu_switcheroo_can_switch,
1026 };
1027
1028 /**
1029  * amdgpu_device_ip_set_clockgating_state - set the CG state
1030  *
1031  * @dev: amdgpu_device pointer
1032  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1033  * @state: clockgating state (gate or ungate)
1034  *
1035  * Sets the requested clockgating state for all instances of
1036  * the hardware IP specified.
1037  * Returns the error code from the last instance.
1038  */
1039 int amdgpu_device_ip_set_clockgating_state(void *dev,
1040                                            enum amd_ip_block_type block_type,
1041                                            enum amd_clockgating_state state)
1042 {
1043         struct amdgpu_device *adev = dev;
1044         int i, r = 0;
1045
1046         for (i = 0; i < adev->num_ip_blocks; i++) {
1047                 if (!adev->ip_blocks[i].status.valid)
1048                         continue;
1049                 if (adev->ip_blocks[i].version->type != block_type)
1050                         continue;
1051                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1052                         continue;
1053                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1054                         (void *)adev, state);
1055                 if (r)
1056                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1057                                   adev->ip_blocks[i].version->funcs->name, r);
1058         }
1059         return r;
1060 }
1061
1062 /**
1063  * amdgpu_device_ip_set_powergating_state - set the PG state
1064  *
1065  * @dev: amdgpu_device pointer
1066  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1067  * @state: powergating state (gate or ungate)
1068  *
1069  * Sets the requested powergating state for all instances of
1070  * the hardware IP specified.
1071  * Returns the error code from the last instance.
1072  */
1073 int amdgpu_device_ip_set_powergating_state(void *dev,
1074                                            enum amd_ip_block_type block_type,
1075                                            enum amd_powergating_state state)
1076 {
1077         struct amdgpu_device *adev = dev;
1078         int i, r = 0;
1079
1080         for (i = 0; i < adev->num_ip_blocks; i++) {
1081                 if (!adev->ip_blocks[i].status.valid)
1082                         continue;
1083                 if (adev->ip_blocks[i].version->type != block_type)
1084                         continue;
1085                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1086                         continue;
1087                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1088                         (void *)adev, state);
1089                 if (r)
1090                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1091                                   adev->ip_blocks[i].version->funcs->name, r);
1092         }
1093         return r;
1094 }
1095
1096 /**
1097  * amdgpu_device_ip_get_clockgating_state - get the CG state
1098  *
1099  * @adev: amdgpu_device pointer
1100  * @flags: clockgating feature flags
1101  *
1102  * Walks the list of IPs on the device and updates the clockgating
1103  * flags for each IP.
1104  * Updates @flags with the feature flags for each hardware IP where
1105  * clockgating is enabled.
1106  */
1107 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1108                                             u32 *flags)
1109 {
1110         int i;
1111
1112         for (i = 0; i < adev->num_ip_blocks; i++) {
1113                 if (!adev->ip_blocks[i].status.valid)
1114                         continue;
1115                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1116                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1117         }
1118 }
1119
1120 /**
1121  * amdgpu_device_ip_wait_for_idle - wait for idle
1122  *
1123  * @adev: amdgpu_device pointer
1124  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1125  *
1126  * Waits for the request hardware IP to be idle.
1127  * Returns 0 for success or a negative error code on failure.
1128  */
1129 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1130                                    enum amd_ip_block_type block_type)
1131 {
1132         int i, r;
1133
1134         for (i = 0; i < adev->num_ip_blocks; i++) {
1135                 if (!adev->ip_blocks[i].status.valid)
1136                         continue;
1137                 if (adev->ip_blocks[i].version->type == block_type) {
1138                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1139                         if (r)
1140                                 return r;
1141                         break;
1142                 }
1143         }
1144         return 0;
1145
1146 }
1147
1148 /**
1149  * amdgpu_device_ip_is_idle - is the hardware IP idle
1150  *
1151  * @adev: amdgpu_device pointer
1152  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1153  *
1154  * Check if the hardware IP is idle or not.
1155  * Returns true if it the IP is idle, false if not.
1156  */
1157 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1158                               enum amd_ip_block_type block_type)
1159 {
1160         int i;
1161
1162         for (i = 0; i < adev->num_ip_blocks; i++) {
1163                 if (!adev->ip_blocks[i].status.valid)
1164                         continue;
1165                 if (adev->ip_blocks[i].version->type == block_type)
1166                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1167         }
1168         return true;
1169
1170 }
1171
1172 /**
1173  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1174  *
1175  * @adev: amdgpu_device pointer
1176  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1177  *
1178  * Returns a pointer to the hardware IP block structure
1179  * if it exists for the asic, otherwise NULL.
1180  */
1181 struct amdgpu_ip_block *
1182 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1183                               enum amd_ip_block_type type)
1184 {
1185         int i;
1186
1187         for (i = 0; i < adev->num_ip_blocks; i++)
1188                 if (adev->ip_blocks[i].version->type == type)
1189                         return &adev->ip_blocks[i];
1190
1191         return NULL;
1192 }
1193
1194 /**
1195  * amdgpu_device_ip_block_version_cmp
1196  *
1197  * @adev: amdgpu_device pointer
1198  * @type: enum amd_ip_block_type
1199  * @major: major version
1200  * @minor: minor version
1201  *
1202  * return 0 if equal or greater
1203  * return 1 if smaller or the ip_block doesn't exist
1204  */
1205 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1206                                        enum amd_ip_block_type type,
1207                                        u32 major, u32 minor)
1208 {
1209         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1210
1211         if (ip_block && ((ip_block->version->major > major) ||
1212                         ((ip_block->version->major == major) &&
1213                         (ip_block->version->minor >= minor))))
1214                 return 0;
1215
1216         return 1;
1217 }
1218
1219 /**
1220  * amdgpu_device_ip_block_add
1221  *
1222  * @adev: amdgpu_device pointer
1223  * @ip_block_version: pointer to the IP to add
1224  *
1225  * Adds the IP block driver information to the collection of IPs
1226  * on the asic.
1227  */
1228 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1229                                const struct amdgpu_ip_block_version *ip_block_version)
1230 {
1231         if (!ip_block_version)
1232                 return -EINVAL;
1233
1234         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1235                   ip_block_version->funcs->name);
1236
1237         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1238
1239         return 0;
1240 }
1241
1242 /**
1243  * amdgpu_device_enable_virtual_display - enable virtual display feature
1244  *
1245  * @adev: amdgpu_device pointer
1246  *
1247  * Enabled the virtual display feature if the user has enabled it via
1248  * the module parameter virtual_display.  This feature provides a virtual
1249  * display hardware on headless boards or in virtualized environments.
1250  * This function parses and validates the configuration string specified by
1251  * the user and configues the virtual display configuration (number of
1252  * virtual connectors, crtcs, etc.) specified.
1253  */
1254 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1255 {
1256         adev->enable_virtual_display = false;
1257
1258         if (amdgpu_virtual_display) {
1259                 struct drm_device *ddev = adev->ddev;
1260                 const char *pci_address_name = pci_name(ddev->pdev);
1261                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1262
1263                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1264                 pciaddstr_tmp = pciaddstr;
1265                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1266                         pciaddname = strsep(&pciaddname_tmp, ",");
1267                         if (!strcmp("all", pciaddname)
1268                             || !strcmp(pci_address_name, pciaddname)) {
1269                                 long num_crtc;
1270                                 int res = -1;
1271
1272                                 adev->enable_virtual_display = true;
1273
1274                                 if (pciaddname_tmp)
1275                                         res = kstrtol(pciaddname_tmp, 10,
1276                                                       &num_crtc);
1277
1278                                 if (!res) {
1279                                         if (num_crtc < 1)
1280                                                 num_crtc = 1;
1281                                         if (num_crtc > 6)
1282                                                 num_crtc = 6;
1283                                         adev->mode_info.num_crtc = num_crtc;
1284                                 } else {
1285                                         adev->mode_info.num_crtc = 1;
1286                                 }
1287                                 break;
1288                         }
1289                 }
1290
1291                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1292                          amdgpu_virtual_display, pci_address_name,
1293                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1294
1295                 kfree(pciaddstr);
1296         }
1297 }
1298
1299 /**
1300  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1301  *
1302  * @adev: amdgpu_device pointer
1303  *
1304  * Parses the asic configuration parameters specified in the gpu info
1305  * firmware and makes them availale to the driver for use in configuring
1306  * the asic.
1307  * Returns 0 on success, -EINVAL on failure.
1308  */
1309 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1310 {
1311         const char *chip_name;
1312         char fw_name[30];
1313         int err;
1314         const struct gpu_info_firmware_header_v1_0 *hdr;
1315
1316         adev->firmware.gpu_info_fw = NULL;
1317
1318         switch (adev->asic_type) {
1319         case CHIP_TOPAZ:
1320         case CHIP_TONGA:
1321         case CHIP_FIJI:
1322         case CHIP_POLARIS10:
1323         case CHIP_POLARIS11:
1324         case CHIP_POLARIS12:
1325         case CHIP_VEGAM:
1326         case CHIP_CARRIZO:
1327         case CHIP_STONEY:
1328 #ifdef CONFIG_DRM_AMDGPU_SI
1329         case CHIP_VERDE:
1330         case CHIP_TAHITI:
1331         case CHIP_PITCAIRN:
1332         case CHIP_OLAND:
1333         case CHIP_HAINAN:
1334 #endif
1335 #ifdef CONFIG_DRM_AMDGPU_CIK
1336         case CHIP_BONAIRE:
1337         case CHIP_HAWAII:
1338         case CHIP_KAVERI:
1339         case CHIP_KABINI:
1340         case CHIP_MULLINS:
1341 #endif
1342         case CHIP_VEGA20:
1343         default:
1344                 return 0;
1345         case CHIP_VEGA10:
1346                 chip_name = "vega10";
1347                 break;
1348         case CHIP_VEGA12:
1349                 chip_name = "vega12";
1350                 break;
1351         case CHIP_RAVEN:
1352                 if (adev->rev_id >= 8)
1353                         chip_name = "raven2";
1354                 else if (adev->pdev->device == 0x15d8)
1355                         chip_name = "picasso";
1356                 else
1357                         chip_name = "raven";
1358                 break;
1359         }
1360
1361         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1362         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1363         if (err) {
1364                 dev_err(adev->dev,
1365                         "Failed to load gpu_info firmware \"%s\"\n",
1366                         fw_name);
1367                 goto out;
1368         }
1369         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1370         if (err) {
1371                 dev_err(adev->dev,
1372                         "Failed to validate gpu_info firmware \"%s\"\n",
1373                         fw_name);
1374                 goto out;
1375         }
1376
1377         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1378         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1379
1380         switch (hdr->version_major) {
1381         case 1:
1382         {
1383                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1384                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1385                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1386
1387                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1388                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1389                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1390                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1391                 adev->gfx.config.max_texture_channel_caches =
1392                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1393                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1394                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1395                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1396                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1397                 adev->gfx.config.double_offchip_lds_buf =
1398                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1399                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1400                 adev->gfx.cu_info.max_waves_per_simd =
1401                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1402                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1403                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1404                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1405                 break;
1406         }
1407         default:
1408                 dev_err(adev->dev,
1409                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1410                 err = -EINVAL;
1411                 goto out;
1412         }
1413 out:
1414         return err;
1415 }
1416
1417 /**
1418  * amdgpu_device_ip_early_init - run early init for hardware IPs
1419  *
1420  * @adev: amdgpu_device pointer
1421  *
1422  * Early initialization pass for hardware IPs.  The hardware IPs that make
1423  * up each asic are discovered each IP's early_init callback is run.  This
1424  * is the first stage in initializing the asic.
1425  * Returns 0 on success, negative error code on failure.
1426  */
1427 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1428 {
1429         int i, r;
1430
1431         amdgpu_device_enable_virtual_display(adev);
1432
1433         switch (adev->asic_type) {
1434         case CHIP_TOPAZ:
1435         case CHIP_TONGA:
1436         case CHIP_FIJI:
1437         case CHIP_POLARIS10:
1438         case CHIP_POLARIS11:
1439         case CHIP_POLARIS12:
1440         case CHIP_VEGAM:
1441         case CHIP_CARRIZO:
1442         case CHIP_STONEY:
1443                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1444                         adev->family = AMDGPU_FAMILY_CZ;
1445                 else
1446                         adev->family = AMDGPU_FAMILY_VI;
1447
1448                 r = vi_set_ip_blocks(adev);
1449                 if (r)
1450                         return r;
1451                 break;
1452 #ifdef CONFIG_DRM_AMDGPU_SI
1453         case CHIP_VERDE:
1454         case CHIP_TAHITI:
1455         case CHIP_PITCAIRN:
1456         case CHIP_OLAND:
1457         case CHIP_HAINAN:
1458                 adev->family = AMDGPU_FAMILY_SI;
1459                 r = si_set_ip_blocks(adev);
1460                 if (r)
1461                         return r;
1462                 break;
1463 #endif
1464 #ifdef CONFIG_DRM_AMDGPU_CIK
1465         case CHIP_BONAIRE:
1466         case CHIP_HAWAII:
1467         case CHIP_KAVERI:
1468         case CHIP_KABINI:
1469         case CHIP_MULLINS:
1470                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1471                         adev->family = AMDGPU_FAMILY_CI;
1472                 else
1473                         adev->family = AMDGPU_FAMILY_KV;
1474
1475                 r = cik_set_ip_blocks(adev);
1476                 if (r)
1477                         return r;
1478                 break;
1479 #endif
1480         case CHIP_VEGA10:
1481         case CHIP_VEGA12:
1482         case CHIP_VEGA20:
1483         case CHIP_RAVEN:
1484                 if (adev->asic_type == CHIP_RAVEN)
1485                         adev->family = AMDGPU_FAMILY_RV;
1486                 else
1487                         adev->family = AMDGPU_FAMILY_AI;
1488
1489                 r = soc15_set_ip_blocks(adev);
1490                 if (r)
1491                         return r;
1492                 break;
1493         default:
1494                 /* FIXME: not supported yet */
1495                 return -EINVAL;
1496         }
1497
1498         r = amdgpu_device_parse_gpu_info_fw(adev);
1499         if (r)
1500                 return r;
1501
1502         amdgpu_amdkfd_device_probe(adev);
1503
1504         if (amdgpu_sriov_vf(adev)) {
1505                 r = amdgpu_virt_request_full_gpu(adev, true);
1506                 if (r)
1507                         return -EAGAIN;
1508         }
1509
1510         adev->pm.pp_feature = amdgpu_pp_feature_mask;
1511         if (amdgpu_sriov_vf(adev))
1512                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1513
1514         for (i = 0; i < adev->num_ip_blocks; i++) {
1515                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1516                         DRM_ERROR("disabled ip block: %d <%s>\n",
1517                                   i, adev->ip_blocks[i].version->funcs->name);
1518                         adev->ip_blocks[i].status.valid = false;
1519                 } else {
1520                         if (adev->ip_blocks[i].version->funcs->early_init) {
1521                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1522                                 if (r == -ENOENT) {
1523                                         adev->ip_blocks[i].status.valid = false;
1524                                 } else if (r) {
1525                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1526                                                   adev->ip_blocks[i].version->funcs->name, r);
1527                                         return r;
1528                                 } else {
1529                                         adev->ip_blocks[i].status.valid = true;
1530                                 }
1531                         } else {
1532                                 adev->ip_blocks[i].status.valid = true;
1533                         }
1534                 }
1535         }
1536
1537         adev->cg_flags &= amdgpu_cg_mask;
1538         adev->pg_flags &= amdgpu_pg_mask;
1539
1540         return 0;
1541 }
1542
1543 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1544 {
1545         int i, r;
1546
1547         for (i = 0; i < adev->num_ip_blocks; i++) {
1548                 if (!adev->ip_blocks[i].status.sw)
1549                         continue;
1550                 if (adev->ip_blocks[i].status.hw)
1551                         continue;
1552                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1553                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1554                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1555                         if (r) {
1556                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1557                                           adev->ip_blocks[i].version->funcs->name, r);
1558                                 return r;
1559                         }
1560                         adev->ip_blocks[i].status.hw = true;
1561                 }
1562         }
1563
1564         return 0;
1565 }
1566
1567 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1568 {
1569         int i, r;
1570
1571         for (i = 0; i < adev->num_ip_blocks; i++) {
1572                 if (!adev->ip_blocks[i].status.sw)
1573                         continue;
1574                 if (adev->ip_blocks[i].status.hw)
1575                         continue;
1576                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1577                 if (r) {
1578                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1579                                   adev->ip_blocks[i].version->funcs->name, r);
1580                         return r;
1581                 }
1582                 adev->ip_blocks[i].status.hw = true;
1583         }
1584
1585         return 0;
1586 }
1587
1588 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1589 {
1590         int r = 0;
1591         int i;
1592
1593         if (adev->asic_type >= CHIP_VEGA10) {
1594                 for (i = 0; i < adev->num_ip_blocks; i++) {
1595                         if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
1596                                 if (adev->in_gpu_reset || adev->in_suspend) {
1597                                         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
1598                                                 break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
1599                                         r = adev->ip_blocks[i].version->funcs->resume(adev);
1600                                         if (r) {
1601                                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
1602                                                           adev->ip_blocks[i].version->funcs->name, r);
1603                                                 return r;
1604                                         }
1605                                 } else {
1606                                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1607                                         if (r) {
1608                                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1609                                                   adev->ip_blocks[i].version->funcs->name, r);
1610                                                 return r;
1611                                         }
1612                                 }
1613                                 adev->ip_blocks[i].status.hw = true;
1614                         }
1615                 }
1616         }
1617
1618         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
1619                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
1620                 if (r) {
1621                         pr_err("firmware loading failed\n");
1622                         return r;
1623                 }
1624         }
1625
1626         return 0;
1627 }
1628
1629 /**
1630  * amdgpu_device_ip_init - run init for hardware IPs
1631  *
1632  * @adev: amdgpu_device pointer
1633  *
1634  * Main initialization pass for hardware IPs.  The list of all the hardware
1635  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1636  * are run.  sw_init initializes the software state associated with each IP
1637  * and hw_init initializes the hardware associated with each IP.
1638  * Returns 0 on success, negative error code on failure.
1639  */
1640 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1641 {
1642         int i, r;
1643
1644         r = amdgpu_ras_init(adev);
1645         if (r)
1646                 return r;
1647
1648         for (i = 0; i < adev->num_ip_blocks; i++) {
1649                 if (!adev->ip_blocks[i].status.valid)
1650                         continue;
1651                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1652                 if (r) {
1653                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1654                                   adev->ip_blocks[i].version->funcs->name, r);
1655                         goto init_failed;
1656                 }
1657                 adev->ip_blocks[i].status.sw = true;
1658
1659                 /* need to do gmc hw init early so we can allocate gpu mem */
1660                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1661                         r = amdgpu_device_vram_scratch_init(adev);
1662                         if (r) {
1663                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1664                                 goto init_failed;
1665                         }
1666                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1667                         if (r) {
1668                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1669                                 goto init_failed;
1670                         }
1671                         r = amdgpu_device_wb_init(adev);
1672                         if (r) {
1673                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1674                                 goto init_failed;
1675                         }
1676                         adev->ip_blocks[i].status.hw = true;
1677
1678                         /* right after GMC hw init, we create CSA */
1679                         if (amdgpu_sriov_vf(adev)) {
1680                                 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1681                                                                 AMDGPU_GEM_DOMAIN_VRAM,
1682                                                                 AMDGPU_CSA_SIZE);
1683                                 if (r) {
1684                                         DRM_ERROR("allocate CSA failed %d\n", r);
1685                                         goto init_failed;
1686                                 }
1687                         }
1688                 }
1689         }
1690
1691         r = amdgpu_ib_pool_init(adev);
1692         if (r) {
1693                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1694                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1695                 goto init_failed;
1696         }
1697
1698         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1699         if (r)
1700                 goto init_failed;
1701
1702         r = amdgpu_device_ip_hw_init_phase1(adev);
1703         if (r)
1704                 goto init_failed;
1705
1706         r = amdgpu_device_fw_loading(adev);
1707         if (r)
1708                 goto init_failed;
1709
1710         r = amdgpu_device_ip_hw_init_phase2(adev);
1711         if (r)
1712                 goto init_failed;
1713
1714         if (adev->gmc.xgmi.num_physical_nodes > 1)
1715                 amdgpu_xgmi_add_device(adev);
1716         amdgpu_amdkfd_device_init(adev);
1717
1718 init_failed:
1719         if (amdgpu_sriov_vf(adev)) {
1720                 if (!r)
1721                         amdgpu_virt_init_data_exchange(adev);
1722                 amdgpu_virt_release_full_gpu(adev, true);
1723         }
1724
1725         return r;
1726 }
1727
1728 /**
1729  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1730  *
1731  * @adev: amdgpu_device pointer
1732  *
1733  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1734  * this function before a GPU reset.  If the value is retained after a
1735  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1736  */
1737 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1738 {
1739         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1740 }
1741
1742 /**
1743  * amdgpu_device_check_vram_lost - check if vram is valid
1744  *
1745  * @adev: amdgpu_device pointer
1746  *
1747  * Checks the reset magic value written to the gart pointer in VRAM.
1748  * The driver calls this after a GPU reset to see if the contents of
1749  * VRAM is lost or now.
1750  * returns true if vram is lost, false if not.
1751  */
1752 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1753 {
1754         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1755                         AMDGPU_RESET_MAGIC_NUM);
1756 }
1757
1758 /**
1759  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1760  *
1761  * @adev: amdgpu_device pointer
1762  *
1763  * The list of all the hardware IPs that make up the asic is walked and the
1764  * set_clockgating_state callbacks are run.
1765  * Late initialization pass enabling clockgating for hardware IPs.
1766  * Fini or suspend, pass disabling clockgating for hardware IPs.
1767  * Returns 0 on success, negative error code on failure.
1768  */
1769
1770 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1771                                                 enum amd_clockgating_state state)
1772 {
1773         int i, j, r;
1774
1775         if (amdgpu_emu_mode == 1)
1776                 return 0;
1777
1778         for (j = 0; j < adev->num_ip_blocks; j++) {
1779                 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1780                 if (!adev->ip_blocks[i].status.late_initialized)
1781                         continue;
1782                 /* skip CG for VCE/UVD, it's handled specially */
1783                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1784                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1785                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1786                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1787                         /* enable clockgating to save power */
1788                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1789                                                                                      state);
1790                         if (r) {
1791                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1792                                           adev->ip_blocks[i].version->funcs->name, r);
1793                                 return r;
1794                         }
1795                 }
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1802 {
1803         int i, j, r;
1804
1805         if (amdgpu_emu_mode == 1)
1806                 return 0;
1807
1808         for (j = 0; j < adev->num_ip_blocks; j++) {
1809                 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1810                 if (!adev->ip_blocks[i].status.late_initialized)
1811                         continue;
1812                 /* skip CG for VCE/UVD, it's handled specially */
1813                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1814                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1815                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1816                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1817                         /* enable powergating to save power */
1818                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1819                                                                                         state);
1820                         if (r) {
1821                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1822                                           adev->ip_blocks[i].version->funcs->name, r);
1823                                 return r;
1824                         }
1825                 }
1826         }
1827         return 0;
1828 }
1829
1830 /**
1831  * amdgpu_device_ip_late_init - run late init for hardware IPs
1832  *
1833  * @adev: amdgpu_device pointer
1834  *
1835  * Late initialization pass for hardware IPs.  The list of all the hardware
1836  * IPs that make up the asic is walked and the late_init callbacks are run.
1837  * late_init covers any special initialization that an IP requires
1838  * after all of the have been initialized or something that needs to happen
1839  * late in the init process.
1840  * Returns 0 on success, negative error code on failure.
1841  */
1842 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1843 {
1844         int i = 0, r;
1845
1846         for (i = 0; i < adev->num_ip_blocks; i++) {
1847                 if (!adev->ip_blocks[i].status.hw)
1848                         continue;
1849                 if (adev->ip_blocks[i].version->funcs->late_init) {
1850                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1851                         if (r) {
1852                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1853                                           adev->ip_blocks[i].version->funcs->name, r);
1854                                 return r;
1855                         }
1856                 }
1857                 adev->ip_blocks[i].status.late_initialized = true;
1858         }
1859
1860         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
1861         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1862
1863         queue_delayed_work(system_wq, &adev->late_init_work,
1864                            msecs_to_jiffies(AMDGPU_RESUME_MS));
1865
1866         amdgpu_device_fill_reset_magic(adev);
1867
1868         return 0;
1869 }
1870
1871 /**
1872  * amdgpu_device_ip_fini - run fini for hardware IPs
1873  *
1874  * @adev: amdgpu_device pointer
1875  *
1876  * Main teardown pass for hardware IPs.  The list of all the hardware
1877  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1878  * are run.  hw_fini tears down the hardware associated with each IP
1879  * and sw_fini tears down any software state associated with each IP.
1880  * Returns 0 on success, negative error code on failure.
1881  */
1882 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1883 {
1884         int i, r;
1885
1886         amdgpu_ras_pre_fini(adev);
1887
1888         if (adev->gmc.xgmi.num_physical_nodes > 1)
1889                 amdgpu_xgmi_remove_device(adev);
1890
1891         amdgpu_amdkfd_device_fini(adev);
1892
1893         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1894         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1895
1896         /* need to disable SMC first */
1897         for (i = 0; i < adev->num_ip_blocks; i++) {
1898                 if (!adev->ip_blocks[i].status.hw)
1899                         continue;
1900                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1901                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1902                         /* XXX handle errors */
1903                         if (r) {
1904                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1905                                           adev->ip_blocks[i].version->funcs->name, r);
1906                         }
1907                         adev->ip_blocks[i].status.hw = false;
1908                         break;
1909                 }
1910         }
1911
1912         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1913                 if (!adev->ip_blocks[i].status.hw)
1914                         continue;
1915
1916                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1917                 /* XXX handle errors */
1918                 if (r) {
1919                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1920                                   adev->ip_blocks[i].version->funcs->name, r);
1921                 }
1922
1923                 adev->ip_blocks[i].status.hw = false;
1924         }
1925
1926
1927         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1928                 if (!adev->ip_blocks[i].status.sw)
1929                         continue;
1930
1931                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1932                         amdgpu_ucode_free_bo(adev);
1933                         amdgpu_free_static_csa(&adev->virt.csa_obj);
1934                         amdgpu_device_wb_fini(adev);
1935                         amdgpu_device_vram_scratch_fini(adev);
1936                         amdgpu_ib_pool_fini(adev);
1937                 }
1938
1939                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1940                 /* XXX handle errors */
1941                 if (r) {
1942                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1943                                   adev->ip_blocks[i].version->funcs->name, r);
1944                 }
1945                 adev->ip_blocks[i].status.sw = false;
1946                 adev->ip_blocks[i].status.valid = false;
1947         }
1948
1949         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1950                 if (!adev->ip_blocks[i].status.late_initialized)
1951                         continue;
1952                 if (adev->ip_blocks[i].version->funcs->late_fini)
1953                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1954                 adev->ip_blocks[i].status.late_initialized = false;
1955         }
1956
1957         amdgpu_ras_fini(adev);
1958
1959         if (amdgpu_sriov_vf(adev))
1960                 if (amdgpu_virt_release_full_gpu(adev, false))
1961                         DRM_ERROR("failed to release exclusive mode on fini\n");
1962
1963         return 0;
1964 }
1965
1966 static int amdgpu_device_enable_mgpu_fan_boost(void)
1967 {
1968         struct amdgpu_gpu_instance *gpu_ins;
1969         struct amdgpu_device *adev;
1970         int i, ret = 0;
1971
1972         mutex_lock(&mgpu_info.mutex);
1973
1974         /*
1975          * MGPU fan boost feature should be enabled
1976          * only when there are two or more dGPUs in
1977          * the system
1978          */
1979         if (mgpu_info.num_dgpu < 2)
1980                 goto out;
1981
1982         for (i = 0; i < mgpu_info.num_dgpu; i++) {
1983                 gpu_ins = &(mgpu_info.gpu_ins[i]);
1984                 adev = gpu_ins->adev;
1985                 if (!(adev->flags & AMD_IS_APU) &&
1986                     !gpu_ins->mgpu_fan_enabled &&
1987                     adev->powerplay.pp_funcs &&
1988                     adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1989                         ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1990                         if (ret)
1991                                 break;
1992
1993                         gpu_ins->mgpu_fan_enabled = 1;
1994                 }
1995         }
1996
1997 out:
1998         mutex_unlock(&mgpu_info.mutex);
1999
2000         return ret;
2001 }
2002
2003 /**
2004  * amdgpu_device_ip_late_init_func_handler - work handler for ib test
2005  *
2006  * @work: work_struct.
2007  */
2008 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
2009 {
2010         struct amdgpu_device *adev =
2011                 container_of(work, struct amdgpu_device, late_init_work.work);
2012         int r;
2013
2014         r = amdgpu_ib_ring_tests(adev);
2015         if (r)
2016                 DRM_ERROR("ib ring test failed (%d).\n", r);
2017
2018         r = amdgpu_device_enable_mgpu_fan_boost();
2019         if (r)
2020                 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2021
2022         /*set to low pstate by default */
2023         amdgpu_xgmi_set_pstate(adev, 0);
2024
2025 }
2026
2027 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2028 {
2029         struct amdgpu_device *adev =
2030                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2031
2032         mutex_lock(&adev->gfx.gfx_off_mutex);
2033         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2034                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2035                         adev->gfx.gfx_off_state = true;
2036         }
2037         mutex_unlock(&adev->gfx.gfx_off_mutex);
2038 }
2039
2040 /**
2041  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2042  *
2043  * @adev: amdgpu_device pointer
2044  *
2045  * Main suspend function for hardware IPs.  The list of all the hardware
2046  * IPs that make up the asic is walked, clockgating is disabled and the
2047  * suspend callbacks are run.  suspend puts the hardware and software state
2048  * in each IP into a state suitable for suspend.
2049  * Returns 0 on success, negative error code on failure.
2050  */
2051 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2052 {
2053         int i, r;
2054
2055         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2056         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2057
2058         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2059                 if (!adev->ip_blocks[i].status.valid)
2060                         continue;
2061                 /* displays are handled separately */
2062                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2063                         /* XXX handle errors */
2064                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
2065                         /* XXX handle errors */
2066                         if (r) {
2067                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2068                                           adev->ip_blocks[i].version->funcs->name, r);
2069                         }
2070                 }
2071         }
2072
2073         return 0;
2074 }
2075
2076 /**
2077  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2078  *
2079  * @adev: amdgpu_device pointer
2080  *
2081  * Main suspend function for hardware IPs.  The list of all the hardware
2082  * IPs that make up the asic is walked, clockgating is disabled and the
2083  * suspend callbacks are run.  suspend puts the hardware and software state
2084  * in each IP into a state suitable for suspend.
2085  * Returns 0 on success, negative error code on failure.
2086  */
2087 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2088 {
2089         int i, r;
2090
2091         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2092                 if (!adev->ip_blocks[i].status.valid)
2093                         continue;
2094                 /* displays are handled in phase1 */
2095                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2096                         continue;
2097                 /* XXX handle errors */
2098                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2099                 /* XXX handle errors */
2100                 if (r) {
2101                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2102                                   adev->ip_blocks[i].version->funcs->name, r);
2103                 }
2104         }
2105
2106         return 0;
2107 }
2108
2109 /**
2110  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2111  *
2112  * @adev: amdgpu_device pointer
2113  *
2114  * Main suspend function for hardware IPs.  The list of all the hardware
2115  * IPs that make up the asic is walked, clockgating is disabled and the
2116  * suspend callbacks are run.  suspend puts the hardware and software state
2117  * in each IP into a state suitable for suspend.
2118  * Returns 0 on success, negative error code on failure.
2119  */
2120 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2121 {
2122         int r;
2123
2124         if (amdgpu_sriov_vf(adev))
2125                 amdgpu_virt_request_full_gpu(adev, false);
2126
2127         r = amdgpu_device_ip_suspend_phase1(adev);
2128         if (r)
2129                 return r;
2130         r = amdgpu_device_ip_suspend_phase2(adev);
2131
2132         if (amdgpu_sriov_vf(adev))
2133                 amdgpu_virt_release_full_gpu(adev, false);
2134
2135         return r;
2136 }
2137
2138 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2139 {
2140         int i, r;
2141
2142         static enum amd_ip_block_type ip_order[] = {
2143                 AMD_IP_BLOCK_TYPE_GMC,
2144                 AMD_IP_BLOCK_TYPE_COMMON,
2145                 AMD_IP_BLOCK_TYPE_PSP,
2146                 AMD_IP_BLOCK_TYPE_IH,
2147         };
2148
2149         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2150                 int j;
2151                 struct amdgpu_ip_block *block;
2152
2153                 for (j = 0; j < adev->num_ip_blocks; j++) {
2154                         block = &adev->ip_blocks[j];
2155
2156                         if (block->version->type != ip_order[i] ||
2157                                 !block->status.valid)
2158                                 continue;
2159
2160                         r = block->version->funcs->hw_init(adev);
2161                         DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2162                         if (r)
2163                                 return r;
2164                 }
2165         }
2166
2167         return 0;
2168 }
2169
2170 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2171 {
2172         int i, r;
2173
2174         static enum amd_ip_block_type ip_order[] = {
2175                 AMD_IP_BLOCK_TYPE_SMC,
2176                 AMD_IP_BLOCK_TYPE_DCE,
2177                 AMD_IP_BLOCK_TYPE_GFX,
2178                 AMD_IP_BLOCK_TYPE_SDMA,
2179                 AMD_IP_BLOCK_TYPE_UVD,
2180                 AMD_IP_BLOCK_TYPE_VCE
2181         };
2182
2183         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2184                 int j;
2185                 struct amdgpu_ip_block *block;
2186
2187                 for (j = 0; j < adev->num_ip_blocks; j++) {
2188                         block = &adev->ip_blocks[j];
2189
2190                         if (block->version->type != ip_order[i] ||
2191                                 !block->status.valid)
2192                                 continue;
2193
2194                         r = block->version->funcs->hw_init(adev);
2195                         DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2196                         if (r)
2197                                 return r;
2198                 }
2199         }
2200
2201         return 0;
2202 }
2203
2204 /**
2205  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2206  *
2207  * @adev: amdgpu_device pointer
2208  *
2209  * First resume function for hardware IPs.  The list of all the hardware
2210  * IPs that make up the asic is walked and the resume callbacks are run for
2211  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2212  * after a suspend and updates the software state as necessary.  This
2213  * function is also used for restoring the GPU after a GPU reset.
2214  * Returns 0 on success, negative error code on failure.
2215  */
2216 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2217 {
2218         int i, r;
2219
2220         for (i = 0; i < adev->num_ip_blocks; i++) {
2221                 if (!adev->ip_blocks[i].status.valid)
2222                         continue;
2223                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2224                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2225                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2226                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2227                         if (r) {
2228                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2229                                           adev->ip_blocks[i].version->funcs->name, r);
2230                                 return r;
2231                         }
2232                 }
2233         }
2234
2235         return 0;
2236 }
2237
2238 /**
2239  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2240  *
2241  * @adev: amdgpu_device pointer
2242  *
2243  * First resume function for hardware IPs.  The list of all the hardware
2244  * IPs that make up the asic is walked and the resume callbacks are run for
2245  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2246  * functional state after a suspend and updates the software state as
2247  * necessary.  This function is also used for restoring the GPU after a GPU
2248  * reset.
2249  * Returns 0 on success, negative error code on failure.
2250  */
2251 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2252 {
2253         int i, r;
2254
2255         for (i = 0; i < adev->num_ip_blocks; i++) {
2256                 if (!adev->ip_blocks[i].status.valid)
2257                         continue;
2258                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2259                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2260                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2261                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2262                         continue;
2263                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2264                 if (r) {
2265                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2266                                   adev->ip_blocks[i].version->funcs->name, r);
2267                         return r;
2268                 }
2269         }
2270
2271         return 0;
2272 }
2273
2274 /**
2275  * amdgpu_device_ip_resume - run resume for hardware IPs
2276  *
2277  * @adev: amdgpu_device pointer
2278  *
2279  * Main resume function for hardware IPs.  The hardware IPs
2280  * are split into two resume functions because they are
2281  * are also used in in recovering from a GPU reset and some additional
2282  * steps need to be take between them.  In this case (S3/S4) they are
2283  * run sequentially.
2284  * Returns 0 on success, negative error code on failure.
2285  */
2286 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2287 {
2288         int r;
2289
2290         r = amdgpu_device_ip_resume_phase1(adev);
2291         if (r)
2292                 return r;
2293
2294         r = amdgpu_device_fw_loading(adev);
2295         if (r)
2296                 return r;
2297
2298         r = amdgpu_device_ip_resume_phase2(adev);
2299
2300         return r;
2301 }
2302
2303 /**
2304  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2305  *
2306  * @adev: amdgpu_device pointer
2307  *
2308  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2309  */
2310 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2311 {
2312         if (amdgpu_sriov_vf(adev)) {
2313                 if (adev->is_atom_fw) {
2314                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2315                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2316                 } else {
2317                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2318                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2319                 }
2320
2321                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2322                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2323         }
2324 }
2325
2326 /**
2327  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2328  *
2329  * @asic_type: AMD asic type
2330  *
2331  * Check if there is DC (new modesetting infrastructre) support for an asic.
2332  * returns true if DC has support, false if not.
2333  */
2334 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2335 {
2336         switch (asic_type) {
2337 #if defined(CONFIG_DRM_AMD_DC)
2338         case CHIP_BONAIRE:
2339         case CHIP_KAVERI:
2340         case CHIP_KABINI:
2341         case CHIP_MULLINS:
2342                 /*
2343                  * We have systems in the wild with these ASICs that require
2344                  * LVDS and VGA support which is not supported with DC.
2345                  *
2346                  * Fallback to the non-DC driver here by default so as not to
2347                  * cause regressions.
2348                  */
2349                 return amdgpu_dc > 0;
2350         case CHIP_HAWAII:
2351         case CHIP_CARRIZO:
2352         case CHIP_STONEY:
2353         case CHIP_POLARIS10:
2354         case CHIP_POLARIS11:
2355         case CHIP_POLARIS12:
2356         case CHIP_VEGAM:
2357         case CHIP_TONGA:
2358         case CHIP_FIJI:
2359         case CHIP_VEGA10:
2360         case CHIP_VEGA12:
2361         case CHIP_VEGA20:
2362 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2363         case CHIP_RAVEN:
2364 #endif
2365                 return amdgpu_dc != 0;
2366 #endif
2367         default:
2368                 return false;
2369         }
2370 }
2371
2372 /**
2373  * amdgpu_device_has_dc_support - check if dc is supported
2374  *
2375  * @adev: amdgpu_device_pointer
2376  *
2377  * Returns true for supported, false for not supported
2378  */
2379 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2380 {
2381         if (amdgpu_sriov_vf(adev))
2382                 return false;
2383
2384         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2385 }
2386
2387
2388 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2389 {
2390         struct amdgpu_device *adev =
2391                 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2392
2393         adev->asic_reset_res =  amdgpu_asic_reset(adev);
2394         if (adev->asic_reset_res)
2395                 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2396                          adev->asic_reset_res, adev->ddev->unique);
2397 }
2398
2399
2400 /**
2401  * amdgpu_device_init - initialize the driver
2402  *
2403  * @adev: amdgpu_device pointer
2404  * @ddev: drm dev pointer
2405  * @pdev: pci dev pointer
2406  * @flags: driver flags
2407  *
2408  * Initializes the driver info and hw (all asics).
2409  * Returns 0 for success or an error on failure.
2410  * Called at driver startup.
2411  */
2412 int amdgpu_device_init(struct amdgpu_device *adev,
2413                        struct drm_device *ddev,
2414                        struct pci_dev *pdev,
2415                        uint32_t flags)
2416 {
2417         int r, i;
2418         bool runtime = false;
2419         u32 max_MBps;
2420
2421         adev->shutdown = false;
2422         adev->dev = &pdev->dev;
2423         adev->ddev = ddev;
2424         adev->pdev = pdev;
2425         adev->flags = flags;
2426         adev->asic_type = flags & AMD_ASIC_MASK;
2427         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2428         if (amdgpu_emu_mode == 1)
2429                 adev->usec_timeout *= 2;
2430         adev->gmc.gart_size = 512 * 1024 * 1024;
2431         adev->accel_working = false;
2432         adev->num_rings = 0;
2433         adev->mman.buffer_funcs = NULL;
2434         adev->mman.buffer_funcs_ring = NULL;
2435         adev->vm_manager.vm_pte_funcs = NULL;
2436         adev->vm_manager.vm_pte_num_rqs = 0;
2437         adev->gmc.gmc_funcs = NULL;
2438         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2439         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2440
2441         adev->smc_rreg = &amdgpu_invalid_rreg;
2442         adev->smc_wreg = &amdgpu_invalid_wreg;
2443         adev->pcie_rreg = &amdgpu_invalid_rreg;
2444         adev->pcie_wreg = &amdgpu_invalid_wreg;
2445         adev->pciep_rreg = &amdgpu_invalid_rreg;
2446         adev->pciep_wreg = &amdgpu_invalid_wreg;
2447         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2448         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2449         adev->didt_rreg = &amdgpu_invalid_rreg;
2450         adev->didt_wreg = &amdgpu_invalid_wreg;
2451         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2452         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2453         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2454         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2455
2456         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2457                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2458                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2459
2460         /* mutex initialization are all done here so we
2461          * can recall function without having locking issues */
2462         atomic_set(&adev->irq.ih.lock, 0);
2463         mutex_init(&adev->firmware.mutex);
2464         mutex_init(&adev->pm.mutex);
2465         mutex_init(&adev->gfx.gpu_clock_mutex);
2466         mutex_init(&adev->srbm_mutex);
2467         mutex_init(&adev->gfx.pipe_reserve_mutex);
2468         mutex_init(&adev->gfx.gfx_off_mutex);
2469         mutex_init(&adev->grbm_idx_mutex);
2470         mutex_init(&adev->mn_lock);
2471         mutex_init(&adev->virt.vf_errors.lock);
2472         hash_init(adev->mn_hash);
2473         mutex_init(&adev->lock_reset);
2474         mutex_init(&adev->virt.dpm_mutex);
2475
2476         amdgpu_device_check_arguments(adev);
2477
2478         spin_lock_init(&adev->mmio_idx_lock);
2479         spin_lock_init(&adev->smc_idx_lock);
2480         spin_lock_init(&adev->pcie_idx_lock);
2481         spin_lock_init(&adev->uvd_ctx_idx_lock);
2482         spin_lock_init(&adev->didt_idx_lock);
2483         spin_lock_init(&adev->gc_cac_idx_lock);
2484         spin_lock_init(&adev->se_cac_idx_lock);
2485         spin_lock_init(&adev->audio_endpt_idx_lock);
2486         spin_lock_init(&adev->mm_stats.lock);
2487
2488         INIT_LIST_HEAD(&adev->shadow_list);
2489         mutex_init(&adev->shadow_list_lock);
2490
2491         INIT_LIST_HEAD(&adev->ring_lru_list);
2492         spin_lock_init(&adev->ring_lru_list_lock);
2493
2494         INIT_DELAYED_WORK(&adev->late_init_work,
2495                           amdgpu_device_ip_late_init_func_handler);
2496         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2497                           amdgpu_device_delay_enable_gfx_off);
2498
2499         INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2500
2501         adev->gfx.gfx_off_req_count = 1;
2502         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2503
2504         /* Registers mapping */
2505         /* TODO: block userspace mapping of io register */
2506         if (adev->asic_type >= CHIP_BONAIRE) {
2507                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2508                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2509         } else {
2510                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2511                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2512         }
2513
2514         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2515         if (adev->rmmio == NULL) {
2516                 return -ENOMEM;
2517         }
2518         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2519         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2520
2521         /* io port mapping */
2522         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2523                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2524                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2525                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2526                         break;
2527                 }
2528         }
2529         if (adev->rio_mem == NULL)
2530                 DRM_INFO("PCI I/O BAR is not found.\n");
2531
2532         amdgpu_device_get_pcie_info(adev);
2533
2534         /* early init functions */
2535         r = amdgpu_device_ip_early_init(adev);
2536         if (r)
2537                 return r;
2538
2539         /* doorbell bar mapping and doorbell index init*/
2540         amdgpu_device_doorbell_init(adev);
2541
2542         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2543         /* this will fail for cards that aren't VGA class devices, just
2544          * ignore it */
2545         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2546
2547         if (amdgpu_device_is_px(ddev))
2548                 runtime = true;
2549         if (!pci_is_thunderbolt_attached(adev->pdev))
2550                 vga_switcheroo_register_client(adev->pdev,
2551                                                &amdgpu_switcheroo_ops, runtime);
2552         if (runtime)
2553                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2554
2555         if (amdgpu_emu_mode == 1) {
2556                 /* post the asic on emulation mode */
2557                 emu_soc_asic_init(adev);
2558                 goto fence_driver_init;
2559         }
2560
2561         /* Read BIOS */
2562         if (!amdgpu_get_bios(adev)) {
2563                 r = -EINVAL;
2564                 goto failed;
2565         }
2566
2567         r = amdgpu_atombios_init(adev);
2568         if (r) {
2569                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2570                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2571                 goto failed;
2572         }
2573
2574         /* detect if we are with an SRIOV vbios */
2575         amdgpu_device_detect_sriov_bios(adev);
2576
2577         /* check if we need to reset the asic
2578          *  E.g., driver was not cleanly unloaded previously, etc.
2579          */
2580         if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2581                 r = amdgpu_asic_reset(adev);
2582                 if (r) {
2583                         dev_err(adev->dev, "asic reset on init failed\n");
2584                         goto failed;
2585                 }
2586         }
2587
2588         /* Post card if necessary */
2589         if (amdgpu_device_need_post(adev)) {
2590                 if (!adev->bios) {
2591                         dev_err(adev->dev, "no vBIOS found\n");
2592                         r = -EINVAL;
2593                         goto failed;
2594                 }
2595                 DRM_INFO("GPU posting now...\n");
2596                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2597                 if (r) {
2598                         dev_err(adev->dev, "gpu post error!\n");
2599                         goto failed;
2600                 }
2601         }
2602
2603         if (adev->is_atom_fw) {
2604                 /* Initialize clocks */
2605                 r = amdgpu_atomfirmware_get_clock_info(adev);
2606                 if (r) {
2607                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2608                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2609                         goto failed;
2610                 }
2611         } else {
2612                 /* Initialize clocks */
2613                 r = amdgpu_atombios_get_clock_info(adev);
2614                 if (r) {
2615                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2616                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2617                         goto failed;
2618                 }
2619                 /* init i2c buses */
2620                 if (!amdgpu_device_has_dc_support(adev))
2621                         amdgpu_atombios_i2c_init(adev);
2622         }
2623
2624 fence_driver_init:
2625         /* Fence driver */
2626         r = amdgpu_fence_driver_init(adev);
2627         if (r) {
2628                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2629                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2630                 goto failed;
2631         }
2632
2633         /* init the mode config */
2634         drm_mode_config_init(adev->ddev);
2635
2636         r = amdgpu_device_ip_init(adev);
2637         if (r) {
2638                 /* failed in exclusive mode due to timeout */
2639                 if (amdgpu_sriov_vf(adev) &&
2640                     !amdgpu_sriov_runtime(adev) &&
2641                     amdgpu_virt_mmio_blocked(adev) &&
2642                     !amdgpu_virt_wait_reset(adev)) {
2643                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2644                         /* Don't send request since VF is inactive. */
2645                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2646                         adev->virt.ops = NULL;
2647                         r = -EAGAIN;
2648                         goto failed;
2649                 }
2650                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2651                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2652                 if (amdgpu_virt_request_full_gpu(adev, false))
2653                         amdgpu_virt_release_full_gpu(adev, false);
2654                 goto failed;
2655         }
2656
2657         adev->accel_working = true;
2658
2659         amdgpu_vm_check_compute_bug(adev);
2660
2661         /* Initialize the buffer migration limit. */
2662         if (amdgpu_moverate >= 0)
2663                 max_MBps = amdgpu_moverate;
2664         else
2665                 max_MBps = 8; /* Allow 8 MB/s. */
2666         /* Get a log2 for easy divisions. */
2667         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2668
2669         amdgpu_fbdev_init(adev);
2670
2671         r = amdgpu_pm_sysfs_init(adev);
2672         if (r)
2673                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2674
2675         r = amdgpu_debugfs_gem_init(adev);
2676         if (r)
2677                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2678
2679         r = amdgpu_debugfs_regs_init(adev);
2680         if (r)
2681                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2682
2683         r = amdgpu_debugfs_firmware_init(adev);
2684         if (r)
2685                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2686
2687         r = amdgpu_debugfs_init(adev);
2688         if (r)
2689                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2690
2691         if ((amdgpu_testing & 1)) {
2692                 if (adev->accel_working)
2693                         amdgpu_test_moves(adev);
2694                 else
2695                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2696         }
2697         if (amdgpu_benchmarking) {
2698                 if (adev->accel_working)
2699                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2700                 else
2701                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2702         }
2703
2704         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2705          * explicit gating rather than handling it automatically.
2706          */
2707         r = amdgpu_device_ip_late_init(adev);
2708         if (r) {
2709                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2710                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2711                 goto failed;
2712         }
2713
2714         /* must succeed. */
2715         amdgpu_ras_post_init(adev);
2716
2717         return 0;
2718
2719 failed:
2720         amdgpu_vf_error_trans_all(adev);
2721         if (runtime)
2722                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2723
2724         return r;
2725 }
2726
2727 /**
2728  * amdgpu_device_fini - tear down the driver
2729  *
2730  * @adev: amdgpu_device pointer
2731  *
2732  * Tear down the driver info (all asics).
2733  * Called at driver shutdown.
2734  */
2735 void amdgpu_device_fini(struct amdgpu_device *adev)
2736 {
2737         int r;
2738
2739         DRM_INFO("amdgpu: finishing device.\n");
2740         adev->shutdown = true;
2741         /* disable all interrupts */
2742         amdgpu_irq_disable_all(adev);
2743         if (adev->mode_info.mode_config_initialized){
2744                 if (!amdgpu_device_has_dc_support(adev))
2745                         drm_helper_force_disable_all(adev->ddev);
2746                 else
2747                         drm_atomic_helper_shutdown(adev->ddev);
2748         }
2749         amdgpu_fence_driver_fini(adev);
2750         amdgpu_pm_sysfs_fini(adev);
2751         amdgpu_fbdev_fini(adev);
2752         r = amdgpu_device_ip_fini(adev);
2753         if (adev->firmware.gpu_info_fw) {
2754                 release_firmware(adev->firmware.gpu_info_fw);
2755                 adev->firmware.gpu_info_fw = NULL;
2756         }
2757         adev->accel_working = false;
2758         cancel_delayed_work_sync(&adev->late_init_work);
2759         /* free i2c buses */
2760         if (!amdgpu_device_has_dc_support(adev))
2761                 amdgpu_i2c_fini(adev);
2762
2763         if (amdgpu_emu_mode != 1)
2764                 amdgpu_atombios_fini(adev);
2765
2766         kfree(adev->bios);
2767         adev->bios = NULL;
2768         if (!pci_is_thunderbolt_attached(adev->pdev))
2769                 vga_switcheroo_unregister_client(adev->pdev);
2770         if (adev->flags & AMD_IS_PX)
2771                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2772         vga_client_register(adev->pdev, NULL, NULL, NULL);
2773         if (adev->rio_mem)
2774                 pci_iounmap(adev->pdev, adev->rio_mem);
2775         adev->rio_mem = NULL;
2776         iounmap(adev->rmmio);
2777         adev->rmmio = NULL;
2778         amdgpu_device_doorbell_fini(adev);
2779         amdgpu_debugfs_regs_cleanup(adev);
2780 }
2781
2782
2783 /*
2784  * Suspend & resume.
2785  */
2786 /**
2787  * amdgpu_device_suspend - initiate device suspend
2788  *
2789  * @dev: drm dev pointer
2790  * @suspend: suspend state
2791  * @fbcon : notify the fbdev of suspend
2792  *
2793  * Puts the hw in the suspend state (all asics).
2794  * Returns 0 for success or an error on failure.
2795  * Called at driver suspend.
2796  */
2797 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2798 {
2799         struct amdgpu_device *adev;
2800         struct drm_crtc *crtc;
2801         struct drm_connector *connector;
2802         int r;
2803
2804         if (dev == NULL || dev->dev_private == NULL) {
2805                 return -ENODEV;
2806         }
2807
2808         adev = dev->dev_private;
2809
2810         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2811                 return 0;
2812
2813         adev->in_suspend = true;
2814         drm_kms_helper_poll_disable(dev);
2815
2816         if (fbcon)
2817                 amdgpu_fbdev_set_suspend(adev, 1);
2818
2819         cancel_delayed_work_sync(&adev->late_init_work);
2820
2821         if (!amdgpu_device_has_dc_support(adev)) {
2822                 /* turn off display hw */
2823                 drm_modeset_lock_all(dev);
2824                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2825                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2826                 }
2827                 drm_modeset_unlock_all(dev);
2828                         /* unpin the front buffers and cursors */
2829                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2830                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2831                         struct drm_framebuffer *fb = crtc->primary->fb;
2832                         struct amdgpu_bo *robj;
2833
2834                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2835                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2836                                 r = amdgpu_bo_reserve(aobj, true);
2837                                 if (r == 0) {
2838                                         amdgpu_bo_unpin(aobj);
2839                                         amdgpu_bo_unreserve(aobj);
2840                                 }
2841                         }
2842
2843                         if (fb == NULL || fb->obj[0] == NULL) {
2844                                 continue;
2845                         }
2846                         robj = gem_to_amdgpu_bo(fb->obj[0]);
2847                         /* don't unpin kernel fb objects */
2848                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2849                                 r = amdgpu_bo_reserve(robj, true);
2850                                 if (r == 0) {
2851                                         amdgpu_bo_unpin(robj);
2852                                         amdgpu_bo_unreserve(robj);
2853                                 }
2854                         }
2855                 }
2856         }
2857
2858         amdgpu_amdkfd_suspend(adev);
2859
2860         r = amdgpu_device_ip_suspend_phase1(adev);
2861
2862         /* evict vram memory */
2863         amdgpu_bo_evict_vram(adev);
2864
2865         amdgpu_fence_driver_suspend(adev);
2866
2867         r = amdgpu_device_ip_suspend_phase2(adev);
2868
2869         /* evict remaining vram memory
2870          * This second call to evict vram is to evict the gart page table
2871          * using the CPU.
2872          */
2873         amdgpu_bo_evict_vram(adev);
2874
2875         pci_save_state(dev->pdev);
2876         if (suspend) {
2877                 /* Shut down the device */
2878                 pci_disable_device(dev->pdev);
2879                 pci_set_power_state(dev->pdev, PCI_D3hot);
2880         } else {
2881                 r = amdgpu_asic_reset(adev);
2882                 if (r)
2883                         DRM_ERROR("amdgpu asic reset failed\n");
2884         }
2885
2886         return 0;
2887 }
2888
2889 /**
2890  * amdgpu_device_resume - initiate device resume
2891  *
2892  * @dev: drm dev pointer
2893  * @resume: resume state
2894  * @fbcon : notify the fbdev of resume
2895  *
2896  * Bring the hw back to operating state (all asics).
2897  * Returns 0 for success or an error on failure.
2898  * Called at driver resume.
2899  */
2900 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2901 {
2902         struct drm_connector *connector;
2903         struct amdgpu_device *adev = dev->dev_private;
2904         struct drm_crtc *crtc;
2905         int r = 0;
2906
2907         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2908                 return 0;
2909
2910         if (resume) {
2911                 pci_set_power_state(dev->pdev, PCI_D0);
2912                 pci_restore_state(dev->pdev);
2913                 r = pci_enable_device(dev->pdev);
2914                 if (r)
2915                         return r;
2916         }
2917
2918         /* post card */
2919         if (amdgpu_device_need_post(adev)) {
2920                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2921                 if (r)
2922                         DRM_ERROR("amdgpu asic init failed\n");
2923         }
2924
2925         r = amdgpu_device_ip_resume(adev);
2926         if (r) {
2927                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2928                 return r;
2929         }
2930         amdgpu_fence_driver_resume(adev);
2931
2932
2933         r = amdgpu_device_ip_late_init(adev);
2934         if (r)
2935                 return r;
2936
2937         if (!amdgpu_device_has_dc_support(adev)) {
2938                 /* pin cursors */
2939                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2940                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2941
2942                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2943                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2944                                 r = amdgpu_bo_reserve(aobj, true);
2945                                 if (r == 0) {
2946                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2947                                         if (r != 0)
2948                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2949                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2950                                         amdgpu_bo_unreserve(aobj);
2951                                 }
2952                         }
2953                 }
2954         }
2955         r = amdgpu_amdkfd_resume(adev);
2956         if (r)
2957                 return r;
2958
2959         /* Make sure IB tests flushed */
2960         flush_delayed_work(&adev->late_init_work);
2961
2962         /* blat the mode back in */
2963         if (fbcon) {
2964                 if (!amdgpu_device_has_dc_support(adev)) {
2965                         /* pre DCE11 */
2966                         drm_helper_resume_force_mode(dev);
2967
2968                         /* turn on display hw */
2969                         drm_modeset_lock_all(dev);
2970                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2971                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2972                         }
2973                         drm_modeset_unlock_all(dev);
2974                 }
2975                 amdgpu_fbdev_set_suspend(adev, 0);
2976         }
2977
2978         drm_kms_helper_poll_enable(dev);
2979
2980         /*
2981          * Most of the connector probing functions try to acquire runtime pm
2982          * refs to ensure that the GPU is powered on when connector polling is
2983          * performed. Since we're calling this from a runtime PM callback,
2984          * trying to acquire rpm refs will cause us to deadlock.
2985          *
2986          * Since we're guaranteed to be holding the rpm lock, it's safe to
2987          * temporarily disable the rpm helpers so this doesn't deadlock us.
2988          */
2989 #ifdef CONFIG_PM
2990         dev->dev->power.disable_depth++;
2991 #endif
2992         if (!amdgpu_device_has_dc_support(adev))
2993                 drm_helper_hpd_irq_event(dev);
2994         else
2995                 drm_kms_helper_hotplug_event(dev);
2996 #ifdef CONFIG_PM
2997         dev->dev->power.disable_depth--;
2998 #endif
2999         adev->in_suspend = false;
3000
3001         return 0;
3002 }
3003
3004 /**
3005  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3006  *
3007  * @adev: amdgpu_device pointer
3008  *
3009  * The list of all the hardware IPs that make up the asic is walked and
3010  * the check_soft_reset callbacks are run.  check_soft_reset determines
3011  * if the asic is still hung or not.
3012  * Returns true if any of the IPs are still in a hung state, false if not.
3013  */
3014 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3015 {
3016         int i;
3017         bool asic_hang = false;
3018
3019         if (amdgpu_sriov_vf(adev))
3020                 return true;
3021
3022         if (amdgpu_asic_need_full_reset(adev))
3023                 return true;
3024
3025         for (i = 0; i < adev->num_ip_blocks; i++) {
3026                 if (!adev->ip_blocks[i].status.valid)
3027                         continue;
3028                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3029                         adev->ip_blocks[i].status.hang =
3030                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3031                 if (adev->ip_blocks[i].status.hang) {
3032                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3033                         asic_hang = true;
3034                 }
3035         }
3036         return asic_hang;
3037 }
3038
3039 /**
3040  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3041  *
3042  * @adev: amdgpu_device pointer
3043  *
3044  * The list of all the hardware IPs that make up the asic is walked and the
3045  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
3046  * handles any IP specific hardware or software state changes that are
3047  * necessary for a soft reset to succeed.
3048  * Returns 0 on success, negative error code on failure.
3049  */
3050 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3051 {
3052         int i, r = 0;
3053
3054         for (i = 0; i < adev->num_ip_blocks; i++) {
3055                 if (!adev->ip_blocks[i].status.valid)
3056                         continue;
3057                 if (adev->ip_blocks[i].status.hang &&
3058                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3059                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3060                         if (r)
3061                                 return r;
3062                 }
3063         }
3064
3065         return 0;
3066 }
3067
3068 /**
3069  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3070  *
3071  * @adev: amdgpu_device pointer
3072  *
3073  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
3074  * reset is necessary to recover.
3075  * Returns true if a full asic reset is required, false if not.
3076  */
3077 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3078 {
3079         int i;
3080
3081         if (amdgpu_asic_need_full_reset(adev))
3082                 return true;
3083
3084         for (i = 0; i < adev->num_ip_blocks; i++) {
3085                 if (!adev->ip_blocks[i].status.valid)
3086                         continue;
3087                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3088                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3089                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3090                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3091                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3092                         if (adev->ip_blocks[i].status.hang) {
3093                                 DRM_INFO("Some block need full reset!\n");
3094                                 return true;
3095                         }
3096                 }
3097         }
3098         return false;
3099 }
3100
3101 /**
3102  * amdgpu_device_ip_soft_reset - do a soft reset
3103  *
3104  * @adev: amdgpu_device pointer
3105  *
3106  * The list of all the hardware IPs that make up the asic is walked and the
3107  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3108  * IP specific hardware or software state changes that are necessary to soft
3109  * reset the IP.
3110  * Returns 0 on success, negative error code on failure.
3111  */
3112 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3113 {
3114         int i, r = 0;
3115
3116         for (i = 0; i < adev->num_ip_blocks; i++) {
3117                 if (!adev->ip_blocks[i].status.valid)
3118                         continue;
3119                 if (adev->ip_blocks[i].status.hang &&
3120                     adev->ip_blocks[i].version->funcs->soft_reset) {
3121                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3122                         if (r)
3123                                 return r;
3124                 }
3125         }
3126
3127         return 0;
3128 }
3129
3130 /**
3131  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3132  *
3133  * @adev: amdgpu_device pointer
3134  *
3135  * The list of all the hardware IPs that make up the asic is walked and the
3136  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3137  * handles any IP specific hardware or software state changes that are
3138  * necessary after the IP has been soft reset.
3139  * Returns 0 on success, negative error code on failure.
3140  */
3141 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3142 {
3143         int i, r = 0;
3144
3145         for (i = 0; i < adev->num_ip_blocks; i++) {
3146                 if (!adev->ip_blocks[i].status.valid)
3147                         continue;
3148                 if (adev->ip_blocks[i].status.hang &&
3149                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3150                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3151                 if (r)
3152                         return r;
3153         }
3154
3155         return 0;
3156 }
3157
3158 /**
3159  * amdgpu_device_recover_vram - Recover some VRAM contents
3160  *
3161  * @adev: amdgpu_device pointer
3162  *
3163  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3164  * restore things like GPUVM page tables after a GPU reset where
3165  * the contents of VRAM might be lost.
3166  *
3167  * Returns:
3168  * 0 on success, negative error code on failure.
3169  */
3170 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3171 {
3172         struct dma_fence *fence = NULL, *next = NULL;
3173         struct amdgpu_bo *shadow;
3174         long r = 1, tmo;
3175
3176         if (amdgpu_sriov_runtime(adev))
3177                 tmo = msecs_to_jiffies(8000);
3178         else
3179                 tmo = msecs_to_jiffies(100);
3180
3181         DRM_INFO("recover vram bo from shadow start\n");
3182         mutex_lock(&adev->shadow_list_lock);
3183         list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3184
3185                 /* No need to recover an evicted BO */
3186                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3187                     shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3188                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3189                         continue;
3190
3191                 r = amdgpu_bo_restore_shadow(shadow, &next);
3192                 if (r)
3193                         break;
3194
3195                 if (fence) {
3196                         tmo = dma_fence_wait_timeout(fence, false, tmo);
3197                         dma_fence_put(fence);
3198                         fence = next;
3199                         if (tmo == 0) {
3200                                 r = -ETIMEDOUT;
3201                                 break;
3202                         } else if (tmo < 0) {
3203                                 r = tmo;
3204                                 break;
3205                         }
3206                 } else {
3207                         fence = next;
3208                 }
3209         }
3210         mutex_unlock(&adev->shadow_list_lock);
3211
3212         if (fence)
3213                 tmo = dma_fence_wait_timeout(fence, false, tmo);
3214         dma_fence_put(fence);
3215
3216         if (r < 0 || tmo <= 0) {
3217                 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3218                 return -EIO;
3219         }
3220
3221         DRM_INFO("recover vram bo from shadow done\n");
3222         return 0;
3223 }
3224
3225
3226 /**
3227  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3228  *
3229  * @adev: amdgpu device pointer
3230  * @from_hypervisor: request from hypervisor
3231  *
3232  * do VF FLR and reinitialize Asic
3233  * return 0 means succeeded otherwise failed
3234  */
3235 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3236                                      bool from_hypervisor)
3237 {
3238         int r;
3239
3240         if (from_hypervisor)
3241                 r = amdgpu_virt_request_full_gpu(adev, true);
3242         else
3243                 r = amdgpu_virt_reset_gpu(adev);
3244         if (r)
3245                 return r;
3246
3247         amdgpu_amdkfd_pre_reset(adev);
3248
3249         /* Resume IP prior to SMC */
3250         r = amdgpu_device_ip_reinit_early_sriov(adev);
3251         if (r)
3252                 goto error;
3253
3254         /* we need recover gart prior to run SMC/CP/SDMA resume */
3255         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3256
3257         r = amdgpu_device_fw_loading(adev);
3258         if (r)
3259                 return r;
3260
3261         /* now we are okay to resume SMC/CP/SDMA */
3262         r = amdgpu_device_ip_reinit_late_sriov(adev);
3263         if (r)
3264                 goto error;
3265
3266         amdgpu_irq_gpu_reset_resume_helper(adev);
3267         r = amdgpu_ib_ring_tests(adev);
3268         amdgpu_amdkfd_post_reset(adev);
3269
3270 error:
3271         amdgpu_virt_init_data_exchange(adev);
3272         amdgpu_virt_release_full_gpu(adev, true);
3273         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3274                 atomic_inc(&adev->vram_lost_counter);
3275                 r = amdgpu_device_recover_vram(adev);
3276         }
3277
3278         return r;
3279 }
3280
3281 /**
3282  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3283  *
3284  * @adev: amdgpu device pointer
3285  *
3286  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3287  * a hung GPU.
3288  */
3289 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3290 {
3291         if (!amdgpu_device_ip_check_soft_reset(adev)) {
3292                 DRM_INFO("Timeout, but no hardware hang detected.\n");
3293                 return false;
3294         }
3295
3296         if (amdgpu_gpu_recovery == 0)
3297                 goto disabled;
3298
3299         if (amdgpu_sriov_vf(adev))
3300                 return true;
3301
3302         if (amdgpu_gpu_recovery == -1) {
3303                 switch (adev->asic_type) {
3304                 case CHIP_BONAIRE:
3305                 case CHIP_HAWAII:
3306                 case CHIP_TOPAZ:
3307                 case CHIP_TONGA:
3308                 case CHIP_FIJI:
3309                 case CHIP_POLARIS10:
3310                 case CHIP_POLARIS11:
3311                 case CHIP_POLARIS12:
3312                 case CHIP_VEGAM:
3313                 case CHIP_VEGA20:
3314                 case CHIP_VEGA10:
3315                 case CHIP_VEGA12:
3316                         break;
3317                 default:
3318                         goto disabled;
3319                 }
3320         }
3321
3322         return true;
3323
3324 disabled:
3325                 DRM_INFO("GPU recovery disabled.\n");
3326                 return false;
3327 }
3328
3329
3330 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3331                                         struct amdgpu_job *job,
3332                                         bool *need_full_reset_arg)
3333 {
3334         int i, r = 0;
3335         bool need_full_reset  = *need_full_reset_arg;
3336
3337         /* block all schedulers and reset given job's ring */
3338         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3339                 struct amdgpu_ring *ring = adev->rings[i];
3340
3341                 if (!ring || !ring->sched.thread)
3342                         continue;
3343
3344                 drm_sched_stop(&ring->sched);
3345
3346                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3347                 amdgpu_fence_driver_force_completion(ring);
3348         }
3349
3350         if(job)
3351                 drm_sched_increase_karma(&job->base);
3352
3353
3354
3355         if (!amdgpu_sriov_vf(adev)) {
3356
3357                 if (!need_full_reset)
3358                         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3359
3360                 if (!need_full_reset) {
3361                         amdgpu_device_ip_pre_soft_reset(adev);
3362                         r = amdgpu_device_ip_soft_reset(adev);
3363                         amdgpu_device_ip_post_soft_reset(adev);
3364                         if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3365                                 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3366                                 need_full_reset = true;
3367                         }
3368                 }
3369
3370                 if (need_full_reset)
3371                         r = amdgpu_device_ip_suspend(adev);
3372
3373                 *need_full_reset_arg = need_full_reset;
3374         }
3375
3376         return r;
3377 }
3378
3379 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3380                                struct list_head *device_list_handle,
3381                                bool *need_full_reset_arg)
3382 {
3383         struct amdgpu_device *tmp_adev = NULL;
3384         bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3385         int r = 0;
3386
3387         /*
3388          * ASIC reset has to be done on all HGMI hive nodes ASAP
3389          * to allow proper links negotiation in FW (within 1 sec)
3390          */
3391         if (need_full_reset) {
3392                 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3393                         /* For XGMI run all resets in parallel to speed up the process */
3394                         if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3395                                 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3396                                         r = -EALREADY;
3397                         } else
3398                                 r = amdgpu_asic_reset(tmp_adev);
3399
3400                         if (r) {
3401                                 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3402                                          r, tmp_adev->ddev->unique);
3403                                 break;
3404                         }
3405                 }
3406
3407                 /* For XGMI wait for all PSP resets to complete before proceed */
3408                 if (!r) {
3409                         list_for_each_entry(tmp_adev, device_list_handle,
3410                                             gmc.xgmi.head) {
3411                                 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3412                                         flush_work(&tmp_adev->xgmi_reset_work);
3413                                         r = tmp_adev->asic_reset_res;
3414                                         if (r)
3415                                                 break;
3416                                 }
3417                         }
3418
3419                         list_for_each_entry(tmp_adev, device_list_handle,
3420                                         gmc.xgmi.head) {
3421                                 amdgpu_ras_reserve_bad_pages(tmp_adev);
3422                         }
3423                 }
3424         }
3425
3426
3427         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3428                 if (need_full_reset) {
3429                         /* post card */
3430                         if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3431                                 DRM_WARN("asic atom init failed!");
3432
3433                         if (!r) {
3434                                 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3435                                 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3436                                 if (r)
3437                                         goto out;
3438
3439                                 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3440                                 if (vram_lost) {
3441                                         DRM_INFO("VRAM is lost due to GPU reset!\n");
3442                                         atomic_inc(&tmp_adev->vram_lost_counter);
3443                                 }
3444
3445                                 r = amdgpu_gtt_mgr_recover(
3446                                         &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3447                                 if (r)
3448                                         goto out;
3449
3450                                 r = amdgpu_device_fw_loading(tmp_adev);
3451                                 if (r)
3452                                         return r;
3453
3454                                 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3455                                 if (r)
3456                                         goto out;
3457
3458                                 if (vram_lost)
3459                                         amdgpu_device_fill_reset_magic(tmp_adev);
3460
3461                                 /* Update PSP FW topology after reset */
3462                                 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3463                                         r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3464                         }
3465                 }
3466
3467
3468 out:
3469                 if (!r) {
3470                         amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3471                         r = amdgpu_ib_ring_tests(tmp_adev);
3472                         if (r) {
3473                                 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3474                                 r = amdgpu_device_ip_suspend(tmp_adev);
3475                                 need_full_reset = true;
3476                                 r = -EAGAIN;
3477                                 goto end;
3478                         }
3479                 }
3480
3481                 if (!r)
3482                         r = amdgpu_device_recover_vram(tmp_adev);
3483                 else
3484                         tmp_adev->asic_reset_res = r;
3485         }
3486
3487 end:
3488         *need_full_reset_arg = need_full_reset;
3489         return r;
3490 }
3491
3492 static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
3493                                           struct amdgpu_job *job)
3494 {
3495         int i;
3496
3497         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3498                 struct amdgpu_ring *ring = adev->rings[i];
3499
3500                 if (!ring || !ring->sched.thread)
3501                         continue;
3502
3503                 if (!adev->asic_reset_res)
3504                         drm_sched_resubmit_jobs(&ring->sched);
3505
3506                 drm_sched_start(&ring->sched, !adev->asic_reset_res);
3507         }
3508
3509         if (!amdgpu_device_has_dc_support(adev)) {
3510                 drm_helper_resume_force_mode(adev->ddev);
3511         }
3512
3513         adev->asic_reset_res = 0;
3514 }
3515
3516 static void amdgpu_device_lock_adev(struct amdgpu_device *adev)
3517 {
3518         mutex_lock(&adev->lock_reset);
3519         atomic_inc(&adev->gpu_reset_counter);
3520         adev->in_gpu_reset = 1;
3521         /* Block kfd: SRIOV would do it separately */
3522         if (!amdgpu_sriov_vf(adev))
3523                 amdgpu_amdkfd_pre_reset(adev);
3524 }
3525
3526 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3527 {
3528         /*unlock kfd: SRIOV would do it separately */
3529         if (!amdgpu_sriov_vf(adev))
3530                 amdgpu_amdkfd_post_reset(adev);
3531         amdgpu_vf_error_trans_all(adev);
3532         adev->in_gpu_reset = 0;
3533         mutex_unlock(&adev->lock_reset);
3534 }
3535
3536
3537 /**
3538  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3539  *
3540  * @adev: amdgpu device pointer
3541  * @job: which job trigger hang
3542  *
3543  * Attempt to reset the GPU if it has hung (all asics).
3544  * Attempt to do soft-reset or full-reset and reinitialize Asic
3545  * Returns 0 for success or an error on failure.
3546  */
3547
3548 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3549                               struct amdgpu_job *job)
3550 {
3551         int r;
3552         struct amdgpu_hive_info *hive = NULL;
3553         bool need_full_reset = false;
3554         struct amdgpu_device *tmp_adev = NULL;
3555         struct list_head device_list, *device_list_handle =  NULL;
3556
3557         INIT_LIST_HEAD(&device_list);
3558
3559         dev_info(adev->dev, "GPU reset begin!\n");
3560
3561         /*
3562          * In case of XGMI hive disallow concurrent resets to be triggered
3563          * by different nodes. No point also since the one node already executing
3564          * reset will also reset all the other nodes in the hive.
3565          */
3566         hive = amdgpu_get_xgmi_hive(adev, 0);
3567         if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
3568             !mutex_trylock(&hive->reset_lock))
3569                 return 0;
3570
3571         /* Start with adev pre asic reset first for soft reset check.*/
3572         amdgpu_device_lock_adev(adev);
3573         r = amdgpu_device_pre_asic_reset(adev,
3574                                          job,
3575                                          &need_full_reset);
3576         if (r) {
3577                 /*TODO Should we stop ?*/
3578                 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3579                           r, adev->ddev->unique);
3580                 adev->asic_reset_res = r;
3581         }
3582
3583         /* Build list of devices to reset */
3584         if  (need_full_reset && adev->gmc.xgmi.num_physical_nodes > 1) {
3585                 if (!hive) {
3586                         amdgpu_device_unlock_adev(adev);
3587                         return -ENODEV;
3588                 }
3589
3590                 /*
3591                  * In case we are in XGMI hive mode device reset is done for all the
3592                  * nodes in the hive to retrain all XGMI links and hence the reset
3593                  * sequence is executed in loop on all nodes.
3594                  */
3595                 device_list_handle = &hive->device_list;
3596         } else {
3597                 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3598                 device_list_handle = &device_list;
3599         }
3600
3601 retry:  /* Rest of adevs pre asic reset from XGMI hive. */
3602         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3603
3604                 if (tmp_adev == adev)
3605                         continue;
3606
3607                 amdgpu_device_lock_adev(tmp_adev);
3608                 r = amdgpu_device_pre_asic_reset(tmp_adev,
3609                                                  NULL,
3610                                                  &need_full_reset);
3611                 /*TODO Should we stop ?*/
3612                 if (r) {
3613                         DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3614                                   r, tmp_adev->ddev->unique);
3615                         tmp_adev->asic_reset_res = r;
3616                 }
3617         }
3618
3619         /* Actual ASIC resets if needed.*/
3620         /* TODO Implement XGMI hive reset logic for SRIOV */
3621         if (amdgpu_sriov_vf(adev)) {
3622                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3623                 if (r)
3624                         adev->asic_reset_res = r;
3625         } else {
3626                 r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3627                 if (r && r == -EAGAIN)
3628                         goto retry;
3629         }
3630
3631         /* Post ASIC reset for all devs .*/
3632         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3633                 amdgpu_device_post_asic_reset(tmp_adev, tmp_adev == adev ? job : NULL);
3634
3635                 if (r) {
3636                         /* bad news, how to tell it to userspace ? */
3637                         dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3638                         amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3639                 } else {
3640                         dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3641                 }
3642
3643                 amdgpu_device_unlock_adev(tmp_adev);
3644         }
3645
3646         if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
3647                 mutex_unlock(&hive->reset_lock);
3648
3649         if (r)
3650                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3651         return r;
3652 }
3653
3654 static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
3655                                                   enum pci_bus_speed *speed,
3656                                                   enum pcie_link_width *width)
3657 {
3658         struct pci_dev *pdev = adev->pdev;
3659         enum pci_bus_speed cur_speed;
3660         enum pcie_link_width cur_width;
3661         u32 ret = 1;
3662
3663         *speed = PCI_SPEED_UNKNOWN;
3664         *width = PCIE_LNK_WIDTH_UNKNOWN;
3665
3666         while (pdev) {
3667                 cur_speed = pcie_get_speed_cap(pdev);
3668                 cur_width = pcie_get_width_cap(pdev);
3669                 ret = pcie_bandwidth_available(adev->pdev, NULL,
3670                                                        NULL, &cur_width);
3671                 if (!ret)
3672                         cur_width = PCIE_LNK_WIDTH_RESRV;
3673
3674                 if (cur_speed != PCI_SPEED_UNKNOWN) {
3675                         if (*speed == PCI_SPEED_UNKNOWN)
3676                                 *speed = cur_speed;
3677                         else if (cur_speed < *speed)
3678                                 *speed = cur_speed;
3679                 }
3680
3681                 if (cur_width != PCIE_LNK_WIDTH_UNKNOWN) {
3682                         if (*width == PCIE_LNK_WIDTH_UNKNOWN)
3683                                 *width = cur_width;
3684                         else if (cur_width < *width)
3685                                 *width = cur_width;
3686                 }
3687                 pdev = pci_upstream_bridge(pdev);
3688         }
3689 }
3690
3691 /**
3692  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3693  *
3694  * @adev: amdgpu_device pointer
3695  *
3696  * Fetchs and stores in the driver the PCIE capabilities (gen speed
3697  * and lanes) of the slot the device is in. Handles APUs and
3698  * virtualized environments where PCIE config space may not be available.
3699  */
3700 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3701 {
3702         struct pci_dev *pdev;
3703         enum pci_bus_speed speed_cap, platform_speed_cap;
3704         enum pcie_link_width platform_link_width;
3705
3706         if (amdgpu_pcie_gen_cap)
3707                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3708
3709         if (amdgpu_pcie_lane_cap)
3710                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3711
3712         /* covers APUs as well */
3713         if (pci_is_root_bus(adev->pdev->bus)) {
3714                 if (adev->pm.pcie_gen_mask == 0)
3715                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3716                 if (adev->pm.pcie_mlw_mask == 0)
3717                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3718                 return;
3719         }
3720
3721         if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3722                 return;
3723
3724         amdgpu_device_get_min_pci_speed_width(adev, &platform_speed_cap,
3725                                               &platform_link_width);
3726
3727         if (adev->pm.pcie_gen_mask == 0) {
3728                 /* asic caps */
3729                 pdev = adev->pdev;
3730                 speed_cap = pcie_get_speed_cap(pdev);
3731                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3732                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3733                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3734                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3735                 } else {
3736                         if (speed_cap == PCIE_SPEED_16_0GT)
3737                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3738                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3739                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3740                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3741                         else if (speed_cap == PCIE_SPEED_8_0GT)
3742                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3743                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3744                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3745                         else if (speed_cap == PCIE_SPEED_5_0GT)
3746                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3747                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3748                         else
3749                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3750                 }
3751                 /* platform caps */
3752                 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
3753                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3754                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3755                 } else {
3756                         if (platform_speed_cap == PCIE_SPEED_16_0GT)
3757                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3758                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3759                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3760                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3761                         else if (platform_speed_cap == PCIE_SPEED_8_0GT)
3762                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3763                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3764                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3765                         else if (platform_speed_cap == PCIE_SPEED_5_0GT)
3766                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3767                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3768                         else
3769                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3770
3771                 }
3772         }
3773         if (adev->pm.pcie_mlw_mask == 0) {
3774                 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3775                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3776                 } else {
3777                         switch (platform_link_width) {
3778                         case PCIE_LNK_X32:
3779                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3780                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3781                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3782                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3783                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3784                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3785                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3786                                 break;
3787                         case PCIE_LNK_X16:
3788                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3789                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3790                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3791                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3792                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3793                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3794                                 break;
3795                         case PCIE_LNK_X12:
3796                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3797                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3798                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3799                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3800                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3801                                 break;
3802                         case PCIE_LNK_X8:
3803                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3804                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3805                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3806                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3807                                 break;
3808                         case PCIE_LNK_X4:
3809                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3810                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3811                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3812                                 break;
3813                         case PCIE_LNK_X2:
3814                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3815                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3816                                 break;
3817                         case PCIE_LNK_X1:
3818                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3819                                 break;
3820                         default:
3821                                 break;
3822                         }
3823                 }
3824         }
3825 }
3826