2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #include "bif/bif_4_1_d.h"
57 #include <linux/pci.h>
58 #include <linux/firmware.h>
59 #include "amdgpu_vf_error.h"
61 #include "amdgpu_amdkfd.h"
62 #include "amdgpu_pm.h"
64 #include "amdgpu_xgmi.h"
65 #include "amdgpu_ras.h"
66 #include "amdgpu_pmu.h"
67 #include "amdgpu_fru_eeprom.h"
69 #include <linux/suspend.h>
70 #include <drm/task_barrier.h>
71 #include <linux/pm_runtime.h>
73 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
74 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
75 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
76 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
77 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
78 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
79 MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
80 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
82 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
84 #define AMDGPU_RESUME_MS 2000
86 const char *amdgpu_asic_name[] = {
119 * DOC: pcie_replay_count
121 * The amdgpu driver provides a sysfs API for reporting the total number
122 * of PCIe replays (NAKs)
123 * The file pcie_replay_count is used for this and returns the total
124 * number of replays as a sum of the NAKs generated and NAKs received
127 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
128 struct device_attribute *attr, char *buf)
130 struct drm_device *ddev = dev_get_drvdata(dev);
131 struct amdgpu_device *adev = ddev->dev_private;
132 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
134 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
137 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
138 amdgpu_device_get_pcie_replay_count, NULL);
140 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
145 * The amdgpu driver provides a sysfs API for reporting the product name
147 * The file serial_number is used for this and returns the product name
148 * as returned from the FRU.
149 * NOTE: This is only available for certain server cards
152 static ssize_t amdgpu_device_get_product_name(struct device *dev,
153 struct device_attribute *attr, char *buf)
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = ddev->dev_private;
158 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
161 static DEVICE_ATTR(product_name, S_IRUGO,
162 amdgpu_device_get_product_name, NULL);
165 * DOC: product_number
167 * The amdgpu driver provides a sysfs API for reporting the part number
169 * The file serial_number is used for this and returns the part number
170 * as returned from the FRU.
171 * NOTE: This is only available for certain server cards
174 static ssize_t amdgpu_device_get_product_number(struct device *dev,
175 struct device_attribute *attr, char *buf)
177 struct drm_device *ddev = dev_get_drvdata(dev);
178 struct amdgpu_device *adev = ddev->dev_private;
180 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
183 static DEVICE_ATTR(product_number, S_IRUGO,
184 amdgpu_device_get_product_number, NULL);
189 * The amdgpu driver provides a sysfs API for reporting the serial number
191 * The file serial_number is used for this and returns the serial number
192 * as returned from the FRU.
193 * NOTE: This is only available for certain server cards
196 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
197 struct device_attribute *attr, char *buf)
199 struct drm_device *ddev = dev_get_drvdata(dev);
200 struct amdgpu_device *adev = ddev->dev_private;
202 return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial);
205 static DEVICE_ATTR(serial_number, S_IRUGO,
206 amdgpu_device_get_serial_number, NULL);
209 * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control
211 * @dev: drm_device pointer
213 * Returns true if the device is a dGPU with HG/PX power control,
214 * otherwise return false.
216 bool amdgpu_device_supports_boco(struct drm_device *dev)
218 struct amdgpu_device *adev = dev->dev_private;
220 if (adev->flags & AMD_IS_PX)
226 * amdgpu_device_supports_baco - Does the device support BACO
228 * @dev: drm_device pointer
230 * Returns true if the device supporte BACO,
231 * otherwise return false.
233 bool amdgpu_device_supports_baco(struct drm_device *dev)
235 struct amdgpu_device *adev = dev->dev_private;
237 return amdgpu_asic_supports_baco(adev);
241 * VRAM access helper functions.
243 * amdgpu_device_vram_access - read/write a buffer in vram
245 * @adev: amdgpu_device pointer
246 * @pos: offset of the buffer in vram
247 * @buf: virtual address of the buffer in system memory
248 * @size: read/write size, sizeof(@buf) must > @size
249 * @write: true - write to vram, otherwise - read from vram
251 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
252 uint32_t *buf, size_t size, bool write)
258 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
259 for (last = pos + size; pos < last; pos += 4) {
260 uint32_t tmp = pos >> 31;
262 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
264 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
268 WREG32_NO_KIQ(mmMM_DATA, *buf++);
270 *buf++ = RREG32_NO_KIQ(mmMM_DATA);
272 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
276 * device register access helper functions.
279 * amdgpu_device_rreg - read a register
281 * @adev: amdgpu_device pointer
282 * @reg: dword aligned register offset
283 * @acc_flags: access flags which require special behavior
285 * Returns the 32 bit value from the offset specified.
287 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
292 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
293 return amdgpu_kiq_rreg(adev, reg);
295 if ((reg * 4) < adev->rmmio_size)
296 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
298 ret = adev->pcie_rreg(adev, (reg * 4));
299 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
304 * MMIO register read with bytes helper functions
305 * @offset:bytes offset from MMIO start
310 * amdgpu_mm_rreg8 - read a memory mapped IO register
312 * @adev: amdgpu_device pointer
313 * @offset: byte aligned register offset
315 * Returns the 8 bit value from the offset specified.
317 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
318 if (offset < adev->rmmio_size)
319 return (readb(adev->rmmio + offset));
324 * MMIO register write with bytes helper functions
325 * @offset:bytes offset from MMIO start
326 * @value: the value want to be written to the register
330 * amdgpu_mm_wreg8 - read a memory mapped IO register
332 * @adev: amdgpu_device pointer
333 * @offset: byte aligned register offset
334 * @value: 8 bit value to write
336 * Writes the value specified to the offset specified.
338 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
339 if (offset < adev->rmmio_size)
340 writeb(value, adev->rmmio + offset);
345 void static inline amdgpu_device_wreg_no_kiq(struct amdgpu_device *adev, uint32_t reg,
346 uint32_t v, uint32_t acc_flags)
348 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
350 if ((reg * 4) < adev->rmmio_size)
351 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
353 adev->pcie_wreg(adev, (reg * 4), v);
357 * amdgpu_device_wreg - write to a register
359 * @adev: amdgpu_device pointer
360 * @reg: dword aligned register offset
361 * @v: 32 bit value to write to the register
362 * @acc_flags: access flags which require special behavior
364 * Writes the value specified to the offset specified.
366 void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
369 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
370 return amdgpu_kiq_wreg(adev, reg, v);
372 amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);
376 * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
378 * this function is invoked only the debugfs register access
380 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
383 if (amdgpu_sriov_fullaccess(adev) &&
384 adev->gfx.rlc.funcs &&
385 adev->gfx.rlc.funcs->is_rlcg_access_range) {
387 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
388 return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
391 amdgpu_device_wreg_no_kiq(adev, reg, v, acc_flags);
395 * amdgpu_io_rreg - read an IO register
397 * @adev: amdgpu_device pointer
398 * @reg: dword aligned register offset
400 * Returns the 32 bit value from the offset specified.
402 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
404 if ((reg * 4) < adev->rio_mem_size)
405 return ioread32(adev->rio_mem + (reg * 4));
407 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
408 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
413 * amdgpu_io_wreg - write to an IO register
415 * @adev: amdgpu_device pointer
416 * @reg: dword aligned register offset
417 * @v: 32 bit value to write to the register
419 * Writes the value specified to the offset specified.
421 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
423 if ((reg * 4) < adev->rio_mem_size)
424 iowrite32(v, adev->rio_mem + (reg * 4));
426 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
427 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
432 * amdgpu_mm_rdoorbell - read a doorbell dword
434 * @adev: amdgpu_device pointer
435 * @index: doorbell index
437 * Returns the value in the doorbell aperture at the
438 * requested doorbell index (CIK).
440 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
442 if (index < adev->doorbell.num_doorbells) {
443 return readl(adev->doorbell.ptr + index);
445 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
451 * amdgpu_mm_wdoorbell - write a doorbell dword
453 * @adev: amdgpu_device pointer
454 * @index: doorbell index
457 * Writes @v to the doorbell aperture at the
458 * requested doorbell index (CIK).
460 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
462 if (index < adev->doorbell.num_doorbells) {
463 writel(v, adev->doorbell.ptr + index);
465 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
470 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
472 * @adev: amdgpu_device pointer
473 * @index: doorbell index
475 * Returns the value in the doorbell aperture at the
476 * requested doorbell index (VEGA10+).
478 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
480 if (index < adev->doorbell.num_doorbells) {
481 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
483 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
489 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
491 * @adev: amdgpu_device pointer
492 * @index: doorbell index
495 * Writes @v to the doorbell aperture at the
496 * requested doorbell index (VEGA10+).
498 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
500 if (index < adev->doorbell.num_doorbells) {
501 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
503 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
508 * amdgpu_invalid_rreg - dummy reg read function
510 * @adev: amdgpu device pointer
511 * @reg: offset of register
513 * Dummy register read function. Used for register blocks
514 * that certain asics don't have (all asics).
515 * Returns the value in the register.
517 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
519 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
525 * amdgpu_invalid_wreg - dummy reg write function
527 * @adev: amdgpu device pointer
528 * @reg: offset of register
529 * @v: value to write to the register
531 * Dummy register read function. Used for register blocks
532 * that certain asics don't have (all asics).
534 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
536 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
542 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
544 * @adev: amdgpu device pointer
545 * @reg: offset of register
547 * Dummy register read function. Used for register blocks
548 * that certain asics don't have (all asics).
549 * Returns the value in the register.
551 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
553 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
559 * amdgpu_invalid_wreg64 - dummy reg write function
561 * @adev: amdgpu device pointer
562 * @reg: offset of register
563 * @v: value to write to the register
565 * Dummy register read function. Used for register blocks
566 * that certain asics don't have (all asics).
568 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
570 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
576 * amdgpu_block_invalid_rreg - dummy reg read function
578 * @adev: amdgpu device pointer
579 * @block: offset of instance
580 * @reg: offset of register
582 * Dummy register read function. Used for register blocks
583 * that certain asics don't have (all asics).
584 * Returns the value in the register.
586 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
587 uint32_t block, uint32_t reg)
589 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
596 * amdgpu_block_invalid_wreg - dummy reg write function
598 * @adev: amdgpu device pointer
599 * @block: offset of instance
600 * @reg: offset of register
601 * @v: value to write to the register
603 * Dummy register read function. Used for register blocks
604 * that certain asics don't have (all asics).
606 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
608 uint32_t reg, uint32_t v)
610 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
616 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
618 * @adev: amdgpu device pointer
620 * Allocates a scratch page of VRAM for use by various things in the
623 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
625 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
626 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
627 &adev->vram_scratch.robj,
628 &adev->vram_scratch.gpu_addr,
629 (void **)&adev->vram_scratch.ptr);
633 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
635 * @adev: amdgpu device pointer
637 * Frees the VRAM scratch page.
639 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
641 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
645 * amdgpu_device_program_register_sequence - program an array of registers.
647 * @adev: amdgpu_device pointer
648 * @registers: pointer to the register array
649 * @array_size: size of the register array
651 * Programs an array or registers with and and or masks.
652 * This is a helper for setting golden registers.
654 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
655 const u32 *registers,
656 const u32 array_size)
658 u32 tmp, reg, and_mask, or_mask;
664 for (i = 0; i < array_size; i +=3) {
665 reg = registers[i + 0];
666 and_mask = registers[i + 1];
667 or_mask = registers[i + 2];
669 if (and_mask == 0xffffffff) {
674 if (adev->family >= AMDGPU_FAMILY_AI)
675 tmp |= (or_mask & and_mask);
684 * amdgpu_device_pci_config_reset - reset the GPU
686 * @adev: amdgpu_device pointer
688 * Resets the GPU using the pci config reset sequence.
689 * Only applicable to asics prior to vega10.
691 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
693 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
697 * GPU doorbell aperture helpers function.
700 * amdgpu_device_doorbell_init - Init doorbell driver information.
702 * @adev: amdgpu_device pointer
704 * Init doorbell driver information (CIK)
705 * Returns 0 on success, error on failure.
707 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
710 /* No doorbell on SI hardware generation */
711 if (adev->asic_type < CHIP_BONAIRE) {
712 adev->doorbell.base = 0;
713 adev->doorbell.size = 0;
714 adev->doorbell.num_doorbells = 0;
715 adev->doorbell.ptr = NULL;
719 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
722 amdgpu_asic_init_doorbell_index(adev);
724 /* doorbell bar mapping */
725 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
726 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
728 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
729 adev->doorbell_index.max_assignment+1);
730 if (adev->doorbell.num_doorbells == 0)
733 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
734 * paging queue doorbell use the second page. The
735 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
736 * doorbells are in the first page. So with paging queue enabled,
737 * the max num_doorbells should + 1 page (0x400 in dword)
739 if (adev->asic_type >= CHIP_VEGA10)
740 adev->doorbell.num_doorbells += 0x400;
742 adev->doorbell.ptr = ioremap(adev->doorbell.base,
743 adev->doorbell.num_doorbells *
745 if (adev->doorbell.ptr == NULL)
752 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
754 * @adev: amdgpu_device pointer
756 * Tear down doorbell driver information (CIK)
758 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
760 iounmap(adev->doorbell.ptr);
761 adev->doorbell.ptr = NULL;
767 * amdgpu_device_wb_*()
768 * Writeback is the method by which the GPU updates special pages in memory
769 * with the status of certain GPU events (fences, ring pointers,etc.).
773 * amdgpu_device_wb_fini - Disable Writeback and free memory
775 * @adev: amdgpu_device pointer
777 * Disables Writeback and frees the Writeback memory (all asics).
778 * Used at driver shutdown.
780 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
782 if (adev->wb.wb_obj) {
783 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
785 (void **)&adev->wb.wb);
786 adev->wb.wb_obj = NULL;
791 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
793 * @adev: amdgpu_device pointer
795 * Initializes writeback and allocates writeback memory (all asics).
796 * Used at driver startup.
797 * Returns 0 on success or an -error on failure.
799 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
803 if (adev->wb.wb_obj == NULL) {
804 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
805 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
806 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
807 &adev->wb.wb_obj, &adev->wb.gpu_addr,
808 (void **)&adev->wb.wb);
810 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
814 adev->wb.num_wb = AMDGPU_MAX_WB;
815 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
817 /* clear wb memory */
818 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
825 * amdgpu_device_wb_get - Allocate a wb entry
827 * @adev: amdgpu_device pointer
830 * Allocate a wb slot for use by the driver (all asics).
831 * Returns 0 on success or -EINVAL on failure.
833 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
835 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
837 if (offset < adev->wb.num_wb) {
838 __set_bit(offset, adev->wb.used);
839 *wb = offset << 3; /* convert to dw offset */
847 * amdgpu_device_wb_free - Free a wb entry
849 * @adev: amdgpu_device pointer
852 * Free a wb slot allocated for use by the driver (all asics)
854 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
857 if (wb < adev->wb.num_wb)
858 __clear_bit(wb, adev->wb.used);
862 * amdgpu_device_resize_fb_bar - try to resize FB BAR
864 * @adev: amdgpu_device pointer
866 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
867 * to fail, but if any of the BARs is not accessible after the size we abort
868 * driver loading by returning -ENODEV.
870 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
872 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
873 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
874 struct pci_bus *root;
875 struct resource *res;
881 if (amdgpu_sriov_vf(adev))
884 /* Check if the root BUS has 64bit memory resources */
885 root = adev->pdev->bus;
889 pci_bus_for_each_resource(root, res, i) {
890 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
891 res->start > 0x100000000ull)
895 /* Trying to resize is pointless without a root hub window above 4GB */
899 /* Disable memory decoding while we change the BAR addresses and size */
900 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
901 pci_write_config_word(adev->pdev, PCI_COMMAND,
902 cmd & ~PCI_COMMAND_MEMORY);
904 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
905 amdgpu_device_doorbell_fini(adev);
906 if (adev->asic_type >= CHIP_BONAIRE)
907 pci_release_resource(adev->pdev, 2);
909 pci_release_resource(adev->pdev, 0);
911 r = pci_resize_resource(adev->pdev, 0, rbar_size);
913 DRM_INFO("Not enough PCI address space for a large BAR.");
914 else if (r && r != -ENOTSUPP)
915 DRM_ERROR("Problem resizing BAR0 (%d).", r);
917 pci_assign_unassigned_bus_resources(adev->pdev->bus);
919 /* When the doorbell or fb BAR isn't available we have no chance of
922 r = amdgpu_device_doorbell_init(adev);
923 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
926 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
932 * GPU helpers function.
935 * amdgpu_device_need_post - check if the hw need post or not
937 * @adev: amdgpu_device pointer
939 * Check if the asic has been initialized (all asics) at driver startup
940 * or post is needed if hw reset is performed.
941 * Returns true if need or false if not.
943 bool amdgpu_device_need_post(struct amdgpu_device *adev)
947 if (amdgpu_sriov_vf(adev))
950 if (amdgpu_passthrough(adev)) {
951 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
952 * some old smc fw still need driver do vPost otherwise gpu hang, while
953 * those smc fw version above 22.15 doesn't have this flaw, so we force
954 * vpost executed for smc version below 22.15
956 if (adev->asic_type == CHIP_FIJI) {
959 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
960 /* force vPost if error occured */
964 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
965 if (fw_ver < 0x00160e00)
970 if (adev->has_hw_reset) {
971 adev->has_hw_reset = false;
975 /* bios scratch used on CIK+ */
976 if (adev->asic_type >= CHIP_BONAIRE)
977 return amdgpu_atombios_scratch_need_asic_init(adev);
979 /* check MEM_SIZE for older asics */
980 reg = amdgpu_asic_get_config_memsize(adev);
982 if ((reg != 0) && (reg != 0xffffffff))
988 /* if we get transitioned to only one device, take VGA back */
990 * amdgpu_device_vga_set_decode - enable/disable vga decode
992 * @cookie: amdgpu_device pointer
993 * @state: enable/disable vga decode
995 * Enable/disable vga decode (all asics).
996 * Returns VGA resource flags.
998 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
1000 struct amdgpu_device *adev = cookie;
1001 amdgpu_asic_set_vga_state(adev, state);
1003 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1004 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1006 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1010 * amdgpu_device_check_block_size - validate the vm block size
1012 * @adev: amdgpu_device pointer
1014 * Validates the vm block size specified via module parameter.
1015 * The vm block size defines number of bits in page table versus page directory,
1016 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1017 * page table and the remaining bits are in the page directory.
1019 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1021 /* defines number of bits in page table versus page directory,
1022 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1023 * page table and the remaining bits are in the page directory */
1024 if (amdgpu_vm_block_size == -1)
1027 if (amdgpu_vm_block_size < 9) {
1028 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1029 amdgpu_vm_block_size);
1030 amdgpu_vm_block_size = -1;
1035 * amdgpu_device_check_vm_size - validate the vm size
1037 * @adev: amdgpu_device pointer
1039 * Validates the vm size in GB specified via module parameter.
1040 * The VM size is the size of the GPU virtual memory space in GB.
1042 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1044 /* no need to check the default value */
1045 if (amdgpu_vm_size == -1)
1048 if (amdgpu_vm_size < 1) {
1049 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1051 amdgpu_vm_size = -1;
1055 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1058 bool is_os_64 = (sizeof(void *) == 8);
1059 uint64_t total_memory;
1060 uint64_t dram_size_seven_GB = 0x1B8000000;
1061 uint64_t dram_size_three_GB = 0xB8000000;
1063 if (amdgpu_smu_memory_pool_size == 0)
1067 DRM_WARN("Not 64-bit OS, feature not supported\n");
1071 total_memory = (uint64_t)si.totalram * si.mem_unit;
1073 if ((amdgpu_smu_memory_pool_size == 1) ||
1074 (amdgpu_smu_memory_pool_size == 2)) {
1075 if (total_memory < dram_size_three_GB)
1077 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1078 (amdgpu_smu_memory_pool_size == 8)) {
1079 if (total_memory < dram_size_seven_GB)
1082 DRM_WARN("Smu memory pool size not supported\n");
1085 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1090 DRM_WARN("No enough system memory\n");
1092 adev->pm.smu_prv_buffer_size = 0;
1096 * amdgpu_device_check_arguments - validate module params
1098 * @adev: amdgpu_device pointer
1100 * Validates certain module parameters and updates
1101 * the associated values used by the driver (all asics).
1103 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1105 if (amdgpu_sched_jobs < 4) {
1106 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1108 amdgpu_sched_jobs = 4;
1109 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1110 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1112 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1115 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1116 /* gart size must be greater or equal to 32M */
1117 dev_warn(adev->dev, "gart size (%d) too small\n",
1119 amdgpu_gart_size = -1;
1122 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1123 /* gtt size must be greater or equal to 32M */
1124 dev_warn(adev->dev, "gtt size (%d) too small\n",
1126 amdgpu_gtt_size = -1;
1129 /* valid range is between 4 and 9 inclusive */
1130 if (amdgpu_vm_fragment_size != -1 &&
1131 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1132 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1133 amdgpu_vm_fragment_size = -1;
1136 amdgpu_device_check_smu_prv_buffer_size(adev);
1138 amdgpu_device_check_vm_size(adev);
1140 amdgpu_device_check_block_size(adev);
1142 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1144 amdgpu_gmc_tmz_set(adev);
1150 * amdgpu_switcheroo_set_state - set switcheroo state
1152 * @pdev: pci dev pointer
1153 * @state: vga_switcheroo state
1155 * Callback for the switcheroo driver. Suspends or resumes the
1156 * the asics before or after it is powered up using ACPI methods.
1158 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1160 struct drm_device *dev = pci_get_drvdata(pdev);
1163 if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF)
1166 if (state == VGA_SWITCHEROO_ON) {
1167 pr_info("switched on\n");
1168 /* don't suspend or resume card normally */
1169 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1171 pci_set_power_state(dev->pdev, PCI_D0);
1172 pci_restore_state(dev->pdev);
1173 r = pci_enable_device(dev->pdev);
1175 DRM_WARN("pci_enable_device failed (%d)\n", r);
1176 amdgpu_device_resume(dev, true);
1178 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1179 drm_kms_helper_poll_enable(dev);
1181 pr_info("switched off\n");
1182 drm_kms_helper_poll_disable(dev);
1183 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1184 amdgpu_device_suspend(dev, true);
1185 pci_save_state(dev->pdev);
1186 /* Shut down the device */
1187 pci_disable_device(dev->pdev);
1188 pci_set_power_state(dev->pdev, PCI_D3cold);
1189 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1194 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1196 * @pdev: pci dev pointer
1198 * Callback for the switcheroo driver. Check of the switcheroo
1199 * state can be changed.
1200 * Returns true if the state can be changed, false if not.
1202 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1204 struct drm_device *dev = pci_get_drvdata(pdev);
1207 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1208 * locking inversion with the driver load path. And the access here is
1209 * completely racy anyway. So don't bother with locking for now.
1211 return atomic_read(&dev->open_count) == 0;
1214 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1215 .set_gpu_state = amdgpu_switcheroo_set_state,
1217 .can_switch = amdgpu_switcheroo_can_switch,
1221 * amdgpu_device_ip_set_clockgating_state - set the CG state
1223 * @dev: amdgpu_device pointer
1224 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1225 * @state: clockgating state (gate or ungate)
1227 * Sets the requested clockgating state for all instances of
1228 * the hardware IP specified.
1229 * Returns the error code from the last instance.
1231 int amdgpu_device_ip_set_clockgating_state(void *dev,
1232 enum amd_ip_block_type block_type,
1233 enum amd_clockgating_state state)
1235 struct amdgpu_device *adev = dev;
1238 for (i = 0; i < adev->num_ip_blocks; i++) {
1239 if (!adev->ip_blocks[i].status.valid)
1241 if (adev->ip_blocks[i].version->type != block_type)
1243 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1245 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1246 (void *)adev, state);
1248 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1249 adev->ip_blocks[i].version->funcs->name, r);
1255 * amdgpu_device_ip_set_powergating_state - set the PG state
1257 * @dev: amdgpu_device pointer
1258 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1259 * @state: powergating state (gate or ungate)
1261 * Sets the requested powergating state for all instances of
1262 * the hardware IP specified.
1263 * Returns the error code from the last instance.
1265 int amdgpu_device_ip_set_powergating_state(void *dev,
1266 enum amd_ip_block_type block_type,
1267 enum amd_powergating_state state)
1269 struct amdgpu_device *adev = dev;
1272 for (i = 0; i < adev->num_ip_blocks; i++) {
1273 if (!adev->ip_blocks[i].status.valid)
1275 if (adev->ip_blocks[i].version->type != block_type)
1277 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1279 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1280 (void *)adev, state);
1282 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1283 adev->ip_blocks[i].version->funcs->name, r);
1289 * amdgpu_device_ip_get_clockgating_state - get the CG state
1291 * @adev: amdgpu_device pointer
1292 * @flags: clockgating feature flags
1294 * Walks the list of IPs on the device and updates the clockgating
1295 * flags for each IP.
1296 * Updates @flags with the feature flags for each hardware IP where
1297 * clockgating is enabled.
1299 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1304 for (i = 0; i < adev->num_ip_blocks; i++) {
1305 if (!adev->ip_blocks[i].status.valid)
1307 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1308 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1313 * amdgpu_device_ip_wait_for_idle - wait for idle
1315 * @adev: amdgpu_device pointer
1316 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1318 * Waits for the request hardware IP to be idle.
1319 * Returns 0 for success or a negative error code on failure.
1321 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1322 enum amd_ip_block_type block_type)
1326 for (i = 0; i < adev->num_ip_blocks; i++) {
1327 if (!adev->ip_blocks[i].status.valid)
1329 if (adev->ip_blocks[i].version->type == block_type) {
1330 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1341 * amdgpu_device_ip_is_idle - is the hardware IP idle
1343 * @adev: amdgpu_device pointer
1344 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1346 * Check if the hardware IP is idle or not.
1347 * Returns true if it the IP is idle, false if not.
1349 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1350 enum amd_ip_block_type block_type)
1354 for (i = 0; i < adev->num_ip_blocks; i++) {
1355 if (!adev->ip_blocks[i].status.valid)
1357 if (adev->ip_blocks[i].version->type == block_type)
1358 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1365 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1367 * @adev: amdgpu_device pointer
1368 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1370 * Returns a pointer to the hardware IP block structure
1371 * if it exists for the asic, otherwise NULL.
1373 struct amdgpu_ip_block *
1374 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1375 enum amd_ip_block_type type)
1379 for (i = 0; i < adev->num_ip_blocks; i++)
1380 if (adev->ip_blocks[i].version->type == type)
1381 return &adev->ip_blocks[i];
1387 * amdgpu_device_ip_block_version_cmp
1389 * @adev: amdgpu_device pointer
1390 * @type: enum amd_ip_block_type
1391 * @major: major version
1392 * @minor: minor version
1394 * return 0 if equal or greater
1395 * return 1 if smaller or the ip_block doesn't exist
1397 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1398 enum amd_ip_block_type type,
1399 u32 major, u32 minor)
1401 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1403 if (ip_block && ((ip_block->version->major > major) ||
1404 ((ip_block->version->major == major) &&
1405 (ip_block->version->minor >= minor))))
1412 * amdgpu_device_ip_block_add
1414 * @adev: amdgpu_device pointer
1415 * @ip_block_version: pointer to the IP to add
1417 * Adds the IP block driver information to the collection of IPs
1420 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1421 const struct amdgpu_ip_block_version *ip_block_version)
1423 if (!ip_block_version)
1426 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1427 ip_block_version->funcs->name);
1429 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1435 * amdgpu_device_enable_virtual_display - enable virtual display feature
1437 * @adev: amdgpu_device pointer
1439 * Enabled the virtual display feature if the user has enabled it via
1440 * the module parameter virtual_display. This feature provides a virtual
1441 * display hardware on headless boards or in virtualized environments.
1442 * This function parses and validates the configuration string specified by
1443 * the user and configues the virtual display configuration (number of
1444 * virtual connectors, crtcs, etc.) specified.
1446 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1448 adev->enable_virtual_display = false;
1450 if (amdgpu_virtual_display) {
1451 struct drm_device *ddev = adev->ddev;
1452 const char *pci_address_name = pci_name(ddev->pdev);
1453 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1455 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1456 pciaddstr_tmp = pciaddstr;
1457 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1458 pciaddname = strsep(&pciaddname_tmp, ",");
1459 if (!strcmp("all", pciaddname)
1460 || !strcmp(pci_address_name, pciaddname)) {
1464 adev->enable_virtual_display = true;
1467 res = kstrtol(pciaddname_tmp, 10,
1475 adev->mode_info.num_crtc = num_crtc;
1477 adev->mode_info.num_crtc = 1;
1483 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1484 amdgpu_virtual_display, pci_address_name,
1485 adev->enable_virtual_display, adev->mode_info.num_crtc);
1492 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1494 * @adev: amdgpu_device pointer
1496 * Parses the asic configuration parameters specified in the gpu info
1497 * firmware and makes them availale to the driver for use in configuring
1499 * Returns 0 on success, -EINVAL on failure.
1501 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1503 const char *chip_name;
1506 const struct gpu_info_firmware_header_v1_0 *hdr;
1508 adev->firmware.gpu_info_fw = NULL;
1510 switch (adev->asic_type) {
1514 case CHIP_POLARIS10:
1515 case CHIP_POLARIS11:
1516 case CHIP_POLARIS12:
1520 #ifdef CONFIG_DRM_AMDGPU_SI
1527 #ifdef CONFIG_DRM_AMDGPU_CIK
1538 chip_name = "vega10";
1541 chip_name = "vega12";
1544 if (adev->rev_id >= 8)
1545 chip_name = "raven2";
1546 else if (adev->pdev->device == 0x15d8)
1547 chip_name = "picasso";
1549 chip_name = "raven";
1552 chip_name = "arcturus";
1555 chip_name = "renoir";
1558 chip_name = "navi10";
1561 chip_name = "navi14";
1564 chip_name = "navi12";
1568 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1569 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1572 "Failed to load gpu_info firmware \"%s\"\n",
1576 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1579 "Failed to validate gpu_info firmware \"%s\"\n",
1584 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1585 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1587 switch (hdr->version_major) {
1590 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1591 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1592 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1594 if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1595 goto parse_soc_bounding_box;
1597 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1598 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1599 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1600 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1601 adev->gfx.config.max_texture_channel_caches =
1602 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1603 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1604 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1605 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1606 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1607 adev->gfx.config.double_offchip_lds_buf =
1608 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1609 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1610 adev->gfx.cu_info.max_waves_per_simd =
1611 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1612 adev->gfx.cu_info.max_scratch_slots_per_cu =
1613 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1614 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1615 if (hdr->version_minor >= 1) {
1616 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
1617 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
1618 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1619 adev->gfx.config.num_sc_per_sh =
1620 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
1621 adev->gfx.config.num_packer_per_sc =
1622 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
1625 parse_soc_bounding_box:
1627 * soc bounding box info is not integrated in disocovery table,
1628 * we always need to parse it from gpu info firmware.
1630 if (hdr->version_minor == 2) {
1631 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
1632 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
1633 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1634 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
1640 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1649 * amdgpu_device_ip_early_init - run early init for hardware IPs
1651 * @adev: amdgpu_device pointer
1653 * Early initialization pass for hardware IPs. The hardware IPs that make
1654 * up each asic are discovered each IP's early_init callback is run. This
1655 * is the first stage in initializing the asic.
1656 * Returns 0 on success, negative error code on failure.
1658 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1662 amdgpu_device_enable_virtual_display(adev);
1664 switch (adev->asic_type) {
1668 case CHIP_POLARIS10:
1669 case CHIP_POLARIS11:
1670 case CHIP_POLARIS12:
1674 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1675 adev->family = AMDGPU_FAMILY_CZ;
1677 adev->family = AMDGPU_FAMILY_VI;
1679 r = vi_set_ip_blocks(adev);
1683 #ifdef CONFIG_DRM_AMDGPU_SI
1689 adev->family = AMDGPU_FAMILY_SI;
1690 r = si_set_ip_blocks(adev);
1695 #ifdef CONFIG_DRM_AMDGPU_CIK
1701 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1702 adev->family = AMDGPU_FAMILY_CI;
1704 adev->family = AMDGPU_FAMILY_KV;
1706 r = cik_set_ip_blocks(adev);
1717 if (adev->asic_type == CHIP_RAVEN ||
1718 adev->asic_type == CHIP_RENOIR)
1719 adev->family = AMDGPU_FAMILY_RV;
1721 adev->family = AMDGPU_FAMILY_AI;
1723 r = soc15_set_ip_blocks(adev);
1730 adev->family = AMDGPU_FAMILY_NV;
1732 r = nv_set_ip_blocks(adev);
1737 /* FIXME: not supported yet */
1741 r = amdgpu_device_parse_gpu_info_fw(adev);
1745 if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
1746 amdgpu_discovery_get_gfx_info(adev);
1748 amdgpu_amdkfd_device_probe(adev);
1750 if (amdgpu_sriov_vf(adev)) {
1751 /* handle vbios stuff prior full access mode for new handshake */
1752 if (adev->virt.req_init_data_ver == 1) {
1753 if (!amdgpu_get_bios(adev)) {
1754 DRM_ERROR("failed to get vbios\n");
1758 r = amdgpu_atombios_init(adev);
1760 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1761 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1767 /* we need to send REQ_GPU here for legacy handshaker otherwise the vbios
1768 * will not be prepared by host for this VF */
1769 if (amdgpu_sriov_vf(adev) && adev->virt.req_init_data_ver < 1) {
1770 r = amdgpu_virt_request_full_gpu(adev, true);
1775 adev->pm.pp_feature = amdgpu_pp_feature_mask;
1776 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
1777 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1779 for (i = 0; i < adev->num_ip_blocks; i++) {
1780 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1781 DRM_ERROR("disabled ip block: %d <%s>\n",
1782 i, adev->ip_blocks[i].version->funcs->name);
1783 adev->ip_blocks[i].status.valid = false;
1785 if (adev->ip_blocks[i].version->funcs->early_init) {
1786 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1788 adev->ip_blocks[i].status.valid = false;
1790 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1791 adev->ip_blocks[i].version->funcs->name, r);
1794 adev->ip_blocks[i].status.valid = true;
1797 adev->ip_blocks[i].status.valid = true;
1800 /* get the vbios after the asic_funcs are set up */
1801 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
1802 /* skip vbios handling for new handshake */
1803 if (amdgpu_sriov_vf(adev) && adev->virt.req_init_data_ver == 1)
1807 if (!amdgpu_get_bios(adev))
1810 r = amdgpu_atombios_init(adev);
1812 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1813 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1819 adev->cg_flags &= amdgpu_cg_mask;
1820 adev->pg_flags &= amdgpu_pg_mask;
1825 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1829 for (i = 0; i < adev->num_ip_blocks; i++) {
1830 if (!adev->ip_blocks[i].status.sw)
1832 if (adev->ip_blocks[i].status.hw)
1834 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1835 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1836 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1837 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1839 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1840 adev->ip_blocks[i].version->funcs->name, r);
1843 adev->ip_blocks[i].status.hw = true;
1850 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1854 for (i = 0; i < adev->num_ip_blocks; i++) {
1855 if (!adev->ip_blocks[i].status.sw)
1857 if (adev->ip_blocks[i].status.hw)
1859 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1861 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1862 adev->ip_blocks[i].version->funcs->name, r);
1865 adev->ip_blocks[i].status.hw = true;
1871 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1875 uint32_t smu_version;
1877 if (adev->asic_type >= CHIP_VEGA10) {
1878 for (i = 0; i < adev->num_ip_blocks; i++) {
1879 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
1882 /* no need to do the fw loading again if already done*/
1883 if (adev->ip_blocks[i].status.hw == true)
1886 if (adev->in_gpu_reset || adev->in_suspend) {
1887 r = adev->ip_blocks[i].version->funcs->resume(adev);
1889 DRM_ERROR("resume of IP block <%s> failed %d\n",
1890 adev->ip_blocks[i].version->funcs->name, r);
1894 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1896 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1897 adev->ip_blocks[i].version->funcs->name, r);
1902 adev->ip_blocks[i].status.hw = true;
1907 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
1908 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1914 * amdgpu_device_ip_init - run init for hardware IPs
1916 * @adev: amdgpu_device pointer
1918 * Main initialization pass for hardware IPs. The list of all the hardware
1919 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1920 * are run. sw_init initializes the software state associated with each IP
1921 * and hw_init initializes the hardware associated with each IP.
1922 * Returns 0 on success, negative error code on failure.
1924 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1928 r = amdgpu_ras_init(adev);
1932 if (amdgpu_sriov_vf(adev) && adev->virt.req_init_data_ver > 0) {
1933 r = amdgpu_virt_request_full_gpu(adev, true);
1938 for (i = 0; i < adev->num_ip_blocks; i++) {
1939 if (!adev->ip_blocks[i].status.valid)
1941 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1943 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1944 adev->ip_blocks[i].version->funcs->name, r);
1947 adev->ip_blocks[i].status.sw = true;
1949 /* need to do gmc hw init early so we can allocate gpu mem */
1950 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1951 r = amdgpu_device_vram_scratch_init(adev);
1953 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1956 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1958 DRM_ERROR("hw_init %d failed %d\n", i, r);
1961 r = amdgpu_device_wb_init(adev);
1963 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1966 adev->ip_blocks[i].status.hw = true;
1968 /* right after GMC hw init, we create CSA */
1969 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1970 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1971 AMDGPU_GEM_DOMAIN_VRAM,
1974 DRM_ERROR("allocate CSA failed %d\n", r);
1981 if (amdgpu_sriov_vf(adev))
1982 amdgpu_virt_init_data_exchange(adev);
1984 r = amdgpu_ib_pool_init(adev);
1986 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1987 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1991 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1995 r = amdgpu_device_ip_hw_init_phase1(adev);
1999 r = amdgpu_device_fw_loading(adev);
2003 r = amdgpu_device_ip_hw_init_phase2(adev);
2008 * retired pages will be loaded from eeprom and reserved here,
2009 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2010 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2011 * for I2C communication which only true at this point.
2012 * recovery_init may fail, but it can free all resources allocated by
2013 * itself and its failure should not stop amdgpu init process.
2015 * Note: theoretically, this should be called before all vram allocations
2016 * to protect retired page from abusing
2018 amdgpu_ras_recovery_init(adev);
2020 if (adev->gmc.xgmi.num_physical_nodes > 1)
2021 amdgpu_xgmi_add_device(adev);
2022 amdgpu_amdkfd_device_init(adev);
2024 amdgpu_fru_get_product_info(adev);
2027 if (amdgpu_sriov_vf(adev))
2028 amdgpu_virt_release_full_gpu(adev, true);
2034 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2036 * @adev: amdgpu_device pointer
2038 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2039 * this function before a GPU reset. If the value is retained after a
2040 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2042 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2044 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2048 * amdgpu_device_check_vram_lost - check if vram is valid
2050 * @adev: amdgpu_device pointer
2052 * Checks the reset magic value written to the gart pointer in VRAM.
2053 * The driver calls this after a GPU reset to see if the contents of
2054 * VRAM is lost or now.
2055 * returns true if vram is lost, false if not.
2057 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2059 if (memcmp(adev->gart.ptr, adev->reset_magic,
2060 AMDGPU_RESET_MAGIC_NUM))
2063 if (!adev->in_gpu_reset)
2067 * For all ASICs with baco/mode1 reset, the VRAM is
2068 * always assumed to be lost.
2070 switch (amdgpu_asic_reset_method(adev)) {
2071 case AMD_RESET_METHOD_BACO:
2072 case AMD_RESET_METHOD_MODE1:
2080 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2082 * @adev: amdgpu_device pointer
2083 * @state: clockgating state (gate or ungate)
2085 * The list of all the hardware IPs that make up the asic is walked and the
2086 * set_clockgating_state callbacks are run.
2087 * Late initialization pass enabling clockgating for hardware IPs.
2088 * Fini or suspend, pass disabling clockgating for hardware IPs.
2089 * Returns 0 on success, negative error code on failure.
2092 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2093 enum amd_clockgating_state state)
2097 if (amdgpu_emu_mode == 1)
2100 for (j = 0; j < adev->num_ip_blocks; j++) {
2101 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2102 if (!adev->ip_blocks[i].status.late_initialized)
2104 /* skip CG for VCE/UVD, it's handled specially */
2105 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2106 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2107 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2108 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2109 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2110 /* enable clockgating to save power */
2111 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2114 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2115 adev->ip_blocks[i].version->funcs->name, r);
2124 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
2128 if (amdgpu_emu_mode == 1)
2131 for (j = 0; j < adev->num_ip_blocks; j++) {
2132 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2133 if (!adev->ip_blocks[i].status.late_initialized)
2135 /* skip CG for VCE/UVD, it's handled specially */
2136 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2137 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2138 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2139 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2140 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2141 /* enable powergating to save power */
2142 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2145 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2146 adev->ip_blocks[i].version->funcs->name, r);
2154 static int amdgpu_device_enable_mgpu_fan_boost(void)
2156 struct amdgpu_gpu_instance *gpu_ins;
2157 struct amdgpu_device *adev;
2160 mutex_lock(&mgpu_info.mutex);
2163 * MGPU fan boost feature should be enabled
2164 * only when there are two or more dGPUs in
2167 if (mgpu_info.num_dgpu < 2)
2170 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2171 gpu_ins = &(mgpu_info.gpu_ins[i]);
2172 adev = gpu_ins->adev;
2173 if (!(adev->flags & AMD_IS_APU) &&
2174 !gpu_ins->mgpu_fan_enabled &&
2175 adev->powerplay.pp_funcs &&
2176 adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
2177 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2181 gpu_ins->mgpu_fan_enabled = 1;
2186 mutex_unlock(&mgpu_info.mutex);
2192 * amdgpu_device_ip_late_init - run late init for hardware IPs
2194 * @adev: amdgpu_device pointer
2196 * Late initialization pass for hardware IPs. The list of all the hardware
2197 * IPs that make up the asic is walked and the late_init callbacks are run.
2198 * late_init covers any special initialization that an IP requires
2199 * after all of the have been initialized or something that needs to happen
2200 * late in the init process.
2201 * Returns 0 on success, negative error code on failure.
2203 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2205 struct amdgpu_gpu_instance *gpu_instance;
2208 for (i = 0; i < adev->num_ip_blocks; i++) {
2209 if (!adev->ip_blocks[i].status.hw)
2211 if (adev->ip_blocks[i].version->funcs->late_init) {
2212 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2214 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2215 adev->ip_blocks[i].version->funcs->name, r);
2219 adev->ip_blocks[i].status.late_initialized = true;
2222 amdgpu_ras_set_error_query_ready(adev, true);
2224 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2225 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2227 amdgpu_device_fill_reset_magic(adev);
2229 r = amdgpu_device_enable_mgpu_fan_boost();
2231 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2234 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2235 mutex_lock(&mgpu_info.mutex);
2238 * Reset device p-state to low as this was booted with high.
2240 * This should be performed only after all devices from the same
2241 * hive get initialized.
2243 * However, it's unknown how many device in the hive in advance.
2244 * As this is counted one by one during devices initializations.
2246 * So, we wait for all XGMI interlinked devices initialized.
2247 * This may bring some delays as those devices may come from
2248 * different hives. But that should be OK.
2250 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2251 for (i = 0; i < mgpu_info.num_gpu; i++) {
2252 gpu_instance = &(mgpu_info.gpu_ins[i]);
2253 if (gpu_instance->adev->flags & AMD_IS_APU)
2256 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2257 AMDGPU_XGMI_PSTATE_MIN);
2259 DRM_ERROR("pstate setting failed (%d).\n", r);
2265 mutex_unlock(&mgpu_info.mutex);
2272 * amdgpu_device_ip_fini - run fini for hardware IPs
2274 * @adev: amdgpu_device pointer
2276 * Main teardown pass for hardware IPs. The list of all the hardware
2277 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2278 * are run. hw_fini tears down the hardware associated with each IP
2279 * and sw_fini tears down any software state associated with each IP.
2280 * Returns 0 on success, negative error code on failure.
2282 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2286 amdgpu_ras_pre_fini(adev);
2288 if (adev->gmc.xgmi.num_physical_nodes > 1)
2289 amdgpu_xgmi_remove_device(adev);
2291 amdgpu_amdkfd_device_fini(adev);
2293 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2294 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2296 /* need to disable SMC first */
2297 for (i = 0; i < adev->num_ip_blocks; i++) {
2298 if (!adev->ip_blocks[i].status.hw)
2300 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2301 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2302 /* XXX handle errors */
2304 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2305 adev->ip_blocks[i].version->funcs->name, r);
2307 adev->ip_blocks[i].status.hw = false;
2312 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2313 if (!adev->ip_blocks[i].status.hw)
2316 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2317 /* XXX handle errors */
2319 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2320 adev->ip_blocks[i].version->funcs->name, r);
2323 adev->ip_blocks[i].status.hw = false;
2327 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2328 if (!adev->ip_blocks[i].status.sw)
2331 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2332 amdgpu_ucode_free_bo(adev);
2333 amdgpu_free_static_csa(&adev->virt.csa_obj);
2334 amdgpu_device_wb_fini(adev);
2335 amdgpu_device_vram_scratch_fini(adev);
2336 amdgpu_ib_pool_fini(adev);
2339 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2340 /* XXX handle errors */
2342 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2343 adev->ip_blocks[i].version->funcs->name, r);
2345 adev->ip_blocks[i].status.sw = false;
2346 adev->ip_blocks[i].status.valid = false;
2349 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2350 if (!adev->ip_blocks[i].status.late_initialized)
2352 if (adev->ip_blocks[i].version->funcs->late_fini)
2353 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2354 adev->ip_blocks[i].status.late_initialized = false;
2357 amdgpu_ras_fini(adev);
2359 if (amdgpu_sriov_vf(adev))
2360 if (amdgpu_virt_release_full_gpu(adev, false))
2361 DRM_ERROR("failed to release exclusive mode on fini\n");
2367 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2369 * @work: work_struct.
2371 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2373 struct amdgpu_device *adev =
2374 container_of(work, struct amdgpu_device, delayed_init_work.work);
2377 r = amdgpu_ib_ring_tests(adev);
2379 DRM_ERROR("ib ring test failed (%d).\n", r);
2382 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2384 struct amdgpu_device *adev =
2385 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2387 mutex_lock(&adev->gfx.gfx_off_mutex);
2388 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2389 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2390 adev->gfx.gfx_off_state = true;
2392 mutex_unlock(&adev->gfx.gfx_off_mutex);
2396 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2398 * @adev: amdgpu_device pointer
2400 * Main suspend function for hardware IPs. The list of all the hardware
2401 * IPs that make up the asic is walked, clockgating is disabled and the
2402 * suspend callbacks are run. suspend puts the hardware and software state
2403 * in each IP into a state suitable for suspend.
2404 * Returns 0 on success, negative error code on failure.
2406 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2410 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2411 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2413 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2414 if (!adev->ip_blocks[i].status.valid)
2416 /* displays are handled separately */
2417 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2418 /* XXX handle errors */
2419 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2420 /* XXX handle errors */
2422 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2423 adev->ip_blocks[i].version->funcs->name, r);
2426 adev->ip_blocks[i].status.hw = false;
2434 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2436 * @adev: amdgpu_device pointer
2438 * Main suspend function for hardware IPs. The list of all the hardware
2439 * IPs that make up the asic is walked, clockgating is disabled and the
2440 * suspend callbacks are run. suspend puts the hardware and software state
2441 * in each IP into a state suitable for suspend.
2442 * Returns 0 on success, negative error code on failure.
2444 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2448 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2449 if (!adev->ip_blocks[i].status.valid)
2451 /* displays are handled in phase1 */
2452 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2454 /* PSP lost connection when err_event_athub occurs */
2455 if (amdgpu_ras_intr_triggered() &&
2456 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2457 adev->ip_blocks[i].status.hw = false;
2460 /* XXX handle errors */
2461 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2462 /* XXX handle errors */
2464 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2465 adev->ip_blocks[i].version->funcs->name, r);
2467 adev->ip_blocks[i].status.hw = false;
2468 /* handle putting the SMC in the appropriate state */
2469 if(!amdgpu_sriov_vf(adev)){
2470 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2471 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2473 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2474 adev->mp1_state, r);
2479 adev->ip_blocks[i].status.hw = false;
2486 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2488 * @adev: amdgpu_device pointer
2490 * Main suspend function for hardware IPs. The list of all the hardware
2491 * IPs that make up the asic is walked, clockgating is disabled and the
2492 * suspend callbacks are run. suspend puts the hardware and software state
2493 * in each IP into a state suitable for suspend.
2494 * Returns 0 on success, negative error code on failure.
2496 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2500 if (amdgpu_sriov_vf(adev))
2501 amdgpu_virt_request_full_gpu(adev, false);
2503 r = amdgpu_device_ip_suspend_phase1(adev);
2506 r = amdgpu_device_ip_suspend_phase2(adev);
2508 if (amdgpu_sriov_vf(adev))
2509 amdgpu_virt_release_full_gpu(adev, false);
2514 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2518 static enum amd_ip_block_type ip_order[] = {
2519 AMD_IP_BLOCK_TYPE_GMC,
2520 AMD_IP_BLOCK_TYPE_COMMON,
2521 AMD_IP_BLOCK_TYPE_PSP,
2522 AMD_IP_BLOCK_TYPE_IH,
2525 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2527 struct amdgpu_ip_block *block;
2529 for (j = 0; j < adev->num_ip_blocks; j++) {
2530 block = &adev->ip_blocks[j];
2532 block->status.hw = false;
2533 if (block->version->type != ip_order[i] ||
2534 !block->status.valid)
2537 r = block->version->funcs->hw_init(adev);
2538 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2541 block->status.hw = true;
2548 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2552 static enum amd_ip_block_type ip_order[] = {
2553 AMD_IP_BLOCK_TYPE_SMC,
2554 AMD_IP_BLOCK_TYPE_DCE,
2555 AMD_IP_BLOCK_TYPE_GFX,
2556 AMD_IP_BLOCK_TYPE_SDMA,
2557 AMD_IP_BLOCK_TYPE_UVD,
2558 AMD_IP_BLOCK_TYPE_VCE,
2559 AMD_IP_BLOCK_TYPE_VCN
2562 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2564 struct amdgpu_ip_block *block;
2566 for (j = 0; j < adev->num_ip_blocks; j++) {
2567 block = &adev->ip_blocks[j];
2569 if (block->version->type != ip_order[i] ||
2570 !block->status.valid ||
2574 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
2575 r = block->version->funcs->resume(adev);
2577 r = block->version->funcs->hw_init(adev);
2579 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2582 block->status.hw = true;
2590 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2592 * @adev: amdgpu_device pointer
2594 * First resume function for hardware IPs. The list of all the hardware
2595 * IPs that make up the asic is walked and the resume callbacks are run for
2596 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2597 * after a suspend and updates the software state as necessary. This
2598 * function is also used for restoring the GPU after a GPU reset.
2599 * Returns 0 on success, negative error code on failure.
2601 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2605 for (i = 0; i < adev->num_ip_blocks; i++) {
2606 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2608 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2609 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2610 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2612 r = adev->ip_blocks[i].version->funcs->resume(adev);
2614 DRM_ERROR("resume of IP block <%s> failed %d\n",
2615 adev->ip_blocks[i].version->funcs->name, r);
2618 adev->ip_blocks[i].status.hw = true;
2626 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2628 * @adev: amdgpu_device pointer
2630 * First resume function for hardware IPs. The list of all the hardware
2631 * IPs that make up the asic is walked and the resume callbacks are run for
2632 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2633 * functional state after a suspend and updates the software state as
2634 * necessary. This function is also used for restoring the GPU after a GPU
2636 * Returns 0 on success, negative error code on failure.
2638 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2642 for (i = 0; i < adev->num_ip_blocks; i++) {
2643 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
2645 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2646 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2647 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2648 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2650 r = adev->ip_blocks[i].version->funcs->resume(adev);
2652 DRM_ERROR("resume of IP block <%s> failed %d\n",
2653 adev->ip_blocks[i].version->funcs->name, r);
2656 adev->ip_blocks[i].status.hw = true;
2663 * amdgpu_device_ip_resume - run resume for hardware IPs
2665 * @adev: amdgpu_device pointer
2667 * Main resume function for hardware IPs. The hardware IPs
2668 * are split into two resume functions because they are
2669 * are also used in in recovering from a GPU reset and some additional
2670 * steps need to be take between them. In this case (S3/S4) they are
2672 * Returns 0 on success, negative error code on failure.
2674 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2678 r = amdgpu_device_ip_resume_phase1(adev);
2682 r = amdgpu_device_fw_loading(adev);
2686 r = amdgpu_device_ip_resume_phase2(adev);
2692 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2694 * @adev: amdgpu_device pointer
2696 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2698 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2700 if (amdgpu_sriov_vf(adev)) {
2701 if (adev->is_atom_fw) {
2702 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2703 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2705 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2706 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2709 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2710 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2715 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2717 * @asic_type: AMD asic type
2719 * Check if there is DC (new modesetting infrastructre) support for an asic.
2720 * returns true if DC has support, false if not.
2722 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2724 switch (asic_type) {
2725 #if defined(CONFIG_DRM_AMD_DC)
2731 * We have systems in the wild with these ASICs that require
2732 * LVDS and VGA support which is not supported with DC.
2734 * Fallback to the non-DC driver here by default so as not to
2735 * cause regressions.
2737 return amdgpu_dc > 0;
2741 case CHIP_POLARIS10:
2742 case CHIP_POLARIS11:
2743 case CHIP_POLARIS12:
2750 #if defined(CONFIG_DRM_AMD_DC_DCN)
2757 return amdgpu_dc != 0;
2761 DRM_INFO("Display Core has been requested via kernel parameter "
2762 "but isn't supported by ASIC, ignoring\n");
2768 * amdgpu_device_has_dc_support - check if dc is supported
2770 * @adev: amdgpu_device_pointer
2772 * Returns true for supported, false for not supported
2774 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2776 if (amdgpu_sriov_vf(adev))
2779 return amdgpu_device_asic_has_dc_support(adev->asic_type);
2783 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2785 struct amdgpu_device *adev =
2786 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2787 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
2789 /* It's a bug to not have a hive within this function */
2794 * Use task barrier to synchronize all xgmi reset works across the
2795 * hive. task_barrier_enter and task_barrier_exit will block
2796 * until all the threads running the xgmi reset works reach
2797 * those points. task_barrier_full will do both blocks.
2799 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
2801 task_barrier_enter(&hive->tb);
2802 adev->asic_reset_res = amdgpu_device_baco_enter(adev->ddev);
2804 if (adev->asic_reset_res)
2807 task_barrier_exit(&hive->tb);
2808 adev->asic_reset_res = amdgpu_device_baco_exit(adev->ddev);
2810 if (adev->asic_reset_res)
2813 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
2814 adev->mmhub.funcs->reset_ras_error_count(adev);
2817 task_barrier_full(&hive->tb);
2818 adev->asic_reset_res = amdgpu_asic_reset(adev);
2822 if (adev->asic_reset_res)
2823 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2824 adev->asic_reset_res, adev->ddev->unique);
2827 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
2829 char *input = amdgpu_lockup_timeout;
2830 char *timeout_setting = NULL;
2836 * By default timeout for non compute jobs is 10000.
2837 * And there is no timeout enforced on compute jobs.
2838 * In SR-IOV or passthrough mode, timeout for compute
2839 * jobs are 60000 by default.
2841 adev->gfx_timeout = msecs_to_jiffies(10000);
2842 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
2843 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
2844 adev->compute_timeout = msecs_to_jiffies(60000);
2846 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
2848 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
2849 while ((timeout_setting = strsep(&input, ",")) &&
2850 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
2851 ret = kstrtol(timeout_setting, 0, &timeout);
2858 } else if (timeout < 0) {
2859 timeout = MAX_SCHEDULE_TIMEOUT;
2861 timeout = msecs_to_jiffies(timeout);
2866 adev->gfx_timeout = timeout;
2869 adev->compute_timeout = timeout;
2872 adev->sdma_timeout = timeout;
2875 adev->video_timeout = timeout;
2882 * There is only one value specified and
2883 * it should apply to all non-compute jobs.
2886 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
2887 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
2888 adev->compute_timeout = adev->gfx_timeout;
2896 * amdgpu_device_init - initialize the driver
2898 * @adev: amdgpu_device pointer
2899 * @ddev: drm dev pointer
2900 * @pdev: pci dev pointer
2901 * @flags: driver flags
2903 * Initializes the driver info and hw (all asics).
2904 * Returns 0 for success or an error on failure.
2905 * Called at driver startup.
2907 int amdgpu_device_init(struct amdgpu_device *adev,
2908 struct drm_device *ddev,
2909 struct pci_dev *pdev,
2916 adev->shutdown = false;
2917 adev->dev = &pdev->dev;
2920 adev->flags = flags;
2922 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
2923 adev->asic_type = amdgpu_force_asic_type;
2925 adev->asic_type = flags & AMD_ASIC_MASK;
2927 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2928 if (amdgpu_emu_mode == 1)
2929 adev->usec_timeout *= 10;
2930 adev->gmc.gart_size = 512 * 1024 * 1024;
2931 adev->accel_working = false;
2932 adev->num_rings = 0;
2933 adev->mman.buffer_funcs = NULL;
2934 adev->mman.buffer_funcs_ring = NULL;
2935 adev->vm_manager.vm_pte_funcs = NULL;
2936 adev->vm_manager.vm_pte_num_scheds = 0;
2937 adev->gmc.gmc_funcs = NULL;
2938 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2939 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2941 adev->smc_rreg = &amdgpu_invalid_rreg;
2942 adev->smc_wreg = &amdgpu_invalid_wreg;
2943 adev->pcie_rreg = &amdgpu_invalid_rreg;
2944 adev->pcie_wreg = &amdgpu_invalid_wreg;
2945 adev->pciep_rreg = &amdgpu_invalid_rreg;
2946 adev->pciep_wreg = &amdgpu_invalid_wreg;
2947 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
2948 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
2949 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2950 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2951 adev->didt_rreg = &amdgpu_invalid_rreg;
2952 adev->didt_wreg = &amdgpu_invalid_wreg;
2953 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2954 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2955 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2956 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2958 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2959 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2960 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2962 /* mutex initialization are all done here so we
2963 * can recall function without having locking issues */
2964 atomic_set(&adev->irq.ih.lock, 0);
2965 mutex_init(&adev->firmware.mutex);
2966 mutex_init(&adev->pm.mutex);
2967 mutex_init(&adev->gfx.gpu_clock_mutex);
2968 mutex_init(&adev->srbm_mutex);
2969 mutex_init(&adev->gfx.pipe_reserve_mutex);
2970 mutex_init(&adev->gfx.gfx_off_mutex);
2971 mutex_init(&adev->grbm_idx_mutex);
2972 mutex_init(&adev->mn_lock);
2973 mutex_init(&adev->virt.vf_errors.lock);
2974 hash_init(adev->mn_hash);
2975 mutex_init(&adev->lock_reset);
2976 mutex_init(&adev->psp.mutex);
2977 mutex_init(&adev->notifier_lock);
2979 r = amdgpu_device_check_arguments(adev);
2983 spin_lock_init(&adev->mmio_idx_lock);
2984 spin_lock_init(&adev->smc_idx_lock);
2985 spin_lock_init(&adev->pcie_idx_lock);
2986 spin_lock_init(&adev->uvd_ctx_idx_lock);
2987 spin_lock_init(&adev->didt_idx_lock);
2988 spin_lock_init(&adev->gc_cac_idx_lock);
2989 spin_lock_init(&adev->se_cac_idx_lock);
2990 spin_lock_init(&adev->audio_endpt_idx_lock);
2991 spin_lock_init(&adev->mm_stats.lock);
2993 INIT_LIST_HEAD(&adev->shadow_list);
2994 mutex_init(&adev->shadow_list_lock);
2996 INIT_DELAYED_WORK(&adev->delayed_init_work,
2997 amdgpu_device_delayed_init_work_handler);
2998 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2999 amdgpu_device_delay_enable_gfx_off);
3001 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3003 adev->gfx.gfx_off_req_count = 1;
3004 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3006 /* Registers mapping */
3007 /* TODO: block userspace mapping of io register */
3008 if (adev->asic_type >= CHIP_BONAIRE) {
3009 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3010 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3012 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3013 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3016 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3017 if (adev->rmmio == NULL) {
3020 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3021 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3023 /* io port mapping */
3024 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3025 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
3026 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
3027 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
3031 if (adev->rio_mem == NULL)
3032 DRM_INFO("PCI I/O BAR is not found.\n");
3034 /* enable PCIE atomic ops */
3035 r = pci_enable_atomic_ops_to_root(adev->pdev,
3036 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3037 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3039 adev->have_atomics_support = false;
3040 DRM_INFO("PCIE atomic ops is not supported\n");
3042 adev->have_atomics_support = true;
3045 amdgpu_device_get_pcie_info(adev);
3048 DRM_INFO("MCBP is enabled\n");
3050 if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
3051 adev->enable_mes = true;
3053 /* detect hw virtualization here */
3054 amdgpu_detect_virtualization(adev);
3056 r = amdgpu_device_get_job_timeout_settings(adev);
3058 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3062 /* early init functions */
3063 r = amdgpu_device_ip_early_init(adev);
3067 /* doorbell bar mapping and doorbell index init*/
3068 amdgpu_device_doorbell_init(adev);
3070 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3071 /* this will fail for cards that aren't VGA class devices, just
3073 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
3075 if (amdgpu_device_supports_boco(ddev))
3077 if (amdgpu_has_atpx() &&
3078 (amdgpu_is_atpx_hybrid() ||
3079 amdgpu_has_atpx_dgpu_power_cntl()) &&
3080 !pci_is_thunderbolt_attached(adev->pdev))
3081 vga_switcheroo_register_client(adev->pdev,
3082 &amdgpu_switcheroo_ops, boco);
3084 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3086 if (amdgpu_emu_mode == 1) {
3087 /* post the asic on emulation mode */
3088 emu_soc_asic_init(adev);
3089 goto fence_driver_init;
3092 /* detect if we are with an SRIOV vbios */
3093 amdgpu_device_detect_sriov_bios(adev);
3095 /* check if we need to reset the asic
3096 * E.g., driver was not cleanly unloaded previously, etc.
3098 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3099 r = amdgpu_asic_reset(adev);
3101 dev_err(adev->dev, "asic reset on init failed\n");
3106 /* Post card if necessary */
3107 if (amdgpu_device_need_post(adev)) {
3109 dev_err(adev->dev, "no vBIOS found\n");
3113 DRM_INFO("GPU posting now...\n");
3114 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
3116 dev_err(adev->dev, "gpu post error!\n");
3121 if (adev->is_atom_fw) {
3122 /* Initialize clocks */
3123 r = amdgpu_atomfirmware_get_clock_info(adev);
3125 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3126 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3130 /* Initialize clocks */
3131 r = amdgpu_atombios_get_clock_info(adev);
3133 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3134 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3137 /* init i2c buses */
3138 if (!amdgpu_device_has_dc_support(adev))
3139 amdgpu_atombios_i2c_init(adev);
3144 r = amdgpu_fence_driver_init(adev);
3146 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
3147 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3151 /* init the mode config */
3152 drm_mode_config_init(adev->ddev);
3154 r = amdgpu_device_ip_init(adev);
3156 /* failed in exclusive mode due to timeout */
3157 if (amdgpu_sriov_vf(adev) &&
3158 !amdgpu_sriov_runtime(adev) &&
3159 amdgpu_virt_mmio_blocked(adev) &&
3160 !amdgpu_virt_wait_reset(adev)) {
3161 dev_err(adev->dev, "VF exclusive mode timeout\n");
3162 /* Don't send request since VF is inactive. */
3163 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3164 adev->virt.ops = NULL;
3168 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3169 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3174 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3175 adev->gfx.config.max_shader_engines,
3176 adev->gfx.config.max_sh_per_se,
3177 adev->gfx.config.max_cu_per_sh,
3178 adev->gfx.cu_info.number);
3180 adev->accel_working = true;
3182 amdgpu_vm_check_compute_bug(adev);
3184 /* Initialize the buffer migration limit. */
3185 if (amdgpu_moverate >= 0)
3186 max_MBps = amdgpu_moverate;
3188 max_MBps = 8; /* Allow 8 MB/s. */
3189 /* Get a log2 for easy divisions. */
3190 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3192 amdgpu_fbdev_init(adev);
3194 r = amdgpu_pm_sysfs_init(adev);
3196 adev->pm_sysfs_en = false;
3197 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3199 adev->pm_sysfs_en = true;
3201 r = amdgpu_ucode_sysfs_init(adev);
3203 adev->ucode_sysfs_en = false;
3204 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3206 adev->ucode_sysfs_en = true;
3208 if ((amdgpu_testing & 1)) {
3209 if (adev->accel_working)
3210 amdgpu_test_moves(adev);
3212 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
3214 if (amdgpu_benchmarking) {
3215 if (adev->accel_working)
3216 amdgpu_benchmark(adev, amdgpu_benchmarking);
3218 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
3222 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3223 * Otherwise the mgpu fan boost feature will be skipped due to the
3224 * gpu instance is counted less.
3226 amdgpu_register_gpu_instance(adev);
3228 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3229 * explicit gating rather than handling it automatically.
3231 r = amdgpu_device_ip_late_init(adev);
3233 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3234 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3239 amdgpu_ras_resume(adev);
3241 queue_delayed_work(system_wq, &adev->delayed_init_work,
3242 msecs_to_jiffies(AMDGPU_RESUME_MS));
3244 r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
3246 dev_err(adev->dev, "Could not create pcie_replay_count");
3250 r = device_create_file(adev->dev, &dev_attr_product_name);
3252 dev_err(adev->dev, "Could not create product_name");
3256 r = device_create_file(adev->dev, &dev_attr_product_number);
3258 dev_err(adev->dev, "Could not create product_number");
3262 r = device_create_file(adev->dev, &dev_attr_serial_number);
3264 dev_err(adev->dev, "Could not create serial_number");
3268 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3269 r = amdgpu_pmu_init(adev);
3271 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3276 amdgpu_vf_error_trans_all(adev);
3278 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3284 * amdgpu_device_fini - tear down the driver
3286 * @adev: amdgpu_device pointer
3288 * Tear down the driver info (all asics).
3289 * Called at driver shutdown.
3291 void amdgpu_device_fini(struct amdgpu_device *adev)
3295 DRM_INFO("amdgpu: finishing device.\n");
3296 flush_delayed_work(&adev->delayed_init_work);
3297 adev->shutdown = true;
3299 /* make sure IB test finished before entering exclusive mode
3300 * to avoid preemption on IB test
3302 if (amdgpu_sriov_vf(adev))
3303 amdgpu_virt_request_full_gpu(adev, false);
3305 /* disable all interrupts */
3306 amdgpu_irq_disable_all(adev);
3307 if (adev->mode_info.mode_config_initialized){
3308 if (!amdgpu_device_has_dc_support(adev))
3309 drm_helper_force_disable_all(adev->ddev);
3311 drm_atomic_helper_shutdown(adev->ddev);
3313 amdgpu_fence_driver_fini(adev);
3314 if (adev->pm_sysfs_en)
3315 amdgpu_pm_sysfs_fini(adev);
3316 amdgpu_fbdev_fini(adev);
3317 r = amdgpu_device_ip_fini(adev);
3318 if (adev->firmware.gpu_info_fw) {
3319 release_firmware(adev->firmware.gpu_info_fw);
3320 adev->firmware.gpu_info_fw = NULL;
3322 adev->accel_working = false;
3323 /* free i2c buses */
3324 if (!amdgpu_device_has_dc_support(adev))
3325 amdgpu_i2c_fini(adev);
3327 if (amdgpu_emu_mode != 1)
3328 amdgpu_atombios_fini(adev);
3332 if (amdgpu_has_atpx() &&
3333 (amdgpu_is_atpx_hybrid() ||
3334 amdgpu_has_atpx_dgpu_power_cntl()) &&
3335 !pci_is_thunderbolt_attached(adev->pdev))
3336 vga_switcheroo_unregister_client(adev->pdev);
3337 if (amdgpu_device_supports_boco(adev->ddev))
3338 vga_switcheroo_fini_domain_pm_ops(adev->dev);
3339 vga_client_register(adev->pdev, NULL, NULL, NULL);
3341 pci_iounmap(adev->pdev, adev->rio_mem);
3342 adev->rio_mem = NULL;
3343 iounmap(adev->rmmio);
3345 amdgpu_device_doorbell_fini(adev);
3347 device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
3348 if (adev->ucode_sysfs_en)
3349 amdgpu_ucode_sysfs_fini(adev);
3350 device_remove_file(adev->dev, &dev_attr_product_name);
3351 device_remove_file(adev->dev, &dev_attr_product_number);
3352 device_remove_file(adev->dev, &dev_attr_serial_number);
3353 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3354 amdgpu_pmu_fini(adev);
3355 if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
3356 amdgpu_discovery_fini(adev);
3364 * amdgpu_device_suspend - initiate device suspend
3366 * @dev: drm dev pointer
3367 * @suspend: suspend state
3368 * @fbcon : notify the fbdev of suspend
3370 * Puts the hw in the suspend state (all asics).
3371 * Returns 0 for success or an error on failure.
3372 * Called at driver suspend.
3374 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
3376 struct amdgpu_device *adev;
3377 struct drm_crtc *crtc;
3378 struct drm_connector *connector;
3379 struct drm_connector_list_iter iter;
3382 if (dev == NULL || dev->dev_private == NULL) {
3386 adev = dev->dev_private;
3388 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3391 adev->in_suspend = true;
3392 drm_kms_helper_poll_disable(dev);
3395 amdgpu_fbdev_set_suspend(adev, 1);
3397 cancel_delayed_work_sync(&adev->delayed_init_work);
3399 if (!amdgpu_device_has_dc_support(adev)) {
3400 /* turn off display hw */
3401 drm_modeset_lock_all(dev);
3402 drm_connector_list_iter_begin(dev, &iter);
3403 drm_for_each_connector_iter(connector, &iter)
3404 drm_helper_connector_dpms(connector,
3406 drm_connector_list_iter_end(&iter);
3407 drm_modeset_unlock_all(dev);
3408 /* unpin the front buffers and cursors */
3409 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3410 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3411 struct drm_framebuffer *fb = crtc->primary->fb;
3412 struct amdgpu_bo *robj;
3414 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3415 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3416 r = amdgpu_bo_reserve(aobj, true);
3418 amdgpu_bo_unpin(aobj);
3419 amdgpu_bo_unreserve(aobj);
3423 if (fb == NULL || fb->obj[0] == NULL) {
3426 robj = gem_to_amdgpu_bo(fb->obj[0]);
3427 /* don't unpin kernel fb objects */
3428 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
3429 r = amdgpu_bo_reserve(robj, true);
3431 amdgpu_bo_unpin(robj);
3432 amdgpu_bo_unreserve(robj);
3438 amdgpu_ras_suspend(adev);
3440 r = amdgpu_device_ip_suspend_phase1(adev);
3442 amdgpu_amdkfd_suspend(adev, !fbcon);
3444 /* evict vram memory */
3445 amdgpu_bo_evict_vram(adev);
3447 amdgpu_fence_driver_suspend(adev);
3449 r = amdgpu_device_ip_suspend_phase2(adev);
3451 /* evict remaining vram memory
3452 * This second call to evict vram is to evict the gart page table
3455 amdgpu_bo_evict_vram(adev);
3461 * amdgpu_device_resume - initiate device resume
3463 * @dev: drm dev pointer
3464 * @resume: resume state
3465 * @fbcon : notify the fbdev of resume
3467 * Bring the hw back to operating state (all asics).
3468 * Returns 0 for success or an error on failure.
3469 * Called at driver resume.
3471 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
3473 struct drm_connector *connector;
3474 struct drm_connector_list_iter iter;
3475 struct amdgpu_device *adev = dev->dev_private;
3476 struct drm_crtc *crtc;
3479 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
3483 if (amdgpu_device_need_post(adev)) {
3484 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
3486 DRM_ERROR("amdgpu asic init failed\n");
3489 r = amdgpu_device_ip_resume(adev);
3491 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
3494 amdgpu_fence_driver_resume(adev);
3497 r = amdgpu_device_ip_late_init(adev);
3501 queue_delayed_work(system_wq, &adev->delayed_init_work,
3502 msecs_to_jiffies(AMDGPU_RESUME_MS));
3504 if (!amdgpu_device_has_dc_support(adev)) {
3506 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3507 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3509 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
3510 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
3511 r = amdgpu_bo_reserve(aobj, true);
3513 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
3515 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
3516 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
3517 amdgpu_bo_unreserve(aobj);
3522 r = amdgpu_amdkfd_resume(adev, !fbcon);
3526 /* Make sure IB tests flushed */
3527 flush_delayed_work(&adev->delayed_init_work);
3529 /* blat the mode back in */
3531 if (!amdgpu_device_has_dc_support(adev)) {
3533 drm_helper_resume_force_mode(dev);
3535 /* turn on display hw */
3536 drm_modeset_lock_all(dev);
3538 drm_connector_list_iter_begin(dev, &iter);
3539 drm_for_each_connector_iter(connector, &iter)
3540 drm_helper_connector_dpms(connector,
3542 drm_connector_list_iter_end(&iter);
3544 drm_modeset_unlock_all(dev);
3546 amdgpu_fbdev_set_suspend(adev, 0);
3549 drm_kms_helper_poll_enable(dev);
3551 amdgpu_ras_resume(adev);
3554 * Most of the connector probing functions try to acquire runtime pm
3555 * refs to ensure that the GPU is powered on when connector polling is
3556 * performed. Since we're calling this from a runtime PM callback,
3557 * trying to acquire rpm refs will cause us to deadlock.
3559 * Since we're guaranteed to be holding the rpm lock, it's safe to
3560 * temporarily disable the rpm helpers so this doesn't deadlock us.
3563 dev->dev->power.disable_depth++;
3565 if (!amdgpu_device_has_dc_support(adev))
3566 drm_helper_hpd_irq_event(dev);
3568 drm_kms_helper_hotplug_event(dev);
3570 dev->dev->power.disable_depth--;
3572 adev->in_suspend = false;
3578 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3580 * @adev: amdgpu_device pointer
3582 * The list of all the hardware IPs that make up the asic is walked and
3583 * the check_soft_reset callbacks are run. check_soft_reset determines
3584 * if the asic is still hung or not.
3585 * Returns true if any of the IPs are still in a hung state, false if not.
3587 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3590 bool asic_hang = false;
3592 if (amdgpu_sriov_vf(adev))
3595 if (amdgpu_asic_need_full_reset(adev))
3598 for (i = 0; i < adev->num_ip_blocks; i++) {
3599 if (!adev->ip_blocks[i].status.valid)
3601 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3602 adev->ip_blocks[i].status.hang =
3603 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3604 if (adev->ip_blocks[i].status.hang) {
3605 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3613 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3615 * @adev: amdgpu_device pointer
3617 * The list of all the hardware IPs that make up the asic is walked and the
3618 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3619 * handles any IP specific hardware or software state changes that are
3620 * necessary for a soft reset to succeed.
3621 * Returns 0 on success, negative error code on failure.
3623 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3627 for (i = 0; i < adev->num_ip_blocks; i++) {
3628 if (!adev->ip_blocks[i].status.valid)
3630 if (adev->ip_blocks[i].status.hang &&
3631 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3632 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3642 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3644 * @adev: amdgpu_device pointer
3646 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3647 * reset is necessary to recover.
3648 * Returns true if a full asic reset is required, false if not.
3650 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3654 if (amdgpu_asic_need_full_reset(adev))
3657 for (i = 0; i < adev->num_ip_blocks; i++) {
3658 if (!adev->ip_blocks[i].status.valid)
3660 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3661 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3662 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3663 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3664 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3665 if (adev->ip_blocks[i].status.hang) {
3666 DRM_INFO("Some block need full reset!\n");
3675 * amdgpu_device_ip_soft_reset - do a soft reset
3677 * @adev: amdgpu_device pointer
3679 * The list of all the hardware IPs that make up the asic is walked and the
3680 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3681 * IP specific hardware or software state changes that are necessary to soft
3683 * Returns 0 on success, negative error code on failure.
3685 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3689 for (i = 0; i < adev->num_ip_blocks; i++) {
3690 if (!adev->ip_blocks[i].status.valid)
3692 if (adev->ip_blocks[i].status.hang &&
3693 adev->ip_blocks[i].version->funcs->soft_reset) {
3694 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3704 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3706 * @adev: amdgpu_device pointer
3708 * The list of all the hardware IPs that make up the asic is walked and the
3709 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3710 * handles any IP specific hardware or software state changes that are
3711 * necessary after the IP has been soft reset.
3712 * Returns 0 on success, negative error code on failure.
3714 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3718 for (i = 0; i < adev->num_ip_blocks; i++) {
3719 if (!adev->ip_blocks[i].status.valid)
3721 if (adev->ip_blocks[i].status.hang &&
3722 adev->ip_blocks[i].version->funcs->post_soft_reset)
3723 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3732 * amdgpu_device_recover_vram - Recover some VRAM contents
3734 * @adev: amdgpu_device pointer
3736 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
3737 * restore things like GPUVM page tables after a GPU reset where
3738 * the contents of VRAM might be lost.
3741 * 0 on success, negative error code on failure.
3743 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3745 struct dma_fence *fence = NULL, *next = NULL;
3746 struct amdgpu_bo *shadow;
3749 if (amdgpu_sriov_runtime(adev))
3750 tmo = msecs_to_jiffies(8000);
3752 tmo = msecs_to_jiffies(100);
3754 DRM_INFO("recover vram bo from shadow start\n");
3755 mutex_lock(&adev->shadow_list_lock);
3756 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3758 /* No need to recover an evicted BO */
3759 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3760 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3761 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3764 r = amdgpu_bo_restore_shadow(shadow, &next);
3769 tmo = dma_fence_wait_timeout(fence, false, tmo);
3770 dma_fence_put(fence);
3775 } else if (tmo < 0) {
3783 mutex_unlock(&adev->shadow_list_lock);
3786 tmo = dma_fence_wait_timeout(fence, false, tmo);
3787 dma_fence_put(fence);
3789 if (r < 0 || tmo <= 0) {
3790 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3794 DRM_INFO("recover vram bo from shadow done\n");
3800 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3802 * @adev: amdgpu device pointer
3803 * @from_hypervisor: request from hypervisor
3805 * do VF FLR and reinitialize Asic
3806 * return 0 means succeeded otherwise failed
3808 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3809 bool from_hypervisor)
3813 if (from_hypervisor)
3814 r = amdgpu_virt_request_full_gpu(adev, true);
3816 r = amdgpu_virt_reset_gpu(adev);
3820 amdgpu_amdkfd_pre_reset(adev);
3822 /* Resume IP prior to SMC */
3823 r = amdgpu_device_ip_reinit_early_sriov(adev);
3827 amdgpu_virt_init_data_exchange(adev);
3828 /* we need recover gart prior to run SMC/CP/SDMA resume */
3829 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3831 r = amdgpu_device_fw_loading(adev);
3835 /* now we are okay to resume SMC/CP/SDMA */
3836 r = amdgpu_device_ip_reinit_late_sriov(adev);
3840 amdgpu_irq_gpu_reset_resume_helper(adev);
3841 r = amdgpu_ib_ring_tests(adev);
3842 amdgpu_amdkfd_post_reset(adev);
3845 amdgpu_virt_release_full_gpu(adev, true);
3846 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3847 amdgpu_inc_vram_lost(adev);
3848 r = amdgpu_device_recover_vram(adev);
3855 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3857 * @adev: amdgpu device pointer
3859 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3862 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3864 if (!amdgpu_device_ip_check_soft_reset(adev)) {
3865 DRM_INFO("Timeout, but no hardware hang detected.\n");
3869 if (amdgpu_gpu_recovery == 0)
3872 if (amdgpu_sriov_vf(adev))
3875 if (amdgpu_gpu_recovery == -1) {
3876 switch (adev->asic_type) {
3882 case CHIP_POLARIS10:
3883 case CHIP_POLARIS11:
3884 case CHIP_POLARIS12:
3904 DRM_INFO("GPU recovery disabled.\n");
3909 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3910 struct amdgpu_job *job,
3911 bool *need_full_reset_arg)
3914 bool need_full_reset = *need_full_reset_arg;
3916 /* block all schedulers and reset given job's ring */
3917 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3918 struct amdgpu_ring *ring = adev->rings[i];
3920 if (!ring || !ring->sched.thread)
3923 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3924 amdgpu_fence_driver_force_completion(ring);
3928 drm_sched_increase_karma(&job->base);
3930 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3931 if (!amdgpu_sriov_vf(adev)) {
3933 if (!need_full_reset)
3934 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3936 if (!need_full_reset) {
3937 amdgpu_device_ip_pre_soft_reset(adev);
3938 r = amdgpu_device_ip_soft_reset(adev);
3939 amdgpu_device_ip_post_soft_reset(adev);
3940 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3941 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3942 need_full_reset = true;
3946 if (need_full_reset)
3947 r = amdgpu_device_ip_suspend(adev);
3949 *need_full_reset_arg = need_full_reset;
3955 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3956 struct list_head *device_list_handle,
3957 bool *need_full_reset_arg)
3959 struct amdgpu_device *tmp_adev = NULL;
3960 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3964 * ASIC reset has to be done on all HGMI hive nodes ASAP
3965 * to allow proper links negotiation in FW (within 1 sec)
3967 if (need_full_reset) {
3968 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3969 /* For XGMI run all resets in parallel to speed up the process */
3970 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3971 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
3974 r = amdgpu_asic_reset(tmp_adev);
3977 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3978 r, tmp_adev->ddev->unique);
3983 /* For XGMI wait for all resets to complete before proceed */
3985 list_for_each_entry(tmp_adev, device_list_handle,
3987 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3988 flush_work(&tmp_adev->xgmi_reset_work);
3989 r = tmp_adev->asic_reset_res;
3997 if (!r && amdgpu_ras_intr_triggered()) {
3998 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3999 if (tmp_adev->mmhub.funcs &&
4000 tmp_adev->mmhub.funcs->reset_ras_error_count)
4001 tmp_adev->mmhub.funcs->reset_ras_error_count(tmp_adev);
4004 amdgpu_ras_intr_cleared();
4007 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4008 if (need_full_reset) {
4010 if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
4011 DRM_WARN("asic atom init failed!");
4014 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4015 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4019 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4021 DRM_INFO("VRAM is lost due to GPU reset!\n");
4022 amdgpu_inc_vram_lost(tmp_adev);
4025 r = amdgpu_gtt_mgr_recover(
4026 &tmp_adev->mman.bdev.man[TTM_PL_TT]);
4030 r = amdgpu_device_fw_loading(tmp_adev);
4034 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4039 amdgpu_device_fill_reset_magic(tmp_adev);
4042 * Add this ASIC as tracked as reset was already
4043 * complete successfully.
4045 amdgpu_register_gpu_instance(tmp_adev);
4047 r = amdgpu_device_ip_late_init(tmp_adev);
4051 amdgpu_fbdev_set_suspend(tmp_adev, 0);
4054 amdgpu_ras_resume(tmp_adev);
4056 /* Update PSP FW topology after reset */
4057 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4058 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
4065 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
4066 r = amdgpu_ib_ring_tests(tmp_adev);
4068 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
4069 r = amdgpu_device_ip_suspend(tmp_adev);
4070 need_full_reset = true;
4077 r = amdgpu_device_recover_vram(tmp_adev);
4079 tmp_adev->asic_reset_res = r;
4083 *need_full_reset_arg = need_full_reset;
4087 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
4090 if (!mutex_trylock(&adev->lock_reset))
4093 mutex_lock(&adev->lock_reset);
4095 atomic_inc(&adev->gpu_reset_counter);
4096 adev->in_gpu_reset = true;
4097 switch (amdgpu_asic_reset_method(adev)) {
4098 case AMD_RESET_METHOD_MODE1:
4099 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
4101 case AMD_RESET_METHOD_MODE2:
4102 adev->mp1_state = PP_MP1_STATE_RESET;
4105 adev->mp1_state = PP_MP1_STATE_NONE;
4112 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4114 amdgpu_vf_error_trans_all(adev);
4115 adev->mp1_state = PP_MP1_STATE_NONE;
4116 adev->in_gpu_reset = false;
4117 mutex_unlock(&adev->lock_reset);
4120 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
4122 struct pci_dev *p = NULL;
4124 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4125 adev->pdev->bus->number, 1);
4127 pm_runtime_enable(&(p->dev));
4128 pm_runtime_resume(&(p->dev));
4132 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
4134 enum amd_reset_method reset_method;
4135 struct pci_dev *p = NULL;
4139 * For now, only BACO and mode1 reset are confirmed
4140 * to suffer the audio issue without proper suspended.
4142 reset_method = amdgpu_asic_reset_method(adev);
4143 if ((reset_method != AMD_RESET_METHOD_BACO) &&
4144 (reset_method != AMD_RESET_METHOD_MODE1))
4147 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
4148 adev->pdev->bus->number, 1);
4152 expires = pm_runtime_autosuspend_expiration(&(p->dev));
4155 * If we cannot get the audio device autosuspend delay,
4156 * a fixed 4S interval will be used. Considering 3S is
4157 * the audio controller default autosuspend delay setting.
4158 * 4S used here is guaranteed to cover that.
4160 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4L;
4162 while (!pm_runtime_status_suspended(&(p->dev))) {
4163 if (!pm_runtime_suspend(&(p->dev)))
4166 if (expires < ktime_get_mono_fast_ns()) {
4167 dev_warn(adev->dev, "failed to suspend display audio\n");
4168 /* TODO: abort the succeeding gpu reset? */
4173 pm_runtime_disable(&(p->dev));
4179 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
4181 * @adev: amdgpu device pointer
4182 * @job: which job trigger hang
4184 * Attempt to reset the GPU if it has hung (all asics).
4185 * Attempt to do soft-reset or full-reset and reinitialize Asic
4186 * Returns 0 for success or an error on failure.
4189 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
4190 struct amdgpu_job *job)
4192 struct list_head device_list, *device_list_handle = NULL;
4193 bool need_full_reset = false;
4194 bool job_signaled = false;
4195 struct amdgpu_hive_info *hive = NULL;
4196 struct amdgpu_device *tmp_adev = NULL;
4198 bool in_ras_intr = amdgpu_ras_intr_triggered();
4200 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
4202 bool audio_suspended = false;
4205 * Flush RAM to disk so that after reboot
4206 * the user can read log and see why the system rebooted.
4208 if (in_ras_intr && !use_baco && amdgpu_ras_get_context(adev)->reboot) {
4210 DRM_WARN("Emergency reboot.");
4213 emergency_restart();
4216 dev_info(adev->dev, "GPU %s begin!\n",
4217 (in_ras_intr && !use_baco) ? "jobs stop":"reset");
4220 * Here we trylock to avoid chain of resets executing from
4221 * either trigger by jobs on different adevs in XGMI hive or jobs on
4222 * different schedulers for same device while this TO handler is running.
4223 * We always reset all schedulers for device and all devices for XGMI
4224 * hive so that should take care of them too.
4226 hive = amdgpu_get_xgmi_hive(adev, true);
4227 if (hive && !mutex_trylock(&hive->reset_lock)) {
4228 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
4229 job ? job->base.id : -1, hive->hive_id);
4230 mutex_unlock(&hive->hive_lock);
4235 * Build list of devices to reset.
4236 * In case we are in XGMI hive mode, resort the device list
4237 * to put adev in the 1st position.
4239 INIT_LIST_HEAD(&device_list);
4240 if (adev->gmc.xgmi.num_physical_nodes > 1) {
4243 if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list))
4244 list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list);
4245 device_list_handle = &hive->device_list;
4247 list_add_tail(&adev->gmc.xgmi.head, &device_list);
4248 device_list_handle = &device_list;
4251 /* block all schedulers and reset given job's ring */
4252 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4253 if (!amdgpu_device_lock_adev(tmp_adev, !hive)) {
4254 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
4255 job ? job->base.id : -1);
4256 mutex_unlock(&hive->hive_lock);
4261 * Try to put the audio codec into suspend state
4262 * before gpu reset started.
4264 * Due to the power domain of the graphics device
4265 * is shared with AZ power domain. Without this,
4266 * we may change the audio hardware from behind
4267 * the audio driver's back. That will trigger
4268 * some audio codec errors.
4270 if (!amdgpu_device_suspend_display_audio(tmp_adev))
4271 audio_suspended = true;
4273 amdgpu_ras_set_error_query_ready(tmp_adev, false);
4275 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
4277 if (!amdgpu_sriov_vf(tmp_adev))
4278 amdgpu_amdkfd_pre_reset(tmp_adev);
4281 * Mark these ASICs to be reseted as untracked first
4282 * And add them back after reset completed
4284 amdgpu_unregister_gpu_instance(tmp_adev);
4286 amdgpu_fbdev_set_suspend(tmp_adev, 1);
4288 /* disable ras on ALL IPs */
4289 if (!(in_ras_intr && !use_baco) &&
4290 amdgpu_device_ip_need_full_reset(tmp_adev))
4291 amdgpu_ras_suspend(tmp_adev);
4293 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4294 struct amdgpu_ring *ring = tmp_adev->rings[i];
4296 if (!ring || !ring->sched.thread)
4299 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
4301 if (in_ras_intr && !use_baco)
4302 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
4306 if (in_ras_intr && !use_baco)
4307 goto skip_sched_resume;
4310 * Must check guilty signal here since after this point all old
4311 * HW fences are force signaled.
4313 * job->base holds a reference to parent fence
4315 if (job && job->base.s_fence->parent &&
4316 dma_fence_is_signaled(job->base.s_fence->parent)) {
4317 job_signaled = true;
4318 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
4322 retry: /* Rest of adevs pre asic reset from XGMI hive. */
4323 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4324 r = amdgpu_device_pre_asic_reset(tmp_adev,
4327 /*TODO Should we stop ?*/
4329 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
4330 r, tmp_adev->ddev->unique);
4331 tmp_adev->asic_reset_res = r;
4335 /* Actual ASIC resets if needed.*/
4336 /* TODO Implement XGMI hive reset logic for SRIOV */
4337 if (amdgpu_sriov_vf(adev)) {
4338 r = amdgpu_device_reset_sriov(adev, job ? false : true);
4340 adev->asic_reset_res = r;
4342 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
4343 if (r && r == -EAGAIN)
4349 /* Post ASIC reset for all devs .*/
4350 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4352 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4353 struct amdgpu_ring *ring = tmp_adev->rings[i];
4355 if (!ring || !ring->sched.thread)
4358 /* No point to resubmit jobs if we didn't HW reset*/
4359 if (!tmp_adev->asic_reset_res && !job_signaled)
4360 drm_sched_resubmit_jobs(&ring->sched);
4362 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
4365 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
4366 drm_helper_resume_force_mode(tmp_adev->ddev);
4369 tmp_adev->asic_reset_res = 0;
4372 /* bad news, how to tell it to userspace ? */
4373 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
4374 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
4376 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
4381 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
4382 /*unlock kfd: SRIOV would do it separately */
4383 if (!(in_ras_intr && !use_baco) && !amdgpu_sriov_vf(tmp_adev))
4384 amdgpu_amdkfd_post_reset(tmp_adev);
4385 if (audio_suspended)
4386 amdgpu_device_resume_display_audio(tmp_adev);
4387 amdgpu_device_unlock_adev(tmp_adev);
4391 mutex_unlock(&hive->reset_lock);
4392 mutex_unlock(&hive->hive_lock);
4396 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
4401 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
4403 * @adev: amdgpu_device pointer
4405 * Fetchs and stores in the driver the PCIE capabilities (gen speed
4406 * and lanes) of the slot the device is in. Handles APUs and
4407 * virtualized environments where PCIE config space may not be available.
4409 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
4411 struct pci_dev *pdev;
4412 enum pci_bus_speed speed_cap, platform_speed_cap;
4413 enum pcie_link_width platform_link_width;
4415 if (amdgpu_pcie_gen_cap)
4416 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
4418 if (amdgpu_pcie_lane_cap)
4419 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
4421 /* covers APUs as well */
4422 if (pci_is_root_bus(adev->pdev->bus)) {
4423 if (adev->pm.pcie_gen_mask == 0)
4424 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4425 if (adev->pm.pcie_mlw_mask == 0)
4426 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4430 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
4433 pcie_bandwidth_available(adev->pdev, NULL,
4434 &platform_speed_cap, &platform_link_width);
4436 if (adev->pm.pcie_gen_mask == 0) {
4439 speed_cap = pcie_get_speed_cap(pdev);
4440 if (speed_cap == PCI_SPEED_UNKNOWN) {
4441 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4442 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4443 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4445 if (speed_cap == PCIE_SPEED_16_0GT)
4446 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4447 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4448 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4449 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
4450 else if (speed_cap == PCIE_SPEED_8_0GT)
4451 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4452 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4453 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
4454 else if (speed_cap == PCIE_SPEED_5_0GT)
4455 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4456 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
4458 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
4461 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
4462 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4463 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4465 if (platform_speed_cap == PCIE_SPEED_16_0GT)
4466 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4467 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4468 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
4469 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
4470 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
4471 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4472 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
4473 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
4474 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
4475 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
4476 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
4478 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
4482 if (adev->pm.pcie_mlw_mask == 0) {
4483 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
4484 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
4486 switch (platform_link_width) {
4488 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
4489 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4490 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4491 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4492 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4493 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4494 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4497 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
4498 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4499 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4500 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4501 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4502 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4505 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
4506 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4507 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4508 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4509 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4512 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
4513 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4514 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4515 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4518 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
4519 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4520 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4523 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
4524 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
4527 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
4536 int amdgpu_device_baco_enter(struct drm_device *dev)
4538 struct amdgpu_device *adev = dev->dev_private;
4539 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4541 if (!amdgpu_device_supports_baco(adev->ddev))
4544 if (ras && ras->supported)
4545 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
4547 return amdgpu_dpm_baco_enter(adev);
4550 int amdgpu_device_baco_exit(struct drm_device *dev)
4552 struct amdgpu_device *adev = dev->dev_private;
4553 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4556 if (!amdgpu_device_supports_baco(adev->ddev))
4559 ret = amdgpu_dpm_baco_exit(adev);
4563 if (ras && ras->supported)
4564 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);