drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/console.h>
  31 #include <linux/slab.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <linux/vgaarb.h>
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/efi.h>
  39 #include "amdgpu.h"
  40 #include "amdgpu_trace.h"
  41 #include "amdgpu_i2c.h"
  42 #include "atom.h"
  43 #include "amdgpu_atombios.h"
  44 #include "amdgpu_atomfirmware.h"
  45 #include "amd_pcie.h"
  46 #ifdef CONFIG_DRM_AMDGPU_SI
  47 #include "si.h"
  48 #endif
  49 #ifdef CONFIG_DRM_AMDGPU_CIK
  50 #include "cik.h"
  51 #endif
  52 #include "vi.h"
  53 #include "soc15.h"
  54 #include "bif/bif_4_1_d.h"
  55 #include <linux/pci.h>
  56 #include <linux/firmware.h>
  57 #include "amdgpu_vf_error.h"
  58
  59 #include "amdgpu_amdkfd.h"
  60 #include "amdgpu_pm.h"
  61
  62 #include "amdgpu_xgmi.h"
  63 #include "amdgpu_ras.h"
  64
  65 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  66 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
  67 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  68 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
  69 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
  70
  71 #define AMDGPU_RESUME_MS                2000
  72
  73 static const char *amdgpu_asic_name[] = {
  74         "TAHITI",
  75         "PITCAIRN",
  76         "VERDE",
  77         "OLAND",
  78         "HAINAN",
  79         "BONAIRE",
  80         "KAVERI",
  81         "KABINI",
  82         "HAWAII",
  83         "MULLINS",
  84         "TOPAZ",
  85         "TONGA",
  86         "FIJI",
  87         "CARRIZO",
  88         "STONEY",
  89         "POLARIS10",
  90         "POLARIS11",
  91         "POLARIS12",
  92         "VEGAM",
  93         "VEGA10",
  94         "VEGA12",
  95         "VEGA20",
  96         "RAVEN",
  97         "LAST",
  98 };
  99
 100 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 101
 102 /**
 103  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 104  *
 105  * @dev: drm_device pointer
 106  *
 107  * Returns true if the device is a dGPU with HG/PX power control,
 108  * otherwise return false.
 109  */
 110 bool amdgpu_device_is_px(struct drm_device *dev)
 111 {
 112         struct amdgpu_device *adev = dev->dev_private;
 113
 114         if (adev->flags & AMD_IS_PX)
 115                 return true;
 116         return false;
 117 }
 118
 119 /*
 120  * MMIO register access helper functions.
 121  */
 122 /**
 123  * amdgpu_mm_rreg - read a memory mapped IO register
 124  *
 125  * @adev: amdgpu_device pointer
 126  * @reg: dword aligned register offset
 127  * @acc_flags: access flags which require special behavior
 128  *
 129  * Returns the 32 bit value from the offset specified.
 130  */
 131 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 132                         uint32_t acc_flags)
 133 {
 134         uint32_t ret;
 135
 136         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 137                 return amdgpu_virt_kiq_rreg(adev, reg);
 138
 139         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 140                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 141         else {
 142                 unsigned long flags;
 143
 144                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 145                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 146                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 147                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 148         }
 149         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 150         return ret;
 151 }
 152
 153 /*
 154  * MMIO register read with bytes helper functions
 155  * @offset:bytes offset from MMIO start
 156  *
 157 */
 158
 159 /**
 160  * amdgpu_mm_rreg8 - read a memory mapped IO register
 161  *
 162  * @adev: amdgpu_device pointer
 163  * @offset: byte aligned register offset
 164  *
 165  * Returns the 8 bit value from the offset specified.
 166  */
 167 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 168         if (offset < adev->rmmio_size)
 169                 return (readb(adev->rmmio + offset));
 170         BUG();
 171 }
 172
 173 /*
 174  * MMIO register write with bytes helper functions
 175  * @offset:bytes offset from MMIO start
 176  * @value: the value want to be written to the register
 177  *
 178 */
 179 /**
 180  * amdgpu_mm_wreg8 - read a memory mapped IO register
 181  *
 182  * @adev: amdgpu_device pointer
 183  * @offset: byte aligned register offset
 184  * @value: 8 bit value to write
 185  *
 186  * Writes the value specified to the offset specified.
 187  */
 188 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 189         if (offset < adev->rmmio_size)
 190                 writeb(value, adev->rmmio + offset);
 191         else
 192                 BUG();
 193 }
 194
 195 /**
 196  * amdgpu_mm_wreg - write to a memory mapped IO register
 197  *
 198  * @adev: amdgpu_device pointer
 199  * @reg: dword aligned register offset
 200  * @v: 32 bit value to write to the register
 201  * @acc_flags: access flags which require special behavior
 202  *
 203  * Writes the value specified to the offset specified.
 204  */
 205 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 206                     uint32_t acc_flags)
 207 {
 208         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 209
 210         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 211                 adev->last_mm_index = v;
 212         }
 213
 214         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 215                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 216
 217         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 218                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 219         else {
 220                 unsigned long flags;
 221
 222                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 223                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 224                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 225                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 226         }
 227
 228         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 229                 udelay(500);
 230         }
 231 }
 232
 233 /**
 234  * amdgpu_io_rreg - read an IO register
 235  *
 236  * @adev: amdgpu_device pointer
 237  * @reg: dword aligned register offset
 238  *
 239  * Returns the 32 bit value from the offset specified.
 240  */
 241 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 242 {
 243         if ((reg * 4) < adev->rio_mem_size)
 244                 return ioread32(adev->rio_mem + (reg * 4));
 245         else {
 246                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 247                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 248         }
 249 }
 250
 251 /**
 252  * amdgpu_io_wreg - write to an IO register
 253  *
 254  * @adev: amdgpu_device pointer
 255  * @reg: dword aligned register offset
 256  * @v: 32 bit value to write to the register
 257  *
 258  * Writes the value specified to the offset specified.
 259  */
 260 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 261 {
 262         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 263                 adev->last_mm_index = v;
 264         }
 265
 266         if ((reg * 4) < adev->rio_mem_size)
 267                 iowrite32(v, adev->rio_mem + (reg * 4));
 268         else {
 269                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 270                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 271         }
 272
 273         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 274                 udelay(500);
 275         }
 276 }
 277
 278 /**
 279  * amdgpu_mm_rdoorbell - read a doorbell dword
 280  *
 281  * @adev: amdgpu_device pointer
 282  * @index: doorbell index
 283  *
 284  * Returns the value in the doorbell aperture at the
 285  * requested doorbell index (CIK).
 286  */
 287 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 288 {
 289         if (index < adev->doorbell.num_doorbells) {
 290                 return readl(adev->doorbell.ptr + index);
 291         } else {
 292                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 293                 return 0;
 294         }
 295 }
 296
 297 /**
 298  * amdgpu_mm_wdoorbell - write a doorbell dword
 299  *
 300  * @adev: amdgpu_device pointer
 301  * @index: doorbell index
 302  * @v: value to write
 303  *
 304  * Writes @v to the doorbell aperture at the
 305  * requested doorbell index (CIK).
 306  */
 307 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 308 {
 309         if (index < adev->doorbell.num_doorbells) {
 310                 writel(v, adev->doorbell.ptr + index);
 311         } else {
 312                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 313         }
 314 }
 315
 316 /**
 317  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 318  *
 319  * @adev: amdgpu_device pointer
 320  * @index: doorbell index
 321  *
 322  * Returns the value in the doorbell aperture at the
 323  * requested doorbell index (VEGA10+).
 324  */
 325 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 326 {
 327         if (index < adev->doorbell.num_doorbells) {
 328                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 329         } else {
 330                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 331                 return 0;
 332         }
 333 }
 334
 335 /**
 336  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 337  *
 338  * @adev: amdgpu_device pointer
 339  * @index: doorbell index
 340  * @v: value to write
 341  *
 342  * Writes @v to the doorbell aperture at the
 343  * requested doorbell index (VEGA10+).
 344  */
 345 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 346 {
 347         if (index < adev->doorbell.num_doorbells) {
 348                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 349         } else {
 350                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 351         }
 352 }
 353
 354 /**
 355  * amdgpu_invalid_rreg - dummy reg read function
 356  *
 357  * @adev: amdgpu device pointer
 358  * @reg: offset of register
 359  *
 360  * Dummy register read function.  Used for register blocks
 361  * that certain asics don't have (all asics).
 362  * Returns the value in the register.
 363  */
 364 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 365 {
 366         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 367         BUG();
 368         return 0;
 369 }
 370
 371 /**
 372  * amdgpu_invalid_wreg - dummy reg write function
 373  *
 374  * @adev: amdgpu device pointer
 375  * @reg: offset of register
 376  * @v: value to write to the register
 377  *
 378  * Dummy register read function.  Used for register blocks
 379  * that certain asics don't have (all asics).
 380  */
 381 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 382 {
 383         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 384                   reg, v);
 385         BUG();
 386 }
 387
 388 /**
 389  * amdgpu_block_invalid_rreg - dummy reg read function
 390  *
 391  * @adev: amdgpu device pointer
 392  * @block: offset of instance
 393  * @reg: offset of register
 394  *
 395  * Dummy register read function.  Used for register blocks
 396  * that certain asics don't have (all asics).
 397  * Returns the value in the register.
 398  */
 399 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 400                                           uint32_t block, uint32_t reg)
 401 {
 402         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 403                   reg, block);
 404         BUG();
 405         return 0;
 406 }
 407
 408 /**
 409  * amdgpu_block_invalid_wreg - dummy reg write function
 410  *
 411  * @adev: amdgpu device pointer
 412  * @block: offset of instance
 413  * @reg: offset of register
 414  * @v: value to write to the register
 415  *
 416  * Dummy register read function.  Used for register blocks
 417  * that certain asics don't have (all asics).
 418  */
 419 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 420                                       uint32_t block,
 421                                       uint32_t reg, uint32_t v)
 422 {
 423         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 424                   reg, block, v);
 425         BUG();
 426 }
 427
 428 /**
 429  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 430  *
 431  * @adev: amdgpu device pointer
 432  *
 433  * Allocates a scratch page of VRAM for use by various things in the
 434  * driver.
 435  */
 436 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 437 {
 438         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 439                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 440                                        &adev->vram_scratch.robj,
 441                                        &adev->vram_scratch.gpu_addr,
 442                                        (void **)&adev->vram_scratch.ptr);
 443 }
 444
 445 /**
 446  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 447  *
 448  * @adev: amdgpu device pointer
 449  *
 450  * Frees the VRAM scratch page.
 451  */
 452 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 453 {
 454         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 455 }
 456
 457 /**
 458  * amdgpu_device_program_register_sequence - program an array of registers.
 459  *
 460  * @adev: amdgpu_device pointer
 461  * @registers: pointer to the register array
 462  * @array_size: size of the register array
 463  *
 464  * Programs an array or registers with and and or masks.
 465  * This is a helper for setting golden registers.
 466  */
 467 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 468                                              const u32 *registers,
 469                                              const u32 array_size)
 470 {
 471         u32 tmp, reg, and_mask, or_mask;
 472         int i;
 473
 474         if (array_size % 3)
 475                 return;
 476
 477         for (i = 0; i < array_size; i +=3) {
 478                 reg = registers[i + 0];
 479                 and_mask = registers[i + 1];
 480                 or_mask = registers[i + 2];
 481
 482                 if (and_mask == 0xffffffff) {
 483                         tmp = or_mask;
 484                 } else {
 485                         tmp = RREG32(reg);
 486                         tmp &= ~and_mask;
 487                         tmp |= or_mask;
 488                 }
 489                 WREG32(reg, tmp);
 490         }
 491 }
 492
 493 /**
 494  * amdgpu_device_pci_config_reset - reset the GPU
 495  *
 496  * @adev: amdgpu_device pointer
 497  *
 498  * Resets the GPU using the pci config reset sequence.
 499  * Only applicable to asics prior to vega10.
 500  */
 501 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 502 {
 503         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 504 }
 505
 506 /*
 507  * GPU doorbell aperture helpers function.
 508  */
 509 /**
 510  * amdgpu_device_doorbell_init - Init doorbell driver information.
 511  *
 512  * @adev: amdgpu_device pointer
 513  *
 514  * Init doorbell driver information (CIK)
 515  * Returns 0 on success, error on failure.
 516  */
 517 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 518 {
 519
 520         /* No doorbell on SI hardware generation */
 521         if (adev->asic_type < CHIP_BONAIRE) {
 522                 adev->doorbell.base = 0;
 523                 adev->doorbell.size = 0;
 524                 adev->doorbell.num_doorbells = 0;
 525                 adev->doorbell.ptr = NULL;
 526                 return 0;
 527         }
 528
 529         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 530                 return -EINVAL;
 531
 532         amdgpu_asic_init_doorbell_index(adev);
 533
 534         /* doorbell bar mapping */
 535         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 536         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 537
 538         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 539                                              adev->doorbell_index.max_assignment+1);
 540         if (adev->doorbell.num_doorbells == 0)
 541                 return -EINVAL;
 542
 543         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
 544          * paging queue doorbell use the second page. The
 545          * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
 546          * doorbells are in the first page. So with paging queue enabled,
 547          * the max num_doorbells should + 1 page (0x400 in dword)
 548          */
 549         if (adev->asic_type >= CHIP_VEGA10)
 550                 adev->doorbell.num_doorbells += 0x400;
 551
 552         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 553                                      adev->doorbell.num_doorbells *
 554                                      sizeof(u32));
 555         if (adev->doorbell.ptr == NULL)
 556                 return -ENOMEM;
 557
 558         return 0;
 559 }
 560
 561 /**
 562  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 563  *
 564  * @adev: amdgpu_device pointer
 565  *
 566  * Tear down doorbell driver information (CIK)
 567  */
 568 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 569 {
 570         iounmap(adev->doorbell.ptr);
 571         adev->doorbell.ptr = NULL;
 572 }
 573
 574
 575
 576 /*
 577  * amdgpu_device_wb_*()
 578  * Writeback is the method by which the GPU updates special pages in memory
 579  * with the status of certain GPU events (fences, ring pointers,etc.).
 580  */
 581
 582 /**
 583  * amdgpu_device_wb_fini - Disable Writeback and free memory
 584  *
 585  * @adev: amdgpu_device pointer
 586  *
 587  * Disables Writeback and frees the Writeback memory (all asics).
 588  * Used at driver shutdown.
 589  */
 590 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 591 {
 592         if (adev->wb.wb_obj) {
 593                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 594                                       &adev->wb.gpu_addr,
 595                                       (void **)&adev->wb.wb);
 596                 adev->wb.wb_obj = NULL;
 597         }
 598 }
 599
 600 /**
 601  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 602  *
 603  * @adev: amdgpu_device pointer
 604  *
 605  * Initializes writeback and allocates writeback memory (all asics).
 606  * Used at driver startup.
 607  * Returns 0 on success or an -error on failure.
 608  */
 609 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 610 {
 611         int r;
 612
 613         if (adev->wb.wb_obj == NULL) {
 614                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 615                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 616                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 617                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 618                                             (void **)&adev->wb.wb);
 619                 if (r) {
 620                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 621                         return r;
 622                 }
 623
 624                 adev->wb.num_wb = AMDGPU_MAX_WB;
 625                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 626
 627                 /* clear wb memory */
 628                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 629         }
 630
 631         return 0;
 632 }
 633
 634 /**
 635  * amdgpu_device_wb_get - Allocate a wb entry
 636  *
 637  * @adev: amdgpu_device pointer
 638  * @wb: wb index
 639  *
 640  * Allocate a wb slot for use by the driver (all asics).
 641  * Returns 0 on success or -EINVAL on failure.
 642  */
 643 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 644 {
 645         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 646
 647         if (offset < adev->wb.num_wb) {
 648                 __set_bit(offset, adev->wb.used);
 649                 *wb = offset << 3; /* convert to dw offset */
 650                 return 0;
 651         } else {
 652                 return -EINVAL;
 653         }
 654 }
 655
 656 /**
 657  * amdgpu_device_wb_free - Free a wb entry
 658  *
 659  * @adev: amdgpu_device pointer
 660  * @wb: wb index
 661  *
 662  * Free a wb slot allocated for use by the driver (all asics)
 663  */
 664 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 665 {
 666         wb >>= 3;
 667         if (wb < adev->wb.num_wb)
 668                 __clear_bit(wb, adev->wb.used);
 669 }
 670
 671 /**
 672  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 673  *
 674  * @adev: amdgpu_device pointer
 675  *
 676  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 677  * to fail, but if any of the BARs is not accessible after the size we abort
 678  * driver loading by returning -ENODEV.
 679  */
 680 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 681 {
 682         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 683         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 684         struct pci_bus *root;
 685         struct resource *res;
 686         unsigned i;
 687         u16 cmd;
 688         int r;
 689
 690         /* Bypass for VF */
 691         if (amdgpu_sriov_vf(adev))
 692                 return 0;
 693
 694         /* Check if the root BUS has 64bit memory resources */
 695         root = adev->pdev->bus;
 696         while (root->parent)
 697                 root = root->parent;
 698
 699         pci_bus_for_each_resource(root, res, i) {
 700                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 701                     res->start > 0x100000000ull)
 702                         break;
 703         }
 704
 705         /* Trying to resize is pointless without a root hub window above 4GB */
 706         if (!res)
 707                 return 0;
 708
 709         /* Disable memory decoding while we change the BAR addresses and size */
 710         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 711         pci_write_config_word(adev->pdev, PCI_COMMAND,
 712                               cmd & ~PCI_COMMAND_MEMORY);
 713
 714         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 715         amdgpu_device_doorbell_fini(adev);
 716         if (adev->asic_type >= CHIP_BONAIRE)
 717                 pci_release_resource(adev->pdev, 2);
 718
 719         pci_release_resource(adev->pdev, 0);
 720
 721         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 722         if (r == -ENOSPC)
 723                 DRM_INFO("Not enough PCI address space for a large BAR.");
 724         else if (r && r != -ENOTSUPP)
 725                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 726
 727         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 728
 729         /* When the doorbell or fb BAR isn't available we have no chance of
 730          * using the device.
 731          */
 732         r = amdgpu_device_doorbell_init(adev);
 733         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 734                 return -ENODEV;
 735
 736         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 737
 738         return 0;
 739 }
 740
 741 /*
 742  * GPU helpers function.
 743  */
 744 /**
 745  * amdgpu_device_need_post - check if the hw need post or not
 746  *
 747  * @adev: amdgpu_device pointer
 748  *
 749  * Check if the asic has been initialized (all asics) at driver startup
 750  * or post is needed if  hw reset is performed.
 751  * Returns true if need or false if not.
 752  */
 753 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 754 {
 755         uint32_t reg;
 756
 757         if (amdgpu_sriov_vf(adev))
 758                 return false;
 759
 760         if (amdgpu_passthrough(adev)) {
 761                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 762                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 763                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 764                  * vpost executed for smc version below 22.15
 765                  */
 766                 if (adev->asic_type == CHIP_FIJI) {
 767                         int err;
 768                         uint32_t fw_ver;
 769                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 770                         /* force vPost if error occured */
 771                         if (err)
 772                                 return true;
 773
 774                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 775                         if (fw_ver < 0x00160e00)
 776                                 return true;
 777                 }
 778         }
 779
 780         if (adev->has_hw_reset) {
 781                 adev->has_hw_reset = false;
 782                 return true;
 783         }
 784
 785         /* bios scratch used on CIK+ */
 786         if (adev->asic_type >= CHIP_BONAIRE)
 787                 return amdgpu_atombios_scratch_need_asic_init(adev);
 788
 789         /* check MEM_SIZE for older asics */
 790         reg = amdgpu_asic_get_config_memsize(adev);
 791
 792         if ((reg != 0) && (reg != 0xffffffff))
 793                 return false;
 794
 795         return true;
 796 }
 797
 798 /* if we get transitioned to only one device, take VGA back */
 799 /**
 800  * amdgpu_device_vga_set_decode - enable/disable vga decode
 801  *
 802  * @cookie: amdgpu_device pointer
 803  * @state: enable/disable vga decode
 804  *
 805  * Enable/disable vga decode (all asics).
 806  * Returns VGA resource flags.
 807  */
 808 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 809 {
 810         struct amdgpu_device *adev = cookie;
 811         amdgpu_asic_set_vga_state(adev, state);
 812         if (state)
 813                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 814                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 815         else
 816                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 817 }
 818
 819 /**
 820  * amdgpu_device_check_block_size - validate the vm block size
 821  *
 822  * @adev: amdgpu_device pointer
 823  *
 824  * Validates the vm block size specified via module parameter.
 825  * The vm block size defines number of bits in page table versus page directory,
 826  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 827  * page table and the remaining bits are in the page directory.
 828  */
 829 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 830 {
 831         /* defines number of bits in page table versus page directory,
 832          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 833          * page table and the remaining bits are in the page directory */
 834         if (amdgpu_vm_block_size == -1)
 835                 return;
 836
 837         if (amdgpu_vm_block_size < 9) {
 838                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 839                          amdgpu_vm_block_size);
 840                 amdgpu_vm_block_size = -1;
 841         }
 842 }
 843
 844 /**
 845  * amdgpu_device_check_vm_size - validate the vm size
 846  *
 847  * @adev: amdgpu_device pointer
 848  *
 849  * Validates the vm size in GB specified via module parameter.
 850  * The VM size is the size of the GPU virtual memory space in GB.
 851  */
 852 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 853 {
 854         /* no need to check the default value */
 855         if (amdgpu_vm_size == -1)
 856                 return;
 857
 858         if (amdgpu_vm_size < 1) {
 859                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 860                          amdgpu_vm_size);
 861                 amdgpu_vm_size = -1;
 862         }
 863 }
 864
 865 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 866 {
 867         struct sysinfo si;
 868         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 869         uint64_t total_memory;
 870         uint64_t dram_size_seven_GB = 0x1B8000000;
 871         uint64_t dram_size_three_GB = 0xB8000000;
 872
 873         if (amdgpu_smu_memory_pool_size == 0)
 874                 return;
 875
 876         if (!is_os_64) {
 877                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 878                 goto def_value;
 879         }
 880         si_meminfo(&si);
 881         total_memory = (uint64_t)si.totalram * si.mem_unit;
 882
 883         if ((amdgpu_smu_memory_pool_size == 1) ||
 884                 (amdgpu_smu_memory_pool_size == 2)) {
 885                 if (total_memory < dram_size_three_GB)
 886                         goto def_value1;
 887         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 888                 (amdgpu_smu_memory_pool_size == 8)) {
 889                 if (total_memory < dram_size_seven_GB)
 890                         goto def_value1;
 891         } else {
 892                 DRM_WARN("Smu memory pool size not supported\n");
 893                 goto def_value;
 894         }
 895         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 896
 897         return;
 898
 899 def_value1:
 900         DRM_WARN("No enough system memory\n");
 901 def_value:
 902         adev->pm.smu_prv_buffer_size = 0;
 903 }
 904
 905 /**
 906  * amdgpu_device_check_arguments - validate module params
 907  *
 908  * @adev: amdgpu_device pointer
 909  *
 910  * Validates certain module parameters and updates
 911  * the associated values used by the driver (all asics).
 912  */
 913 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
 914 {
 915         if (amdgpu_sched_jobs < 4) {
 916                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 917                          amdgpu_sched_jobs);
 918                 amdgpu_sched_jobs = 4;
 919         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 920                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 921                          amdgpu_sched_jobs);
 922                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 923         }
 924
 925         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 926                 /* gart size must be greater or equal to 32M */
 927                 dev_warn(adev->dev, "gart size (%d) too small\n",
 928                          amdgpu_gart_size);
 929                 amdgpu_gart_size = -1;
 930         }
 931
 932         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 933                 /* gtt size must be greater or equal to 32M */
 934                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 935                                  amdgpu_gtt_size);
 936                 amdgpu_gtt_size = -1;
 937         }
 938
 939         /* valid range is between 4 and 9 inclusive */
 940         if (amdgpu_vm_fragment_size != -1 &&
 941             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 942                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 943                 amdgpu_vm_fragment_size = -1;
 944         }
 945
 946         amdgpu_device_check_smu_prv_buffer_size(adev);
 947
 948         amdgpu_device_check_vm_size(adev);
 949
 950         amdgpu_device_check_block_size(adev);
 951
 952         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
 953             !is_power_of_2(amdgpu_vram_page_split))) {
 954                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
 955                          amdgpu_vram_page_split);
 956                 amdgpu_vram_page_split = 1024;
 957         }
 958
 959         if (amdgpu_lockup_timeout == 0) {
 960                 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
 961                 amdgpu_lockup_timeout = 10000;
 962         }
 963
 964         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 965 }
 966
 967 /**
 968  * amdgpu_switcheroo_set_state - set switcheroo state
 969  *
 970  * @pdev: pci dev pointer
 971  * @state: vga_switcheroo state
 972  *
 973  * Callback for the switcheroo driver.  Suspends or resumes the
 974  * the asics before or after it is powered up using ACPI methods.
 975  */
 976 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 977 {
 978         struct drm_device *dev = pci_get_drvdata(pdev);
 979
 980         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
 981                 return;
 982
 983         if (state == VGA_SWITCHEROO_ON) {
 984                 pr_info("amdgpu: switched on\n");
 985                 /* don't suspend or resume card normally */
 986                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 987
 988                 amdgpu_device_resume(dev, true, true);
 989
 990                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 991                 drm_kms_helper_poll_enable(dev);
 992         } else {
 993                 pr_info("amdgpu: switched off\n");
 994                 drm_kms_helper_poll_disable(dev);
 995                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 996                 amdgpu_device_suspend(dev, true, true);
 997                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 998         }
 999 }
1000
1001 /**
1002  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1003  *
1004  * @pdev: pci dev pointer
1005  *
1006  * Callback for the switcheroo driver.  Check of the switcheroo
1007  * state can be changed.
1008  * Returns true if the state can be changed, false if not.
1009  */
1010 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1011 {
1012         struct drm_device *dev = pci_get_drvdata(pdev);
1013
1014         /*
1015         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1016         * locking inversion with the driver load path. And the access here is
1017         * completely racy anyway. So don't bother with locking for now.
1018         */
1019         return dev->open_count == 0;
1020 }
1021
1022 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1023         .set_gpu_state = amdgpu_switcheroo_set_state,
1024         .reprobe = NULL,
1025         .can_switch = amdgpu_switcheroo_can_switch,
1026 };
1027
1028 /**
1029  * amdgpu_device_ip_set_clockgating_state - set the CG state
1030  *
1031  * @dev: amdgpu_device pointer
1032  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1033  * @state: clockgating state (gate or ungate)
1034  *
1035  * Sets the requested clockgating state for all instances of
1036  * the hardware IP specified.
1037  * Returns the error code from the last instance.
1038  */
1039 int amdgpu_device_ip_set_clockgating_state(void *dev,
1040                                            enum amd_ip_block_type block_type,
1041                                            enum amd_clockgating_state state)
1042 {
1043         struct amdgpu_device *adev = dev;
1044         int i, r = 0;
1045
1046         for (i = 0; i < adev->num_ip_blocks; i++) {
1047                 if (!adev->ip_blocks[i].status.valid)
1048                         continue;
1049                 if (adev->ip_blocks[i].version->type != block_type)
1050                         continue;
1051                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1052                         continue;
1053                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1054                         (void *)adev, state);
1055                 if (r)
1056                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1057                                   adev->ip_blocks[i].version->funcs->name, r);
1058         }
1059         return r;
1060 }
1061
1062 /**
1063  * amdgpu_device_ip_set_powergating_state - set the PG state
1064  *
1065  * @dev: amdgpu_device pointer
1066  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1067  * @state: powergating state (gate or ungate)
1068  *
1069  * Sets the requested powergating state for all instances of
1070  * the hardware IP specified.
1071  * Returns the error code from the last instance.
1072  */
1073 int amdgpu_device_ip_set_powergating_state(void *dev,
1074                                            enum amd_ip_block_type block_type,
1075                                            enum amd_powergating_state state)
1076 {
1077         struct amdgpu_device *adev = dev;
1078         int i, r = 0;
1079
1080         for (i = 0; i < adev->num_ip_blocks; i++) {
1081                 if (!adev->ip_blocks[i].status.valid)
1082                         continue;
1083                 if (adev->ip_blocks[i].version->type != block_type)
1084                         continue;
1085                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1086                         continue;
1087                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1088                         (void *)adev, state);
1089                 if (r)
1090                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1091                                   adev->ip_blocks[i].version->funcs->name, r);
1092         }
1093         return r;
1094 }
1095
1096 /**
1097  * amdgpu_device_ip_get_clockgating_state - get the CG state
1098  *
1099  * @adev: amdgpu_device pointer
1100  * @flags: clockgating feature flags
1101  *
1102  * Walks the list of IPs on the device and updates the clockgating
1103  * flags for each IP.
1104  * Updates @flags with the feature flags for each hardware IP where
1105  * clockgating is enabled.
1106  */
1107 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1108                                             u32 *flags)
1109 {
1110         int i;
1111
1112         for (i = 0; i < adev->num_ip_blocks; i++) {
1113                 if (!adev->ip_blocks[i].status.valid)
1114                         continue;
1115                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1116                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1117         }
1118 }
1119
1120 /**
1121  * amdgpu_device_ip_wait_for_idle - wait for idle
1122  *
1123  * @adev: amdgpu_device pointer
1124  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1125  *
1126  * Waits for the request hardware IP to be idle.
1127  * Returns 0 for success or a negative error code on failure.
1128  */
1129 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1130                                    enum amd_ip_block_type block_type)
1131 {
1132         int i, r;
1133
1134         for (i = 0; i < adev->num_ip_blocks; i++) {
1135                 if (!adev->ip_blocks[i].status.valid)
1136                         continue;
1137                 if (adev->ip_blocks[i].version->type == block_type) {
1138                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1139                         if (r)
1140                                 return r;
1141                         break;
1142                 }
1143         }
1144         return 0;
1145
1146 }
1147
1148 /**
1149  * amdgpu_device_ip_is_idle - is the hardware IP idle
1150  *
1151  * @adev: amdgpu_device pointer
1152  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1153  *
1154  * Check if the hardware IP is idle or not.
1155  * Returns true if it the IP is idle, false if not.
1156  */
1157 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1158                               enum amd_ip_block_type block_type)
1159 {
1160         int i;
1161
1162         for (i = 0; i < adev->num_ip_blocks; i++) {
1163                 if (!adev->ip_blocks[i].status.valid)
1164                         continue;
1165                 if (adev->ip_blocks[i].version->type == block_type)
1166                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1167         }
1168         return true;
1169
1170 }
1171
1172 /**
1173  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1174  *
1175  * @adev: amdgpu_device pointer
1176  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1177  *
1178  * Returns a pointer to the hardware IP block structure
1179  * if it exists for the asic, otherwise NULL.
1180  */
1181 struct amdgpu_ip_block *
1182 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1183                               enum amd_ip_block_type type)
1184 {
1185         int i;
1186
1187         for (i = 0; i < adev->num_ip_blocks; i++)
1188                 if (adev->ip_blocks[i].version->type == type)
1189                         return &adev->ip_blocks[i];
1190
1191         return NULL;
1192 }
1193
1194 /**
1195  * amdgpu_device_ip_block_version_cmp
1196  *
1197  * @adev: amdgpu_device pointer
1198  * @type: enum amd_ip_block_type
1199  * @major: major version
1200  * @minor: minor version
1201  *
1202  * return 0 if equal or greater
1203  * return 1 if smaller or the ip_block doesn't exist
1204  */
1205 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1206                                        enum amd_ip_block_type type,
1207                                        u32 major, u32 minor)
1208 {
1209         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1210
1211         if (ip_block && ((ip_block->version->major > major) ||
1212                         ((ip_block->version->major == major) &&
1213                         (ip_block->version->minor >= minor))))
1214                 return 0;
1215
1216         return 1;
1217 }
1218
1219 /**
1220  * amdgpu_device_ip_block_add
1221  *
1222  * @adev: amdgpu_device pointer
1223  * @ip_block_version: pointer to the IP to add
1224  *
1225  * Adds the IP block driver information to the collection of IPs
1226  * on the asic.
1227  */
1228 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1229                                const struct amdgpu_ip_block_version *ip_block_version)
1230 {
1231         if (!ip_block_version)
1232                 return -EINVAL;
1233
1234         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1235                   ip_block_version->funcs->name);
1236
1237         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1238
1239         return 0;
1240 }
1241
1242 /**
1243  * amdgpu_device_enable_virtual_display - enable virtual display feature
1244  *
1245  * @adev: amdgpu_device pointer
1246  *
1247  * Enabled the virtual display feature if the user has enabled it via
1248  * the module parameter virtual_display.  This feature provides a virtual
1249  * display hardware on headless boards or in virtualized environments.
1250  * This function parses and validates the configuration string specified by
1251  * the user and configues the virtual display configuration (number of
1252  * virtual connectors, crtcs, etc.) specified.
1253  */
1254 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1255 {
1256         adev->enable_virtual_display = false;
1257
1258         if (amdgpu_virtual_display) {
1259                 struct drm_device *ddev = adev->ddev;
1260                 const char *pci_address_name = pci_name(ddev->pdev);
1261                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1262
1263                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1264                 pciaddstr_tmp = pciaddstr;
1265                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1266                         pciaddname = strsep(&pciaddname_tmp, ",");
1267                         if (!strcmp("all", pciaddname)
1268                             || !strcmp(pci_address_name, pciaddname)) {
1269                                 long num_crtc;
1270                                 int res = -1;
1271
1272                                 adev->enable_virtual_display = true;
1273
1274                                 if (pciaddname_tmp)
1275                                         res = kstrtol(pciaddname_tmp, 10,
1276                                                       &num_crtc);
1277
1278                                 if (!res) {
1279                                         if (num_crtc < 1)
1280                                                 num_crtc = 1;
1281                                         if (num_crtc > 6)
1282                                                 num_crtc = 6;
1283                                         adev->mode_info.num_crtc = num_crtc;
1284                                 } else {
1285                                         adev->mode_info.num_crtc = 1;
1286                                 }
1287                                 break;
1288                         }
1289                 }
1290
1291                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1292                          amdgpu_virtual_display, pci_address_name,
1293                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1294
1295                 kfree(pciaddstr);
1296         }
1297 }
1298
1299 /**
1300  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1301  *
1302  * @adev: amdgpu_device pointer
1303  *
1304  * Parses the asic configuration parameters specified in the gpu info
1305  * firmware and makes them availale to the driver for use in configuring
1306  * the asic.
1307  * Returns 0 on success, -EINVAL on failure.
1308  */
1309 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1310 {
1311         const char *chip_name;
1312         char fw_name[30];
1313         int err;
1314         const struct gpu_info_firmware_header_v1_0 *hdr;
1315
1316         adev->firmware.gpu_info_fw = NULL;
1317
1318         switch (adev->asic_type) {
1319         case CHIP_TOPAZ:
1320         case CHIP_TONGA:
1321         case CHIP_FIJI:
1322         case CHIP_POLARIS10:
1323         case CHIP_POLARIS11:
1324         case CHIP_POLARIS12:
1325         case CHIP_VEGAM:
1326         case CHIP_CARRIZO:
1327         case CHIP_STONEY:
1328 #ifdef CONFIG_DRM_AMDGPU_SI
1329         case CHIP_VERDE:
1330         case CHIP_TAHITI:
1331         case CHIP_PITCAIRN:
1332         case CHIP_OLAND:
1333         case CHIP_HAINAN:
1334 #endif
1335 #ifdef CONFIG_DRM_AMDGPU_CIK
1336         case CHIP_BONAIRE:
1337         case CHIP_HAWAII:
1338         case CHIP_KAVERI:
1339         case CHIP_KABINI:
1340         case CHIP_MULLINS:
1341 #endif
1342         case CHIP_VEGA20:
1343         default:
1344                 return 0;
1345         case CHIP_VEGA10:
1346                 chip_name = "vega10";
1347                 break;
1348         case CHIP_VEGA12:
1349                 chip_name = "vega12";
1350                 break;
1351         case CHIP_RAVEN:
1352                 if (adev->rev_id >= 8)
1353                         chip_name = "raven2";
1354                 else if (adev->pdev->device == 0x15d8)
1355                         chip_name = "picasso";
1356                 else
1357                         chip_name = "raven";
1358                 break;
1359         }
1360
1361         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1362         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1363         if (err) {
1364                 dev_err(adev->dev,
1365                         "Failed to load gpu_info firmware \"%s\"\n",
1366                         fw_name);
1367                 goto out;
1368         }
1369         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1370         if (err) {
1371                 dev_err(adev->dev,
1372                         "Failed to validate gpu_info firmware \"%s\"\n",
1373                         fw_name);
1374                 goto out;
1375         }
1376
1377         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1378         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1379
1380         switch (hdr->version_major) {
1381         case 1:
1382         {
1383                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1384                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1385                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1386
1387                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1388                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1389                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1390                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1391                 adev->gfx.config.max_texture_channel_caches =
1392                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1393                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1394                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1395                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1396                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1397                 adev->gfx.config.double_offchip_lds_buf =
1398                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1399                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1400                 adev->gfx.cu_info.max_waves_per_simd =
1401                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1402                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1403                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1404                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1405                 break;
1406         }
1407         default:
1408                 dev_err(adev->dev,
1409                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1410                 err = -EINVAL;
1411                 goto out;
1412         }
1413 out:
1414         return err;
1415 }
1416
1417 /**
1418  * amdgpu_device_ip_early_init - run early init for hardware IPs
1419  *
1420  * @adev: amdgpu_device pointer
1421  *
1422  * Early initialization pass for hardware IPs.  The hardware IPs that make
1423  * up each asic are discovered each IP's early_init callback is run.  This
1424  * is the first stage in initializing the asic.
1425  * Returns 0 on success, negative error code on failure.
1426  */
1427 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1428 {
1429         int i, r;
1430
1431         amdgpu_device_enable_virtual_display(adev);
1432
1433         switch (adev->asic_type) {
1434         case CHIP_TOPAZ:
1435         case CHIP_TONGA:
1436         case CHIP_FIJI:
1437         case CHIP_POLARIS10:
1438         case CHIP_POLARIS11:
1439         case CHIP_POLARIS12:
1440         case CHIP_VEGAM:
1441         case CHIP_CARRIZO:
1442         case CHIP_STONEY:
1443                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1444                         adev->family = AMDGPU_FAMILY_CZ;
1445                 else
1446                         adev->family = AMDGPU_FAMILY_VI;
1447
1448                 r = vi_set_ip_blocks(adev);
1449                 if (r)
1450                         return r;
1451                 break;
1452 #ifdef CONFIG_DRM_AMDGPU_SI
1453         case CHIP_VERDE:
1454         case CHIP_TAHITI:
1455         case CHIP_PITCAIRN:
1456         case CHIP_OLAND:
1457         case CHIP_HAINAN:
1458                 adev->family = AMDGPU_FAMILY_SI;
1459                 r = si_set_ip_blocks(adev);
1460                 if (r)
1461                         return r;
1462                 break;
1463 #endif
1464 #ifdef CONFIG_DRM_AMDGPU_CIK
1465         case CHIP_BONAIRE:
1466         case CHIP_HAWAII:
1467         case CHIP_KAVERI:
1468         case CHIP_KABINI:
1469         case CHIP_MULLINS:
1470                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1471                         adev->family = AMDGPU_FAMILY_CI;
1472                 else
1473                         adev->family = AMDGPU_FAMILY_KV;
1474
1475                 r = cik_set_ip_blocks(adev);
1476                 if (r)
1477                         return r;
1478                 break;
1479 #endif
1480         case CHIP_VEGA10:
1481         case CHIP_VEGA12:
1482         case CHIP_VEGA20:
1483         case CHIP_RAVEN:
1484                 if (adev->asic_type == CHIP_RAVEN)
1485                         adev->family = AMDGPU_FAMILY_RV;
1486                 else
1487                         adev->family = AMDGPU_FAMILY_AI;
1488
1489                 r = soc15_set_ip_blocks(adev);
1490                 if (r)
1491                         return r;
1492                 break;
1493         default:
1494                 /* FIXME: not supported yet */
1495                 return -EINVAL;
1496         }
1497
1498         r = amdgpu_device_parse_gpu_info_fw(adev);
1499         if (r)
1500                 return r;
1501
1502         amdgpu_amdkfd_device_probe(adev);
1503
1504         if (amdgpu_sriov_vf(adev)) {
1505                 r = amdgpu_virt_request_full_gpu(adev, true);
1506                 if (r)
1507                         return -EAGAIN;
1508         }
1509
1510         adev->pm.pp_feature = amdgpu_pp_feature_mask;
1511
1512         for (i = 0; i < adev->num_ip_blocks; i++) {
1513                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1514                         DRM_ERROR("disabled ip block: %d <%s>\n",
1515                                   i, adev->ip_blocks[i].version->funcs->name);
1516                         adev->ip_blocks[i].status.valid = false;
1517                 } else {
1518                         if (adev->ip_blocks[i].version->funcs->early_init) {
1519                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1520                                 if (r == -ENOENT) {
1521                                         adev->ip_blocks[i].status.valid = false;
1522                                 } else if (r) {
1523                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1524                                                   adev->ip_blocks[i].version->funcs->name, r);
1525                                         return r;
1526                                 } else {
1527                                         adev->ip_blocks[i].status.valid = true;
1528                                 }
1529                         } else {
1530                                 adev->ip_blocks[i].status.valid = true;
1531                         }
1532                 }
1533         }
1534
1535         adev->cg_flags &= amdgpu_cg_mask;
1536         adev->pg_flags &= amdgpu_pg_mask;
1537
1538         return 0;
1539 }
1540
1541 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1542 {
1543         int i, r;
1544
1545         for (i = 0; i < adev->num_ip_blocks; i++) {
1546                 if (!adev->ip_blocks[i].status.sw)
1547                         continue;
1548                 if (adev->ip_blocks[i].status.hw)
1549                         continue;
1550                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1551                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1552                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1553                         if (r) {
1554                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1555                                           adev->ip_blocks[i].version->funcs->name, r);
1556                                 return r;
1557                         }
1558                         adev->ip_blocks[i].status.hw = true;
1559                 }
1560         }
1561
1562         return 0;
1563 }
1564
1565 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1566 {
1567         int i, r;
1568
1569         for (i = 0; i < adev->num_ip_blocks; i++) {
1570                 if (!adev->ip_blocks[i].status.sw)
1571                         continue;
1572                 if (adev->ip_blocks[i].status.hw)
1573                         continue;
1574                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1575                 if (r) {
1576                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1577                                   adev->ip_blocks[i].version->funcs->name, r);
1578                         return r;
1579                 }
1580                 adev->ip_blocks[i].status.hw = true;
1581         }
1582
1583         return 0;
1584 }
1585
1586 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1587 {
1588         int r = 0;
1589         int i;
1590
1591         if (adev->asic_type >= CHIP_VEGA10) {
1592                 for (i = 0; i < adev->num_ip_blocks; i++) {
1593                         if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
1594                                 if (adev->in_gpu_reset || adev->in_suspend) {
1595                                         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
1596                                                 break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
1597                                         r = adev->ip_blocks[i].version->funcs->resume(adev);
1598                                         if (r) {
1599                                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
1600                                                           adev->ip_blocks[i].version->funcs->name, r);
1601                                                 return r;
1602                                         }
1603                                 } else {
1604                                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1605                                         if (r) {
1606                                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1607                                                   adev->ip_blocks[i].version->funcs->name, r);
1608                                                 return r;
1609                                         }
1610                                 }
1611                                 adev->ip_blocks[i].status.hw = true;
1612                         }
1613                 }
1614         }
1615
1616         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
1617                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
1618                 if (r) {
1619                         pr_err("firmware loading failed\n");
1620                         return r;
1621                 }
1622         }
1623
1624         return 0;
1625 }
1626
1627 /**
1628  * amdgpu_device_ip_init - run init for hardware IPs
1629  *
1630  * @adev: amdgpu_device pointer
1631  *
1632  * Main initialization pass for hardware IPs.  The list of all the hardware
1633  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1634  * are run.  sw_init initializes the software state associated with each IP
1635  * and hw_init initializes the hardware associated with each IP.
1636  * Returns 0 on success, negative error code on failure.
1637  */
1638 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1639 {
1640         int i, r;
1641
1642         r = amdgpu_ras_init(adev);
1643         if (r)
1644                 return r;
1645
1646         for (i = 0; i < adev->num_ip_blocks; i++) {
1647                 if (!adev->ip_blocks[i].status.valid)
1648                         continue;
1649                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1650                 if (r) {
1651                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1652                                   adev->ip_blocks[i].version->funcs->name, r);
1653                         goto init_failed;
1654                 }
1655                 adev->ip_blocks[i].status.sw = true;
1656
1657                 /* need to do gmc hw init early so we can allocate gpu mem */
1658                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1659                         r = amdgpu_device_vram_scratch_init(adev);
1660                         if (r) {
1661                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1662                                 goto init_failed;
1663                         }
1664                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1665                         if (r) {
1666                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1667                                 goto init_failed;
1668                         }
1669                         r = amdgpu_device_wb_init(adev);
1670                         if (r) {
1671                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1672                                 goto init_failed;
1673                         }
1674                         adev->ip_blocks[i].status.hw = true;
1675
1676                         /* right after GMC hw init, we create CSA */
1677                         if (amdgpu_sriov_vf(adev)) {
1678                                 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1679                                                                 AMDGPU_GEM_DOMAIN_VRAM,
1680                                                                 AMDGPU_CSA_SIZE);
1681                                 if (r) {
1682                                         DRM_ERROR("allocate CSA failed %d\n", r);
1683                                         goto init_failed;
1684                                 }
1685                         }
1686                 }
1687         }
1688
1689         r = amdgpu_ib_pool_init(adev);
1690         if (r) {
1691                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1692                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1693                 goto init_failed;
1694         }
1695
1696         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1697         if (r)
1698                 goto init_failed;
1699
1700         r = amdgpu_device_ip_hw_init_phase1(adev);
1701         if (r)
1702                 goto init_failed;
1703
1704         r = amdgpu_device_fw_loading(adev);
1705         if (r)
1706                 goto init_failed;
1707
1708         r = amdgpu_device_ip_hw_init_phase2(adev);
1709         if (r)
1710                 goto init_failed;
1711
1712         if (adev->gmc.xgmi.num_physical_nodes > 1)
1713                 amdgpu_xgmi_add_device(adev);
1714         amdgpu_amdkfd_device_init(adev);
1715
1716 init_failed:
1717         if (amdgpu_sriov_vf(adev)) {
1718                 if (!r)
1719                         amdgpu_virt_init_data_exchange(adev);
1720                 amdgpu_virt_release_full_gpu(adev, true);
1721         }
1722
1723         return r;
1724 }
1725
1726 /**
1727  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1728  *
1729  * @adev: amdgpu_device pointer
1730  *
1731  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1732  * this function before a GPU reset.  If the value is retained after a
1733  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1734  */
1735 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1736 {
1737         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1738 }
1739
1740 /**
1741  * amdgpu_device_check_vram_lost - check if vram is valid
1742  *
1743  * @adev: amdgpu_device pointer
1744  *
1745  * Checks the reset magic value written to the gart pointer in VRAM.
1746  * The driver calls this after a GPU reset to see if the contents of
1747  * VRAM is lost or now.
1748  * returns true if vram is lost, false if not.
1749  */
1750 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1751 {
1752         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1753                         AMDGPU_RESET_MAGIC_NUM);
1754 }
1755
1756 /**
1757  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1758  *
1759  * @adev: amdgpu_device pointer
1760  *
1761  * The list of all the hardware IPs that make up the asic is walked and the
1762  * set_clockgating_state callbacks are run.
1763  * Late initialization pass enabling clockgating for hardware IPs.
1764  * Fini or suspend, pass disabling clockgating for hardware IPs.
1765  * Returns 0 on success, negative error code on failure.
1766  */
1767
1768 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1769                                                 enum amd_clockgating_state state)
1770 {
1771         int i, j, r;
1772
1773         if (amdgpu_emu_mode == 1)
1774                 return 0;
1775
1776         for (j = 0; j < adev->num_ip_blocks; j++) {
1777                 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1778                 if (!adev->ip_blocks[i].status.late_initialized)
1779                         continue;
1780                 /* skip CG for VCE/UVD, it's handled specially */
1781                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1782                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1783                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1784                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1785                         /* enable clockgating to save power */
1786                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1787                                                                                      state);
1788                         if (r) {
1789                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1790                                           adev->ip_blocks[i].version->funcs->name, r);
1791                                 return r;
1792                         }
1793                 }
1794         }
1795
1796         return 0;
1797 }
1798
1799 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1800 {
1801         int i, j, r;
1802
1803         if (amdgpu_emu_mode == 1)
1804                 return 0;
1805
1806         for (j = 0; j < adev->num_ip_blocks; j++) {
1807                 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1808                 if (!adev->ip_blocks[i].status.late_initialized)
1809                         continue;
1810                 /* skip CG for VCE/UVD, it's handled specially */
1811                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1812                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1813                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1814                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1815                         /* enable powergating to save power */
1816                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1817                                                                                         state);
1818                         if (r) {
1819                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1820                                           adev->ip_blocks[i].version->funcs->name, r);
1821                                 return r;
1822                         }
1823                 }
1824         }
1825         return 0;
1826 }
1827
1828 /**
1829  * amdgpu_device_ip_late_init - run late init for hardware IPs
1830  *
1831  * @adev: amdgpu_device pointer
1832  *
1833  * Late initialization pass for hardware IPs.  The list of all the hardware
1834  * IPs that make up the asic is walked and the late_init callbacks are run.
1835  * late_init covers any special initialization that an IP requires
1836  * after all of the have been initialized or something that needs to happen
1837  * late in the init process.
1838  * Returns 0 on success, negative error code on failure.
1839  */
1840 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1841 {
1842         int i = 0, r;
1843
1844         for (i = 0; i < adev->num_ip_blocks; i++) {
1845                 if (!adev->ip_blocks[i].status.hw)
1846                         continue;
1847                 if (adev->ip_blocks[i].version->funcs->late_init) {
1848                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1849                         if (r) {
1850                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1851                                           adev->ip_blocks[i].version->funcs->name, r);
1852                                 return r;
1853                         }
1854                 }
1855                 adev->ip_blocks[i].status.late_initialized = true;
1856         }
1857
1858         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
1859         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1860
1861         queue_delayed_work(system_wq, &adev->late_init_work,
1862                            msecs_to_jiffies(AMDGPU_RESUME_MS));
1863
1864         amdgpu_device_fill_reset_magic(adev);
1865
1866         return 0;
1867 }
1868
1869 /**
1870  * amdgpu_device_ip_fini - run fini for hardware IPs
1871  *
1872  * @adev: amdgpu_device pointer
1873  *
1874  * Main teardown pass for hardware IPs.  The list of all the hardware
1875  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1876  * are run.  hw_fini tears down the hardware associated with each IP
1877  * and sw_fini tears down any software state associated with each IP.
1878  * Returns 0 on success, negative error code on failure.
1879  */
1880 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1881 {
1882         int i, r;
1883
1884         amdgpu_ras_pre_fini(adev);
1885
1886         if (adev->gmc.xgmi.num_physical_nodes > 1)
1887                 amdgpu_xgmi_remove_device(adev);
1888
1889         amdgpu_amdkfd_device_fini(adev);
1890
1891         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1892         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1893
1894         /* need to disable SMC first */
1895         for (i = 0; i < adev->num_ip_blocks; i++) {
1896                 if (!adev->ip_blocks[i].status.hw)
1897                         continue;
1898                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1899                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1900                         /* XXX handle errors */
1901                         if (r) {
1902                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1903                                           adev->ip_blocks[i].version->funcs->name, r);
1904                         }
1905                         adev->ip_blocks[i].status.hw = false;
1906                         break;
1907                 }
1908         }
1909
1910         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1911                 if (!adev->ip_blocks[i].status.hw)
1912                         continue;
1913
1914                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1915                 /* XXX handle errors */
1916                 if (r) {
1917                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1918                                   adev->ip_blocks[i].version->funcs->name, r);
1919                 }
1920
1921                 adev->ip_blocks[i].status.hw = false;
1922         }
1923
1924
1925         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1926                 if (!adev->ip_blocks[i].status.sw)
1927                         continue;
1928
1929                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1930                         amdgpu_ucode_free_bo(adev);
1931                         amdgpu_free_static_csa(&adev->virt.csa_obj);
1932                         amdgpu_device_wb_fini(adev);
1933                         amdgpu_device_vram_scratch_fini(adev);
1934                         amdgpu_ib_pool_fini(adev);
1935                 }
1936
1937                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1938                 /* XXX handle errors */
1939                 if (r) {
1940                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1941                                   adev->ip_blocks[i].version->funcs->name, r);
1942                 }
1943                 adev->ip_blocks[i].status.sw = false;
1944                 adev->ip_blocks[i].status.valid = false;
1945         }
1946
1947         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1948                 if (!adev->ip_blocks[i].status.late_initialized)
1949                         continue;
1950                 if (adev->ip_blocks[i].version->funcs->late_fini)
1951                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1952                 adev->ip_blocks[i].status.late_initialized = false;
1953         }
1954
1955         amdgpu_ras_fini(adev);
1956
1957         if (amdgpu_sriov_vf(adev))
1958                 if (amdgpu_virt_release_full_gpu(adev, false))
1959                         DRM_ERROR("failed to release exclusive mode on fini\n");
1960
1961         return 0;
1962 }
1963
1964 static int amdgpu_device_enable_mgpu_fan_boost(void)
1965 {
1966         struct amdgpu_gpu_instance *gpu_ins;
1967         struct amdgpu_device *adev;
1968         int i, ret = 0;
1969
1970         mutex_lock(&mgpu_info.mutex);
1971
1972         /*
1973          * MGPU fan boost feature should be enabled
1974          * only when there are two or more dGPUs in
1975          * the system
1976          */
1977         if (mgpu_info.num_dgpu < 2)
1978                 goto out;
1979
1980         for (i = 0; i < mgpu_info.num_dgpu; i++) {
1981                 gpu_ins = &(mgpu_info.gpu_ins[i]);
1982                 adev = gpu_ins->adev;
1983                 if (!(adev->flags & AMD_IS_APU) &&
1984                     !gpu_ins->mgpu_fan_enabled &&
1985                     adev->powerplay.pp_funcs &&
1986                     adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1987                         ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1988                         if (ret)
1989                                 break;
1990
1991                         gpu_ins->mgpu_fan_enabled = 1;
1992                 }
1993         }
1994
1995 out:
1996         mutex_unlock(&mgpu_info.mutex);
1997
1998         return ret;
1999 }
2000
2001 /**
2002  * amdgpu_device_ip_late_init_func_handler - work handler for ib test
2003  *
2004  * @work: work_struct.
2005  */
2006 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
2007 {
2008         struct amdgpu_device *adev =
2009                 container_of(work, struct amdgpu_device, late_init_work.work);
2010         int r;
2011
2012         r = amdgpu_ib_ring_tests(adev);
2013         if (r)
2014                 DRM_ERROR("ib ring test failed (%d).\n", r);
2015
2016         r = amdgpu_device_enable_mgpu_fan_boost();
2017         if (r)
2018                 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2019
2020         /*set to low pstate by default */
2021         amdgpu_xgmi_set_pstate(adev, 0);
2022 }
2023
2024 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2025 {
2026         struct amdgpu_device *adev =
2027                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2028
2029         mutex_lock(&adev->gfx.gfx_off_mutex);
2030         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2031                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2032                         adev->gfx.gfx_off_state = true;
2033         }
2034         mutex_unlock(&adev->gfx.gfx_off_mutex);
2035 }
2036
2037 /**
2038  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2039  *
2040  * @adev: amdgpu_device pointer
2041  *
2042  * Main suspend function for hardware IPs.  The list of all the hardware
2043  * IPs that make up the asic is walked, clockgating is disabled and the
2044  * suspend callbacks are run.  suspend puts the hardware and software state
2045  * in each IP into a state suitable for suspend.
2046  * Returns 0 on success, negative error code on failure.
2047  */
2048 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2049 {
2050         int i, r;
2051
2052         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2053         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2054
2055         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2056                 if (!adev->ip_blocks[i].status.valid)
2057                         continue;
2058                 /* displays are handled separately */
2059                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2060                         /* XXX handle errors */
2061                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
2062                         /* XXX handle errors */
2063                         if (r) {
2064                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2065                                           adev->ip_blocks[i].version->funcs->name, r);
2066                         }
2067                 }
2068         }
2069
2070         return 0;
2071 }
2072
2073 /**
2074  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2075  *
2076  * @adev: amdgpu_device pointer
2077  *
2078  * Main suspend function for hardware IPs.  The list of all the hardware
2079  * IPs that make up the asic is walked, clockgating is disabled and the
2080  * suspend callbacks are run.  suspend puts the hardware and software state
2081  * in each IP into a state suitable for suspend.
2082  * Returns 0 on success, negative error code on failure.
2083  */
2084 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2085 {
2086         int i, r;
2087
2088         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2089                 if (!adev->ip_blocks[i].status.valid)
2090                         continue;
2091                 /* displays are handled in phase1 */
2092                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2093                         continue;
2094                 /* XXX handle errors */
2095                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2096                 /* XXX handle errors */
2097                 if (r) {
2098                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2099                                   adev->ip_blocks[i].version->funcs->name, r);
2100                 }
2101         }
2102
2103         return 0;
2104 }
2105
2106 /**
2107  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2108  *
2109  * @adev: amdgpu_device pointer
2110  *
2111  * Main suspend function for hardware IPs.  The list of all the hardware
2112  * IPs that make up the asic is walked, clockgating is disabled and the
2113  * suspend callbacks are run.  suspend puts the hardware and software state
2114  * in each IP into a state suitable for suspend.
2115  * Returns 0 on success, negative error code on failure.
2116  */
2117 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2118 {
2119         int r;
2120
2121         if (amdgpu_sriov_vf(adev))
2122                 amdgpu_virt_request_full_gpu(adev, false);
2123
2124         r = amdgpu_device_ip_suspend_phase1(adev);
2125         if (r)
2126                 return r;
2127         r = amdgpu_device_ip_suspend_phase2(adev);
2128
2129         if (amdgpu_sriov_vf(adev))
2130                 amdgpu_virt_release_full_gpu(adev, false);
2131
2132         return r;
2133 }
2134
2135 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2136 {
2137         int i, r;
2138
2139         static enum amd_ip_block_type ip_order[] = {
2140                 AMD_IP_BLOCK_TYPE_GMC,
2141                 AMD_IP_BLOCK_TYPE_COMMON,
2142                 AMD_IP_BLOCK_TYPE_PSP,
2143                 AMD_IP_BLOCK_TYPE_IH,
2144         };
2145
2146         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2147                 int j;
2148                 struct amdgpu_ip_block *block;
2149
2150                 for (j = 0; j < adev->num_ip_blocks; j++) {
2151                         block = &adev->ip_blocks[j];
2152
2153                         if (block->version->type != ip_order[i] ||
2154                                 !block->status.valid)
2155                                 continue;
2156
2157                         r = block->version->funcs->hw_init(adev);
2158                         DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2159                         if (r)
2160                                 return r;
2161                 }
2162         }
2163
2164         return 0;
2165 }
2166
2167 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2168 {
2169         int i, r;
2170
2171         static enum amd_ip_block_type ip_order[] = {
2172                 AMD_IP_BLOCK_TYPE_SMC,
2173                 AMD_IP_BLOCK_TYPE_DCE,
2174                 AMD_IP_BLOCK_TYPE_GFX,
2175                 AMD_IP_BLOCK_TYPE_SDMA,
2176                 AMD_IP_BLOCK_TYPE_UVD,
2177                 AMD_IP_BLOCK_TYPE_VCE
2178         };
2179
2180         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2181                 int j;
2182                 struct amdgpu_ip_block *block;
2183
2184                 for (j = 0; j < adev->num_ip_blocks; j++) {
2185                         block = &adev->ip_blocks[j];
2186
2187                         if (block->version->type != ip_order[i] ||
2188                                 !block->status.valid)
2189                                 continue;
2190
2191                         r = block->version->funcs->hw_init(adev);
2192                         DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2193                         if (r)
2194                                 return r;
2195                 }
2196         }
2197
2198         return 0;
2199 }
2200
2201 /**
2202  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2203  *
2204  * @adev: amdgpu_device pointer
2205  *
2206  * First resume function for hardware IPs.  The list of all the hardware
2207  * IPs that make up the asic is walked and the resume callbacks are run for
2208  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2209  * after a suspend and updates the software state as necessary.  This
2210  * function is also used for restoring the GPU after a GPU reset.
2211  * Returns 0 on success, negative error code on failure.
2212  */
2213 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2214 {
2215         int i, r;
2216
2217         for (i = 0; i < adev->num_ip_blocks; i++) {
2218                 if (!adev->ip_blocks[i].status.valid)
2219                         continue;
2220                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2221                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2222                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2223                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2224                         if (r) {
2225                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2226                                           adev->ip_blocks[i].version->funcs->name, r);
2227                                 return r;
2228                         }
2229                 }
2230         }
2231
2232         return 0;
2233 }
2234
2235 /**
2236  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2237  *
2238  * @adev: amdgpu_device pointer
2239  *
2240  * First resume function for hardware IPs.  The list of all the hardware
2241  * IPs that make up the asic is walked and the resume callbacks are run for
2242  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2243  * functional state after a suspend and updates the software state as
2244  * necessary.  This function is also used for restoring the GPU after a GPU
2245  * reset.
2246  * Returns 0 on success, negative error code on failure.
2247  */
2248 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2249 {
2250         int i, r;
2251
2252         for (i = 0; i < adev->num_ip_blocks; i++) {
2253                 if (!adev->ip_blocks[i].status.valid)
2254                         continue;
2255                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2256                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2257                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2258                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2259                         continue;
2260                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2261                 if (r) {
2262                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2263                                   adev->ip_blocks[i].version->funcs->name, r);
2264                         return r;
2265                 }
2266         }
2267
2268         return 0;
2269 }
2270
2271 /**
2272  * amdgpu_device_ip_resume - run resume for hardware IPs
2273  *
2274  * @adev: amdgpu_device pointer
2275  *
2276  * Main resume function for hardware IPs.  The hardware IPs
2277  * are split into two resume functions because they are
2278  * are also used in in recovering from a GPU reset and some additional
2279  * steps need to be take between them.  In this case (S3/S4) they are
2280  * run sequentially.
2281  * Returns 0 on success, negative error code on failure.
2282  */
2283 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2284 {
2285         int r;
2286
2287         r = amdgpu_device_ip_resume_phase1(adev);
2288         if (r)
2289                 return r;
2290
2291         r = amdgpu_device_fw_loading(adev);
2292         if (r)
2293                 return r;
2294
2295         r = amdgpu_device_ip_resume_phase2(adev);
2296
2297         return r;
2298 }
2299
2300 /**
2301  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2302  *
2303  * @adev: amdgpu_device pointer
2304  *
2305  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2306  */
2307 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2308 {
2309         if (amdgpu_sriov_vf(adev)) {
2310                 if (adev->is_atom_fw) {
2311                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2312                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2313                 } else {
2314                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2315                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2316                 }
2317
2318                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2319                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2320         }
2321 }
2322
2323 /**
2324  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2325  *
2326  * @asic_type: AMD asic type
2327  *
2328  * Check if there is DC (new modesetting infrastructre) support for an asic.
2329  * returns true if DC has support, false if not.
2330  */
2331 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2332 {
2333         switch (asic_type) {
2334 #if defined(CONFIG_DRM_AMD_DC)
2335         case CHIP_BONAIRE:
2336         case CHIP_KAVERI:
2337         case CHIP_KABINI:
2338         case CHIP_MULLINS:
2339                 /*
2340                  * We have systems in the wild with these ASICs that require
2341                  * LVDS and VGA support which is not supported with DC.
2342                  *
2343                  * Fallback to the non-DC driver here by default so as not to
2344                  * cause regressions.
2345                  */
2346                 return amdgpu_dc > 0;
2347         case CHIP_HAWAII:
2348         case CHIP_CARRIZO:
2349         case CHIP_STONEY:
2350         case CHIP_POLARIS10:
2351         case CHIP_POLARIS11:
2352         case CHIP_POLARIS12:
2353         case CHIP_VEGAM:
2354         case CHIP_TONGA:
2355         case CHIP_FIJI:
2356         case CHIP_VEGA10:
2357         case CHIP_VEGA12:
2358         case CHIP_VEGA20:
2359 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2360         case CHIP_RAVEN:
2361 #endif
2362                 return amdgpu_dc != 0;
2363 #endif
2364         default:
2365                 return false;
2366         }
2367 }
2368
2369 /**
2370  * amdgpu_device_has_dc_support - check if dc is supported
2371  *
2372  * @adev: amdgpu_device_pointer
2373  *
2374  * Returns true for supported, false for not supported
2375  */
2376 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2377 {
2378         if (amdgpu_sriov_vf(adev))
2379                 return false;
2380
2381         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2382 }
2383
2384
2385 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2386 {
2387         struct amdgpu_device *adev =
2388                 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2389
2390         adev->asic_reset_res =  amdgpu_asic_reset(adev);
2391         if (adev->asic_reset_res)
2392                 DRM_WARN("ASIC reset failed with err r, %d for drm dev, %s",
2393                          adev->asic_reset_res, adev->ddev->unique);
2394 }
2395
2396
2397 /**
2398  * amdgpu_device_init - initialize the driver
2399  *
2400  * @adev: amdgpu_device pointer
2401  * @ddev: drm dev pointer
2402  * @pdev: pci dev pointer
2403  * @flags: driver flags
2404  *
2405  * Initializes the driver info and hw (all asics).
2406  * Returns 0 for success or an error on failure.
2407  * Called at driver startup.
2408  */
2409 int amdgpu_device_init(struct amdgpu_device *adev,
2410                        struct drm_device *ddev,
2411                        struct pci_dev *pdev,
2412                        uint32_t flags)
2413 {
2414         int r, i;
2415         bool runtime = false;
2416         u32 max_MBps;
2417
2418         adev->shutdown = false;
2419         adev->dev = &pdev->dev;
2420         adev->ddev = ddev;
2421         adev->pdev = pdev;
2422         adev->flags = flags;
2423         adev->asic_type = flags & AMD_ASIC_MASK;
2424         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2425         if (amdgpu_emu_mode == 1)
2426                 adev->usec_timeout *= 2;
2427         adev->gmc.gart_size = 512 * 1024 * 1024;
2428         adev->accel_working = false;
2429         adev->num_rings = 0;
2430         adev->mman.buffer_funcs = NULL;
2431         adev->mman.buffer_funcs_ring = NULL;
2432         adev->vm_manager.vm_pte_funcs = NULL;
2433         adev->vm_manager.vm_pte_num_rqs = 0;
2434         adev->gmc.gmc_funcs = NULL;
2435         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2436         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2437
2438         adev->smc_rreg = &amdgpu_invalid_rreg;
2439         adev->smc_wreg = &amdgpu_invalid_wreg;
2440         adev->pcie_rreg = &amdgpu_invalid_rreg;
2441         adev->pcie_wreg = &amdgpu_invalid_wreg;
2442         adev->pciep_rreg = &amdgpu_invalid_rreg;
2443         adev->pciep_wreg = &amdgpu_invalid_wreg;
2444         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2445         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2446         adev->didt_rreg = &amdgpu_invalid_rreg;
2447         adev->didt_wreg = &amdgpu_invalid_wreg;
2448         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2449         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2450         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2451         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2452
2453         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2454                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2455                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2456
2457         /* mutex initialization are all done here so we
2458          * can recall function without having locking issues */
2459         atomic_set(&adev->irq.ih.lock, 0);
2460         mutex_init(&adev->firmware.mutex);
2461         mutex_init(&adev->pm.mutex);
2462         mutex_init(&adev->gfx.gpu_clock_mutex);
2463         mutex_init(&adev->srbm_mutex);
2464         mutex_init(&adev->gfx.pipe_reserve_mutex);
2465         mutex_init(&adev->gfx.gfx_off_mutex);
2466         mutex_init(&adev->grbm_idx_mutex);
2467         mutex_init(&adev->mn_lock);
2468         mutex_init(&adev->virt.vf_errors.lock);
2469         hash_init(adev->mn_hash);
2470         mutex_init(&adev->lock_reset);
2471
2472         amdgpu_device_check_arguments(adev);
2473
2474         spin_lock_init(&adev->mmio_idx_lock);
2475         spin_lock_init(&adev->smc_idx_lock);
2476         spin_lock_init(&adev->pcie_idx_lock);
2477         spin_lock_init(&adev->uvd_ctx_idx_lock);
2478         spin_lock_init(&adev->didt_idx_lock);
2479         spin_lock_init(&adev->gc_cac_idx_lock);
2480         spin_lock_init(&adev->se_cac_idx_lock);
2481         spin_lock_init(&adev->audio_endpt_idx_lock);
2482         spin_lock_init(&adev->mm_stats.lock);
2483
2484         INIT_LIST_HEAD(&adev->shadow_list);
2485         mutex_init(&adev->shadow_list_lock);
2486
2487         INIT_LIST_HEAD(&adev->ring_lru_list);
2488         spin_lock_init(&adev->ring_lru_list_lock);
2489
2490         INIT_DELAYED_WORK(&adev->late_init_work,
2491                           amdgpu_device_ip_late_init_func_handler);
2492         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2493                           amdgpu_device_delay_enable_gfx_off);
2494
2495         INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2496
2497         adev->gfx.gfx_off_req_count = 1;
2498         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2499
2500         /* Registers mapping */
2501         /* TODO: block userspace mapping of io register */
2502         if (adev->asic_type >= CHIP_BONAIRE) {
2503                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2504                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2505         } else {
2506                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2507                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2508         }
2509
2510         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2511         if (adev->rmmio == NULL) {
2512                 return -ENOMEM;
2513         }
2514         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2515         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2516
2517         /* io port mapping */
2518         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2519                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2520                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2521                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2522                         break;
2523                 }
2524         }
2525         if (adev->rio_mem == NULL)
2526                 DRM_INFO("PCI I/O BAR is not found.\n");
2527
2528         amdgpu_device_get_pcie_info(adev);
2529
2530         /* early init functions */
2531         r = amdgpu_device_ip_early_init(adev);
2532         if (r)
2533                 return r;
2534
2535         /* doorbell bar mapping and doorbell index init*/
2536         amdgpu_device_doorbell_init(adev);
2537
2538         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2539         /* this will fail for cards that aren't VGA class devices, just
2540          * ignore it */
2541         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2542
2543         if (amdgpu_device_is_px(ddev))
2544                 runtime = true;
2545         if (!pci_is_thunderbolt_attached(adev->pdev))
2546                 vga_switcheroo_register_client(adev->pdev,
2547                                                &amdgpu_switcheroo_ops, runtime);
2548         if (runtime)
2549                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2550
2551         if (amdgpu_emu_mode == 1) {
2552                 /* post the asic on emulation mode */
2553                 emu_soc_asic_init(adev);
2554                 goto fence_driver_init;
2555         }
2556
2557         /* Read BIOS */
2558         if (!amdgpu_get_bios(adev)) {
2559                 r = -EINVAL;
2560                 goto failed;
2561         }
2562
2563         r = amdgpu_atombios_init(adev);
2564         if (r) {
2565                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2566                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2567                 goto failed;
2568         }
2569
2570         /* detect if we are with an SRIOV vbios */
2571         amdgpu_device_detect_sriov_bios(adev);
2572
2573         /* check if we need to reset the asic
2574          *  E.g., driver was not cleanly unloaded previously, etc.
2575          */
2576         if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2577                 r = amdgpu_asic_reset(adev);
2578                 if (r) {
2579                         dev_err(adev->dev, "asic reset on init failed\n");
2580                         goto failed;
2581                 }
2582         }
2583
2584         /* Post card if necessary */
2585         if (amdgpu_device_need_post(adev)) {
2586                 if (!adev->bios) {
2587                         dev_err(adev->dev, "no vBIOS found\n");
2588                         r = -EINVAL;
2589                         goto failed;
2590                 }
2591                 DRM_INFO("GPU posting now...\n");
2592                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2593                 if (r) {
2594                         dev_err(adev->dev, "gpu post error!\n");
2595                         goto failed;
2596                 }
2597         }
2598
2599         if (adev->is_atom_fw) {
2600                 /* Initialize clocks */
2601                 r = amdgpu_atomfirmware_get_clock_info(adev);
2602                 if (r) {
2603                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2604                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2605                         goto failed;
2606                 }
2607         } else {
2608                 /* Initialize clocks */
2609                 r = amdgpu_atombios_get_clock_info(adev);
2610                 if (r) {
2611                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2612                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2613                         goto failed;
2614                 }
2615                 /* init i2c buses */
2616                 if (!amdgpu_device_has_dc_support(adev))
2617                         amdgpu_atombios_i2c_init(adev);
2618         }
2619
2620 fence_driver_init:
2621         /* Fence driver */
2622         r = amdgpu_fence_driver_init(adev);
2623         if (r) {
2624                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2625                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2626                 goto failed;
2627         }
2628
2629         /* init the mode config */
2630         drm_mode_config_init(adev->ddev);
2631
2632         r = amdgpu_device_ip_init(adev);
2633         if (r) {
2634                 /* failed in exclusive mode due to timeout */
2635                 if (amdgpu_sriov_vf(adev) &&
2636                     !amdgpu_sriov_runtime(adev) &&
2637                     amdgpu_virt_mmio_blocked(adev) &&
2638                     !amdgpu_virt_wait_reset(adev)) {
2639                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2640                         /* Don't send request since VF is inactive. */
2641                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2642                         adev->virt.ops = NULL;
2643                         r = -EAGAIN;
2644                         goto failed;
2645                 }
2646                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2647                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2648                 if (amdgpu_virt_request_full_gpu(adev, false))
2649                         amdgpu_virt_release_full_gpu(adev, false);
2650                 goto failed;
2651         }
2652
2653         adev->accel_working = true;
2654
2655         amdgpu_vm_check_compute_bug(adev);
2656
2657         /* Initialize the buffer migration limit. */
2658         if (amdgpu_moverate >= 0)
2659                 max_MBps = amdgpu_moverate;
2660         else
2661                 max_MBps = 8; /* Allow 8 MB/s. */
2662         /* Get a log2 for easy divisions. */
2663         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2664
2665         amdgpu_fbdev_init(adev);
2666
2667         r = amdgpu_pm_sysfs_init(adev);
2668         if (r)
2669                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2670
2671         r = amdgpu_debugfs_gem_init(adev);
2672         if (r)
2673                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2674
2675         r = amdgpu_debugfs_regs_init(adev);
2676         if (r)
2677                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2678
2679         r = amdgpu_debugfs_firmware_init(adev);
2680         if (r)
2681                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2682
2683         r = amdgpu_debugfs_init(adev);
2684         if (r)
2685                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2686
2687         if ((amdgpu_testing & 1)) {
2688                 if (adev->accel_working)
2689                         amdgpu_test_moves(adev);
2690                 else
2691                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2692         }
2693         if (amdgpu_benchmarking) {
2694                 if (adev->accel_working)
2695                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2696                 else
2697                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2698         }
2699
2700         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2701          * explicit gating rather than handling it automatically.
2702          */
2703         r = amdgpu_device_ip_late_init(adev);
2704         if (r) {
2705                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2706                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2707                 goto failed;
2708         }
2709
2710         return 0;
2711
2712 failed:
2713         amdgpu_vf_error_trans_all(adev);
2714         if (runtime)
2715                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2716
2717         return r;
2718 }
2719
2720 /**
2721  * amdgpu_device_fini - tear down the driver
2722  *
2723  * @adev: amdgpu_device pointer
2724  *
2725  * Tear down the driver info (all asics).
2726  * Called at driver shutdown.
2727  */
2728 void amdgpu_device_fini(struct amdgpu_device *adev)
2729 {
2730         int r;
2731
2732         DRM_INFO("amdgpu: finishing device.\n");
2733         adev->shutdown = true;
2734         /* disable all interrupts */
2735         amdgpu_irq_disable_all(adev);
2736         if (adev->mode_info.mode_config_initialized){
2737                 if (!amdgpu_device_has_dc_support(adev))
2738                         drm_helper_force_disable_all(adev->ddev);
2739                 else
2740                         drm_atomic_helper_shutdown(adev->ddev);
2741         }
2742         amdgpu_fence_driver_fini(adev);
2743         amdgpu_pm_sysfs_fini(adev);
2744         amdgpu_fbdev_fini(adev);
2745         r = amdgpu_device_ip_fini(adev);
2746         if (adev->firmware.gpu_info_fw) {
2747                 release_firmware(adev->firmware.gpu_info_fw);
2748                 adev->firmware.gpu_info_fw = NULL;
2749         }
2750         adev->accel_working = false;
2751         cancel_delayed_work_sync(&adev->late_init_work);
2752         /* free i2c buses */
2753         if (!amdgpu_device_has_dc_support(adev))
2754                 amdgpu_i2c_fini(adev);
2755
2756         if (amdgpu_emu_mode != 1)
2757                 amdgpu_atombios_fini(adev);
2758
2759         kfree(adev->bios);
2760         adev->bios = NULL;
2761         if (!pci_is_thunderbolt_attached(adev->pdev))
2762                 vga_switcheroo_unregister_client(adev->pdev);
2763         if (adev->flags & AMD_IS_PX)
2764                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2765         vga_client_register(adev->pdev, NULL, NULL, NULL);
2766         if (adev->rio_mem)
2767                 pci_iounmap(adev->pdev, adev->rio_mem);
2768         adev->rio_mem = NULL;
2769         iounmap(adev->rmmio);
2770         adev->rmmio = NULL;
2771         amdgpu_device_doorbell_fini(adev);
2772         amdgpu_debugfs_regs_cleanup(adev);
2773 }
2774
2775
2776 /*
2777  * Suspend & resume.
2778  */
2779 /**
2780  * amdgpu_device_suspend - initiate device suspend
2781  *
2782  * @dev: drm dev pointer
2783  * @suspend: suspend state
2784  * @fbcon : notify the fbdev of suspend
2785  *
2786  * Puts the hw in the suspend state (all asics).
2787  * Returns 0 for success or an error on failure.
2788  * Called at driver suspend.
2789  */
2790 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2791 {
2792         struct amdgpu_device *adev;
2793         struct drm_crtc *crtc;
2794         struct drm_connector *connector;
2795         int r;
2796
2797         if (dev == NULL || dev->dev_private == NULL) {
2798                 return -ENODEV;
2799         }
2800
2801         adev = dev->dev_private;
2802
2803         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2804                 return 0;
2805
2806         adev->in_suspend = true;
2807         drm_kms_helper_poll_disable(dev);
2808
2809         if (fbcon)
2810                 amdgpu_fbdev_set_suspend(adev, 1);
2811
2812         cancel_delayed_work_sync(&adev->late_init_work);
2813
2814         if (!amdgpu_device_has_dc_support(adev)) {
2815                 /* turn off display hw */
2816                 drm_modeset_lock_all(dev);
2817                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2818                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2819                 }
2820                 drm_modeset_unlock_all(dev);
2821                         /* unpin the front buffers and cursors */
2822                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2823                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2824                         struct drm_framebuffer *fb = crtc->primary->fb;
2825                         struct amdgpu_bo *robj;
2826
2827                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2828                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2829                                 r = amdgpu_bo_reserve(aobj, true);
2830                                 if (r == 0) {
2831                                         amdgpu_bo_unpin(aobj);
2832                                         amdgpu_bo_unreserve(aobj);
2833                                 }
2834                         }
2835
2836                         if (fb == NULL || fb->obj[0] == NULL) {
2837                                 continue;
2838                         }
2839                         robj = gem_to_amdgpu_bo(fb->obj[0]);
2840                         /* don't unpin kernel fb objects */
2841                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2842                                 r = amdgpu_bo_reserve(robj, true);
2843                                 if (r == 0) {
2844                                         amdgpu_bo_unpin(robj);
2845                                         amdgpu_bo_unreserve(robj);
2846                                 }
2847                         }
2848                 }
2849         }
2850
2851         amdgpu_amdkfd_suspend(adev);
2852
2853         r = amdgpu_device_ip_suspend_phase1(adev);
2854
2855         /* evict vram memory */
2856         amdgpu_bo_evict_vram(adev);
2857
2858         amdgpu_fence_driver_suspend(adev);
2859
2860         r = amdgpu_device_ip_suspend_phase2(adev);
2861
2862         /* evict remaining vram memory
2863          * This second call to evict vram is to evict the gart page table
2864          * using the CPU.
2865          */
2866         amdgpu_bo_evict_vram(adev);
2867
2868         pci_save_state(dev->pdev);
2869         if (suspend) {
2870                 /* Shut down the device */
2871                 pci_disable_device(dev->pdev);
2872                 pci_set_power_state(dev->pdev, PCI_D3hot);
2873         } else {
2874                 r = amdgpu_asic_reset(adev);
2875                 if (r)
2876                         DRM_ERROR("amdgpu asic reset failed\n");
2877         }
2878
2879         return 0;
2880 }
2881
2882 /**
2883  * amdgpu_device_resume - initiate device resume
2884  *
2885  * @dev: drm dev pointer
2886  * @resume: resume state
2887  * @fbcon : notify the fbdev of resume
2888  *
2889  * Bring the hw back to operating state (all asics).
2890  * Returns 0 for success or an error on failure.
2891  * Called at driver resume.
2892  */
2893 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2894 {
2895         struct drm_connector *connector;
2896         struct amdgpu_device *adev = dev->dev_private;
2897         struct drm_crtc *crtc;
2898         int r = 0;
2899
2900         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2901                 return 0;
2902
2903         if (resume) {
2904                 pci_set_power_state(dev->pdev, PCI_D0);
2905                 pci_restore_state(dev->pdev);
2906                 r = pci_enable_device(dev->pdev);
2907                 if (r)
2908                         return r;
2909         }
2910
2911         /* post card */
2912         if (amdgpu_device_need_post(adev)) {
2913                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2914                 if (r)
2915                         DRM_ERROR("amdgpu asic init failed\n");
2916         }
2917
2918         r = amdgpu_device_ip_resume(adev);
2919         if (r) {
2920                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2921                 return r;
2922         }
2923         amdgpu_fence_driver_resume(adev);
2924
2925
2926         r = amdgpu_device_ip_late_init(adev);
2927         if (r)
2928                 return r;
2929
2930         if (!amdgpu_device_has_dc_support(adev)) {
2931                 /* pin cursors */
2932                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2933                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2934
2935                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2936                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2937                                 r = amdgpu_bo_reserve(aobj, true);
2938                                 if (r == 0) {
2939                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2940                                         if (r != 0)
2941                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2942                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2943                                         amdgpu_bo_unreserve(aobj);
2944                                 }
2945                         }
2946                 }
2947         }
2948         r = amdgpu_amdkfd_resume(adev);
2949         if (r)
2950                 return r;
2951
2952         /* Make sure IB tests flushed */
2953         flush_delayed_work(&adev->late_init_work);
2954
2955         /* blat the mode back in */
2956         if (fbcon) {
2957                 if (!amdgpu_device_has_dc_support(adev)) {
2958                         /* pre DCE11 */
2959                         drm_helper_resume_force_mode(dev);
2960
2961                         /* turn on display hw */
2962                         drm_modeset_lock_all(dev);
2963                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2964                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2965                         }
2966                         drm_modeset_unlock_all(dev);
2967                 }
2968                 amdgpu_fbdev_set_suspend(adev, 0);
2969         }
2970
2971         drm_kms_helper_poll_enable(dev);
2972
2973         /*
2974          * Most of the connector probing functions try to acquire runtime pm
2975          * refs to ensure that the GPU is powered on when connector polling is
2976          * performed. Since we're calling this from a runtime PM callback,
2977          * trying to acquire rpm refs will cause us to deadlock.
2978          *
2979          * Since we're guaranteed to be holding the rpm lock, it's safe to
2980          * temporarily disable the rpm helpers so this doesn't deadlock us.
2981          */
2982 #ifdef CONFIG_PM
2983         dev->dev->power.disable_depth++;
2984 #endif
2985         if (!amdgpu_device_has_dc_support(adev))
2986                 drm_helper_hpd_irq_event(dev);
2987         else
2988                 drm_kms_helper_hotplug_event(dev);
2989 #ifdef CONFIG_PM
2990         dev->dev->power.disable_depth--;
2991 #endif
2992         adev->in_suspend = false;
2993
2994         return 0;
2995 }
2996
2997 /**
2998  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
2999  *
3000  * @adev: amdgpu_device pointer
3001  *
3002  * The list of all the hardware IPs that make up the asic is walked and
3003  * the check_soft_reset callbacks are run.  check_soft_reset determines
3004  * if the asic is still hung or not.
3005  * Returns true if any of the IPs are still in a hung state, false if not.
3006  */
3007 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3008 {
3009         int i;
3010         bool asic_hang = false;
3011
3012         if (amdgpu_sriov_vf(adev))
3013                 return true;
3014
3015         if (amdgpu_asic_need_full_reset(adev))
3016                 return true;
3017
3018         for (i = 0; i < adev->num_ip_blocks; i++) {
3019                 if (!adev->ip_blocks[i].status.valid)
3020                         continue;
3021                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3022                         adev->ip_blocks[i].status.hang =
3023                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3024                 if (adev->ip_blocks[i].status.hang) {
3025                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3026                         asic_hang = true;
3027                 }
3028         }
3029         return asic_hang;
3030 }
3031
3032 /**
3033  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3034  *
3035  * @adev: amdgpu_device pointer
3036  *
3037  * The list of all the hardware IPs that make up the asic is walked and the
3038  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
3039  * handles any IP specific hardware or software state changes that are
3040  * necessary for a soft reset to succeed.
3041  * Returns 0 on success, negative error code on failure.
3042  */
3043 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3044 {
3045         int i, r = 0;
3046
3047         for (i = 0; i < adev->num_ip_blocks; i++) {
3048                 if (!adev->ip_blocks[i].status.valid)
3049                         continue;
3050                 if (adev->ip_blocks[i].status.hang &&
3051                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3052                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3053                         if (r)
3054                                 return r;
3055                 }
3056         }
3057
3058         return 0;
3059 }
3060
3061 /**
3062  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3063  *
3064  * @adev: amdgpu_device pointer
3065  *
3066  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
3067  * reset is necessary to recover.
3068  * Returns true if a full asic reset is required, false if not.
3069  */
3070 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3071 {
3072         int i;
3073
3074         if (amdgpu_asic_need_full_reset(adev))
3075                 return true;
3076
3077         for (i = 0; i < adev->num_ip_blocks; i++) {
3078                 if (!adev->ip_blocks[i].status.valid)
3079                         continue;
3080                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3081                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3082                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3083                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3084                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3085                         if (adev->ip_blocks[i].status.hang) {
3086                                 DRM_INFO("Some block need full reset!\n");
3087                                 return true;
3088                         }
3089                 }
3090         }
3091         return false;
3092 }
3093
3094 /**
3095  * amdgpu_device_ip_soft_reset - do a soft reset
3096  *
3097  * @adev: amdgpu_device pointer
3098  *
3099  * The list of all the hardware IPs that make up the asic is walked and the
3100  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3101  * IP specific hardware or software state changes that are necessary to soft
3102  * reset the IP.
3103  * Returns 0 on success, negative error code on failure.
3104  */
3105 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3106 {
3107         int i, r = 0;
3108
3109         for (i = 0; i < adev->num_ip_blocks; i++) {
3110                 if (!adev->ip_blocks[i].status.valid)
3111                         continue;
3112                 if (adev->ip_blocks[i].status.hang &&
3113                     adev->ip_blocks[i].version->funcs->soft_reset) {
3114                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3115                         if (r)
3116                                 return r;
3117                 }
3118         }
3119
3120         return 0;
3121 }
3122
3123 /**
3124  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3125  *
3126  * @adev: amdgpu_device pointer
3127  *
3128  * The list of all the hardware IPs that make up the asic is walked and the
3129  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3130  * handles any IP specific hardware or software state changes that are
3131  * necessary after the IP has been soft reset.
3132  * Returns 0 on success, negative error code on failure.
3133  */
3134 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3135 {
3136         int i, r = 0;
3137
3138         for (i = 0; i < adev->num_ip_blocks; i++) {
3139                 if (!adev->ip_blocks[i].status.valid)
3140                         continue;
3141                 if (adev->ip_blocks[i].status.hang &&
3142                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3143                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3144                 if (r)
3145                         return r;
3146         }
3147
3148         return 0;
3149 }
3150
3151 /**
3152  * amdgpu_device_recover_vram - Recover some VRAM contents
3153  *
3154  * @adev: amdgpu_device pointer
3155  *
3156  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3157  * restore things like GPUVM page tables after a GPU reset where
3158  * the contents of VRAM might be lost.
3159  *
3160  * Returns:
3161  * 0 on success, negative error code on failure.
3162  */
3163 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3164 {
3165         struct dma_fence *fence = NULL, *next = NULL;
3166         struct amdgpu_bo *shadow;
3167         long r = 1, tmo;
3168
3169         if (amdgpu_sriov_runtime(adev))
3170                 tmo = msecs_to_jiffies(8000);
3171         else
3172                 tmo = msecs_to_jiffies(100);
3173
3174         DRM_INFO("recover vram bo from shadow start\n");
3175         mutex_lock(&adev->shadow_list_lock);
3176         list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3177
3178                 /* No need to recover an evicted BO */
3179                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3180                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3181                         continue;
3182
3183                 r = amdgpu_bo_restore_shadow(shadow, &next);
3184                 if (r)
3185                         break;
3186
3187                 if (fence) {
3188                         r = dma_fence_wait_timeout(fence, false, tmo);
3189                         dma_fence_put(fence);
3190                         fence = next;
3191                         if (r <= 0)
3192                                 break;
3193                 } else {
3194                         fence = next;
3195                 }
3196         }
3197         mutex_unlock(&adev->shadow_list_lock);
3198
3199         if (fence)
3200                 tmo = dma_fence_wait_timeout(fence, false, tmo);
3201         dma_fence_put(fence);
3202
3203         if (r <= 0 || tmo <= 0) {
3204                 DRM_ERROR("recover vram bo from shadow failed\n");
3205                 return -EIO;
3206         }
3207
3208         DRM_INFO("recover vram bo from shadow done\n");
3209         return 0;
3210 }
3211
3212
3213 /**
3214  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3215  *
3216  * @adev: amdgpu device pointer
3217  * @from_hypervisor: request from hypervisor
3218  *
3219  * do VF FLR and reinitialize Asic
3220  * return 0 means succeeded otherwise failed
3221  */
3222 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3223                                      bool from_hypervisor)
3224 {
3225         int r;
3226
3227         if (from_hypervisor)
3228                 r = amdgpu_virt_request_full_gpu(adev, true);
3229         else
3230                 r = amdgpu_virt_reset_gpu(adev);
3231         if (r)
3232                 return r;
3233
3234         /* Resume IP prior to SMC */
3235         r = amdgpu_device_ip_reinit_early_sriov(adev);
3236         if (r)
3237                 goto error;
3238
3239         /* we need recover gart prior to run SMC/CP/SDMA resume */
3240         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3241
3242         r = amdgpu_device_fw_loading(adev);
3243         if (r)
3244                 return r;
3245
3246         /* now we are okay to resume SMC/CP/SDMA */
3247         r = amdgpu_device_ip_reinit_late_sriov(adev);
3248         if (r)
3249                 goto error;
3250
3251         amdgpu_irq_gpu_reset_resume_helper(adev);
3252         r = amdgpu_ib_ring_tests(adev);
3253
3254 error:
3255         amdgpu_virt_init_data_exchange(adev);
3256         amdgpu_virt_release_full_gpu(adev, true);
3257         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3258                 atomic_inc(&adev->vram_lost_counter);
3259                 r = amdgpu_device_recover_vram(adev);
3260         }
3261
3262         return r;
3263 }
3264
3265 /**
3266  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3267  *
3268  * @adev: amdgpu device pointer
3269  *
3270  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3271  * a hung GPU.
3272  */
3273 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3274 {
3275         if (!amdgpu_device_ip_check_soft_reset(adev)) {
3276                 DRM_INFO("Timeout, but no hardware hang detected.\n");
3277                 return false;
3278         }
3279
3280         if (amdgpu_gpu_recovery == 0)
3281                 goto disabled;
3282
3283         if (amdgpu_sriov_vf(adev))
3284                 return true;
3285
3286         if (amdgpu_gpu_recovery == -1) {
3287                 switch (adev->asic_type) {
3288                 case CHIP_BONAIRE:
3289                 case CHIP_HAWAII:
3290                 case CHIP_TOPAZ:
3291                 case CHIP_TONGA:
3292                 case CHIP_FIJI:
3293                 case CHIP_POLARIS10:
3294                 case CHIP_POLARIS11:
3295                 case CHIP_POLARIS12:
3296                 case CHIP_VEGAM:
3297                 case CHIP_VEGA20:
3298                 case CHIP_VEGA10:
3299                 case CHIP_VEGA12:
3300                         break;
3301                 default:
3302                         goto disabled;
3303                 }
3304         }
3305
3306         return true;
3307
3308 disabled:
3309                 DRM_INFO("GPU recovery disabled.\n");
3310                 return false;
3311 }
3312
3313
3314 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3315                                         struct amdgpu_job *job,
3316                                         bool *need_full_reset_arg)
3317 {
3318         int i, r = 0;
3319         bool need_full_reset  = *need_full_reset_arg;
3320
3321         /* block all schedulers and reset given job's ring */
3322         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3323                 struct amdgpu_ring *ring = adev->rings[i];
3324
3325                 if (!ring || !ring->sched.thread)
3326                         continue;
3327
3328                 drm_sched_stop(&ring->sched);
3329
3330                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3331                 amdgpu_fence_driver_force_completion(ring);
3332         }
3333
3334         if(job)
3335                 drm_sched_increase_karma(&job->base);
3336
3337
3338
3339         if (!amdgpu_sriov_vf(adev)) {
3340
3341                 if (!need_full_reset)
3342                         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3343
3344                 if (!need_full_reset) {
3345                         amdgpu_device_ip_pre_soft_reset(adev);
3346                         r = amdgpu_device_ip_soft_reset(adev);
3347                         amdgpu_device_ip_post_soft_reset(adev);
3348                         if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3349                                 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3350                                 need_full_reset = true;
3351                         }
3352                 }
3353
3354                 if (need_full_reset)
3355                         r = amdgpu_device_ip_suspend(adev);
3356
3357                 *need_full_reset_arg = need_full_reset;
3358         }
3359
3360         return r;
3361 }
3362
3363 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3364                                struct list_head *device_list_handle,
3365                                bool *need_full_reset_arg)
3366 {
3367         struct amdgpu_device *tmp_adev = NULL;
3368         bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3369         int r = 0;
3370
3371         /*
3372          * ASIC reset has to be done on all HGMI hive nodes ASAP
3373          * to allow proper links negotiation in FW (within 1 sec)
3374          */
3375         if (need_full_reset) {
3376                 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3377                         /* For XGMI run all resets in parallel to speed up the process */
3378                         if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3379                                 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3380                                         r = -EALREADY;
3381                         } else
3382                                 r = amdgpu_asic_reset(tmp_adev);
3383
3384                         if (r) {
3385                                 DRM_ERROR("ASIC reset failed with err r, %d for drm dev, %s",
3386                                          r, tmp_adev->ddev->unique);
3387                                 break;
3388                         }
3389                 }
3390
3391                 /* For XGMI wait for all PSP resets to complete before proceed */
3392                 if (!r) {
3393                         list_for_each_entry(tmp_adev, device_list_handle,
3394                                             gmc.xgmi.head) {
3395                                 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3396                                         flush_work(&tmp_adev->xgmi_reset_work);
3397                                         r = tmp_adev->asic_reset_res;
3398                                         if (r)
3399                                                 break;
3400                                 }
3401                         }
3402                 }
3403         }
3404
3405
3406         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3407                 if (need_full_reset) {
3408                         /* post card */
3409                         if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3410                                 DRM_WARN("asic atom init failed!");
3411
3412                         if (!r) {
3413                                 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3414                                 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3415                                 if (r)
3416                                         goto out;
3417
3418                                 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3419                                 if (vram_lost) {
3420                                         DRM_ERROR("VRAM is lost!\n");
3421                                         atomic_inc(&tmp_adev->vram_lost_counter);
3422                                 }
3423
3424                                 r = amdgpu_gtt_mgr_recover(
3425                                         &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3426                                 if (r)
3427                                         goto out;
3428
3429                                 r = amdgpu_device_fw_loading(tmp_adev);
3430                                 if (r)
3431                                         return r;
3432
3433                                 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3434                                 if (r)
3435                                         goto out;
3436
3437                                 if (vram_lost)
3438                                         amdgpu_device_fill_reset_magic(tmp_adev);
3439
3440                                 /* Update PSP FW topology after reset */
3441                                 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3442                                         r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3443                         }
3444                 }
3445
3446
3447 out:
3448                 if (!r) {
3449                         amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3450                         r = amdgpu_ib_ring_tests(tmp_adev);
3451                         if (r) {
3452                                 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3453                                 r = amdgpu_device_ip_suspend(tmp_adev);
3454                                 need_full_reset = true;
3455                                 r = -EAGAIN;
3456                                 goto end;
3457                         }
3458                 }
3459
3460                 if (!r)
3461                         r = amdgpu_device_recover_vram(tmp_adev);
3462                 else
3463                         tmp_adev->asic_reset_res = r;
3464         }
3465
3466 end:
3467         *need_full_reset_arg = need_full_reset;
3468         return r;
3469 }
3470
3471 static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
3472                                           struct amdgpu_job *job)
3473 {
3474         int i;
3475
3476         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3477                 struct amdgpu_ring *ring = adev->rings[i];
3478
3479                 if (!ring || !ring->sched.thread)
3480                         continue;
3481
3482                 if (!adev->asic_reset_res)
3483                         drm_sched_resubmit_jobs(&ring->sched);
3484
3485                 drm_sched_start(&ring->sched, !adev->asic_reset_res);
3486         }
3487
3488         if (!amdgpu_device_has_dc_support(adev)) {
3489                 drm_helper_resume_force_mode(adev->ddev);
3490         }
3491
3492         adev->asic_reset_res = 0;
3493 }
3494
3495 static void amdgpu_device_lock_adev(struct amdgpu_device *adev)
3496 {
3497         mutex_lock(&adev->lock_reset);
3498         atomic_inc(&adev->gpu_reset_counter);
3499         adev->in_gpu_reset = 1;
3500         /* Block kfd: SRIOV would do it separately */
3501         if (!amdgpu_sriov_vf(adev))
3502                 amdgpu_amdkfd_pre_reset(adev);
3503 }
3504
3505 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3506 {
3507         /*unlock kfd: SRIOV would do it separately */
3508         if (!amdgpu_sriov_vf(adev))
3509                 amdgpu_amdkfd_post_reset(adev);
3510         amdgpu_vf_error_trans_all(adev);
3511         adev->in_gpu_reset = 0;
3512         mutex_unlock(&adev->lock_reset);
3513 }
3514
3515
3516 /**
3517  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3518  *
3519  * @adev: amdgpu device pointer
3520  * @job: which job trigger hang
3521  *
3522  * Attempt to reset the GPU if it has hung (all asics).
3523  * Attempt to do soft-reset or full-reset and reinitialize Asic
3524  * Returns 0 for success or an error on failure.
3525  */
3526
3527 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3528                               struct amdgpu_job *job)
3529 {
3530         int r;
3531         struct amdgpu_hive_info *hive = NULL;
3532         bool need_full_reset = false;
3533         struct amdgpu_device *tmp_adev = NULL;
3534         struct list_head device_list, *device_list_handle =  NULL;
3535
3536         INIT_LIST_HEAD(&device_list);
3537
3538         dev_info(adev->dev, "GPU reset begin!\n");
3539
3540         /*
3541          * In case of XGMI hive disallow concurrent resets to be triggered
3542          * by different nodes. No point also since the one node already executing
3543          * reset will also reset all the other nodes in the hive.
3544          */
3545         hive = amdgpu_get_xgmi_hive(adev, 0);
3546         if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
3547             !mutex_trylock(&hive->reset_lock))
3548                 return 0;
3549
3550         /* Start with adev pre asic reset first for soft reset check.*/
3551         amdgpu_device_lock_adev(adev);
3552         r = amdgpu_device_pre_asic_reset(adev,
3553                                          job,
3554                                          &need_full_reset);
3555         if (r) {
3556                 /*TODO Should we stop ?*/
3557                 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3558                           r, adev->ddev->unique);
3559                 adev->asic_reset_res = r;
3560         }
3561
3562         /* Build list of devices to reset */
3563         if  (need_full_reset && adev->gmc.xgmi.num_physical_nodes > 1) {
3564                 if (!hive) {
3565                         amdgpu_device_unlock_adev(adev);
3566                         return -ENODEV;
3567                 }
3568
3569                 /*
3570                  * In case we are in XGMI hive mode device reset is done for all the
3571                  * nodes in the hive to retrain all XGMI links and hence the reset
3572                  * sequence is executed in loop on all nodes.
3573                  */
3574                 device_list_handle = &hive->device_list;
3575         } else {
3576                 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3577                 device_list_handle = &device_list;
3578         }
3579
3580 retry:  /* Rest of adevs pre asic reset from XGMI hive. */
3581         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3582
3583                 if (tmp_adev == adev)
3584                         continue;
3585
3586                 amdgpu_device_lock_adev(tmp_adev);
3587                 r = amdgpu_device_pre_asic_reset(tmp_adev,
3588                                                  NULL,
3589                                                  &need_full_reset);
3590                 /*TODO Should we stop ?*/
3591                 if (r) {
3592                         DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3593                                   r, tmp_adev->ddev->unique);
3594                         tmp_adev->asic_reset_res = r;
3595                 }
3596         }
3597
3598         /* Actual ASIC resets if needed.*/
3599         /* TODO Implement XGMI hive reset logic for SRIOV */
3600         if (amdgpu_sriov_vf(adev)) {
3601                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3602                 if (r)
3603                         adev->asic_reset_res = r;
3604         } else {
3605                 r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3606                 if (r && r == -EAGAIN)
3607                         goto retry;
3608         }
3609
3610         /* Post ASIC reset for all devs .*/
3611         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3612                 amdgpu_device_post_asic_reset(tmp_adev, tmp_adev == adev ? job : NULL);
3613
3614                 if (r) {
3615                         /* bad news, how to tell it to userspace ? */
3616                         dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3617                         amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3618                 } else {
3619                         dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3620                 }
3621
3622                 amdgpu_device_unlock_adev(tmp_adev);
3623         }
3624
3625         if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
3626                 mutex_unlock(&hive->reset_lock);
3627
3628         if (r)
3629                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3630         return r;
3631 }
3632
3633 static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
3634                                                   enum pci_bus_speed *speed,
3635                                                   enum pcie_link_width *width)
3636 {
3637         struct pci_dev *pdev = adev->pdev;
3638         enum pci_bus_speed cur_speed;
3639         enum pcie_link_width cur_width;
3640
3641         *speed = PCI_SPEED_UNKNOWN;
3642         *width = PCIE_LNK_WIDTH_UNKNOWN;
3643
3644         while (pdev) {
3645                 cur_speed = pcie_get_speed_cap(pdev);
3646                 cur_width = pcie_get_width_cap(pdev);
3647
3648                 if (cur_speed != PCI_SPEED_UNKNOWN) {
3649                         if (*speed == PCI_SPEED_UNKNOWN)
3650                                 *speed = cur_speed;
3651                         else if (cur_speed < *speed)
3652                                 *speed = cur_speed;
3653                 }
3654
3655                 if (cur_width != PCIE_LNK_WIDTH_UNKNOWN) {
3656                         if (*width == PCIE_LNK_WIDTH_UNKNOWN)
3657                                 *width = cur_width;
3658                         else if (cur_width < *width)
3659                                 *width = cur_width;
3660                 }
3661                 pdev = pci_upstream_bridge(pdev);
3662         }
3663 }
3664
3665 /**
3666  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3667  *
3668  * @adev: amdgpu_device pointer
3669  *
3670  * Fetchs and stores in the driver the PCIE capabilities (gen speed
3671  * and lanes) of the slot the device is in. Handles APUs and
3672  * virtualized environments where PCIE config space may not be available.
3673  */
3674 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3675 {
3676         struct pci_dev *pdev;
3677         enum pci_bus_speed speed_cap, platform_speed_cap;
3678         enum pcie_link_width platform_link_width;
3679
3680         if (amdgpu_pcie_gen_cap)
3681                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3682
3683         if (amdgpu_pcie_lane_cap)
3684                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3685
3686         /* covers APUs as well */
3687         if (pci_is_root_bus(adev->pdev->bus)) {
3688                 if (adev->pm.pcie_gen_mask == 0)
3689                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3690                 if (adev->pm.pcie_mlw_mask == 0)
3691                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3692                 return;
3693         }
3694
3695         if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3696                 return;
3697
3698         amdgpu_device_get_min_pci_speed_width(adev, &platform_speed_cap,
3699                                               &platform_link_width);
3700
3701         if (adev->pm.pcie_gen_mask == 0) {
3702                 /* asic caps */
3703                 pdev = adev->pdev;
3704                 speed_cap = pcie_get_speed_cap(pdev);
3705                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3706                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3707                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3708                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3709                 } else {
3710                         if (speed_cap == PCIE_SPEED_16_0GT)
3711                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3712                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3713                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3714                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3715                         else if (speed_cap == PCIE_SPEED_8_0GT)
3716                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3717                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3718                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3719                         else if (speed_cap == PCIE_SPEED_5_0GT)
3720                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3721                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3722                         else
3723                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3724                 }
3725                 /* platform caps */
3726                 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
3727                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3728                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3729                 } else {
3730                         if (platform_speed_cap == PCIE_SPEED_16_0GT)
3731                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3732                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3733                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3734                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3735                         else if (platform_speed_cap == PCIE_SPEED_8_0GT)
3736                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3737                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3738                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3739                         else if (platform_speed_cap == PCIE_SPEED_5_0GT)
3740                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3741                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3742                         else
3743                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3744
3745                 }
3746         }
3747         if (adev->pm.pcie_mlw_mask == 0) {
3748                 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3749                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3750                 } else {
3751                         switch (platform_link_width) {
3752                         case PCIE_LNK_X32:
3753                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3754                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3755                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3756                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3757                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3758                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3759                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3760                                 break;
3761                         case PCIE_LNK_X16:
3762                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3763                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3764                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3765                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3766                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3767                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3768                                 break;
3769                         case PCIE_LNK_X12:
3770                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3771                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3772                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3773                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3774                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3775                                 break;
3776                         case PCIE_LNK_X8:
3777                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3778                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3779                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3780                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3781                                 break;
3782                         case PCIE_LNK_X4:
3783                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3784                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3785                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3786                                 break;
3787                         case PCIE_LNK_X2:
3788                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3789                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3790                                 break;
3791                         case PCIE_LNK_X1:
3792                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3793                                 break;
3794                         default:
3795                                 break;
3796                         }
3797                 }
3798         }
3799 }
3800