drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_amdkfd.h"
  30 #include "amdgpu_ucode.h"
  31 #include "gfx_v8_0.h"
  32 #include "gca/gfx_8_0_sh_mask.h"
  33 #include "gca/gfx_8_0_d.h"
  34 #include "gca/gfx_8_0_enum.h"
  35 #include "oss/oss_3_0_sh_mask.h"
  36 #include "oss/oss_3_0_d.h"
  37 #include "gmc/gmc_8_1_sh_mask.h"
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "vi_structs.h"
  40 #include "vid.h"
  41
  42 enum hqd_dequeue_request_type {
  43         NO_ACTION = 0,
  44         DRAIN_PIPE,
  45         RESET_WAVES
  46 };
  47
  48 struct vi_sdma_mqd;
  49
  50 /*
  51  * Register access functions
  52  */
  53
  54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  55                 uint32_t sh_mem_config,
  56                 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
  57                 uint32_t sh_mem_bases);
  58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  59                 unsigned int vmid);
  60 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
  61 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  62                         uint32_t queue_id, uint32_t __user *wptr,
  63                         uint32_t wptr_shift, uint32_t wptr_mask,
  64                         struct mm_struct *mm);
  65 static int kgd_hqd_dump(struct kgd_dev *kgd,
  66                         uint32_t pipe_id, uint32_t queue_id,
  67                         uint32_t (**dump)[2], uint32_t *n_regs);
  68 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
  69                              uint32_t __user *wptr, struct mm_struct *mm);
  70 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
  71                              uint32_t engine_id, uint32_t queue_id,
  72                              uint32_t (**dump)[2], uint32_t *n_regs);
  73 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
  74                 uint32_t pipe_id, uint32_t queue_id);
  75 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
  76 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
  77                                 enum kfd_preempt_type reset_type,
  78                                 unsigned int utimeout, uint32_t pipe_id,
  79                                 uint32_t queue_id);
  80 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
  81                                 unsigned int utimeout);
  82 static int kgd_address_watch_disable(struct kgd_dev *kgd);
  83 static int kgd_address_watch_execute(struct kgd_dev *kgd,
  84                                         unsigned int watch_point_id,
  85                                         uint32_t cntl_val,
  86                                         uint32_t addr_hi,
  87                                         uint32_t addr_lo);
  88 static int kgd_wave_control_execute(struct kgd_dev *kgd,
  89                                         uint32_t gfx_index_val,
  90                                         uint32_t sq_cmd);
  91 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
  92                                         unsigned int watch_point_id,
  93                                         unsigned int reg_offset);
  94
  95 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
  96                 uint8_t vmid);
  97 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
  98                 uint8_t vmid);
  99 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
 100 static void set_scratch_backing_va(struct kgd_dev *kgd,
 101                                         uint64_t va, uint32_t vmid);
 102 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 103                 uint32_t page_table_base);
 104 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 105 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 106
 107 /* Because of REG_GET_FIELD() being used, we put this function in the
 108  * asic specific file.
 109  */
 110 static int get_tile_config(struct kgd_dev *kgd,
 111                 struct tile_config *config)
 112 {
 113         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 114
 115         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 116         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 117                                 MC_ARB_RAMCFG, NOOFBANK);
 118         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 119                                 MC_ARB_RAMCFG, NOOFRANKS);
 120
 121         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 122         config->num_tile_configs =
 123                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 124         config->macro_tile_config_ptr =
 125                         adev->gfx.config.macrotile_mode_array;
 126         config->num_macro_tile_configs =
 127                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 128
 129         return 0;
 130 }
 131
 132 static const struct kfd2kgd_calls kfd2kgd = {
 133         .init_gtt_mem_allocation = alloc_gtt_mem,
 134         .free_gtt_mem = free_gtt_mem,
 135         .get_local_mem_info = get_local_mem_info,
 136         .get_gpu_clock_counter = get_gpu_clock_counter,
 137         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
 138         .alloc_pasid = amdgpu_pasid_alloc,
 139         .free_pasid = amdgpu_pasid_free,
 140         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 141         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 142         .init_interrupts = kgd_init_interrupts,
 143         .hqd_load = kgd_hqd_load,
 144         .hqd_sdma_load = kgd_hqd_sdma_load,
 145         .hqd_dump = kgd_hqd_dump,
 146         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 147         .hqd_is_occupied = kgd_hqd_is_occupied,
 148         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 149         .hqd_destroy = kgd_hqd_destroy,
 150         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 151         .address_watch_disable = kgd_address_watch_disable,
 152         .address_watch_execute = kgd_address_watch_execute,
 153         .wave_control_execute = kgd_wave_control_execute,
 154         .address_watch_get_offset = kgd_address_watch_get_offset,
 155         .get_atc_vmid_pasid_mapping_pasid =
 156                         get_atc_vmid_pasid_mapping_pasid,
 157         .get_atc_vmid_pasid_mapping_valid =
 158                         get_atc_vmid_pasid_mapping_valid,
 159         .get_fw_version = get_fw_version,
 160         .set_scratch_backing_va = set_scratch_backing_va,
 161         .get_tile_config = get_tile_config,
 162         .get_cu_info = get_cu_info,
 163         .get_vram_usage = amdgpu_amdkfd_get_vram_usage,
 164         .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
 165         .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
 166         .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
 167         .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
 168         .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
 169         .set_vm_context_page_table_base = set_vm_context_page_table_base,
 170         .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
 171         .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
 172         .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
 173         .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
 174         .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
 175         .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
 176         .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
 177         .invalidate_tlbs = invalidate_tlbs,
 178         .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
 179         .submit_ib = amdgpu_amdkfd_submit_ib,
 180         .get_vm_fault_info = amdgpu_amdkfd_gpuvm_get_vm_fault_info,
 181         .gpu_recover = amdgpu_amdkfd_gpu_reset,
 182         .set_compute_idle = amdgpu_amdkfd_set_compute_idle
 183 };
 184
 185 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 186 {
 187         return (struct kfd2kgd_calls *)&kfd2kgd;
 188 }
 189
 190 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 191 {
 192         return (struct amdgpu_device *)kgd;
 193 }
 194
 195 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 196                         uint32_t queue, uint32_t vmid)
 197 {
 198         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 199         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 200
 201         mutex_lock(&adev->srbm_mutex);
 202         WREG32(mmSRBM_GFX_CNTL, value);
 203 }
 204
 205 static void unlock_srbm(struct kgd_dev *kgd)
 206 {
 207         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 208
 209         WREG32(mmSRBM_GFX_CNTL, 0);
 210         mutex_unlock(&adev->srbm_mutex);
 211 }
 212
 213 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 214                                 uint32_t queue_id)
 215 {
 216         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 217
 218         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 219         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 220
 221         lock_srbm(kgd, mec, pipe, queue_id, 0);
 222 }
 223
 224 static void release_queue(struct kgd_dev *kgd)
 225 {
 226         unlock_srbm(kgd);
 227 }
 228
 229 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 230                                         uint32_t sh_mem_config,
 231                                         uint32_t sh_mem_ape1_base,
 232                                         uint32_t sh_mem_ape1_limit,
 233                                         uint32_t sh_mem_bases)
 234 {
 235         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 236
 237         lock_srbm(kgd, 0, 0, 0, vmid);
 238
 239         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 240         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 241         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 242         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 243
 244         unlock_srbm(kgd);
 245 }
 246
 247 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 248                                         unsigned int vmid)
 249 {
 250         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 251
 252         /*
 253          * We have to assume that there is no outstanding mapping.
 254          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 255          * a mapping is in progress or because a mapping finished
 256          * and the SW cleared it.
 257          * So the protocol is to always wait & clear.
 258          */
 259         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 260                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 261
 262         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 263
 264         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 265                 cpu_relax();
 266         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 267
 268         /* Mapping vmid to pasid also for IH block */
 269         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 270
 271         return 0;
 272 }
 273
 274 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 275 {
 276         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 277         uint32_t mec;
 278         uint32_t pipe;
 279
 280         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 281         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 282
 283         lock_srbm(kgd, mec, pipe, 0, 0);
 284
 285         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 286                         CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 287
 288         unlock_srbm(kgd);
 289
 290         return 0;
 291 }
 292
 293 static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
 294 {
 295         uint32_t retval;
 296
 297         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 298                 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 299         pr_debug("kfd: sdma base address: 0x%x\n", retval);
 300
 301         return retval;
 302 }
 303
 304 static inline struct vi_mqd *get_mqd(void *mqd)
 305 {
 306         return (struct vi_mqd *)mqd;
 307 }
 308
 309 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
 310 {
 311         return (struct vi_sdma_mqd *)mqd;
 312 }
 313
 314 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 315                         uint32_t queue_id, uint32_t __user *wptr,
 316                         uint32_t wptr_shift, uint32_t wptr_mask,
 317                         struct mm_struct *mm)
 318 {
 319         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 320         struct vi_mqd *m;
 321         uint32_t *mqd_hqd;
 322         uint32_t reg, wptr_val, data;
 323         bool valid_wptr = false;
 324
 325         m = get_mqd(mqd);
 326
 327         acquire_queue(kgd, pipe_id, queue_id);
 328
 329         /* HIQ is set during driver init period with vmid set to 0*/
 330         if (m->cp_hqd_vmid == 0) {
 331                 uint32_t value, mec, pipe;
 332
 333                 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 334                 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 335
 336                 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 337                         mec, pipe, queue_id);
 338                 value = RREG32(mmRLC_CP_SCHEDULERS);
 339                 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 340                         ((mec << 5) | (pipe << 3) | queue_id | 0x80));
 341                 WREG32(mmRLC_CP_SCHEDULERS, value);
 342         }
 343
 344         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
 345         mqd_hqd = &m->cp_mqd_base_addr_lo;
 346
 347         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
 348                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 349
 350         /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
 351          * This is safe since EOP RPTR==WPTR for any inactive HQD
 352          * on ASICs that do not support context-save.
 353          * EOP writes/reads can start anywhere in the ring.
 354          */
 355         if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) {
 356                 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
 357                 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
 358                 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
 359         }
 360
 361         for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
 362                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 363
 364         /* Copy userspace write pointer value to register.
 365          * Activate doorbell logic to monitor subsequent changes.
 366          */
 367         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 368                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 369         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 370
 371         /* read_user_ptr may take the mm->mmap_sem.
 372          * release srbm_mutex to avoid circular dependency between
 373          * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
 374          */
 375         release_queue(kgd);
 376         valid_wptr = read_user_wptr(mm, wptr, wptr_val);
 377         acquire_queue(kgd, pipe_id, queue_id);
 378         if (valid_wptr)
 379                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 380
 381         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 382         WREG32(mmCP_HQD_ACTIVE, data);
 383
 384         release_queue(kgd);
 385
 386         return 0;
 387 }
 388
 389 static int kgd_hqd_dump(struct kgd_dev *kgd,
 390                         uint32_t pipe_id, uint32_t queue_id,
 391                         uint32_t (**dump)[2], uint32_t *n_regs)
 392 {
 393         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 394         uint32_t i = 0, reg;
 395 #define HQD_N_REGS (54+4)
 396 #define DUMP_REG(addr) do {                             \
 397                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 398                         break;                          \
 399                 (*dump)[i][0] = (addr) << 2;            \
 400                 (*dump)[i++][1] = RREG32(addr);         \
 401         } while (0)
 402
 403         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 404         if (*dump == NULL)
 405                 return -ENOMEM;
 406
 407         acquire_queue(kgd, pipe_id, queue_id);
 408
 409         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
 410         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
 411         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
 412         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
 413
 414         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
 415                 DUMP_REG(reg);
 416
 417         release_queue(kgd);
 418
 419         WARN_ON_ONCE(i != HQD_N_REGS);
 420         *n_regs = i;
 421
 422         return 0;
 423 }
 424
 425 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 426                              uint32_t __user *wptr, struct mm_struct *mm)
 427 {
 428         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 429         struct vi_sdma_mqd *m;
 430         unsigned long end_jiffies;
 431         uint32_t sdma_base_addr;
 432         uint32_t data;
 433
 434         m = get_sdma_mqd(mqd);
 435         sdma_base_addr = get_sdma_base_addr(m);
 436         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 437                 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 438
 439         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 440         while (true) {
 441                 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 442                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 443                         break;
 444                 if (time_after(jiffies, end_jiffies))
 445                         return -ETIME;
 446                 usleep_range(500, 1000);
 447         }
 448         if (m->sdma_engine_id) {
 449                 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
 450                 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
 451                                 RESUME_CTX, 0);
 452                 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
 453         } else {
 454                 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
 455                 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
 456                                 RESUME_CTX, 0);
 457                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 458         }
 459
 460         data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
 461                              ENABLE, 1);
 462         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
 463         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
 464
 465         if (read_user_wptr(mm, wptr, data))
 466                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
 467         else
 468                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
 469                        m->sdmax_rlcx_rb_rptr);
 470
 471         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 472                                 m->sdmax_rlcx_virtual_addr);
 473         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
 474         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 475                         m->sdmax_rlcx_rb_base_hi);
 476         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 477                         m->sdmax_rlcx_rb_rptr_addr_lo);
 478         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 479                         m->sdmax_rlcx_rb_rptr_addr_hi);
 480
 481         data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
 482                              RB_ENABLE, 1);
 483         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 484
 485         return 0;
 486 }
 487
 488 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 489                              uint32_t engine_id, uint32_t queue_id,
 490                              uint32_t (**dump)[2], uint32_t *n_regs)
 491 {
 492         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 493         uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
 494                 queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 495         uint32_t i = 0, reg;
 496 #undef HQD_N_REGS
 497 #define HQD_N_REGS (19+4+2+3+7)
 498
 499         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 500         if (*dump == NULL)
 501                 return -ENOMEM;
 502
 503         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 504                 DUMP_REG(sdma_offset + reg);
 505         for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
 506              reg++)
 507                 DUMP_REG(sdma_offset + reg);
 508         for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
 509              reg++)
 510                 DUMP_REG(sdma_offset + reg);
 511         for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
 512              reg++)
 513                 DUMP_REG(sdma_offset + reg);
 514         for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
 515              reg++)
 516                 DUMP_REG(sdma_offset + reg);
 517
 518         WARN_ON_ONCE(i != HQD_N_REGS);
 519         *n_regs = i;
 520
 521         return 0;
 522 }
 523
 524 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 525                                 uint32_t pipe_id, uint32_t queue_id)
 526 {
 527         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 528         uint32_t act;
 529         bool retval = false;
 530         uint32_t low, high;
 531
 532         acquire_queue(kgd, pipe_id, queue_id);
 533         act = RREG32(mmCP_HQD_ACTIVE);
 534         if (act) {
 535                 low = lower_32_bits(queue_address >> 8);
 536                 high = upper_32_bits(queue_address >> 8);
 537
 538                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 539                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 540                         retval = true;
 541         }
 542         release_queue(kgd);
 543         return retval;
 544 }
 545
 546 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 547 {
 548         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 549         struct vi_sdma_mqd *m;
 550         uint32_t sdma_base_addr;
 551         uint32_t sdma_rlc_rb_cntl;
 552
 553         m = get_sdma_mqd(mqd);
 554         sdma_base_addr = get_sdma_base_addr(m);
 555
 556         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 557
 558         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 559                 return true;
 560
 561         return false;
 562 }
 563
 564 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 565                                 enum kfd_preempt_type reset_type,
 566                                 unsigned int utimeout, uint32_t pipe_id,
 567                                 uint32_t queue_id)
 568 {
 569         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 570         uint32_t temp;
 571         enum hqd_dequeue_request_type type;
 572         unsigned long flags, end_jiffies;
 573         int retry;
 574         struct vi_mqd *m = get_mqd(mqd);
 575
 576         if (adev->in_gpu_reset)
 577                 return -EIO;
 578
 579         acquire_queue(kgd, pipe_id, queue_id);
 580
 581         if (m->cp_hqd_vmid == 0)
 582                 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
 583
 584         switch (reset_type) {
 585         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 586                 type = DRAIN_PIPE;
 587                 break;
 588         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 589                 type = RESET_WAVES;
 590                 break;
 591         default:
 592                 type = DRAIN_PIPE;
 593                 break;
 594         }
 595
 596         /* Workaround: If IQ timer is active and the wait time is close to or
 597          * equal to 0, dequeueing is not safe. Wait until either the wait time
 598          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 599          * cleared before continuing. Also, ensure wait times are set to at
 600          * least 0x3.
 601          */
 602         local_irq_save(flags);
 603         preempt_disable();
 604         retry = 5000; /* wait for 500 usecs at maximum */
 605         while (true) {
 606                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 607                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 608                         pr_debug("HW is processing IQ\n");
 609                         goto loop;
 610                 }
 611                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 612                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 613                                         == 3) /* SEM-rearm is safe */
 614                                 break;
 615                         /* Wait time 3 is safe for CP, but our MMIO read/write
 616                          * time is close to 1 microsecond, so check for 10 to
 617                          * leave more buffer room
 618                          */
 619                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 620                                         >= 10)
 621                                 break;
 622                         pr_debug("IQ timer is active\n");
 623                 } else
 624                         break;
 625 loop:
 626                 if (!retry) {
 627                         pr_err("CP HQD IQ timer status time out\n");
 628                         break;
 629                 }
 630                 ndelay(100);
 631                 --retry;
 632         }
 633         retry = 1000;
 634         while (true) {
 635                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 636                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 637                         break;
 638                 pr_debug("Dequeue request is pending\n");
 639
 640                 if (!retry) {
 641                         pr_err("CP HQD dequeue request time out\n");
 642                         break;
 643                 }
 644                 ndelay(100);
 645                 --retry;
 646         }
 647         local_irq_restore(flags);
 648         preempt_enable();
 649
 650         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 651
 652         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 653         while (true) {
 654                 temp = RREG32(mmCP_HQD_ACTIVE);
 655                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 656                         break;
 657                 if (time_after(jiffies, end_jiffies)) {
 658                         pr_err("cp queue preemption time out.\n");
 659                         release_queue(kgd);
 660                         return -ETIME;
 661                 }
 662                 usleep_range(500, 1000);
 663         }
 664
 665         release_queue(kgd);
 666         return 0;
 667 }
 668
 669 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 670                                 unsigned int utimeout)
 671 {
 672         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 673         struct vi_sdma_mqd *m;
 674         uint32_t sdma_base_addr;
 675         uint32_t temp;
 676         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 677
 678         m = get_sdma_mqd(mqd);
 679         sdma_base_addr = get_sdma_base_addr(m);
 680
 681         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 682         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 683         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 684
 685         while (true) {
 686                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 687                 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 688                         break;
 689                 if (time_after(jiffies, end_jiffies))
 690                         return -ETIME;
 691                 usleep_range(500, 1000);
 692         }
 693
 694         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 695         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 696                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 697                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 698
 699         m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 700
 701         return 0;
 702 }
 703
 704 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 705                                                         uint8_t vmid)
 706 {
 707         uint32_t reg;
 708         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 709
 710         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 711         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 712 }
 713
 714 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 715                                                                 uint8_t vmid)
 716 {
 717         uint32_t reg;
 718         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 719
 720         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 721         return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 722 }
 723
 724 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 725 {
 726         return 0;
 727 }
 728
 729 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 730                                         unsigned int watch_point_id,
 731                                         uint32_t cntl_val,
 732                                         uint32_t addr_hi,
 733                                         uint32_t addr_lo)
 734 {
 735         return 0;
 736 }
 737
 738 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 739                                         uint32_t gfx_index_val,
 740                                         uint32_t sq_cmd)
 741 {
 742         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 743         uint32_t data = 0;
 744
 745         mutex_lock(&adev->grbm_idx_mutex);
 746
 747         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 748         WREG32(mmSQ_CMD, sq_cmd);
 749
 750         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 751                 INSTANCE_BROADCAST_WRITES, 1);
 752         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 753                 SH_BROADCAST_WRITES, 1);
 754         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 755                 SE_BROADCAST_WRITES, 1);
 756
 757         WREG32(mmGRBM_GFX_INDEX, data);
 758         mutex_unlock(&adev->grbm_idx_mutex);
 759
 760         return 0;
 761 }
 762
 763 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 764                                         unsigned int watch_point_id,
 765                                         unsigned int reg_offset)
 766 {
 767         return 0;
 768 }
 769
 770 static void set_scratch_backing_va(struct kgd_dev *kgd,
 771                                         uint64_t va, uint32_t vmid)
 772 {
 773         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 774
 775         lock_srbm(kgd, 0, 0, 0, vmid);
 776         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 777         unlock_srbm(kgd);
 778 }
 779
 780 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 781 {
 782         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 783         const union amdgpu_firmware_header *hdr;
 784
 785         switch (type) {
 786         case KGD_ENGINE_PFP:
 787                 hdr = (const union amdgpu_firmware_header *)
 788                                                 adev->gfx.pfp_fw->data;
 789                 break;
 790
 791         case KGD_ENGINE_ME:
 792                 hdr = (const union amdgpu_firmware_header *)
 793                                                 adev->gfx.me_fw->data;
 794                 break;
 795
 796         case KGD_ENGINE_CE:
 797                 hdr = (const union amdgpu_firmware_header *)
 798                                                 adev->gfx.ce_fw->data;
 799                 break;
 800
 801         case KGD_ENGINE_MEC1:
 802                 hdr = (const union amdgpu_firmware_header *)
 803                                                 adev->gfx.mec_fw->data;
 804                 break;
 805
 806         case KGD_ENGINE_MEC2:
 807                 hdr = (const union amdgpu_firmware_header *)
 808                                                 adev->gfx.mec2_fw->data;
 809                 break;
 810
 811         case KGD_ENGINE_RLC:
 812                 hdr = (const union amdgpu_firmware_header *)
 813                                                 adev->gfx.rlc_fw->data;
 814                 break;
 815
 816         case KGD_ENGINE_SDMA1:
 817                 hdr = (const union amdgpu_firmware_header *)
 818                                                 adev->sdma.instance[0].fw->data;
 819                 break;
 820
 821         case KGD_ENGINE_SDMA2:
 822                 hdr = (const union amdgpu_firmware_header *)
 823                                                 adev->sdma.instance[1].fw->data;
 824                 break;
 825
 826         default:
 827                 return 0;
 828         }
 829
 830         if (hdr == NULL)
 831                 return 0;
 832
 833         /* Only 12 bit in use*/
 834         return hdr->common.ucode_version;
 835 }
 836
 837 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 838                 uint32_t page_table_base)
 839 {
 840         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 841
 842         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 843                 pr_err("trying to set page table base for wrong VMID\n");
 844                 return;
 845         }
 846         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
 847 }
 848
 849 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
 850 {
 851         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 852         int vmid;
 853         unsigned int tmp;
 854
 855         if (adev->in_gpu_reset)
 856                 return -EIO;
 857
 858         for (vmid = 0; vmid < 16; vmid++) {
 859                 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
 860                         continue;
 861
 862                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 863                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 864                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 865                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 866                         RREG32(mmVM_INVALIDATE_RESPONSE);
 867                         break;
 868                 }
 869         }
 870
 871         return 0;
 872 }
 873
 874 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
 875 {
 876         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 877
 878         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 879                 pr_err("non kfd vmid %d\n", vmid);
 880                 return -EINVAL;
 881         }
 882
 883         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 884         RREG32(mmVM_INVALIDATE_RESPONSE);
 885         return 0;
 886 }