2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/pci.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
25 #define IOH_EDGE_FALLING 0
26 #define IOH_EDGE_RISING BIT(0)
27 #define IOH_LEVEL_L BIT(1)
28 #define IOH_LEVEL_H (BIT(0) | BIT(1))
29 #define IOH_EDGE_BOTH BIT(2)
30 #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
32 #define IOH_IRQ_BASE 0
50 struct ioh_reg_comn regs[8];
58 * struct ioh_gpio_reg_data - The register store data.
59 * @ien_reg To store contents of interrupt enable register.
60 * @imask_reg: To store contents of interrupt mask regist
61 * @po_reg: To store contents of PO register.
62 * @pm_reg: To store contents of PM register.
63 * @im0_reg: To store contents of interrupt mode regist0
64 * @im1_reg: To store contents of interrupt mode regist1
65 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
67 struct ioh_gpio_reg_data {
78 * struct ioh_gpio - GPIO private data structure.
79 * @base: PCI base address of Memory mapped I/O register.
80 * @reg: Memory mapped IOH GPIO register list.
81 * @dev: Pointer to device structure.
82 * @gpio: Data for GPIO infrastructure.
83 * @ioh_gpio_reg: Memory mapped Register data is saved here
85 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
86 * @ch: Indicate GPIO channel
87 * @irq_base: Save base of IRQ number for interrupt
88 * @spinlock: Used for register access protection
92 struct ioh_regs __iomem *reg;
94 struct gpio_chip gpio;
95 struct ioh_gpio_reg_data ioh_gpio_reg;
102 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
104 static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
107 struct ioh_gpio *chip = gpiochip_get_data(gpio);
110 spin_lock_irqsave(&chip->spinlock, flags);
111 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
113 reg_val |= (1 << nr);
115 reg_val &= ~(1 << nr);
117 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
118 spin_unlock_irqrestore(&chip->spinlock, flags);
121 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
123 struct ioh_gpio *chip = gpiochip_get_data(gpio);
125 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
128 static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
131 struct ioh_gpio *chip = gpiochip_get_data(gpio);
136 spin_lock_irqsave(&chip->spinlock, flags);
137 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
138 ((1 << num_ports[chip->ch]) - 1);
140 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
142 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
144 reg_val |= (1 << nr);
146 reg_val &= ~(1 << nr);
147 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
149 spin_unlock_irqrestore(&chip->spinlock, flags);
154 static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
156 struct ioh_gpio *chip = gpiochip_get_data(gpio);
160 spin_lock_irqsave(&chip->spinlock, flags);
161 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
162 ((1 << num_ports[chip->ch]) - 1);
164 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
165 spin_unlock_irqrestore(&chip->spinlock, flags);
172 * Save register configuration and disable interrupts.
174 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
178 for (i = 0; i < 8; i ++, chip++) {
179 chip->ioh_gpio_reg.po_reg =
180 ioread32(&chip->reg->regs[chip->ch].po);
181 chip->ioh_gpio_reg.pm_reg =
182 ioread32(&chip->reg->regs[chip->ch].pm);
183 chip->ioh_gpio_reg.ien_reg =
184 ioread32(&chip->reg->regs[chip->ch].ien);
185 chip->ioh_gpio_reg.imask_reg =
186 ioread32(&chip->reg->regs[chip->ch].imask);
187 chip->ioh_gpio_reg.im0_reg =
188 ioread32(&chip->reg->regs[chip->ch].im_0);
189 chip->ioh_gpio_reg.im1_reg =
190 ioread32(&chip->reg->regs[chip->ch].im_1);
192 chip->ioh_gpio_reg.use_sel_reg =
193 ioread32(&chip->reg->ioh_sel_reg[i]);
198 * This function restores the register configuration of the GPIO device.
200 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
204 for (i = 0; i < 8; i ++, chip++) {
205 iowrite32(chip->ioh_gpio_reg.po_reg,
206 &chip->reg->regs[chip->ch].po);
207 iowrite32(chip->ioh_gpio_reg.pm_reg,
208 &chip->reg->regs[chip->ch].pm);
209 iowrite32(chip->ioh_gpio_reg.ien_reg,
210 &chip->reg->regs[chip->ch].ien);
211 iowrite32(chip->ioh_gpio_reg.imask_reg,
212 &chip->reg->regs[chip->ch].imask);
213 iowrite32(chip->ioh_gpio_reg.im0_reg,
214 &chip->reg->regs[chip->ch].im_0);
215 iowrite32(chip->ioh_gpio_reg.im1_reg,
216 &chip->reg->regs[chip->ch].im_1);
218 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
219 &chip->reg->ioh_sel_reg[i]);
224 static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
226 struct ioh_gpio *chip = gpiochip_get_data(gpio);
227 return chip->irq_base + offset;
230 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
232 struct gpio_chip *gpio = &chip->gpio;
234 gpio->label = dev_name(chip->dev);
235 gpio->owner = THIS_MODULE;
236 gpio->direction_input = ioh_gpio_direction_input;
237 gpio->get = ioh_gpio_get;
238 gpio->direction_output = ioh_gpio_direction_output;
239 gpio->set = ioh_gpio_set;
240 gpio->dbg_show = NULL;
242 gpio->ngpio = num_port;
243 gpio->can_sleep = false;
244 gpio->to_irq = ioh_gpio_to_irq;
247 static int ioh_irq_type(struct irq_data *d, unsigned int type)
250 void __iomem *im_reg;
257 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
258 struct ioh_gpio *chip = gc->private;
260 ch = irq - chip->irq_base;
261 if (irq <= chip->irq_base + 7) {
262 im_reg = &chip->reg->regs[chip->ch].im_0;
265 im_reg = &chip->reg->regs[chip->ch].im_1;
268 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
269 __func__, irq, type, ch, im_pos, type);
271 spin_lock_irqsave(&chip->spinlock, flags);
274 case IRQ_TYPE_EDGE_RISING:
275 val = IOH_EDGE_RISING;
277 case IRQ_TYPE_EDGE_FALLING:
278 val = IOH_EDGE_FALLING;
280 case IRQ_TYPE_EDGE_BOTH:
283 case IRQ_TYPE_LEVEL_HIGH:
286 case IRQ_TYPE_LEVEL_LOW:
292 dev_warn(chip->dev, "%s: unknown type(%dd)",
297 /* Set interrupt mode */
298 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
299 iowrite32(im | (val << (im_pos * 4)), im_reg);
302 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
305 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
307 /* Enable interrupt */
308 ien = ioread32(&chip->reg->regs[chip->ch].ien);
309 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
311 spin_unlock_irqrestore(&chip->spinlock, flags);
316 static void ioh_irq_unmask(struct irq_data *d)
318 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
319 struct ioh_gpio *chip = gc->private;
321 iowrite32(1 << (d->irq - chip->irq_base),
322 &chip->reg->regs[chip->ch].imaskclr);
325 static void ioh_irq_mask(struct irq_data *d)
327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328 struct ioh_gpio *chip = gc->private;
330 iowrite32(1 << (d->irq - chip->irq_base),
331 &chip->reg->regs[chip->ch].imask);
334 static void ioh_irq_disable(struct irq_data *d)
336 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
337 struct ioh_gpio *chip = gc->private;
341 spin_lock_irqsave(&chip->spinlock, flags);
342 ien = ioread32(&chip->reg->regs[chip->ch].ien);
343 ien &= ~(1 << (d->irq - chip->irq_base));
344 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
345 spin_unlock_irqrestore(&chip->spinlock, flags);
348 static void ioh_irq_enable(struct irq_data *d)
350 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
351 struct ioh_gpio *chip = gc->private;
355 spin_lock_irqsave(&chip->spinlock, flags);
356 ien = ioread32(&chip->reg->regs[chip->ch].ien);
357 ien |= 1 << (d->irq - chip->irq_base);
358 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
359 spin_unlock_irqrestore(&chip->spinlock, flags);
362 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
364 struct ioh_gpio *chip = dev_id;
369 for (i = 0; i < 8; i++, chip++) {
370 reg_val = ioread32(&chip->reg->regs[i].istatus);
371 for (j = 0; j < num_ports[i]; j++) {
372 if (reg_val & BIT(j)) {
374 "%s:[%d]:irq=%d status=0x%x\n",
375 __func__, j, irq, reg_val);
377 &chip->reg->regs[chip->ch].iclr);
378 generic_handle_irq(chip->irq_base + j);
386 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
387 unsigned int irq_start,
390 struct irq_chip_generic *gc;
391 struct irq_chip_type *ct;
394 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
395 chip->base, handle_simple_irq);
402 ct->chip.irq_mask = ioh_irq_mask;
403 ct->chip.irq_unmask = ioh_irq_unmask;
404 ct->chip.irq_set_type = ioh_irq_type;
405 ct->chip.irq_disable = ioh_irq_disable;
406 ct->chip.irq_enable = ioh_irq_enable;
408 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
409 IRQ_GC_INIT_MASK_CACHE,
410 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
415 static int ioh_gpio_probe(struct pci_dev *pdev,
416 const struct pci_device_id *id)
420 struct ioh_gpio *chip;
425 ret = pci_enable_device(pdev);
427 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
431 ret = pci_request_regions(pdev, KBUILD_MODNAME);
433 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
434 goto err_request_regions;
437 base = pci_iomap(pdev, 1, 0);
439 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
444 chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL);
445 if (chip_save == NULL) {
451 for (i = 0; i < 8; i++, chip++) {
452 chip->dev = &pdev->dev;
454 chip->reg = chip->base;
456 spin_lock_init(&chip->spinlock);
457 ioh_gpio_setup(chip, num_ports[i]);
458 ret = gpiochip_add_data(&chip->gpio, chip);
460 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
461 goto err_gpiochip_add;
466 for (j = 0; j < 8; j++, chip++) {
467 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
468 num_ports[j], NUMA_NO_NODE);
471 "ml_ioh_gpio: Failed to get IRQ base num\n");
473 goto err_gpiochip_add;
475 chip->irq_base = irq_base;
477 ret = ioh_gpio_alloc_generic_chip(chip,
478 irq_base, num_ports[j]);
480 goto err_gpiochip_add;
484 ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
485 IRQF_SHARED, KBUILD_MODNAME, chip);
488 "%s request_irq failed\n", __func__);
489 goto err_gpiochip_add;
492 pci_set_drvdata(pdev, chip);
499 gpiochip_remove(&chip->gpio);
505 pci_iounmap(pdev, base);
508 pci_release_regions(pdev);
511 pci_disable_device(pdev);
515 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
519 static void ioh_gpio_remove(struct pci_dev *pdev)
522 struct ioh_gpio *chip = pci_get_drvdata(pdev);
527 for (i = 0; i < 8; i++, chip++)
528 gpiochip_remove(&chip->gpio);
531 pci_iounmap(pdev, chip->base);
532 pci_release_regions(pdev);
533 pci_disable_device(pdev);
538 static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
541 struct ioh_gpio *chip = pci_get_drvdata(pdev);
544 spin_lock_irqsave(&chip->spinlock, flags);
545 ioh_gpio_save_reg_conf(chip);
546 spin_unlock_irqrestore(&chip->spinlock, flags);
548 ret = pci_save_state(pdev);
550 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
553 pci_disable_device(pdev);
554 pci_set_power_state(pdev, PCI_D0);
555 ret = pci_enable_wake(pdev, PCI_D0, 1);
557 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
562 static int ioh_gpio_resume(struct pci_dev *pdev)
565 struct ioh_gpio *chip = pci_get_drvdata(pdev);
568 ret = pci_enable_wake(pdev, PCI_D0, 0);
570 pci_set_power_state(pdev, PCI_D0);
571 ret = pci_enable_device(pdev);
573 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
576 pci_restore_state(pdev);
578 spin_lock_irqsave(&chip->spinlock, flags);
579 iowrite32(0x01, &chip->reg->srst);
580 iowrite32(0x00, &chip->reg->srst);
581 ioh_gpio_restore_reg_conf(chip);
582 spin_unlock_irqrestore(&chip->spinlock, flags);
587 #define ioh_gpio_suspend NULL
588 #define ioh_gpio_resume NULL
591 static const struct pci_device_id ioh_gpio_pcidev_id[] = {
592 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
595 MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
597 static struct pci_driver ioh_gpio_driver = {
598 .name = "ml_ioh_gpio",
599 .id_table = ioh_gpio_pcidev_id,
600 .probe = ioh_gpio_probe,
601 .remove = ioh_gpio_remove,
602 .suspend = ioh_gpio_suspend,
603 .resume = ioh_gpio_resume
606 module_pci_driver(ioh_gpio_driver);
608 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
609 MODULE_LICENSE("GPL");