drivers/firmware/qcom_scm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2015 Linaro Ltd.
   4  */
   5 #include <linux/platform_device.h>
   6 #include <linux/init.h>
   7 #include <linux/cpumask.h>
   8 #include <linux/export.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/qcom_scm.h>
  13 #include <linux/of.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/clk.h>
  17 #include <linux/reset-controller.h>
  18 #include <linux/arm-smccc.h>
  19
  20 #include "qcom_scm.h"
  21
  22 static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
  23 module_param(download_mode, bool, 0);
  24
  25 #define SCM_HAS_CORE_CLK        BIT(0)
  26 #define SCM_HAS_IFACE_CLK       BIT(1)
  27 #define SCM_HAS_BUS_CLK         BIT(2)
  28
  29 struct qcom_scm {
  30         struct device *dev;
  31         struct clk *core_clk;
  32         struct clk *iface_clk;
  33         struct clk *bus_clk;
  34         struct reset_controller_dev reset;
  35
  36         u64 dload_mode_addr;
  37 };
  38
  39 struct qcom_scm_current_perm_info {
  40         __le32 vmid;
  41         __le32 perm;
  42         __le64 ctx;
  43         __le32 ctx_size;
  44         __le32 unused;
  45 };
  46
  47 struct qcom_scm_mem_map_info {
  48         __le64 mem_addr;
  49         __le64 mem_size;
  50 };
  51
  52 #define QCOM_SCM_FLAG_COLDBOOT_CPU0     0x00
  53 #define QCOM_SCM_FLAG_COLDBOOT_CPU1     0x01
  54 #define QCOM_SCM_FLAG_COLDBOOT_CPU2     0x08
  55 #define QCOM_SCM_FLAG_COLDBOOT_CPU3     0x20
  56
  57 #define QCOM_SCM_FLAG_WARMBOOT_CPU0     0x04
  58 #define QCOM_SCM_FLAG_WARMBOOT_CPU1     0x02
  59 #define QCOM_SCM_FLAG_WARMBOOT_CPU2     0x10
  60 #define QCOM_SCM_FLAG_WARMBOOT_CPU3     0x40
  61
  62 struct qcom_scm_wb_entry {
  63         int flag;
  64         void *entry;
  65 };
  66
  67 static struct qcom_scm_wb_entry qcom_scm_wb[] = {
  68         { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
  69         { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
  70         { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
  71         { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
  72 };
  73
  74 static const char *qcom_scm_convention_names[] = {
  75         [SMC_CONVENTION_UNKNOWN] = "unknown",
  76         [SMC_CONVENTION_ARM_32] = "smc arm 32",
  77         [SMC_CONVENTION_ARM_64] = "smc arm 64",
  78         [SMC_CONVENTION_LEGACY] = "smc legacy",
  79 };
  80
  81 static struct qcom_scm *__scm;
  82
  83 static int qcom_scm_clk_enable(void)
  84 {
  85         int ret;
  86
  87         ret = clk_prepare_enable(__scm->core_clk);
  88         if (ret)
  89                 goto bail;
  90
  91         ret = clk_prepare_enable(__scm->iface_clk);
  92         if (ret)
  93                 goto disable_core;
  94
  95         ret = clk_prepare_enable(__scm->bus_clk);
  96         if (ret)
  97                 goto disable_iface;
  98
  99         return 0;
 100
 101 disable_iface:
 102         clk_disable_unprepare(__scm->iface_clk);
 103 disable_core:
 104         clk_disable_unprepare(__scm->core_clk);
 105 bail:
 106         return ret;
 107 }
 108
 109 static void qcom_scm_clk_disable(void)
 110 {
 111         clk_disable_unprepare(__scm->core_clk);
 112         clk_disable_unprepare(__scm->iface_clk);
 113         clk_disable_unprepare(__scm->bus_clk);
 114 }
 115
 116 static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
 117                                         u32 cmd_id);
 118
 119 enum qcom_scm_convention qcom_scm_convention;
 120 static bool has_queried __read_mostly;
 121 static DEFINE_SPINLOCK(query_lock);
 122
 123 static void __query_convention(void)
 124 {
 125         unsigned long flags;
 126         struct qcom_scm_desc desc = {
 127                 .svc = QCOM_SCM_SVC_INFO,
 128                 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
 129                 .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
 130                                            QCOM_SCM_INFO_IS_CALL_AVAIL) |
 131                            (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
 132                 .arginfo = QCOM_SCM_ARGS(1),
 133                 .owner = ARM_SMCCC_OWNER_SIP,
 134         };
 135         struct qcom_scm_res res;
 136         int ret;
 137
 138         spin_lock_irqsave(&query_lock, flags);
 139         if (has_queried)
 140                 goto out;
 141
 142         qcom_scm_convention = SMC_CONVENTION_ARM_64;
 143         // Device isn't required as there is only one argument - no device
 144         // needed to dma_map_single to secure world
 145         ret = scm_smc_call(NULL, &desc, &res, true);
 146         if (!ret && res.result[0] == 1)
 147                 goto out;
 148
 149         qcom_scm_convention = SMC_CONVENTION_ARM_32;
 150         ret = scm_smc_call(NULL, &desc, &res, true);
 151         if (!ret && res.result[0] == 1)
 152                 goto out;
 153
 154         qcom_scm_convention = SMC_CONVENTION_LEGACY;
 155 out:
 156         has_queried = true;
 157         spin_unlock_irqrestore(&query_lock, flags);
 158         pr_info("qcom_scm: convention: %s\n",
 159                 qcom_scm_convention_names[qcom_scm_convention]);
 160 }
 161
 162 static inline enum qcom_scm_convention __get_convention(void)
 163 {
 164         if (unlikely(!has_queried))
 165                 __query_convention();
 166         return qcom_scm_convention;
 167 }
 168
 169 /**
 170  * qcom_scm_call() - Invoke a syscall in the secure world
 171  * @dev:        device
 172  * @svc_id:     service identifier
 173  * @cmd_id:     command identifier
 174  * @desc:       Descriptor structure containing arguments and return values
 175  *
 176  * Sends a command to the SCM and waits for the command to finish processing.
 177  * This should *only* be called in pre-emptible context.
 178  */
 179 static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
 180                          struct qcom_scm_res *res)
 181 {
 182         might_sleep();
 183         switch (__get_convention()) {
 184         case SMC_CONVENTION_ARM_32:
 185         case SMC_CONVENTION_ARM_64:
 186                 return scm_smc_call(dev, desc, res, false);
 187         case SMC_CONVENTION_LEGACY:
 188                 return scm_legacy_call(dev, desc, res);
 189         default:
 190                 pr_err("Unknown current SCM calling convention.\n");
 191                 return -EINVAL;
 192         }
 193 }
 194
 195 /**
 196  * qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
 197  * @dev:        device
 198  * @svc_id:     service identifier
 199  * @cmd_id:     command identifier
 200  * @desc:       Descriptor structure containing arguments and return values
 201  * @res:        Structure containing results from SMC/HVC call
 202  *
 203  * Sends a command to the SCM and waits for the command to finish processing.
 204  * This can be called in atomic context.
 205  */
 206 static int qcom_scm_call_atomic(struct device *dev,
 207                                 const struct qcom_scm_desc *desc,
 208                                 struct qcom_scm_res *res)
 209 {
 210         switch (__get_convention()) {
 211         case SMC_CONVENTION_ARM_32:
 212         case SMC_CONVENTION_ARM_64:
 213                 return scm_smc_call(dev, desc, res, true);
 214         case SMC_CONVENTION_LEGACY:
 215                 return scm_legacy_call_atomic(dev, desc, res);
 216         default:
 217                 pr_err("Unknown current SCM calling convention.\n");
 218                 return -EINVAL;
 219         }
 220 }
 221
 222 static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
 223                                         u32 cmd_id)
 224 {
 225         int ret;
 226         struct qcom_scm_desc desc = {
 227                 .svc = QCOM_SCM_SVC_INFO,
 228                 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
 229                 .owner = ARM_SMCCC_OWNER_SIP,
 230         };
 231         struct qcom_scm_res res;
 232
 233         desc.arginfo = QCOM_SCM_ARGS(1);
 234         switch (__get_convention()) {
 235         case SMC_CONVENTION_ARM_32:
 236         case SMC_CONVENTION_ARM_64:
 237                 desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
 238                                 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
 239                 break;
 240         case SMC_CONVENTION_LEGACY:
 241                 desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id);
 242                 break;
 243         default:
 244                 pr_err("Unknown SMC convention being used\n");
 245                 return -EINVAL;
 246         }
 247
 248         ret = qcom_scm_call(dev, &desc, &res);
 249
 250         return ret ? : res.result[0];
 251 }
 252
 253 /**
 254  * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
 255  * @entry: Entry point function for the cpus
 256  * @cpus: The cpumask of cpus that will use the entry point
 257  *
 258  * Set the Linux entry point for the SCM to transfer control to when coming
 259  * out of a power down. CPU power down may be executed on cpuidle or hotplug.
 260  */
 261 int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
 262 {
 263         int ret;
 264         int flags = 0;
 265         int cpu;
 266         struct qcom_scm_desc desc = {
 267                 .svc = QCOM_SCM_SVC_BOOT,
 268                 .cmd = QCOM_SCM_BOOT_SET_ADDR,
 269                 .arginfo = QCOM_SCM_ARGS(2),
 270         };
 271
 272         /*
 273          * Reassign only if we are switching from hotplug entry point
 274          * to cpuidle entry point or vice versa.
 275          */
 276         for_each_cpu(cpu, cpus) {
 277                 if (entry == qcom_scm_wb[cpu].entry)
 278                         continue;
 279                 flags |= qcom_scm_wb[cpu].flag;
 280         }
 281
 282         /* No change in entry function */
 283         if (!flags)
 284                 return 0;
 285
 286         desc.args[0] = flags;
 287         desc.args[1] = virt_to_phys(entry);
 288
 289         ret = qcom_scm_call(__scm->dev, &desc, NULL);
 290         if (!ret) {
 291                 for_each_cpu(cpu, cpus)
 292                         qcom_scm_wb[cpu].entry = entry;
 293         }
 294
 295         return ret;
 296 }
 297 EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
 298
 299 /**
 300  * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
 301  * @entry: Entry point function for the cpus
 302  * @cpus: The cpumask of cpus that will use the entry point
 303  *
 304  * Set the cold boot address of the cpus. Any cpu outside the supported
 305  * range would be removed from the cpu present mask.
 306  */
 307 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
 308 {
 309         int flags = 0;
 310         int cpu;
 311         int scm_cb_flags[] = {
 312                 QCOM_SCM_FLAG_COLDBOOT_CPU0,
 313                 QCOM_SCM_FLAG_COLDBOOT_CPU1,
 314                 QCOM_SCM_FLAG_COLDBOOT_CPU2,
 315                 QCOM_SCM_FLAG_COLDBOOT_CPU3,
 316         };
 317         struct qcom_scm_desc desc = {
 318                 .svc = QCOM_SCM_SVC_BOOT,
 319                 .cmd = QCOM_SCM_BOOT_SET_ADDR,
 320                 .arginfo = QCOM_SCM_ARGS(2),
 321                 .owner = ARM_SMCCC_OWNER_SIP,
 322         };
 323
 324         if (!cpus || (cpus && cpumask_empty(cpus)))
 325                 return -EINVAL;
 326
 327         for_each_cpu(cpu, cpus) {
 328                 if (cpu < ARRAY_SIZE(scm_cb_flags))
 329                         flags |= scm_cb_flags[cpu];
 330                 else
 331                         set_cpu_present(cpu, false);
 332         }
 333
 334         desc.args[0] = flags;
 335         desc.args[1] = virt_to_phys(entry);
 336
 337         return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
 338 }
 339 EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
 340
 341 /**
 342  * qcom_scm_cpu_power_down() - Power down the cpu
 343  * @flags - Flags to flush cache
 344  *
 345  * This is an end point to power down cpu. If there was a pending interrupt,
 346  * the control would return from this function, otherwise, the cpu jumps to the
 347  * warm boot entry point set for this cpu upon reset.
 348  */
 349 void qcom_scm_cpu_power_down(u32 flags)
 350 {
 351         struct qcom_scm_desc desc = {
 352                 .svc = QCOM_SCM_SVC_BOOT,
 353                 .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
 354                 .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
 355                 .arginfo = QCOM_SCM_ARGS(1),
 356                 .owner = ARM_SMCCC_OWNER_SIP,
 357         };
 358
 359         qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
 360 }
 361 EXPORT_SYMBOL(qcom_scm_cpu_power_down);
 362
 363 int qcom_scm_set_remote_state(u32 state, u32 id)
 364 {
 365         struct qcom_scm_desc desc = {
 366                 .svc = QCOM_SCM_SVC_BOOT,
 367                 .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
 368                 .arginfo = QCOM_SCM_ARGS(2),
 369                 .args[0] = state,
 370                 .args[1] = id,
 371                 .owner = ARM_SMCCC_OWNER_SIP,
 372         };
 373         struct qcom_scm_res res;
 374         int ret;
 375
 376         ret = qcom_scm_call(__scm->dev, &desc, &res);
 377
 378         return ret ? : res.result[0];
 379 }
 380 EXPORT_SYMBOL(qcom_scm_set_remote_state);
 381
 382 static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
 383 {
 384         struct qcom_scm_desc desc = {
 385                 .svc = QCOM_SCM_SVC_BOOT,
 386                 .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
 387                 .arginfo = QCOM_SCM_ARGS(2),
 388                 .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE,
 389                 .owner = ARM_SMCCC_OWNER_SIP,
 390         };
 391
 392         desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
 393
 394         return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
 395 }
 396
 397 static void qcom_scm_set_download_mode(bool enable)
 398 {
 399         bool avail;
 400         int ret = 0;
 401
 402         avail = __qcom_scm_is_call_available(__scm->dev,
 403                                              QCOM_SCM_SVC_BOOT,
 404                                              QCOM_SCM_BOOT_SET_DLOAD_MODE);
 405         if (avail) {
 406                 ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
 407         } else if (__scm->dload_mode_addr) {
 408                 ret = qcom_scm_io_writel(__scm->dload_mode_addr,
 409                                 enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
 410         } else {
 411                 dev_err(__scm->dev,
 412                         "No available mechanism for setting download mode\n");
 413         }
 414
 415         if (ret)
 416                 dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
 417 }
 418
 419 /**
 420  * qcom_scm_pas_init_image() - Initialize peripheral authentication service
 421  *                             state machine for a given peripheral, using the
 422  *                             metadata
 423  * @peripheral: peripheral id
 424  * @metadata:   pointer to memory containing ELF header, program header table
 425  *              and optional blob of data used for authenticating the metadata
 426  *              and the rest of the firmware
 427  * @size:       size of the metadata
 428  *
 429  * Returns 0 on success.
 430  */
 431 int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
 432 {
 433         dma_addr_t mdata_phys;
 434         void *mdata_buf;
 435         int ret;
 436         struct qcom_scm_desc desc = {
 437                 .svc = QCOM_SCM_SVC_PIL,
 438                 .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
 439                 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
 440                 .args[0] = peripheral,
 441                 .owner = ARM_SMCCC_OWNER_SIP,
 442         };
 443         struct qcom_scm_res res;
 444
 445         /*
 446          * During the scm call memory protection will be enabled for the meta
 447          * data blob, so make sure it's physically contiguous, 4K aligned and
 448          * non-cachable to avoid XPU violations.
 449          */
 450         mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
 451                                        GFP_KERNEL);
 452         if (!mdata_buf) {
 453                 dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
 454                 return -ENOMEM;
 455         }
 456         memcpy(mdata_buf, metadata, size);
 457
 458         ret = qcom_scm_clk_enable();
 459         if (ret)
 460                 goto free_metadata;
 461
 462         desc.args[1] = mdata_phys;
 463
 464         ret = qcom_scm_call(__scm->dev, &desc, &res);
 465
 466         qcom_scm_clk_disable();
 467
 468 free_metadata:
 469         dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
 470
 471         return ret ? : res.result[0];
 472 }
 473 EXPORT_SYMBOL(qcom_scm_pas_init_image);
 474
 475 /**
 476  * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
 477  *                            for firmware loading
 478  * @peripheral: peripheral id
 479  * @addr:       start address of memory area to prepare
 480  * @size:       size of the memory area to prepare
 481  *
 482  * Returns 0 on success.
 483  */
 484 int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
 485 {
 486         int ret;
 487         struct qcom_scm_desc desc = {
 488                 .svc = QCOM_SCM_SVC_PIL,
 489                 .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
 490                 .arginfo = QCOM_SCM_ARGS(3),
 491                 .args[0] = peripheral,
 492                 .args[1] = addr,
 493                 .args[2] = size,
 494                 .owner = ARM_SMCCC_OWNER_SIP,
 495         };
 496         struct qcom_scm_res res;
 497
 498         ret = qcom_scm_clk_enable();
 499         if (ret)
 500                 return ret;
 501
 502         ret = qcom_scm_call(__scm->dev, &desc, &res);
 503         qcom_scm_clk_disable();
 504
 505         return ret ? : res.result[0];
 506 }
 507 EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
 508
 509 /**
 510  * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
 511  *                                 and reset the remote processor
 512  * @peripheral: peripheral id
 513  *
 514  * Return 0 on success.
 515  */
 516 int qcom_scm_pas_auth_and_reset(u32 peripheral)
 517 {
 518         int ret;
 519         struct qcom_scm_desc desc = {
 520                 .svc = QCOM_SCM_SVC_PIL,
 521                 .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
 522                 .arginfo = QCOM_SCM_ARGS(1),
 523                 .args[0] = peripheral,
 524                 .owner = ARM_SMCCC_OWNER_SIP,
 525         };
 526         struct qcom_scm_res res;
 527
 528         ret = qcom_scm_clk_enable();
 529         if (ret)
 530                 return ret;
 531
 532         ret = qcom_scm_call(__scm->dev, &desc, &res);
 533         qcom_scm_clk_disable();
 534
 535         return ret ? : res.result[0];
 536 }
 537 EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
 538
 539 /**
 540  * qcom_scm_pas_shutdown() - Shut down the remote processor
 541  * @peripheral: peripheral id
 542  *
 543  * Returns 0 on success.
 544  */
 545 int qcom_scm_pas_shutdown(u32 peripheral)
 546 {
 547         int ret;
 548         struct qcom_scm_desc desc = {
 549                 .svc = QCOM_SCM_SVC_PIL,
 550                 .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
 551                 .arginfo = QCOM_SCM_ARGS(1),
 552                 .args[0] = peripheral,
 553                 .owner = ARM_SMCCC_OWNER_SIP,
 554         };
 555         struct qcom_scm_res res;
 556
 557         ret = qcom_scm_clk_enable();
 558         if (ret)
 559                 return ret;
 560
 561         ret = qcom_scm_call(__scm->dev, &desc, &res);
 562
 563         qcom_scm_clk_disable();
 564
 565         return ret ? : res.result[0];
 566 }
 567 EXPORT_SYMBOL(qcom_scm_pas_shutdown);
 568
 569 /**
 570  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
 571  *                            available for the given peripherial
 572  * @peripheral: peripheral id
 573  *
 574  * Returns true if PAS is supported for this peripheral, otherwise false.
 575  */
 576 bool qcom_scm_pas_supported(u32 peripheral)
 577 {
 578         int ret;
 579         struct qcom_scm_desc desc = {
 580                 .svc = QCOM_SCM_SVC_PIL,
 581                 .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
 582                 .arginfo = QCOM_SCM_ARGS(1),
 583                 .args[0] = peripheral,
 584                 .owner = ARM_SMCCC_OWNER_SIP,
 585         };
 586         struct qcom_scm_res res;
 587
 588         ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
 589                                            QCOM_SCM_PIL_PAS_IS_SUPPORTED);
 590         if (ret <= 0)
 591                 return false;
 592
 593         ret = qcom_scm_call(__scm->dev, &desc, &res);
 594
 595         return ret ? false : !!res.result[0];
 596 }
 597 EXPORT_SYMBOL(qcom_scm_pas_supported);
 598
 599 static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
 600 {
 601         struct qcom_scm_desc desc = {
 602                 .svc = QCOM_SCM_SVC_PIL,
 603                 .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
 604                 .arginfo = QCOM_SCM_ARGS(2),
 605                 .args[0] = reset,
 606                 .args[1] = 0,
 607                 .owner = ARM_SMCCC_OWNER_SIP,
 608         };
 609         struct qcom_scm_res res;
 610         int ret;
 611
 612         ret = qcom_scm_call(__scm->dev, &desc, &res);
 613
 614         return ret ? : res.result[0];
 615 }
 616
 617 static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
 618                                      unsigned long idx)
 619 {
 620         if (idx != 0)
 621                 return -EINVAL;
 622
 623         return __qcom_scm_pas_mss_reset(__scm->dev, 1);
 624 }
 625
 626 static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
 627                                        unsigned long idx)
 628 {
 629         if (idx != 0)
 630                 return -EINVAL;
 631
 632         return __qcom_scm_pas_mss_reset(__scm->dev, 0);
 633 }
 634
 635 static const struct reset_control_ops qcom_scm_pas_reset_ops = {
 636         .assert = qcom_scm_pas_reset_assert,
 637         .deassert = qcom_scm_pas_reset_deassert,
 638 };
 639
 640 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
 641 {
 642         struct qcom_scm_desc desc = {
 643                 .svc = QCOM_SCM_SVC_IO,
 644                 .cmd = QCOM_SCM_IO_READ,
 645                 .arginfo = QCOM_SCM_ARGS(1),
 646                 .args[0] = addr,
 647                 .owner = ARM_SMCCC_OWNER_SIP,
 648         };
 649         struct qcom_scm_res res;
 650         int ret;
 651
 652
 653         ret = qcom_scm_call_atomic(__scm->dev, &desc, &res);
 654         if (ret >= 0)
 655                 *val = res.result[0];
 656
 657         return ret < 0 ? ret : 0;
 658 }
 659 EXPORT_SYMBOL(qcom_scm_io_readl);
 660
 661 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
 662 {
 663         struct qcom_scm_desc desc = {
 664                 .svc = QCOM_SCM_SVC_IO,
 665                 .cmd = QCOM_SCM_IO_WRITE,
 666                 .arginfo = QCOM_SCM_ARGS(2),
 667                 .args[0] = addr,
 668                 .args[1] = val,
 669                 .owner = ARM_SMCCC_OWNER_SIP,
 670         };
 671
 672         return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
 673 }
 674 EXPORT_SYMBOL(qcom_scm_io_writel);
 675
 676 /**
 677  * qcom_scm_restore_sec_cfg_available() - Check if secure environment
 678  * supports restore security config interface.
 679  *
 680  * Return true if restore-cfg interface is supported, false if not.
 681  */
 682 bool qcom_scm_restore_sec_cfg_available(void)
 683 {
 684         return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
 685                                             QCOM_SCM_MP_RESTORE_SEC_CFG);
 686 }
 687 EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
 688
 689 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
 690 {
 691         struct qcom_scm_desc desc = {
 692                 .svc = QCOM_SCM_SVC_MP,
 693                 .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
 694                 .arginfo = QCOM_SCM_ARGS(2),
 695                 .args[0] = device_id,
 696                 .args[1] = spare,
 697                 .owner = ARM_SMCCC_OWNER_SIP,
 698         };
 699         struct qcom_scm_res res;
 700         int ret;
 701
 702         ret = qcom_scm_call(__scm->dev, &desc, &res);
 703
 704         return ret ? : res.result[0];
 705 }
 706 EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
 707
 708 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
 709 {
 710         struct qcom_scm_desc desc = {
 711                 .svc = QCOM_SCM_SVC_MP,
 712                 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
 713                 .arginfo = QCOM_SCM_ARGS(1),
 714                 .args[0] = spare,
 715                 .owner = ARM_SMCCC_OWNER_SIP,
 716         };
 717         struct qcom_scm_res res;
 718         int ret;
 719
 720         ret = qcom_scm_call(__scm->dev, &desc, &res);
 721
 722         if (size)
 723                 *size = res.result[0];
 724
 725         return ret ? : res.result[1];
 726 }
 727 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
 728
 729 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
 730 {
 731         struct qcom_scm_desc desc = {
 732                 .svc = QCOM_SCM_SVC_MP,
 733                 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
 734                 .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
 735                                          QCOM_SCM_VAL),
 736                 .args[0] = addr,
 737                 .args[1] = size,
 738                 .args[2] = spare,
 739                 .owner = ARM_SMCCC_OWNER_SIP,
 740         };
 741         int ret;
 742
 743         desc.args[0] = addr;
 744         desc.args[1] = size;
 745         desc.args[2] = spare;
 746         desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
 747                                      QCOM_SCM_VAL);
 748
 749         ret = qcom_scm_call(__scm->dev, &desc, NULL);
 750
 751         /* the pg table has been initialized already, ignore the error */
 752         if (ret == -EPERM)
 753                 ret = 0;
 754
 755         return ret;
 756 }
 757 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
 758
 759 int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
 760                                    u32 cp_nonpixel_start,
 761                                    u32 cp_nonpixel_size)
 762 {
 763         int ret;
 764         struct qcom_scm_desc desc = {
 765                 .svc = QCOM_SCM_SVC_MP,
 766                 .cmd = QCOM_SCM_MP_VIDEO_VAR,
 767                 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL,
 768                                          QCOM_SCM_VAL, QCOM_SCM_VAL),
 769                 .args[0] = cp_start,
 770                 .args[1] = cp_size,
 771                 .args[2] = cp_nonpixel_start,
 772                 .args[3] = cp_nonpixel_size,
 773                 .owner = ARM_SMCCC_OWNER_SIP,
 774         };
 775         struct qcom_scm_res res;
 776
 777         ret = qcom_scm_call(__scm->dev, &desc, &res);
 778
 779         return ret ? : res.result[0];
 780 }
 781 EXPORT_SYMBOL(qcom_scm_mem_protect_video_var);
 782
 783 static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
 784                                  size_t mem_sz, phys_addr_t src, size_t src_sz,
 785                                  phys_addr_t dest, size_t dest_sz)
 786 {
 787         int ret;
 788         struct qcom_scm_desc desc = {
 789                 .svc = QCOM_SCM_SVC_MP,
 790                 .cmd = QCOM_SCM_MP_ASSIGN,
 791                 .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
 792                                          QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
 793                                          QCOM_SCM_VAL, QCOM_SCM_VAL),
 794                 .args[0] = mem_region,
 795                 .args[1] = mem_sz,
 796                 .args[2] = src,
 797                 .args[3] = src_sz,
 798                 .args[4] = dest,
 799                 .args[5] = dest_sz,
 800                 .args[6] = 0,
 801                 .owner = ARM_SMCCC_OWNER_SIP,
 802         };
 803         struct qcom_scm_res res;
 804
 805         ret = qcom_scm_call(dev, &desc, &res);
 806
 807         return ret ? : res.result[0];
 808 }
 809
 810 /**
 811  * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
 812  * @mem_addr: mem region whose ownership need to be reassigned
 813  * @mem_sz:   size of the region.
 814  * @srcvm:    vmid for current set of owners, each set bit in
 815  *            flag indicate a unique owner
 816  * @newvm:    array having new owners and corresponding permission
 817  *            flags
 818  * @dest_cnt: number of owners in next set.
 819  *
 820  * Return negative errno on failure or 0 on success with @srcvm updated.
 821  */
 822 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
 823                         unsigned int *srcvm,
 824                         const struct qcom_scm_vmperm *newvm,
 825                         unsigned int dest_cnt)
 826 {
 827         struct qcom_scm_current_perm_info *destvm;
 828         struct qcom_scm_mem_map_info *mem_to_map;
 829         phys_addr_t mem_to_map_phys;
 830         phys_addr_t dest_phys;
 831         dma_addr_t ptr_phys;
 832         size_t mem_to_map_sz;
 833         size_t dest_sz;
 834         size_t src_sz;
 835         size_t ptr_sz;
 836         int next_vm;
 837         __le32 *src;
 838         void *ptr;
 839         int ret, i, b;
 840         unsigned long srcvm_bits = *srcvm;
 841
 842         src_sz = hweight_long(srcvm_bits) * sizeof(*src);
 843         mem_to_map_sz = sizeof(*mem_to_map);
 844         dest_sz = dest_cnt * sizeof(*destvm);
 845         ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
 846                         ALIGN(dest_sz, SZ_64);
 847
 848         ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
 849         if (!ptr)
 850                 return -ENOMEM;
 851
 852         /* Fill source vmid detail */
 853         src = ptr;
 854         i = 0;
 855         for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG)
 856                 src[i++] = cpu_to_le32(b);
 857
 858         /* Fill details of mem buff to map */
 859         mem_to_map = ptr + ALIGN(src_sz, SZ_64);
 860         mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
 861         mem_to_map->mem_addr = cpu_to_le64(mem_addr);
 862         mem_to_map->mem_size = cpu_to_le64(mem_sz);
 863
 864         next_vm = 0;
 865         /* Fill details of next vmid detail */
 866         destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
 867         dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
 868         for (i = 0; i < dest_cnt; i++, destvm++, newvm++) {
 869                 destvm->vmid = cpu_to_le32(newvm->vmid);
 870                 destvm->perm = cpu_to_le32(newvm->perm);
 871                 destvm->ctx = 0;
 872                 destvm->ctx_size = 0;
 873                 next_vm |= BIT(newvm->vmid);
 874         }
 875
 876         ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
 877                                     ptr_phys, src_sz, dest_phys, dest_sz);
 878         dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys);
 879         if (ret) {
 880                 dev_err(__scm->dev,
 881                         "Assign memory protection call failed %d\n", ret);
 882                 return -EINVAL;
 883         }
 884
 885         *srcvm = next_vm;
 886         return 0;
 887 }
 888 EXPORT_SYMBOL(qcom_scm_assign_mem);
 889
 890 /**
 891  * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
 892  */
 893 bool qcom_scm_ocmem_lock_available(void)
 894 {
 895         return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
 896                                             QCOM_SCM_OCMEM_LOCK_CMD);
 897 }
 898 EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
 899
 900 /**
 901  * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
 902  * region to the specified initiator
 903  *
 904  * @id:     tz initiator id
 905  * @offset: OCMEM offset
 906  * @size:   OCMEM size
 907  * @mode:   access mode (WIDE/NARROW)
 908  */
 909 int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
 910                         u32 mode)
 911 {
 912         struct qcom_scm_desc desc = {
 913                 .svc = QCOM_SCM_SVC_OCMEM,
 914                 .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
 915                 .args[0] = id,
 916                 .args[1] = offset,
 917                 .args[2] = size,
 918                 .args[3] = mode,
 919                 .arginfo = QCOM_SCM_ARGS(4),
 920         };
 921
 922         return qcom_scm_call(__scm->dev, &desc, NULL);
 923 }
 924 EXPORT_SYMBOL(qcom_scm_ocmem_lock);
 925
 926 /**
 927  * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
 928  * region from the specified initiator
 929  *
 930  * @id:     tz initiator id
 931  * @offset: OCMEM offset
 932  * @size:   OCMEM size
 933  */
 934 int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
 935 {
 936         struct qcom_scm_desc desc = {
 937                 .svc = QCOM_SCM_SVC_OCMEM,
 938                 .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
 939                 .args[0] = id,
 940                 .args[1] = offset,
 941                 .args[2] = size,
 942                 .arginfo = QCOM_SCM_ARGS(3),
 943         };
 944
 945         return qcom_scm_call(__scm->dev, &desc, NULL);
 946 }
 947 EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
 948
 949 /**
 950  * qcom_scm_ice_available() - Is the ICE key programming interface available?
 951  *
 952  * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and
 953  *         qcom_scm_ice_set_key() are available.
 954  */
 955 bool qcom_scm_ice_available(void)
 956 {
 957         return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
 958                                             QCOM_SCM_ES_INVALIDATE_ICE_KEY) &&
 959                 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
 960                                              QCOM_SCM_ES_CONFIG_SET_ICE_KEY);
 961 }
 962 EXPORT_SYMBOL(qcom_scm_ice_available);
 963
 964 /**
 965  * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
 966  * @index: the keyslot to invalidate
 967  *
 968  * The UFSHCI standard defines a standard way to do this, but it doesn't work on
 969  * these SoCs; only this SCM call does.
 970  *
 971  * Return: 0 on success; -errno on failure.
 972  */
 973 int qcom_scm_ice_invalidate_key(u32 index)
 974 {
 975         struct qcom_scm_desc desc = {
 976                 .svc = QCOM_SCM_SVC_ES,
 977                 .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY,
 978                 .arginfo = QCOM_SCM_ARGS(1),
 979                 .args[0] = index,
 980                 .owner = ARM_SMCCC_OWNER_SIP,
 981         };
 982
 983         return qcom_scm_call(__scm->dev, &desc, NULL);
 984 }
 985 EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);
 986
 987 /**
 988  * qcom_scm_ice_set_key() - Set an inline encryption key
 989  * @index: the keyslot into which to set the key
 990  * @key: the key to program
 991  * @key_size: the size of the key in bytes
 992  * @cipher: the encryption algorithm the key is for
 993  * @data_unit_size: the encryption data unit size, i.e. the size of each
 994  *                  individual plaintext and ciphertext.  Given in 512-byte
 995  *                  units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc.
 996  *
 997  * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it
 998  * can then be used to encrypt/decrypt UFS I/O requests inline.
 999  *
1000  * The UFSHCI standard defines a standard way to do this, but it doesn't work on
1001  * these SoCs; only this SCM call does.
1002  *
1003  * Return: 0 on success; -errno on failure.
1004  */
1005 int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
1006                          enum qcom_scm_ice_cipher cipher, u32 data_unit_size)
1007 {
1008         struct qcom_scm_desc desc = {
1009                 .svc = QCOM_SCM_SVC_ES,
1010                 .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY,
1011                 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW,
1012                                          QCOM_SCM_VAL, QCOM_SCM_VAL,
1013                                          QCOM_SCM_VAL),
1014                 .args[0] = index,
1015                 .args[2] = key_size,
1016                 .args[3] = cipher,
1017                 .args[4] = data_unit_size,
1018                 .owner = ARM_SMCCC_OWNER_SIP,
1019         };
1020         void *keybuf;
1021         dma_addr_t key_phys;
1022         int ret;
1023
1024         /*
1025          * 'key' may point to vmalloc()'ed memory, but we need to pass a
1026          * physical address that's been properly flushed.  The sanctioned way to
1027          * do this is by using the DMA API.  But as is best practice for crypto
1028          * keys, we also must wipe the key after use.  This makes kmemdup() +
1029          * dma_map_single() not clearly correct, since the DMA API can use
1030          * bounce buffers.  Instead, just use dma_alloc_coherent().  Programming
1031          * keys is normally rare and thus not performance-critical.
1032          */
1033
1034         keybuf = dma_alloc_coherent(__scm->dev, key_size, &key_phys,
1035                                     GFP_KERNEL);
1036         if (!keybuf)
1037                 return -ENOMEM;
1038         memcpy(keybuf, key, key_size);
1039         desc.args[1] = key_phys;
1040
1041         ret = qcom_scm_call(__scm->dev, &desc, NULL);
1042
1043         memzero_explicit(keybuf, key_size);
1044
1045         dma_free_coherent(__scm->dev, key_size, keybuf, key_phys);
1046         return ret;
1047 }
1048 EXPORT_SYMBOL(qcom_scm_ice_set_key);
1049
1050 /**
1051  * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
1052  *
1053  * Return true if HDCP is supported, false if not.
1054  */
1055 bool qcom_scm_hdcp_available(void)
1056 {
1057         int ret = qcom_scm_clk_enable();
1058
1059         if (ret)
1060                 return ret;
1061
1062         ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
1063                                                 QCOM_SCM_HDCP_INVOKE);
1064
1065         qcom_scm_clk_disable();
1066
1067         return ret > 0;
1068 }
1069 EXPORT_SYMBOL(qcom_scm_hdcp_available);
1070
1071 /**
1072  * qcom_scm_hdcp_req() - Send HDCP request.
1073  * @req: HDCP request array
1074  * @req_cnt: HDCP request array count
1075  * @resp: response buffer passed to SCM
1076  *
1077  * Write HDCP register(s) through SCM.
1078  */
1079 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
1080 {
1081         int ret;
1082         struct qcom_scm_desc desc = {
1083                 .svc = QCOM_SCM_SVC_HDCP,
1084                 .cmd = QCOM_SCM_HDCP_INVOKE,
1085                 .arginfo = QCOM_SCM_ARGS(10),
1086                 .args = {
1087                         req[0].addr,
1088                         req[0].val,
1089                         req[1].addr,
1090                         req[1].val,
1091                         req[2].addr,
1092                         req[2].val,
1093                         req[3].addr,
1094                         req[3].val,
1095                         req[4].addr,
1096                         req[4].val
1097                 },
1098                 .owner = ARM_SMCCC_OWNER_SIP,
1099         };
1100         struct qcom_scm_res res;
1101
1102         if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
1103                 return -ERANGE;
1104
1105         ret = qcom_scm_clk_enable();
1106         if (ret)
1107                 return ret;
1108
1109         ret = qcom_scm_call(__scm->dev, &desc, &res);
1110         *resp = res.result[0];
1111
1112         qcom_scm_clk_disable();
1113
1114         return ret;
1115 }
1116 EXPORT_SYMBOL(qcom_scm_hdcp_req);
1117
1118 int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
1119 {
1120         struct qcom_scm_desc desc = {
1121                 .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
1122                 .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
1123                 .arginfo = QCOM_SCM_ARGS(2),
1124                 .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL,
1125                 .args[1] = en,
1126                 .owner = ARM_SMCCC_OWNER_SIP,
1127         };
1128
1129
1130         return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
1131 }
1132 EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
1133
1134 static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
1135 {
1136         struct device_node *tcsr;
1137         struct device_node *np = dev->of_node;
1138         struct resource res;
1139         u32 offset;
1140         int ret;
1141
1142         tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
1143         if (!tcsr)
1144                 return 0;
1145
1146         ret = of_address_to_resource(tcsr, 0, &res);
1147         of_node_put(tcsr);
1148         if (ret)
1149                 return ret;
1150
1151         ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
1152         if (ret < 0)
1153                 return ret;
1154
1155         *addr = res.start + offset;
1156
1157         return 0;
1158 }
1159
1160 /**
1161  * qcom_scm_is_available() - Checks if SCM is available
1162  */
1163 bool qcom_scm_is_available(void)
1164 {
1165         return !!__scm;
1166 }
1167 EXPORT_SYMBOL(qcom_scm_is_available);
1168
1169 static int qcom_scm_probe(struct platform_device *pdev)
1170 {
1171         struct qcom_scm *scm;
1172         unsigned long clks;
1173         int ret;
1174
1175         scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
1176         if (!scm)
1177                 return -ENOMEM;
1178
1179         ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
1180         if (ret < 0)
1181                 return ret;
1182
1183         clks = (unsigned long)of_device_get_match_data(&pdev->dev);
1184
1185         scm->core_clk = devm_clk_get(&pdev->dev, "core");
1186         if (IS_ERR(scm->core_clk)) {
1187                 if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
1188                         return PTR_ERR(scm->core_clk);
1189
1190                 if (clks & SCM_HAS_CORE_CLK) {
1191                         dev_err(&pdev->dev, "failed to acquire core clk\n");
1192                         return PTR_ERR(scm->core_clk);
1193                 }
1194
1195                 scm->core_clk = NULL;
1196         }
1197
1198         scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
1199         if (IS_ERR(scm->iface_clk)) {
1200                 if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
1201                         return PTR_ERR(scm->iface_clk);
1202
1203                 if (clks & SCM_HAS_IFACE_CLK) {
1204                         dev_err(&pdev->dev, "failed to acquire iface clk\n");
1205                         return PTR_ERR(scm->iface_clk);
1206                 }
1207
1208                 scm->iface_clk = NULL;
1209         }
1210
1211         scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
1212         if (IS_ERR(scm->bus_clk)) {
1213                 if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
1214                         return PTR_ERR(scm->bus_clk);
1215
1216                 if (clks & SCM_HAS_BUS_CLK) {
1217                         dev_err(&pdev->dev, "failed to acquire bus clk\n");
1218                         return PTR_ERR(scm->bus_clk);
1219                 }
1220
1221                 scm->bus_clk = NULL;
1222         }
1223
1224         scm->reset.ops = &qcom_scm_pas_reset_ops;
1225         scm->reset.nr_resets = 1;
1226         scm->reset.of_node = pdev->dev.of_node;
1227         ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
1228         if (ret)
1229                 return ret;
1230
1231         /* vote for max clk rate for highest performance */
1232         ret = clk_set_rate(scm->core_clk, INT_MAX);
1233         if (ret)
1234                 return ret;
1235
1236         __scm = scm;
1237         __scm->dev = &pdev->dev;
1238
1239         __query_convention();
1240
1241         /*
1242          * If requested enable "download mode", from this point on warmboot
1243          * will cause the the boot stages to enter download mode, unless
1244          * disabled below by a clean shutdown/reboot.
1245          */
1246         if (download_mode)
1247                 qcom_scm_set_download_mode(true);
1248
1249         return 0;
1250 }
1251
1252 static void qcom_scm_shutdown(struct platform_device *pdev)
1253 {
1254         /* Clean shutdown, disable download mode to allow normal restart */
1255         if (download_mode)
1256                 qcom_scm_set_download_mode(false);
1257 }
1258
1259 static const struct of_device_id qcom_scm_dt_match[] = {
1260         { .compatible = "qcom,scm-apq8064",
1261           /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
1262         },
1263         { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
1264                                                              SCM_HAS_IFACE_CLK |
1265                                                              SCM_HAS_BUS_CLK)
1266         },
1267         { .compatible = "qcom,scm-ipq4019" },
1268         { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
1269         { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
1270         { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
1271                                                              SCM_HAS_IFACE_CLK |
1272                                                              SCM_HAS_BUS_CLK)
1273         },
1274         { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
1275                                                              SCM_HAS_IFACE_CLK |
1276                                                              SCM_HAS_BUS_CLK)
1277         },
1278         { .compatible = "qcom,scm-msm8994" },
1279         { .compatible = "qcom,scm-msm8996" },
1280         { .compatible = "qcom,scm" },
1281         {}
1282 };
1283
1284 static struct platform_driver qcom_scm_driver = {
1285         .driver = {
1286                 .name   = "qcom_scm",
1287                 .of_match_table = qcom_scm_dt_match,
1288         },
1289         .probe = qcom_scm_probe,
1290         .shutdown = qcom_scm_shutdown,
1291 };
1292
1293 static int __init qcom_scm_init(void)
1294 {
1295         return platform_driver_register(&qcom_scm_driver);
1296 }
1297 subsys_initcall(qcom_scm_init);