drivers/firmware/qcom_scm-smc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <linux/io.h>
   6 #include <linux/errno.h>
   7 #include <linux/delay.h>
   8 #include <linux/mutex.h>
   9 #include <linux/slab.h>
  10 #include <linux/types.h>
  11 #include <linux/qcom_scm.h>
  12 #include <linux/arm-smccc.h>
  13 #include <linux/dma-mapping.h>
  14
  15 #include "qcom_scm.h"
  16
  17 /**
  18  * struct arm_smccc_args
  19  * @args:       The array of values used in registers in smc instruction
  20  */
  21 struct arm_smccc_args {
  22         unsigned long args[8];
  23 };
  24
  25 static DEFINE_MUTEX(qcom_scm_lock);
  26
  27 #define QCOM_SCM_EBUSY_WAIT_MS 30
  28 #define QCOM_SCM_EBUSY_MAX_RETRY 20
  29
  30 #define SCM_SMC_N_REG_ARGS      4
  31 #define SCM_SMC_FIRST_EXT_IDX   (SCM_SMC_N_REG_ARGS - 1)
  32 #define SCM_SMC_N_EXT_ARGS      (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)
  33 #define SCM_SMC_FIRST_REG_IDX   2
  34 #define SCM_SMC_LAST_REG_IDX    (SCM_SMC_FIRST_REG_IDX + SCM_SMC_N_REG_ARGS - 1)
  35
  36 static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
  37                                struct arm_smccc_res *res)
  38 {
  39         unsigned long a0 = smc->args[0];
  40         struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
  41
  42         quirk.state.a6 = 0;
  43
  44         do {
  45                 arm_smccc_smc_quirk(a0, smc->args[1], smc->args[2],
  46                                     smc->args[3], smc->args[4], smc->args[5],
  47                                     quirk.state.a6, smc->args[7], res, &quirk);
  48
  49                 if (res->a0 == QCOM_SCM_INTERRUPTED)
  50                         a0 = res->a0;
  51
  52         } while (res->a0 == QCOM_SCM_INTERRUPTED);
  53 }
  54
  55 static void __scm_smc_do(const struct arm_smccc_args *smc,
  56                          struct arm_smccc_res *res, bool atomic)
  57 {
  58         int retry_count = 0;
  59
  60         if (atomic) {
  61                 __scm_smc_do_quirk(smc, res);
  62                 return;
  63         }
  64
  65         do {
  66                 mutex_lock(&qcom_scm_lock);
  67
  68                 __scm_smc_do_quirk(smc, res);
  69
  70                 mutex_unlock(&qcom_scm_lock);
  71
  72                 if (res->a0 == QCOM_SCM_V2_EBUSY) {
  73                         if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
  74                                 break;
  75                         msleep(QCOM_SCM_EBUSY_WAIT_MS);
  76                 }
  77         }  while (res->a0 == QCOM_SCM_V2_EBUSY);
  78 }
  79
  80 int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
  81                  struct qcom_scm_res *res, bool atomic)
  82 {
  83         int arglen = desc->arginfo & 0xf;
  84         int i;
  85         dma_addr_t args_phys = 0;
  86         void *args_virt = NULL;
  87         size_t alloc_len;
  88         gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
  89         u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
  90         u32 qcom_smccc_convention =
  91                         (qcom_scm_convention == SMC_CONVENTION_ARM_32) ?
  92                         ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
  93         struct arm_smccc_res smc_res;
  94         struct arm_smccc_args smc = {0};
  95
  96         smc.args[0] = ARM_SMCCC_CALL_VAL(
  97                 smccc_call_type,
  98                 qcom_smccc_convention,
  99                 desc->owner,
 100                 SCM_SMC_FNID(desc->svc, desc->cmd));
 101         smc.args[1] = desc->arginfo;
 102         for (i = 0; i < SCM_SMC_N_REG_ARGS; i++)
 103                 smc.args[i + SCM_SMC_FIRST_REG_IDX] = desc->args[i];
 104
 105         if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
 106                 alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
 107                 args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);
 108
 109                 if (!args_virt)
 110                         return -ENOMEM;
 111
 112                 if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
 113                         __le32 *args = args_virt;
 114
 115                         for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
 116                                 args[i] = cpu_to_le32(desc->args[i +
 117                                                       SCM_SMC_FIRST_EXT_IDX]);
 118                 } else {
 119                         __le64 *args = args_virt;
 120
 121                         for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
 122                                 args[i] = cpu_to_le64(desc->args[i +
 123                                                       SCM_SMC_FIRST_EXT_IDX]);
 124                 }
 125
 126                 args_phys = dma_map_single(dev, args_virt, alloc_len,
 127                                            DMA_TO_DEVICE);
 128
 129                 if (dma_mapping_error(dev, args_phys)) {
 130                         kfree(args_virt);
 131                         return -ENOMEM;
 132                 }
 133
 134                 smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
 135         }
 136
 137         __scm_smc_do(&smc, &smc_res, atomic);
 138
 139         if (args_virt) {
 140                 dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
 141                 kfree(args_virt);
 142         }
 143
 144         if (res) {
 145                 res->result[0] = smc_res.a1;
 146                 res->result[1] = smc_res.a2;
 147                 res->result[2] = smc_res.a3;
 148         }
 149
 150         return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
 151 }