drivers/dma/imx-sdma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // drivers/dma/imx-sdma.c
   4 //
   5 // This file contains a driver for the Freescale Smart DMA engine
   6 //
   7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8 //
   9 // Based on code from Freescale:
  10 //
  11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  12
  13 #include <linux/init.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mm.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firmware.h>
  28 #include <linux/slab.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_dma.h>
  35 #include <linux/workqueue.h>
  36
  37 #include <asm/irq.h>
  38 #include <linux/platform_data/dma-imx.h>
  39 #include <linux/regmap.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  42
  43 #include "dmaengine.h"
  44 #include "virt-dma.h"
  45
  46 /* SDMA registers */
  47 #define SDMA_H_C0PTR            0x000
  48 #define SDMA_H_INTR             0x004
  49 #define SDMA_H_STATSTOP         0x008
  50 #define SDMA_H_START            0x00c
  51 #define SDMA_H_EVTOVR           0x010
  52 #define SDMA_H_DSPOVR           0x014
  53 #define SDMA_H_HOSTOVR          0x018
  54 #define SDMA_H_EVTPEND          0x01c
  55 #define SDMA_H_DSPENBL          0x020
  56 #define SDMA_H_RESET            0x024
  57 #define SDMA_H_EVTERR           0x028
  58 #define SDMA_H_INTRMSK          0x02c
  59 #define SDMA_H_PSW              0x030
  60 #define SDMA_H_EVTERRDBG        0x034
  61 #define SDMA_H_CONFIG           0x038
  62 #define SDMA_ONCE_ENB           0x040
  63 #define SDMA_ONCE_DATA          0x044
  64 #define SDMA_ONCE_INSTR         0x048
  65 #define SDMA_ONCE_STAT          0x04c
  66 #define SDMA_ONCE_CMD           0x050
  67 #define SDMA_EVT_MIRROR         0x054
  68 #define SDMA_ILLINSTADDR        0x058
  69 #define SDMA_CHN0ADDR           0x05c
  70 #define SDMA_ONCE_RTB           0x060
  71 #define SDMA_XTRIG_CONF1        0x070
  72 #define SDMA_XTRIG_CONF2        0x074
  73 #define SDMA_CHNENBL0_IMX35     0x200
  74 #define SDMA_CHNENBL0_IMX31     0x080
  75 #define SDMA_CHNPRI_0           0x100
  76
  77 /*
  78  * Buffer descriptor status values.
  79  */
  80 #define BD_DONE  0x01
  81 #define BD_WRAP  0x02
  82 #define BD_CONT  0x04
  83 #define BD_INTR  0x08
  84 #define BD_RROR  0x10
  85 #define BD_LAST  0x20
  86 #define BD_EXTD  0x80
  87
  88 /*
  89  * Data Node descriptor status values.
  90  */
  91 #define DND_END_OF_FRAME  0x80
  92 #define DND_END_OF_XFER   0x40
  93 #define DND_DONE          0x20
  94 #define DND_UNUSED        0x01
  95
  96 /*
  97  * IPCV2 descriptor status values.
  98  */
  99 #define BD_IPCV2_END_OF_FRAME  0x40
 100
 101 #define IPCV2_MAX_NODES        50
 102 /*
 103  * Error bit set in the CCB status field by the SDMA,
 104  * in setbd routine, in case of a transfer error
 105  */
 106 #define DATA_ERROR  0x10000000
 107
 108 /*
 109  * Buffer descriptor commands.
 110  */
 111 #define C0_ADDR             0x01
 112 #define C0_LOAD             0x02
 113 #define C0_DUMP             0x03
 114 #define C0_SETCTX           0x07
 115 #define C0_GETCTX           0x03
 116 #define C0_SETDM            0x01
 117 #define C0_SETPM            0x04
 118 #define C0_GETDM            0x02
 119 #define C0_GETPM            0x08
 120 /*
 121  * Change endianness indicator in the BD command field
 122  */
 123 #define CHANGE_ENDIANNESS   0x80
 124
 125 /*
 126  *  p_2_p watermark_level description
 127  *      Bits            Name                    Description
 128  *      0-7             Lower WML               Lower watermark level
 129  *      8               PS                      1: Pad Swallowing
 130  *                                              0: No Pad Swallowing
 131  *      9               PA                      1: Pad Adding
 132  *                                              0: No Pad Adding
 133  *      10              SPDIF                   If this bit is set both source
 134  *                                              and destination are on SPBA
 135  *      11              Source Bit(SP)          1: Source on SPBA
 136  *                                              0: Source on AIPS
 137  *      12              Destination Bit(DP)     1: Destination on SPBA
 138  *                                              0: Destination on AIPS
 139  *      13-15           ---------               MUST BE 0
 140  *      16-23           Higher WML              HWML
 141  *      24-27           N                       Total number of samples after
 142  *                                              which Pad adding/Swallowing
 143  *                                              must be done. It must be odd.
 144  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 145  *                                              LWML event mask
 146  *                                              0: LWE in EVENTS register
 147  *                                              1: LWE in EVENTS2 register
 148  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 149  *                                              HWML event mask
 150  *                                              0: HWE in EVENTS register
 151  *                                              1: HWE in EVENTS2 register
 152  *      30              ---------               MUST BE 0
 153  *      31              CONT                    1: Amount of samples to be
 154  *                                              transferred is unknown and
 155  *                                              script will keep on
 156  *                                              transferring samples as long as
 157  *                                              both events are detected and
 158  *                                              script must be manually stopped
 159  *                                              by the application
 160  *                                              0: The amount of samples to be
 161  *                                              transferred is equal to the
 162  *                                              count field of mode word
 163  */
 164 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 165 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 166 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 167 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 168 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 169 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 170 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 171 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 172 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 173 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 174
 175 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 176                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 177                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 178
 179 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
 180                                  BIT(DMA_MEM_TO_DEV) | \
 181                                  BIT(DMA_DEV_TO_DEV))
 182
 183 /**
 184  * struct sdma_script_start_addrs - SDMA script start pointers
 185  *
 186  * start addresses of the different functions in the physical
 187  * address space of the SDMA engine.
 188  */
 189 struct sdma_script_start_addrs {
 190         s32 ap_2_ap_addr;
 191         s32 ap_2_bp_addr;
 192         s32 ap_2_ap_fixed_addr;
 193         s32 bp_2_ap_addr;
 194         s32 loopback_on_dsp_side_addr;
 195         s32 mcu_interrupt_only_addr;
 196         s32 firi_2_per_addr;
 197         s32 firi_2_mcu_addr;
 198         s32 per_2_firi_addr;
 199         s32 mcu_2_firi_addr;
 200         s32 uart_2_per_addr;
 201         s32 uart_2_mcu_addr;
 202         s32 per_2_app_addr;
 203         s32 mcu_2_app_addr;
 204         s32 per_2_per_addr;
 205         s32 uartsh_2_per_addr;
 206         s32 uartsh_2_mcu_addr;
 207         s32 per_2_shp_addr;
 208         s32 mcu_2_shp_addr;
 209         s32 ata_2_mcu_addr;
 210         s32 mcu_2_ata_addr;
 211         s32 app_2_per_addr;
 212         s32 app_2_mcu_addr;
 213         s32 shp_2_per_addr;
 214         s32 shp_2_mcu_addr;
 215         s32 mshc_2_mcu_addr;
 216         s32 mcu_2_mshc_addr;
 217         s32 spdif_2_mcu_addr;
 218         s32 mcu_2_spdif_addr;
 219         s32 asrc_2_mcu_addr;
 220         s32 ext_mem_2_ipu_addr;
 221         s32 descrambler_addr;
 222         s32 dptc_dvfs_addr;
 223         s32 utra_addr;
 224         s32 ram_code_start_addr;
 225         /* End of v1 array */
 226         s32 mcu_2_ssish_addr;
 227         s32 ssish_2_mcu_addr;
 228         s32 hdmi_dma_addr;
 229         /* End of v2 array */
 230         s32 zcanfd_2_mcu_addr;
 231         s32 zqspi_2_mcu_addr;
 232         s32 mcu_2_ecspi_addr;
 233         /* End of v3 array */
 234         s32 mcu_2_zqspi_addr;
 235         /* End of v4 array */
 236 };
 237
 238 /*
 239  * Mode/Count of data node descriptors - IPCv2
 240  */
 241 struct sdma_mode_count {
 242 #define SDMA_BD_MAX_CNT 0xffff
 243         u32 count   : 16; /* size of the buffer pointed by this BD */
 244         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 245         u32 command :  8; /* command mostly used for channel 0 */
 246 };
 247
 248 /*
 249  * Buffer descriptor
 250  */
 251 struct sdma_buffer_descriptor {
 252         struct sdma_mode_count  mode;
 253         u32 buffer_addr;        /* address of the buffer described */
 254         u32 ext_buffer_addr;    /* extended buffer address */
 255 } __attribute__ ((packed));
 256
 257 /**
 258  * struct sdma_channel_control - Channel control Block
 259  *
 260  * @current_bd_ptr:     current buffer descriptor processed
 261  * @base_bd_ptr:        first element of buffer descriptor array
 262  * @unused:             padding. The SDMA engine expects an array of 128 byte
 263  *                      control blocks
 264  */
 265 struct sdma_channel_control {
 266         u32 current_bd_ptr;
 267         u32 base_bd_ptr;
 268         u32 unused[2];
 269 } __attribute__ ((packed));
 270
 271 /**
 272  * struct sdma_state_registers - SDMA context for a channel
 273  *
 274  * @pc:         program counter
 275  * @unused1:    unused
 276  * @t:          test bit: status of arithmetic & test instruction
 277  * @rpc:        return program counter
 278  * @unused0:    unused
 279  * @sf:         source fault while loading data
 280  * @spc:        loop start program counter
 281  * @unused2:    unused
 282  * @df:         destination fault while storing data
 283  * @epc:        loop end program counter
 284  * @lm:         loop mode
 285  */
 286 struct sdma_state_registers {
 287         u32 pc     :14;
 288         u32 unused1: 1;
 289         u32 t      : 1;
 290         u32 rpc    :14;
 291         u32 unused0: 1;
 292         u32 sf     : 1;
 293         u32 spc    :14;
 294         u32 unused2: 1;
 295         u32 df     : 1;
 296         u32 epc    :14;
 297         u32 lm     : 2;
 298 } __attribute__ ((packed));
 299
 300 /**
 301  * struct sdma_context_data - sdma context specific to a channel
 302  *
 303  * @channel_state:      channel state bits
 304  * @gReg:               general registers
 305  * @mda:                burst dma destination address register
 306  * @msa:                burst dma source address register
 307  * @ms:                 burst dma status register
 308  * @md:                 burst dma data register
 309  * @pda:                peripheral dma destination address register
 310  * @psa:                peripheral dma source address register
 311  * @ps:                 peripheral dma status register
 312  * @pd:                 peripheral dma data register
 313  * @ca:                 CRC polynomial register
 314  * @cs:                 CRC accumulator register
 315  * @dda:                dedicated core destination address register
 316  * @dsa:                dedicated core source address register
 317  * @ds:                 dedicated core status register
 318  * @dd:                 dedicated core data register
 319  * @scratch0:           1st word of dedicated ram for context switch
 320  * @scratch1:           2nd word of dedicated ram for context switch
 321  * @scratch2:           3rd word of dedicated ram for context switch
 322  * @scratch3:           4th word of dedicated ram for context switch
 323  * @scratch4:           5th word of dedicated ram for context switch
 324  * @scratch5:           6th word of dedicated ram for context switch
 325  * @scratch6:           7th word of dedicated ram for context switch
 326  * @scratch7:           8th word of dedicated ram for context switch
 327  */
 328 struct sdma_context_data {
 329         struct sdma_state_registers  channel_state;
 330         u32  gReg[8];
 331         u32  mda;
 332         u32  msa;
 333         u32  ms;
 334         u32  md;
 335         u32  pda;
 336         u32  psa;
 337         u32  ps;
 338         u32  pd;
 339         u32  ca;
 340         u32  cs;
 341         u32  dda;
 342         u32  dsa;
 343         u32  ds;
 344         u32  dd;
 345         u32  scratch0;
 346         u32  scratch1;
 347         u32  scratch2;
 348         u32  scratch3;
 349         u32  scratch4;
 350         u32  scratch5;
 351         u32  scratch6;
 352         u32  scratch7;
 353 } __attribute__ ((packed));
 354
 355
 356 struct sdma_engine;
 357
 358 /**
 359  * struct sdma_desc - descriptor structor for one transfer
 360  * @vd:                 descriptor for virt dma
 361  * @num_bd:             number of descriptors currently handling
 362  * @bd_phys:            physical address of bd
 363  * @buf_tail:           ID of the buffer that was processed
 364  * @buf_ptail:          ID of the previous buffer that was processed
 365  * @period_len:         period length, used in cyclic.
 366  * @chn_real_count:     the real count updated from bd->mode.count
 367  * @chn_count:          the transfer count set
 368  * @sdmac:              sdma_channel pointer
 369  * @bd:                 pointer of allocate bd
 370  */
 371 struct sdma_desc {
 372         struct virt_dma_desc    vd;
 373         unsigned int            num_bd;
 374         dma_addr_t              bd_phys;
 375         unsigned int            buf_tail;
 376         unsigned int            buf_ptail;
 377         unsigned int            period_len;
 378         unsigned int            chn_real_count;
 379         unsigned int            chn_count;
 380         struct sdma_channel     *sdmac;
 381         struct sdma_buffer_descriptor *bd;
 382 };
 383
 384 /**
 385  * struct sdma_channel - housekeeping for a SDMA channel
 386  *
 387  * @vc:                 virt_dma base structure
 388  * @desc:               sdma description including vd and other special member
 389  * @sdma:               pointer to the SDMA engine for this channel
 390  * @channel:            the channel number, matches dmaengine chan_id + 1
 391  * @direction:          transfer type. Needed for setting SDMA script
 392  * @slave_config:       Slave configuration
 393  * @peripheral_type:    Peripheral type. Needed for setting SDMA script
 394  * @event_id0:          aka dma request line
 395  * @event_id1:          for channels that use 2 events
 396  * @word_size:          peripheral access size
 397  * @pc_from_device:     script address for those device_2_memory
 398  * @pc_to_device:       script address for those memory_2_device
 399  * @device_to_device:   script address for those device_2_device
 400  * @pc_to_pc:           script address for those memory_2_memory
 401  * @flags:              loop mode or not
 402  * @per_address:        peripheral source or destination address in common case
 403  *                      destination address in p_2_p case
 404  * @per_address2:       peripheral source address in p_2_p case
 405  * @event_mask:         event mask used in p_2_p script
 406  * @watermark_level:    value for gReg[7], some script will extend it from
 407  *                      basic watermark such as p_2_p
 408  * @shp_addr:           value for gReg[6]
 409  * @per_addr:           value for gReg[2]
 410  * @status:             status of dma channel
 411  * @context_loaded:     ensure context is only loaded once
 412  * @data:               specific sdma interface structure
 413  * @bd_pool:            dma_pool for bd
 414  * @terminate_worker:   used to call back into terminate work function
 415  */
 416 struct sdma_channel {
 417         struct virt_dma_chan            vc;
 418         struct sdma_desc                *desc;
 419         struct sdma_engine              *sdma;
 420         unsigned int                    channel;
 421         enum dma_transfer_direction             direction;
 422         struct dma_slave_config         slave_config;
 423         enum sdma_peripheral_type       peripheral_type;
 424         unsigned int                    event_id0;
 425         unsigned int                    event_id1;
 426         enum dma_slave_buswidth         word_size;
 427         unsigned int                    pc_from_device, pc_to_device;
 428         unsigned int                    device_to_device;
 429         unsigned int                    pc_to_pc;
 430         unsigned long                   flags;
 431         dma_addr_t                      per_address, per_address2;
 432         unsigned long                   event_mask[2];
 433         unsigned long                   watermark_level;
 434         u32                             shp_addr, per_addr;
 435         enum dma_status                 status;
 436         bool                            context_loaded;
 437         struct imx_dma_data             data;
 438         struct work_struct              terminate_worker;
 439 };
 440
 441 #define IMX_DMA_SG_LOOP         BIT(0)
 442
 443 #define MAX_DMA_CHANNELS 32
 444 #define MXC_SDMA_DEFAULT_PRIORITY 1
 445 #define MXC_SDMA_MIN_PRIORITY 1
 446 #define MXC_SDMA_MAX_PRIORITY 7
 447
 448 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 449
 450 /**
 451  * struct sdma_firmware_header - Layout of the firmware image
 452  *
 453  * @magic:              "SDMA"
 454  * @version_major:      increased whenever layout of struct
 455  *                      sdma_script_start_addrs changes.
 456  * @version_minor:      firmware minor version (for binary compatible changes)
 457  * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
 458  * @num_script_addrs:   Number of script addresses in this image
 459  * @ram_code_start:     offset of SDMA ram image in this firmware image
 460  * @ram_code_size:      size of SDMA ram image
 461  * @script_addrs:       Stores the start address of the SDMA scripts
 462  *                      (in SDMA memory space)
 463  */
 464 struct sdma_firmware_header {
 465         u32     magic;
 466         u32     version_major;
 467         u32     version_minor;
 468         u32     script_addrs_start;
 469         u32     num_script_addrs;
 470         u32     ram_code_start;
 471         u32     ram_code_size;
 472 };
 473
 474 struct sdma_driver_data {
 475         int chnenbl0;
 476         int num_events;
 477         struct sdma_script_start_addrs  *script_addrs;
 478         bool check_ratio;
 479 };
 480
 481 struct sdma_engine {
 482         struct device                   *dev;
 483         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 484         struct sdma_channel_control     *channel_control;
 485         void __iomem                    *regs;
 486         struct sdma_context_data        *context;
 487         dma_addr_t                      context_phys;
 488         struct dma_device               dma_device;
 489         struct clk                      *clk_ipg;
 490         struct clk                      *clk_ahb;
 491         spinlock_t                      channel_0_lock;
 492         u32                             script_number;
 493         struct sdma_script_start_addrs  *script_addrs;
 494         const struct sdma_driver_data   *drvdata;
 495         u32                             spba_start_addr;
 496         u32                             spba_end_addr;
 497         unsigned int                    irq;
 498         dma_addr_t                      bd0_phys;
 499         struct sdma_buffer_descriptor   *bd0;
 500         /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
 501         bool                            clk_ratio;
 502 };
 503
 504 static int sdma_config_write(struct dma_chan *chan,
 505                        struct dma_slave_config *dmaengine_cfg,
 506                        enum dma_transfer_direction direction);
 507
 508 static struct sdma_driver_data sdma_imx31 = {
 509         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 510         .num_events = 32,
 511 };
 512
 513 static struct sdma_script_start_addrs sdma_script_imx25 = {
 514         .ap_2_ap_addr = 729,
 515         .uart_2_mcu_addr = 904,
 516         .per_2_app_addr = 1255,
 517         .mcu_2_app_addr = 834,
 518         .uartsh_2_mcu_addr = 1120,
 519         .per_2_shp_addr = 1329,
 520         .mcu_2_shp_addr = 1048,
 521         .ata_2_mcu_addr = 1560,
 522         .mcu_2_ata_addr = 1479,
 523         .app_2_per_addr = 1189,
 524         .app_2_mcu_addr = 770,
 525         .shp_2_per_addr = 1407,
 526         .shp_2_mcu_addr = 979,
 527 };
 528
 529 static struct sdma_driver_data sdma_imx25 = {
 530         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 531         .num_events = 48,
 532         .script_addrs = &sdma_script_imx25,
 533 };
 534
 535 static struct sdma_driver_data sdma_imx35 = {
 536         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 537         .num_events = 48,
 538 };
 539
 540 static struct sdma_script_start_addrs sdma_script_imx51 = {
 541         .ap_2_ap_addr = 642,
 542         .uart_2_mcu_addr = 817,
 543         .mcu_2_app_addr = 747,
 544         .mcu_2_shp_addr = 961,
 545         .ata_2_mcu_addr = 1473,
 546         .mcu_2_ata_addr = 1392,
 547         .app_2_per_addr = 1033,
 548         .app_2_mcu_addr = 683,
 549         .shp_2_per_addr = 1251,
 550         .shp_2_mcu_addr = 892,
 551 };
 552
 553 static struct sdma_driver_data sdma_imx51 = {
 554         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 555         .num_events = 48,
 556         .script_addrs = &sdma_script_imx51,
 557 };
 558
 559 static struct sdma_script_start_addrs sdma_script_imx53 = {
 560         .ap_2_ap_addr = 642,
 561         .app_2_mcu_addr = 683,
 562         .mcu_2_app_addr = 747,
 563         .uart_2_mcu_addr = 817,
 564         .shp_2_mcu_addr = 891,
 565         .mcu_2_shp_addr = 960,
 566         .uartsh_2_mcu_addr = 1032,
 567         .spdif_2_mcu_addr = 1100,
 568         .mcu_2_spdif_addr = 1134,
 569         .firi_2_mcu_addr = 1193,
 570         .mcu_2_firi_addr = 1290,
 571 };
 572
 573 static struct sdma_driver_data sdma_imx53 = {
 574         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 575         .num_events = 48,
 576         .script_addrs = &sdma_script_imx53,
 577 };
 578
 579 static struct sdma_script_start_addrs sdma_script_imx6q = {
 580         .ap_2_ap_addr = 642,
 581         .uart_2_mcu_addr = 817,
 582         .mcu_2_app_addr = 747,
 583         .per_2_per_addr = 6331,
 584         .uartsh_2_mcu_addr = 1032,
 585         .mcu_2_shp_addr = 960,
 586         .app_2_mcu_addr = 683,
 587         .shp_2_mcu_addr = 891,
 588         .spdif_2_mcu_addr = 1100,
 589         .mcu_2_spdif_addr = 1134,
 590 };
 591
 592 static struct sdma_driver_data sdma_imx6q = {
 593         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 594         .num_events = 48,
 595         .script_addrs = &sdma_script_imx6q,
 596 };
 597
 598 static struct sdma_script_start_addrs sdma_script_imx7d = {
 599         .ap_2_ap_addr = 644,
 600         .uart_2_mcu_addr = 819,
 601         .mcu_2_app_addr = 749,
 602         .uartsh_2_mcu_addr = 1034,
 603         .mcu_2_shp_addr = 962,
 604         .app_2_mcu_addr = 685,
 605         .shp_2_mcu_addr = 893,
 606         .spdif_2_mcu_addr = 1102,
 607         .mcu_2_spdif_addr = 1136,
 608 };
 609
 610 static struct sdma_driver_data sdma_imx7d = {
 611         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 612         .num_events = 48,
 613         .script_addrs = &sdma_script_imx7d,
 614 };
 615
 616 static struct sdma_driver_data sdma_imx8mq = {
 617         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 618         .num_events = 48,
 619         .script_addrs = &sdma_script_imx7d,
 620         .check_ratio = 1,
 621 };
 622
 623 static const struct of_device_id sdma_dt_ids[] = {
 624         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 625         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 626         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 627         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 628         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 629         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 630         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 631         { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
 632         { /* sentinel */ }
 633 };
 634 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 635
 636 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 637 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 638 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 639 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 640
 641 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 642 {
 643         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 644         return chnenbl0 + event * 4;
 645 }
 646
 647 static int sdma_config_ownership(struct sdma_channel *sdmac,
 648                 bool event_override, bool mcu_override, bool dsp_override)
 649 {
 650         struct sdma_engine *sdma = sdmac->sdma;
 651         int channel = sdmac->channel;
 652         unsigned long evt, mcu, dsp;
 653
 654         if (event_override && mcu_override && dsp_override)
 655                 return -EINVAL;
 656
 657         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 658         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 659         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 660
 661         if (dsp_override)
 662                 __clear_bit(channel, &dsp);
 663         else
 664                 __set_bit(channel, &dsp);
 665
 666         if (event_override)
 667                 __clear_bit(channel, &evt);
 668         else
 669                 __set_bit(channel, &evt);
 670
 671         if (mcu_override)
 672                 __clear_bit(channel, &mcu);
 673         else
 674                 __set_bit(channel, &mcu);
 675
 676         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 677         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 678         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 679
 680         return 0;
 681 }
 682
 683 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 684 {
 685         writel(BIT(channel), sdma->regs + SDMA_H_START);
 686 }
 687
 688 /*
 689  * sdma_run_channel0 - run a channel and wait till it's done
 690  */
 691 static int sdma_run_channel0(struct sdma_engine *sdma)
 692 {
 693         int ret;
 694         u32 reg;
 695
 696         sdma_enable_channel(sdma, 0);
 697
 698         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 699                                                 reg, !(reg & 1), 1, 500);
 700         if (ret)
 701                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 702
 703         /* Set bits of CONFIG register with dynamic context switching */
 704         reg = readl(sdma->regs + SDMA_H_CONFIG);
 705         if ((reg & SDMA_H_CONFIG_CSM) == 0) {
 706                 reg |= SDMA_H_CONFIG_CSM;
 707                 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
 708         }
 709
 710         return ret;
 711 }
 712
 713 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 714                 u32 address)
 715 {
 716         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 717         void *buf_virt;
 718         dma_addr_t buf_phys;
 719         int ret;
 720         unsigned long flags;
 721
 722         buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
 723         if (!buf_virt) {
 724                 return -ENOMEM;
 725         }
 726
 727         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 728
 729         bd0->mode.command = C0_SETPM;
 730         bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
 731         bd0->mode.count = size / 2;
 732         bd0->buffer_addr = buf_phys;
 733         bd0->ext_buffer_addr = address;
 734
 735         memcpy(buf_virt, buf, size);
 736
 737         ret = sdma_run_channel0(sdma);
 738
 739         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 740
 741         dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
 742
 743         return ret;
 744 }
 745
 746 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 747 {
 748         struct sdma_engine *sdma = sdmac->sdma;
 749         int channel = sdmac->channel;
 750         unsigned long val;
 751         u32 chnenbl = chnenbl_ofs(sdma, event);
 752
 753         val = readl_relaxed(sdma->regs + chnenbl);
 754         __set_bit(channel, &val);
 755         writel_relaxed(val, sdma->regs + chnenbl);
 756 }
 757
 758 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 759 {
 760         struct sdma_engine *sdma = sdmac->sdma;
 761         int channel = sdmac->channel;
 762         u32 chnenbl = chnenbl_ofs(sdma, event);
 763         unsigned long val;
 764
 765         val = readl_relaxed(sdma->regs + chnenbl);
 766         __clear_bit(channel, &val);
 767         writel_relaxed(val, sdma->regs + chnenbl);
 768 }
 769
 770 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
 771 {
 772         return container_of(t, struct sdma_desc, vd.tx);
 773 }
 774
 775 static void sdma_start_desc(struct sdma_channel *sdmac)
 776 {
 777         struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
 778         struct sdma_desc *desc;
 779         struct sdma_engine *sdma = sdmac->sdma;
 780         int channel = sdmac->channel;
 781
 782         if (!vd) {
 783                 sdmac->desc = NULL;
 784                 return;
 785         }
 786         sdmac->desc = desc = to_sdma_desc(&vd->tx);
 787
 788         list_del(&vd->node);
 789
 790         sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
 791         sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
 792         sdma_enable_channel(sdma, sdmac->channel);
 793 }
 794
 795 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 796 {
 797         struct sdma_buffer_descriptor *bd;
 798         int error = 0;
 799         enum dma_status old_status = sdmac->status;
 800
 801         /*
 802          * loop mode. Iterate over descriptors, re-setup them and
 803          * call callback function.
 804          */
 805         while (sdmac->desc) {
 806                 struct sdma_desc *desc = sdmac->desc;
 807
 808                 bd = &desc->bd[desc->buf_tail];
 809
 810                 if (bd->mode.status & BD_DONE)
 811                         break;
 812
 813                 if (bd->mode.status & BD_RROR) {
 814                         bd->mode.status &= ~BD_RROR;
 815                         sdmac->status = DMA_ERROR;
 816                         error = -EIO;
 817                 }
 818
 819                /*
 820                 * We use bd->mode.count to calculate the residue, since contains
 821                 * the number of bytes present in the current buffer descriptor.
 822                 */
 823
 824                 desc->chn_real_count = bd->mode.count;
 825                 bd->mode.status |= BD_DONE;
 826                 bd->mode.count = desc->period_len;
 827                 desc->buf_ptail = desc->buf_tail;
 828                 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
 829
 830                 /*
 831                  * The callback is called from the interrupt context in order
 832                  * to reduce latency and to avoid the risk of altering the
 833                  * SDMA transaction status by the time the client tasklet is
 834                  * executed.
 835                  */
 836                 spin_unlock(&sdmac->vc.lock);
 837                 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
 838                 spin_lock(&sdmac->vc.lock);
 839
 840                 if (error)
 841                         sdmac->status = old_status;
 842         }
 843 }
 844
 845 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
 846 {
 847         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 848         struct sdma_buffer_descriptor *bd;
 849         int i, error = 0;
 850
 851         sdmac->desc->chn_real_count = 0;
 852         /*
 853          * non loop mode. Iterate over all descriptors, collect
 854          * errors and call callback function
 855          */
 856         for (i = 0; i < sdmac->desc->num_bd; i++) {
 857                 bd = &sdmac->desc->bd[i];
 858
 859                  if (bd->mode.status & (BD_DONE | BD_RROR))
 860                         error = -EIO;
 861                  sdmac->desc->chn_real_count += bd->mode.count;
 862         }
 863
 864         if (error)
 865                 sdmac->status = DMA_ERROR;
 866         else
 867                 sdmac->status = DMA_COMPLETE;
 868 }
 869
 870 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 871 {
 872         struct sdma_engine *sdma = dev_id;
 873         unsigned long stat;
 874
 875         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 876         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 877         /* channel 0 is special and not handled here, see run_channel0() */
 878         stat &= ~1;
 879
 880         while (stat) {
 881                 int channel = fls(stat) - 1;
 882                 struct sdma_channel *sdmac = &sdma->channel[channel];
 883                 struct sdma_desc *desc;
 884
 885                 spin_lock(&sdmac->vc.lock);
 886                 desc = sdmac->desc;
 887                 if (desc) {
 888                         if (sdmac->flags & IMX_DMA_SG_LOOP) {
 889                                 sdma_update_channel_loop(sdmac);
 890                         } else {
 891                                 mxc_sdma_handle_channel_normal(sdmac);
 892                                 vchan_cookie_complete(&desc->vd);
 893                                 sdma_start_desc(sdmac);
 894                         }
 895                 }
 896
 897                 spin_unlock(&sdmac->vc.lock);
 898                 __clear_bit(channel, &stat);
 899         }
 900
 901         return IRQ_HANDLED;
 902 }
 903
 904 /*
 905  * sets the pc of SDMA script according to the peripheral type
 906  */
 907 static void sdma_get_pc(struct sdma_channel *sdmac,
 908                 enum sdma_peripheral_type peripheral_type)
 909 {
 910         struct sdma_engine *sdma = sdmac->sdma;
 911         int per_2_emi = 0, emi_2_per = 0;
 912         /*
 913          * These are needed once we start to support transfers between
 914          * two peripherals or memory-to-memory transfers
 915          */
 916         int per_2_per = 0, emi_2_emi = 0;
 917
 918         sdmac->pc_from_device = 0;
 919         sdmac->pc_to_device = 0;
 920         sdmac->device_to_device = 0;
 921         sdmac->pc_to_pc = 0;
 922
 923         switch (peripheral_type) {
 924         case IMX_DMATYPE_MEMORY:
 925                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 926                 break;
 927         case IMX_DMATYPE_DSP:
 928                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 929                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 930                 break;
 931         case IMX_DMATYPE_FIRI:
 932                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 933                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 934                 break;
 935         case IMX_DMATYPE_UART:
 936                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 937                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 938                 break;
 939         case IMX_DMATYPE_UART_SP:
 940                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 941                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 942                 break;
 943         case IMX_DMATYPE_ATA:
 944                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 945                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 946                 break;
 947         case IMX_DMATYPE_CSPI:
 948         case IMX_DMATYPE_EXT:
 949         case IMX_DMATYPE_SSI:
 950         case IMX_DMATYPE_SAI:
 951                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 952                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 953                 break;
 954         case IMX_DMATYPE_SSI_DUAL:
 955                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 956                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 957                 break;
 958         case IMX_DMATYPE_SSI_SP:
 959         case IMX_DMATYPE_MMC:
 960         case IMX_DMATYPE_SDHC:
 961         case IMX_DMATYPE_CSPI_SP:
 962         case IMX_DMATYPE_ESAI:
 963         case IMX_DMATYPE_MSHC_SP:
 964                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 965                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 966                 break;
 967         case IMX_DMATYPE_ASRC:
 968                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 969                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 970                 per_2_per = sdma->script_addrs->per_2_per_addr;
 971                 break;
 972         case IMX_DMATYPE_ASRC_SP:
 973                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 974                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 975                 per_2_per = sdma->script_addrs->per_2_per_addr;
 976                 break;
 977         case IMX_DMATYPE_MSHC:
 978                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 979                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 980                 break;
 981         case IMX_DMATYPE_CCM:
 982                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 983                 break;
 984         case IMX_DMATYPE_SPDIF:
 985                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 986                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 987                 break;
 988         case IMX_DMATYPE_IPU_MEMORY:
 989                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 990                 break;
 991         default:
 992                 break;
 993         }
 994
 995         sdmac->pc_from_device = per_2_emi;
 996         sdmac->pc_to_device = emi_2_per;
 997         sdmac->device_to_device = per_2_per;
 998         sdmac->pc_to_pc = emi_2_emi;
 999 }
1000
1001 static int sdma_load_context(struct sdma_channel *sdmac)
1002 {
1003         struct sdma_engine *sdma = sdmac->sdma;
1004         int channel = sdmac->channel;
1005         int load_address;
1006         struct sdma_context_data *context = sdma->context;
1007         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
1008         int ret;
1009         unsigned long flags;
1010
1011         if (sdmac->context_loaded)
1012                 return 0;
1013
1014         if (sdmac->direction == DMA_DEV_TO_MEM)
1015                 load_address = sdmac->pc_from_device;
1016         else if (sdmac->direction == DMA_DEV_TO_DEV)
1017                 load_address = sdmac->device_to_device;
1018         else if (sdmac->direction == DMA_MEM_TO_MEM)
1019                 load_address = sdmac->pc_to_pc;
1020         else
1021                 load_address = sdmac->pc_to_device;
1022
1023         if (load_address < 0)
1024                 return load_address;
1025
1026         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1027         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1028         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1029         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1030         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1031         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1032
1033         spin_lock_irqsave(&sdma->channel_0_lock, flags);
1034
1035         memset(context, 0, sizeof(*context));
1036         context->channel_state.pc = load_address;
1037
1038         /* Send by context the event mask,base address for peripheral
1039          * and watermark level
1040          */
1041         context->gReg[0] = sdmac->event_mask[1];
1042         context->gReg[1] = sdmac->event_mask[0];
1043         context->gReg[2] = sdmac->per_addr;
1044         context->gReg[6] = sdmac->shp_addr;
1045         context->gReg[7] = sdmac->watermark_level;
1046
1047         bd0->mode.command = C0_SETDM;
1048         bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
1049         bd0->mode.count = sizeof(*context) / 4;
1050         bd0->buffer_addr = sdma->context_phys;
1051         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1052         ret = sdma_run_channel0(sdma);
1053
1054         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1055
1056         sdmac->context_loaded = true;
1057
1058         return ret;
1059 }
1060
1061 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1062 {
1063         return container_of(chan, struct sdma_channel, vc.chan);
1064 }
1065
1066 static int sdma_disable_channel(struct dma_chan *chan)
1067 {
1068         struct sdma_channel *sdmac = to_sdma_chan(chan);
1069         struct sdma_engine *sdma = sdmac->sdma;
1070         int channel = sdmac->channel;
1071
1072         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1073         sdmac->status = DMA_ERROR;
1074
1075         return 0;
1076 }
1077 static void sdma_channel_terminate_work(struct work_struct *work)
1078 {
1079         struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1080                                                   terminate_worker);
1081         unsigned long flags;
1082         LIST_HEAD(head);
1083
1084         /*
1085          * According to NXP R&D team a delay of one BD SDMA cost time
1086          * (maximum is 1ms) should be added after disable of the channel
1087          * bit, to ensure SDMA core has really been stopped after SDMA
1088          * clients call .device_terminate_all.
1089          */
1090         usleep_range(1000, 2000);
1091
1092         spin_lock_irqsave(&sdmac->vc.lock, flags);
1093         vchan_get_all_descriptors(&sdmac->vc, &head);
1094         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1095         vchan_dma_desc_free_list(&sdmac->vc, &head);
1096         sdmac->context_loaded = false;
1097 }
1098
1099 static int sdma_terminate_all(struct dma_chan *chan)
1100 {
1101         struct sdma_channel *sdmac = to_sdma_chan(chan);
1102         unsigned long flags;
1103
1104         spin_lock_irqsave(&sdmac->vc.lock, flags);
1105
1106         sdma_disable_channel(chan);
1107
1108         if (sdmac->desc) {
1109                 vchan_terminate_vdesc(&sdmac->desc->vd);
1110                 sdmac->desc = NULL;
1111                 schedule_work(&sdmac->terminate_worker);
1112         }
1113
1114         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1115
1116         return 0;
1117 }
1118
1119 static void sdma_channel_synchronize(struct dma_chan *chan)
1120 {
1121         struct sdma_channel *sdmac = to_sdma_chan(chan);
1122
1123         vchan_synchronize(&sdmac->vc);
1124
1125         flush_work(&sdmac->terminate_worker);
1126 }
1127
1128 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1129 {
1130         struct sdma_engine *sdma = sdmac->sdma;
1131
1132         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1133         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1134
1135         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1136         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1137
1138         if (sdmac->event_id0 > 31)
1139                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1140
1141         if (sdmac->event_id1 > 31)
1142                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1143
1144         /*
1145          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1146          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1147          * r0(event_mask[1]) and r1(event_mask[0]).
1148          */
1149         if (lwml > hwml) {
1150                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1151                                                 SDMA_WATERMARK_LEVEL_HWML);
1152                 sdmac->watermark_level |= hwml;
1153                 sdmac->watermark_level |= lwml << 16;
1154                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1155         }
1156
1157         if (sdmac->per_address2 >= sdma->spba_start_addr &&
1158                         sdmac->per_address2 <= sdma->spba_end_addr)
1159                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1160
1161         if (sdmac->per_address >= sdma->spba_start_addr &&
1162                         sdmac->per_address <= sdma->spba_end_addr)
1163                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1164
1165         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1166 }
1167
1168 static int sdma_config_channel(struct dma_chan *chan)
1169 {
1170         struct sdma_channel *sdmac = to_sdma_chan(chan);
1171         int ret;
1172
1173         sdma_disable_channel(chan);
1174
1175         sdmac->event_mask[0] = 0;
1176         sdmac->event_mask[1] = 0;
1177         sdmac->shp_addr = 0;
1178         sdmac->per_addr = 0;
1179
1180         switch (sdmac->peripheral_type) {
1181         case IMX_DMATYPE_DSP:
1182                 sdma_config_ownership(sdmac, false, true, true);
1183                 break;
1184         case IMX_DMATYPE_MEMORY:
1185                 sdma_config_ownership(sdmac, false, true, false);
1186                 break;
1187         default:
1188                 sdma_config_ownership(sdmac, true, true, false);
1189                 break;
1190         }
1191
1192         sdma_get_pc(sdmac, sdmac->peripheral_type);
1193
1194         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1195                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1196                 /* Handle multiple event channels differently */
1197                 if (sdmac->event_id1) {
1198                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1199                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1200                                 sdma_set_watermarklevel_for_p2p(sdmac);
1201                 } else
1202                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1203
1204                 /* Address */
1205                 sdmac->shp_addr = sdmac->per_address;
1206                 sdmac->per_addr = sdmac->per_address2;
1207         } else {
1208                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1209         }
1210
1211         ret = sdma_load_context(sdmac);
1212
1213         return ret;
1214 }
1215
1216 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1217                 unsigned int priority)
1218 {
1219         struct sdma_engine *sdma = sdmac->sdma;
1220         int channel = sdmac->channel;
1221
1222         if (priority < MXC_SDMA_MIN_PRIORITY
1223             || priority > MXC_SDMA_MAX_PRIORITY) {
1224                 return -EINVAL;
1225         }
1226
1227         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1228
1229         return 0;
1230 }
1231
1232 static int sdma_request_channel0(struct sdma_engine *sdma)
1233 {
1234         int ret = -EBUSY;
1235
1236         sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1237                                         GFP_NOWAIT);
1238         if (!sdma->bd0) {
1239                 ret = -ENOMEM;
1240                 goto out;
1241         }
1242
1243         sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1244         sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1245
1246         sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1247         return 0;
1248 out:
1249
1250         return ret;
1251 }
1252
1253
1254 static int sdma_alloc_bd(struct sdma_desc *desc)
1255 {
1256         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1257         int ret = 0;
1258
1259         desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1260                                        &desc->bd_phys, GFP_NOWAIT);
1261         if (!desc->bd) {
1262                 ret = -ENOMEM;
1263                 goto out;
1264         }
1265 out:
1266         return ret;
1267 }
1268
1269 static void sdma_free_bd(struct sdma_desc *desc)
1270 {
1271         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1272
1273         dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1274                           desc->bd_phys);
1275 }
1276
1277 static void sdma_desc_free(struct virt_dma_desc *vd)
1278 {
1279         struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1280
1281         sdma_free_bd(desc);
1282         kfree(desc);
1283 }
1284
1285 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1286 {
1287         struct sdma_channel *sdmac = to_sdma_chan(chan);
1288         struct imx_dma_data *data = chan->private;
1289         struct imx_dma_data mem_data;
1290         int prio, ret;
1291
1292         /*
1293          * MEMCPY may never setup chan->private by filter function such as
1294          * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1295          * Please note in any other slave case, you have to setup chan->private
1296          * with 'struct imx_dma_data' in your own filter function if you want to
1297          * request dma channel by dma_request_channel() rather than
1298          * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1299          * to warn you to correct your filter function.
1300          */
1301         if (!data) {
1302                 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1303                 mem_data.priority = 2;
1304                 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1305                 mem_data.dma_request = 0;
1306                 mem_data.dma_request2 = 0;
1307                 data = &mem_data;
1308
1309                 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1310         }
1311
1312         switch (data->priority) {
1313         case DMA_PRIO_HIGH:
1314                 prio = 3;
1315                 break;
1316         case DMA_PRIO_MEDIUM:
1317                 prio = 2;
1318                 break;
1319         case DMA_PRIO_LOW:
1320         default:
1321                 prio = 1;
1322                 break;
1323         }
1324
1325         sdmac->peripheral_type = data->peripheral_type;
1326         sdmac->event_id0 = data->dma_request;
1327         sdmac->event_id1 = data->dma_request2;
1328
1329         ret = clk_enable(sdmac->sdma->clk_ipg);
1330         if (ret)
1331                 return ret;
1332         ret = clk_enable(sdmac->sdma->clk_ahb);
1333         if (ret)
1334                 goto disable_clk_ipg;
1335
1336         ret = sdma_set_channel_priority(sdmac, prio);
1337         if (ret)
1338                 goto disable_clk_ahb;
1339
1340         return 0;
1341
1342 disable_clk_ahb:
1343         clk_disable(sdmac->sdma->clk_ahb);
1344 disable_clk_ipg:
1345         clk_disable(sdmac->sdma->clk_ipg);
1346         return ret;
1347 }
1348
1349 static void sdma_free_chan_resources(struct dma_chan *chan)
1350 {
1351         struct sdma_channel *sdmac = to_sdma_chan(chan);
1352         struct sdma_engine *sdma = sdmac->sdma;
1353
1354         sdma_terminate_all(chan);
1355
1356         sdma_channel_synchronize(chan);
1357
1358         sdma_event_disable(sdmac, sdmac->event_id0);
1359         if (sdmac->event_id1)
1360                 sdma_event_disable(sdmac, sdmac->event_id1);
1361
1362         sdmac->event_id0 = 0;
1363         sdmac->event_id1 = 0;
1364         sdmac->context_loaded = false;
1365
1366         sdma_set_channel_priority(sdmac, 0);
1367
1368         clk_disable(sdma->clk_ipg);
1369         clk_disable(sdma->clk_ahb);
1370 }
1371
1372 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1373                                 enum dma_transfer_direction direction, u32 bds)
1374 {
1375         struct sdma_desc *desc;
1376
1377         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1378         if (!desc)
1379                 goto err_out;
1380
1381         sdmac->status = DMA_IN_PROGRESS;
1382         sdmac->direction = direction;
1383         sdmac->flags = 0;
1384
1385         desc->chn_count = 0;
1386         desc->chn_real_count = 0;
1387         desc->buf_tail = 0;
1388         desc->buf_ptail = 0;
1389         desc->sdmac = sdmac;
1390         desc->num_bd = bds;
1391
1392         if (sdma_alloc_bd(desc))
1393                 goto err_desc_out;
1394
1395         /* No slave_config called in MEMCPY case, so do here */
1396         if (direction == DMA_MEM_TO_MEM)
1397                 sdma_config_ownership(sdmac, false, true, false);
1398
1399         if (sdma_load_context(sdmac))
1400                 goto err_desc_out;
1401
1402         return desc;
1403
1404 err_desc_out:
1405         kfree(desc);
1406 err_out:
1407         return NULL;
1408 }
1409
1410 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1411                 struct dma_chan *chan, dma_addr_t dma_dst,
1412                 dma_addr_t dma_src, size_t len, unsigned long flags)
1413 {
1414         struct sdma_channel *sdmac = to_sdma_chan(chan);
1415         struct sdma_engine *sdma = sdmac->sdma;
1416         int channel = sdmac->channel;
1417         size_t count;
1418         int i = 0, param;
1419         struct sdma_buffer_descriptor *bd;
1420         struct sdma_desc *desc;
1421
1422         if (!chan || !len)
1423                 return NULL;
1424
1425         dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1426                 &dma_src, &dma_dst, len, channel);
1427
1428         desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1429                                         len / SDMA_BD_MAX_CNT + 1);
1430         if (!desc)
1431                 return NULL;
1432
1433         do {
1434                 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1435                 bd = &desc->bd[i];
1436                 bd->buffer_addr = dma_src;
1437                 bd->ext_buffer_addr = dma_dst;
1438                 bd->mode.count = count;
1439                 desc->chn_count += count;
1440                 bd->mode.command = 0;
1441
1442                 dma_src += count;
1443                 dma_dst += count;
1444                 len -= count;
1445                 i++;
1446
1447                 param = BD_DONE | BD_EXTD | BD_CONT;
1448                 /* last bd */
1449                 if (!len) {
1450                         param |= BD_INTR;
1451                         param |= BD_LAST;
1452                         param &= ~BD_CONT;
1453                 }
1454
1455                 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1456                                 i, count, bd->buffer_addr,
1457                                 param & BD_WRAP ? "wrap" : "",
1458                                 param & BD_INTR ? " intr" : "");
1459
1460                 bd->mode.status = param;
1461         } while (len);
1462
1463         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1464 }
1465
1466 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1467                 struct dma_chan *chan, struct scatterlist *sgl,
1468                 unsigned int sg_len, enum dma_transfer_direction direction,
1469                 unsigned long flags, void *context)
1470 {
1471         struct sdma_channel *sdmac = to_sdma_chan(chan);
1472         struct sdma_engine *sdma = sdmac->sdma;
1473         int i, count;
1474         int channel = sdmac->channel;
1475         struct scatterlist *sg;
1476         struct sdma_desc *desc;
1477
1478         sdma_config_write(chan, &sdmac->slave_config, direction);
1479
1480         desc = sdma_transfer_init(sdmac, direction, sg_len);
1481         if (!desc)
1482                 goto err_out;
1483
1484         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1485                         sg_len, channel);
1486
1487         for_each_sg(sgl, sg, sg_len, i) {
1488                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1489                 int param;
1490
1491                 bd->buffer_addr = sg->dma_address;
1492
1493                 count = sg_dma_len(sg);
1494
1495                 if (count > SDMA_BD_MAX_CNT) {
1496                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1497                                         channel, count, SDMA_BD_MAX_CNT);
1498                         goto err_bd_out;
1499                 }
1500
1501                 bd->mode.count = count;
1502                 desc->chn_count += count;
1503
1504                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1505                         goto err_bd_out;
1506
1507                 switch (sdmac->word_size) {
1508                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1509                         bd->mode.command = 0;
1510                         if (count & 3 || sg->dma_address & 3)
1511                                 goto err_bd_out;
1512                         break;
1513                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1514                         bd->mode.command = 2;
1515                         if (count & 1 || sg->dma_address & 1)
1516                                 goto err_bd_out;
1517                         break;
1518                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1519                         bd->mode.command = 1;
1520                         break;
1521                 default:
1522                         goto err_bd_out;
1523                 }
1524
1525                 param = BD_DONE | BD_EXTD | BD_CONT;
1526
1527                 if (i + 1 == sg_len) {
1528                         param |= BD_INTR;
1529                         param |= BD_LAST;
1530                         param &= ~BD_CONT;
1531                 }
1532
1533                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1534                                 i, count, (u64)sg->dma_address,
1535                                 param & BD_WRAP ? "wrap" : "",
1536                                 param & BD_INTR ? " intr" : "");
1537
1538                 bd->mode.status = param;
1539         }
1540
1541         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1542 err_bd_out:
1543         sdma_free_bd(desc);
1544         kfree(desc);
1545 err_out:
1546         sdmac->status = DMA_ERROR;
1547         return NULL;
1548 }
1549
1550 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1551                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1552                 size_t period_len, enum dma_transfer_direction direction,
1553                 unsigned long flags)
1554 {
1555         struct sdma_channel *sdmac = to_sdma_chan(chan);
1556         struct sdma_engine *sdma = sdmac->sdma;
1557         int num_periods = buf_len / period_len;
1558         int channel = sdmac->channel;
1559         int i = 0, buf = 0;
1560         struct sdma_desc *desc;
1561
1562         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1563
1564         sdma_config_write(chan, &sdmac->slave_config, direction);
1565
1566         desc = sdma_transfer_init(sdmac, direction, num_periods);
1567         if (!desc)
1568                 goto err_out;
1569
1570         desc->period_len = period_len;
1571
1572         sdmac->flags |= IMX_DMA_SG_LOOP;
1573
1574         if (period_len > SDMA_BD_MAX_CNT) {
1575                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1576                                 channel, period_len, SDMA_BD_MAX_CNT);
1577                 goto err_bd_out;
1578         }
1579
1580         while (buf < buf_len) {
1581                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1582                 int param;
1583
1584                 bd->buffer_addr = dma_addr;
1585
1586                 bd->mode.count = period_len;
1587
1588                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1589                         goto err_bd_out;
1590                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1591                         bd->mode.command = 0;
1592                 else
1593                         bd->mode.command = sdmac->word_size;
1594
1595                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1596                 if (i + 1 == num_periods)
1597                         param |= BD_WRAP;
1598
1599                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1600                                 i, period_len, (u64)dma_addr,
1601                                 param & BD_WRAP ? "wrap" : "",
1602                                 param & BD_INTR ? " intr" : "");
1603
1604                 bd->mode.status = param;
1605
1606                 dma_addr += period_len;
1607                 buf += period_len;
1608
1609                 i++;
1610         }
1611
1612         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1613 err_bd_out:
1614         sdma_free_bd(desc);
1615         kfree(desc);
1616 err_out:
1617         sdmac->status = DMA_ERROR;
1618         return NULL;
1619 }
1620
1621 static int sdma_config_write(struct dma_chan *chan,
1622                        struct dma_slave_config *dmaengine_cfg,
1623                        enum dma_transfer_direction direction)
1624 {
1625         struct sdma_channel *sdmac = to_sdma_chan(chan);
1626
1627         if (direction == DMA_DEV_TO_MEM) {
1628                 sdmac->per_address = dmaengine_cfg->src_addr;
1629                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1630                         dmaengine_cfg->src_addr_width;
1631                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1632         } else if (direction == DMA_DEV_TO_DEV) {
1633                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1634                 sdmac->per_address = dmaengine_cfg->dst_addr;
1635                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1636                         SDMA_WATERMARK_LEVEL_LWML;
1637                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1638                         SDMA_WATERMARK_LEVEL_HWML;
1639                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1640         } else {
1641                 sdmac->per_address = dmaengine_cfg->dst_addr;
1642                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1643                         dmaengine_cfg->dst_addr_width;
1644                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1645         }
1646         sdmac->direction = direction;
1647         return sdma_config_channel(chan);
1648 }
1649
1650 static int sdma_config(struct dma_chan *chan,
1651                        struct dma_slave_config *dmaengine_cfg)
1652 {
1653         struct sdma_channel *sdmac = to_sdma_chan(chan);
1654
1655         memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1656
1657         /* Set ENBLn earlier to make sure dma request triggered after that */
1658         if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1659                 return -EINVAL;
1660         sdma_event_enable(sdmac, sdmac->event_id0);
1661
1662         if (sdmac->event_id1) {
1663                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1664                         return -EINVAL;
1665                 sdma_event_enable(sdmac, sdmac->event_id1);
1666         }
1667
1668         return 0;
1669 }
1670
1671 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1672                                       dma_cookie_t cookie,
1673                                       struct dma_tx_state *txstate)
1674 {
1675         struct sdma_channel *sdmac = to_sdma_chan(chan);
1676         struct sdma_desc *desc = NULL;
1677         u32 residue;
1678         struct virt_dma_desc *vd;
1679         enum dma_status ret;
1680         unsigned long flags;
1681
1682         ret = dma_cookie_status(chan, cookie, txstate);
1683         if (ret == DMA_COMPLETE || !txstate)
1684                 return ret;
1685
1686         spin_lock_irqsave(&sdmac->vc.lock, flags);
1687
1688         vd = vchan_find_desc(&sdmac->vc, cookie);
1689         if (vd)
1690                 desc = to_sdma_desc(&vd->tx);
1691         else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie)
1692                 desc = sdmac->desc;
1693
1694         if (desc) {
1695                 if (sdmac->flags & IMX_DMA_SG_LOOP)
1696                         residue = (desc->num_bd - desc->buf_ptail) *
1697                                 desc->period_len - desc->chn_real_count;
1698                 else
1699                         residue = desc->chn_count - desc->chn_real_count;
1700         } else {
1701                 residue = 0;
1702         }
1703
1704         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1705
1706         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1707                          residue);
1708
1709         return sdmac->status;
1710 }
1711
1712 static void sdma_issue_pending(struct dma_chan *chan)
1713 {
1714         struct sdma_channel *sdmac = to_sdma_chan(chan);
1715         unsigned long flags;
1716
1717         spin_lock_irqsave(&sdmac->vc.lock, flags);
1718         if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1719                 sdma_start_desc(sdmac);
1720         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1721 }
1722
1723 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1724 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1725 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1726 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1727
1728 static void sdma_add_scripts(struct sdma_engine *sdma,
1729                 const struct sdma_script_start_addrs *addr)
1730 {
1731         s32 *addr_arr = (u32 *)addr;
1732         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1733         int i;
1734
1735         /* use the default firmware in ROM if missing external firmware */
1736         if (!sdma->script_number)
1737                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1738
1739         if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1740                                   / sizeof(s32)) {
1741                 dev_err(sdma->dev,
1742                         "SDMA script number %d not match with firmware.\n",
1743                         sdma->script_number);
1744                 return;
1745         }
1746
1747         for (i = 0; i < sdma->script_number; i++)
1748                 if (addr_arr[i] > 0)
1749                         saddr_arr[i] = addr_arr[i];
1750 }
1751
1752 static void sdma_load_firmware(const struct firmware *fw, void *context)
1753 {
1754         struct sdma_engine *sdma = context;
1755         const struct sdma_firmware_header *header;
1756         const struct sdma_script_start_addrs *addr;
1757         unsigned short *ram_code;
1758
1759         if (!fw) {
1760                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1761                 /* In this case we just use the ROM firmware. */
1762                 return;
1763         }
1764
1765         if (fw->size < sizeof(*header))
1766                 goto err_firmware;
1767
1768         header = (struct sdma_firmware_header *)fw->data;
1769
1770         if (header->magic != SDMA_FIRMWARE_MAGIC)
1771                 goto err_firmware;
1772         if (header->ram_code_start + header->ram_code_size > fw->size)
1773                 goto err_firmware;
1774         switch (header->version_major) {
1775         case 1:
1776                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1777                 break;
1778         case 2:
1779                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1780                 break;
1781         case 3:
1782                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1783                 break;
1784         case 4:
1785                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1786                 break;
1787         default:
1788                 dev_err(sdma->dev, "unknown firmware version\n");
1789                 goto err_firmware;
1790         }
1791
1792         addr = (void *)header + header->script_addrs_start;
1793         ram_code = (void *)header + header->ram_code_start;
1794
1795         clk_enable(sdma->clk_ipg);
1796         clk_enable(sdma->clk_ahb);
1797         /* download the RAM image for SDMA */
1798         sdma_load_script(sdma, ram_code,
1799                         header->ram_code_size,
1800                         addr->ram_code_start_addr);
1801         clk_disable(sdma->clk_ipg);
1802         clk_disable(sdma->clk_ahb);
1803
1804         sdma_add_scripts(sdma, addr);
1805
1806         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1807                         header->version_major,
1808                         header->version_minor);
1809
1810 err_firmware:
1811         release_firmware(fw);
1812 }
1813
1814 #define EVENT_REMAP_CELLS 3
1815
1816 static int sdma_event_remap(struct sdma_engine *sdma)
1817 {
1818         struct device_node *np = sdma->dev->of_node;
1819         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1820         struct property *event_remap;
1821         struct regmap *gpr;
1822         char propname[] = "fsl,sdma-event-remap";
1823         u32 reg, val, shift, num_map, i;
1824         int ret = 0;
1825
1826         if (IS_ERR(np) || IS_ERR(gpr_np))
1827                 goto out;
1828
1829         event_remap = of_find_property(np, propname, NULL);
1830         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1831         if (!num_map) {
1832                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1833                 goto out;
1834         } else if (num_map % EVENT_REMAP_CELLS) {
1835                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1836                                 propname, EVENT_REMAP_CELLS);
1837                 ret = -EINVAL;
1838                 goto out;
1839         }
1840
1841         gpr = syscon_node_to_regmap(gpr_np);
1842         if (IS_ERR(gpr)) {
1843                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1844                 ret = PTR_ERR(gpr);
1845                 goto out;
1846         }
1847
1848         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1849                 ret = of_property_read_u32_index(np, propname, i, &reg);
1850                 if (ret) {
1851                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1852                                         propname, i);
1853                         goto out;
1854                 }
1855
1856                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1857                 if (ret) {
1858                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1859                                         propname, i + 1);
1860                         goto out;
1861                 }
1862
1863                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1864                 if (ret) {
1865                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1866                                         propname, i + 2);
1867                         goto out;
1868                 }
1869
1870                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1871         }
1872
1873 out:
1874         if (!IS_ERR(gpr_np))
1875                 of_node_put(gpr_np);
1876
1877         return ret;
1878 }
1879
1880 static int sdma_get_firmware(struct sdma_engine *sdma,
1881                 const char *fw_name)
1882 {
1883         int ret;
1884
1885         ret = request_firmware_nowait(THIS_MODULE,
1886                         FW_ACTION_UEVENT, fw_name, sdma->dev,
1887                         GFP_KERNEL, sdma, sdma_load_firmware);
1888
1889         return ret;
1890 }
1891
1892 static int sdma_init(struct sdma_engine *sdma)
1893 {
1894         int i, ret;
1895         dma_addr_t ccb_phys;
1896
1897         ret = clk_enable(sdma->clk_ipg);
1898         if (ret)
1899                 return ret;
1900         ret = clk_enable(sdma->clk_ahb);
1901         if (ret)
1902                 goto disable_clk_ipg;
1903
1904         if (sdma->drvdata->check_ratio &&
1905             (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
1906                 sdma->clk_ratio = 1;
1907
1908         /* Be sure SDMA has not started yet */
1909         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1910
1911         sdma->channel_control = dma_alloc_coherent(sdma->dev,
1912                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1913                         sizeof(struct sdma_context_data),
1914                         &ccb_phys, GFP_KERNEL);
1915
1916         if (!sdma->channel_control) {
1917                 ret = -ENOMEM;
1918                 goto err_dma_alloc;
1919         }
1920
1921         sdma->context = (void *)sdma->channel_control +
1922                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1923         sdma->context_phys = ccb_phys +
1924                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1925
1926         /* disable all channels */
1927         for (i = 0; i < sdma->drvdata->num_events; i++)
1928                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1929
1930         /* All channels have priority 0 */
1931         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1932                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1933
1934         ret = sdma_request_channel0(sdma);
1935         if (ret)
1936                 goto err_dma_alloc;
1937
1938         sdma_config_ownership(&sdma->channel[0], false, true, false);
1939
1940         /* Set Command Channel (Channel Zero) */
1941         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1942
1943         /* Set bits of CONFIG register but with static context switching */
1944         if (sdma->clk_ratio)
1945                 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
1946         else
1947                 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1948
1949         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1950
1951         /* Initializes channel's priorities */
1952         sdma_set_channel_priority(&sdma->channel[0], 7);
1953
1954         clk_disable(sdma->clk_ipg);
1955         clk_disable(sdma->clk_ahb);
1956
1957         return 0;
1958
1959 err_dma_alloc:
1960         clk_disable(sdma->clk_ahb);
1961 disable_clk_ipg:
1962         clk_disable(sdma->clk_ipg);
1963         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1964         return ret;
1965 }
1966
1967 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1968 {
1969         struct sdma_channel *sdmac = to_sdma_chan(chan);
1970         struct imx_dma_data *data = fn_param;
1971
1972         if (!imx_dma_is_general_purpose(chan))
1973                 return false;
1974
1975         sdmac->data = *data;
1976         chan->private = &sdmac->data;
1977
1978         return true;
1979 }
1980
1981 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1982                                    struct of_dma *ofdma)
1983 {
1984         struct sdma_engine *sdma = ofdma->of_dma_data;
1985         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1986         struct imx_dma_data data;
1987
1988         if (dma_spec->args_count != 3)
1989                 return NULL;
1990
1991         data.dma_request = dma_spec->args[0];
1992         data.peripheral_type = dma_spec->args[1];
1993         data.priority = dma_spec->args[2];
1994         /*
1995          * init dma_request2 to zero, which is not used by the dts.
1996          * For P2P, dma_request2 is init from dma_request_channel(),
1997          * chan->private will point to the imx_dma_data, and in
1998          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1999          * be set to sdmac->event_id1.
2000          */
2001         data.dma_request2 = 0;
2002
2003         return __dma_request_channel(&mask, sdma_filter_fn, &data,
2004                                      ofdma->of_node);
2005 }
2006
2007 static int sdma_probe(struct platform_device *pdev)
2008 {
2009         struct device_node *np = pdev->dev.of_node;
2010         struct device_node *spba_bus;
2011         const char *fw_name;
2012         int ret;
2013         int irq;
2014         struct resource *iores;
2015         struct resource spba_res;
2016         int i;
2017         struct sdma_engine *sdma;
2018         s32 *saddr_arr;
2019
2020         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2021         if (ret)
2022                 return ret;
2023
2024         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2025         if (!sdma)
2026                 return -ENOMEM;
2027
2028         spin_lock_init(&sdma->channel_0_lock);
2029
2030         sdma->dev = &pdev->dev;
2031         sdma->drvdata = of_device_get_match_data(sdma->dev);
2032
2033         irq = platform_get_irq(pdev, 0);
2034         if (irq < 0)
2035                 return irq;
2036
2037         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2038         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
2039         if (IS_ERR(sdma->regs))
2040                 return PTR_ERR(sdma->regs);
2041
2042         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2043         if (IS_ERR(sdma->clk_ipg))
2044                 return PTR_ERR(sdma->clk_ipg);
2045
2046         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2047         if (IS_ERR(sdma->clk_ahb))
2048                 return PTR_ERR(sdma->clk_ahb);
2049
2050         ret = clk_prepare(sdma->clk_ipg);
2051         if (ret)
2052                 return ret;
2053
2054         ret = clk_prepare(sdma->clk_ahb);
2055         if (ret)
2056                 goto err_clk;
2057
2058         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2059                                sdma);
2060         if (ret)
2061                 goto err_irq;
2062
2063         sdma->irq = irq;
2064
2065         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2066         if (!sdma->script_addrs) {
2067                 ret = -ENOMEM;
2068                 goto err_irq;
2069         }
2070
2071         /* initially no scripts available */
2072         saddr_arr = (s32 *)sdma->script_addrs;
2073         for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2074                 saddr_arr[i] = -EINVAL;
2075
2076         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2077         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2078         dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2079
2080         INIT_LIST_HEAD(&sdma->dma_device.channels);
2081         /* Initialize channel parameters */
2082         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2083                 struct sdma_channel *sdmac = &sdma->channel[i];
2084
2085                 sdmac->sdma = sdma;
2086
2087                 sdmac->channel = i;
2088                 sdmac->vc.desc_free = sdma_desc_free;
2089                 INIT_WORK(&sdmac->terminate_worker,
2090                                 sdma_channel_terminate_work);
2091                 /*
2092                  * Add the channel to the DMAC list. Do not add channel 0 though
2093                  * because we need it internally in the SDMA driver. This also means
2094                  * that channel 0 in dmaengine counting matches sdma channel 1.
2095                  */
2096                 if (i)
2097                         vchan_init(&sdmac->vc, &sdma->dma_device);
2098         }
2099
2100         ret = sdma_init(sdma);
2101         if (ret)
2102                 goto err_init;
2103
2104         ret = sdma_event_remap(sdma);
2105         if (ret)
2106                 goto err_init;
2107
2108         if (sdma->drvdata->script_addrs)
2109                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2110
2111         sdma->dma_device.dev = &pdev->dev;
2112
2113         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2114         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2115         sdma->dma_device.device_tx_status = sdma_tx_status;
2116         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2117         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2118         sdma->dma_device.device_config = sdma_config;
2119         sdma->dma_device.device_terminate_all = sdma_terminate_all;
2120         sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2121         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2122         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2123         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2124         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2125         sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2126         sdma->dma_device.device_issue_pending = sdma_issue_pending;
2127         sdma->dma_device.copy_align = 2;
2128         dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2129
2130         platform_set_drvdata(pdev, sdma);
2131
2132         ret = dma_async_device_register(&sdma->dma_device);
2133         if (ret) {
2134                 dev_err(&pdev->dev, "unable to register\n");
2135                 goto err_init;
2136         }
2137
2138         if (np) {
2139                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2140                 if (ret) {
2141                         dev_err(&pdev->dev, "failed to register controller\n");
2142                         goto err_register;
2143                 }
2144
2145                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2146                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2147                 if (!ret) {
2148                         sdma->spba_start_addr = spba_res.start;
2149                         sdma->spba_end_addr = spba_res.end;
2150                 }
2151                 of_node_put(spba_bus);
2152         }
2153
2154         /*
2155          * Because that device tree does not encode ROM script address,
2156          * the RAM script in firmware is mandatory for device tree
2157          * probe, otherwise it fails.
2158          */
2159         ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2160                                       &fw_name);
2161         if (ret) {
2162                 dev_warn(&pdev->dev, "failed to get firmware name\n");
2163         } else {
2164                 ret = sdma_get_firmware(sdma, fw_name);
2165                 if (ret)
2166                         dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2167         }
2168
2169         return 0;
2170
2171 err_register:
2172         dma_async_device_unregister(&sdma->dma_device);
2173 err_init:
2174         kfree(sdma->script_addrs);
2175 err_irq:
2176         clk_unprepare(sdma->clk_ahb);
2177 err_clk:
2178         clk_unprepare(sdma->clk_ipg);
2179         return ret;
2180 }
2181
2182 static int sdma_remove(struct platform_device *pdev)
2183 {
2184         struct sdma_engine *sdma = platform_get_drvdata(pdev);
2185         int i;
2186
2187         devm_free_irq(&pdev->dev, sdma->irq, sdma);
2188         dma_async_device_unregister(&sdma->dma_device);
2189         kfree(sdma->script_addrs);
2190         clk_unprepare(sdma->clk_ahb);
2191         clk_unprepare(sdma->clk_ipg);
2192         /* Kill the tasklet */
2193         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2194                 struct sdma_channel *sdmac = &sdma->channel[i];
2195
2196                 tasklet_kill(&sdmac->vc.task);
2197                 sdma_free_chan_resources(&sdmac->vc.chan);
2198         }
2199
2200         platform_set_drvdata(pdev, NULL);
2201         return 0;
2202 }
2203
2204 static struct platform_driver sdma_driver = {
2205         .driver         = {
2206                 .name   = "imx-sdma",
2207                 .of_match_table = sdma_dt_ids,
2208         },
2209         .remove         = sdma_remove,
2210         .probe          = sdma_probe,
2211 };
2212
2213 module_platform_driver(sdma_driver);
2214
2215 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2216 MODULE_DESCRIPTION("i.MX SDMA driver");
2217 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2218 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2219 #endif
2220 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2221 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2222 #endif
2223 MODULE_LICENSE("GPL");